Filter circuit and electronic device

Abstract

The present invention makes it possible to reduce the planar size of a filter circuit provided with inductors and capacitors.　The filter circuit includes a first inductor, a second inductor disposed adjacent to the first inductor, and a first capacitor in which opposing electrodes are each shared with a pattern of an adjacent portion between first and second inductors. The opposing electrodes of the first capacitor may be disposed in the same layer. The opposing electrodes of the first capacitor may be disposed in mutually different layers. The capacitance value of the first capacitor may be set to a value at which common mode noise is attenuated.

Description

Filter circuits and electronic devices

[0001] The present technology relates to a filter circuit and an electronic device. More specifically, the present technology relates to a filter circuit and an electronic device provided with an inductor and a capacitor.

[0002] To attenuate common-mode noise, filter circuits have been proposed in which coils and capacitors are formed on a silicon substrate. For example, a single-layer thin-film filter circuit has been disclosed that has a substrate and a group of thin-film conductors on the surface of the substrate, and outputs a differential signal in response to a differential signal input (see, for example, Patent Document 1).

[0003] JP 2018-195984 A

[0004] However, in the above-mentioned conventional technology, a large number of capacitors arranged separately from the coils are used, which may lead to an increase in the planar size of the filter circuit.

[0005] The present technology was developed in view of these circumstances, and aims to enable a reduction in the planar size of a filter circuit provided with inductors and capacitors.

[0006] The present technology has been made to solve the above-mentioned problems, and a first aspect thereof is a filter circuit including a first inductor, a second inductor arranged adjacent to the first inductor, and a first capacitor whose opposing electrode is shared with patterns of the first inductor and adjacent portions of the second inductor, thereby providing an effect that the capacitor is formed based on a conductor constituting the inductor.

[0007] In the first aspect, the counter electrodes of the first capacitor may be disposed in the same layer, thereby providing an effect that the capacitor is formed in the same layer based on the conductor that constitutes the inductor.

[0008] In the first aspect, the opposing electrodes of the first capacitor may be disposed on different layers, thereby providing an effect that the capacitor is formed between different layers based on the conductor that constitutes the inductor.

[0009] In the first aspect, the pattern width of the portion of the first inductor and the second inductor used for the opposing electrodes may be different from the pattern width of the portion of the first inductor and the second inductor not used for the opposing electrodes, thereby providing an effect that the capacitance value of the capacitor is changed based on the pattern width of the inductor.

[0010] In the first aspect, the capacitance value of the first capacitor may be set to a value that attenuates common-mode noise, thereby providing an effect that a common-mode filter is configured while a capacitor is formed based on a conductor that configures an inductor.

[0011] In the first aspect, the first capacitor may be formed based on capacitive coupling between the first inductor and the second inductor, thereby providing an effect of reducing the area of ​​the capacitor in the filter circuit.

[0012] In addition, in the first aspect, the filter circuit may further include a second capacitor having one end connected to a connection point between the first inductor and the second inductor, thereby providing an effect that a capacitor formed separately from the inductor is mounted on the filter circuit.

[0013] In the first aspect, the filter circuit may further include a conductor layer on which the first inductor, the second inductor, the first capacitor, and the second capacitor are formed, and a semiconductor substrate on which the conductor layer is stacked, thereby achieving the effect of integrating a filter circuit provided with an inductor and a capacitor.

[0014] In addition, in the first aspect, the semiconductor device may further include a pad electrode connected to one end of a series circuit of the first inductor and the second inductor and disposed on the uppermost layer of the conductor layer, thereby providing an effect of allowing a filter circuit to be externally attached.

[0015] In the first aspect, the first inductor, the second inductor, the first capacitor, and the second capacitor may form a single-ended filter, thereby providing an effect of integrating a single-ended filter.

[0016] In the first aspect, a common mode filter may be configured by pairing the single-ended filters, thereby providing an effect of integrating the common mode filter.

[0017] In the first aspect, the common mode filters may be connected in N stages (N is an integer equal to or greater than 1). This brings about an effect that the band is changed while the group delay of the common mode filters is maintained constant.

[0018] In the first aspect, the power supply may further include a DC blocking capacitor connected in series to the series circuit of the first inductor and the second inductor, thereby providing an effect of integrating the filter circuit and the DC blocking capacitor.

[0019] A second aspect of the present invention is an electronic device including a circuit board on which a transmission line is formed, and a filter circuit formed on the circuit board and connected to the transmission line, the filter circuit including a first inductor, a second inductor arranged adjacent to the first inductor, and a first capacitor whose opposing electrode is shared with patterns of adjacent portions of the first inductor and the second inductor, thereby reducing the number of capacitance elements provided in the filter circuit and attenuating noise on the transmission line.

[0020] In a second aspect, the transmission path may support low voltage differential signaling (LVDS), and the filter circuit may be a common mode filter, thereby reducing the number of capacitance elements provided in the common mode filter and attenuating common mode noise on the transmission path.

[0021] In the second aspect, the capacitance value of the first capacitor may be set to a value that allows a differential signal to pass through the transmission line and attenuates common-mode noise, thereby providing an effect that a capacitor is formed based on a conductor that constitutes an inductor, and a common-mode filter is mounted on a circuit board on which the transmission line is formed.

[0022] 1 is a circuit diagram showing a configuration example of a filter circuit according to a first embodiment; FIG. 2 is a plan view showing a layout example of the filter circuit according to the first embodiment; FIG. 3 is a perspective view showing an excerpt of a portion of the filter circuit according to the first embodiment; FIG. 4 is a perspective view showing a current path of the filter circuit according to the first embodiment; FIG. 5 is a perspective view showing a configuration example of an inductor of the filter circuit according to the first embodiment; FIG. 6 is a cross-sectional view showing a configuration example of the filter circuit according to the first embodiment; FIG. 7 is a diagram showing an implementation example of the filter circuit according to the first embodiment; FIG. 8 is a perspective view showing a configuration example of an inductor and a capacitor of the filter circuit according to the second embodiment; FIG. 9 is a perspective view showing a configuration example of an inductor and a capacitor of the filter circuit according to the third embodiment; FIG. 10 is a perspective view showing a configuration example of an inductor and a capacitor of the filter circuit according to the fourth embodiment; FIG. 11 is a plan view showing a layout example of the filter circuit according to the fifth embodiment; FIG. 12 is a circuit diagram showing a configuration example of a filter circuit according to the sixth embodiment; FIG. 13 is a plan view showing a layout example of the filter circuit according to the sixth embodiment; FIG. 14 is a circuit diagram showing a configuration example of the filter circuit according to the seventh embodiment; FIG. 15 is a plan view showing a layout example of the filter circuit according to the seventh embodiment; FIG. 16 is a block diagram showing a schematic configuration example of a vehicle control system; FIG. 17 is an explanatory diagram showing an example of an installation position of an imaging unit.

[0023] Hereinafter, modes for carrying out the present technology (hereinafter referred to as embodiments) will be described. The description will be made in the following order. 1. First embodiment (an example in which a common mode filter capacitor is formed on a laminated inductor of a common mode filter) 2. Second embodiment (an example in which a filter circuit capacitor is formed by laminating inductors of a filter circuit) 3. Third embodiment (an example in which a filter circuit capacitor is formed by laminating inductors of a filter circuit, and the pattern width of the inductor and the pattern width of the capacitor are made different from each other) 4. Fourth embodiment (an example in which a filter circuit capacitor is formed by arranging inductors of a filter circuit adjacent to each other in the horizontal direction) 5. Fifth embodiment (an example in which common mode filters having different layout configurations are connected in three stages) 6. Sixth embodiment (an example in which a DC cut capacitor is integrated on a chip in which a common mode filter capacitor is formed on a laminated inductor of a common mode filter) 7. Seventh embodiment (an example in which a common mode filter capacitor is formed on a laminated inductor of a single-ended filter) 8. Application example to a moving body

[0024] 1 is a circuit diagram showing an example of the configuration of a filter circuit according to a first embodiment. Note that, although the diagram shows an example of a configuration in which common mode filters are connected in three stages, the configuration is not necessarily limited to a three-stage connection of common mode filters, and a configuration in which common mode filters are connected in N stages (N is an integer equal to or greater than 1) may also be used.

[0025] In the figure, this common mode filter 100 includes filter circuits F1 to F6. Each of the filter circuits F1 to F6 can have the same configuration. Differential inputs INA and INB are input to the common mode filter 100, and differential outputs OTA and OTB are output from the common mode filter 100. In this case, the common mode filter 100 can attenuate common mode noise contained in the differential inputs INA and INB and output the differential outputs OTA and OTB.

[0026] A filter circuit F3 is connected to the rear of the filter circuit F1, and a filter circuit F5 is connected to the rear of the filter circuit F3. A filter circuit F4 is connected to the rear of the filter circuit F2, and a filter circuit F6 is connected to the rear of the filter circuit F4. The filter circuits F1 and F2 are connected in parallel, the filter circuits F3 and F4 are connected in parallel, and the filter circuits F5 and F6 are connected in parallel. Differential inputs INA and INB are input to the filter circuits F1 and F2, and differential outputs OTA and OTB are output from the filter circuits F5 and F6.

[0027] Each of the filter circuits F1 to F6 includes an inductor L1, L2 and a capacitor C1, C2. The inductors L1, L2 are connected in series. The inductors L1, L2 may have mutual inductance. A capacitor C1 is connected in parallel to the series circuit of the inductors L1, L2. One end of the capacitor C2 is connected to the connection point of the inductors L1, L2. The filter circuits F1, F2 are connected symmetrically via their respective capacitors C2. The filter circuits F3, F4 are connected symmetrically via their respective capacitors C2. The filter circuits F5, F6 are connected symmetrically via their respective capacitors C2. One end of an inductor L0 is connected to the connection point of the capacitors C2 of the filter circuits F1, F2, the connection point of the capacitors C2 of the filter circuits F3, F4, and the connection point of the capacitors C2 of the filter circuits F5, F6. The other end of the inductor L0 may be grounded.

[0028] Here, the capacitor C1 of each filter circuit F1 to F6 can be formed based on the capacitive coupling of inductors L1 and L2. In this case, the capacitor C1 of each filter circuit F1 to F6 can be arranged in the portion adjacent to inductors L1 and L2. For example, the counter electrode of the capacitor C1 of each filter circuit F1 to F6 can be configured by the pattern of each inductor L1 and L2. In this case, the counter electrode of the capacitor C1 of each filter circuit F1 to F6 can be shared with the pattern of the portion adjacent to inductors L1 and L2.

[0029] Here, the conductors of the inductors L1 and L2 may be arranged on different layers so that they partially overlap each other. In this case, the counter electrodes of the capacitor C1 may be arranged on different layers. Alternatively, the conductors of the inductors L1 and L2 may be arranged on the same plane so that they partially adjoin each other. In this case, the counter electrodes of the capacitor C1 may be arranged on the same layer.

[0030] Here, the capacitance value C of the capacitor C1 of each of the filter circuits F1 to F6 is Ｍ The capacitance of the capacitor C1 can be given by the following equation (1):

[0031] C Ｍ = τ / (Z π 2 ) ... (1)

[0032] However, Z ０ is the characteristic impedance. Characteristic impedance Z ０ is an impedance for matching with the differential transmission line on which the common mode filter 100 is mounted. τ can be given by the following equation (2).

[0033] τ=√(((ω1 2 +ω2 2 ) -√(ω1 2 -ω2 2 ) 2 + (πω1ω2) 2 ) / (2ω1 2 ω2 2 (1 / (π 2 -0.25))) ... (2)

[0034] Here, ω1=2πf1, and ω2=2πf2, where f1 and f2 are frequencies that define the attenuation band of the common mode filter 100.

[0035] Here, by forming the capacitor C1 of each of the filter circuits F1 to F6 based on the capacitive coupling of the inductors L1 and L2, it is possible to reduce the area occupied by the capacitor C1 of the common mode filter 100. In this case, the parasitic capacitance of the inductors L1 and L2 of each of the filter circuits F1 to F6 can be allocated to the capacitance of the capacitor C1, and deterioration of the characteristics of the common mode filter 100 due to the parasitic capacitance of the inductors L1 and L2 can be suppressed.

[0036] Furthermore, by configuring the common mode filter 100 based on a multi-stage connection of the filter circuits F1 to F6, it is possible to widen the band in which the group delay is constant. For example, by setting the number of stages of the filter circuits F1 to F6 to N, it is possible to widen the band in which the group delay is constant by N times.

[0037] FIG. 2 is a plan view showing an example layout of a filter circuit according to the first embodiment, FIG. 3 is a perspective view showing an excerpt of a portion of the filter circuit according to the first embodiment, FIG. 4 is a perspective view showing a current path of the filter circuit according to the first embodiment, FIG. 5 is a perspective view showing an example configuration of an inductor of the filter circuit according to the first embodiment, and FIG. 6 is a cross-sectional view showing an example configuration of the filter circuit according to the first embodiment.

[0038] FIG. 2 shows an example layout corresponding to the circuit of FIG. 1. FIGS. 3 and 4 show inductors L1 and L2 and capacitor C1 of filter circuit F1. FIG. 5 shows an example configuration of inductor L0. FIG. 6 shows an example configuration cut along line A1-A2 in FIG. 2. The drawings used in the following explanation may differ in scale and shape from the actual structure to make each configuration easier to understand.

[0039] 2, the common mode filter 100 is formed on a chip 101. As shown in FIG. 6, the chip 101 includes a substrate 120 and a conductor layer 121. The conductor layer 121 is stacked on the substrate 120. The conductor layer 121 is, for example, a three-layer conductor layer. The material of the substrate 120 may be a semiconductor such as Si or GaAs, or an insulator such as glass or ceramic.

[0040] Patterns H1 to H3 are formed on the conductor layer 121. The patterns H1 to H3 can be conductor patterns. The conductor patterns may include wiring patterns. In this case, the patterns H1 to H3 may be composed of wiring. The pattern H1 can be arranged on the first layer of the conductor layer 121, the pattern H2 on the second layer of the conductor layer 121, and the pattern H3 on the third layer of the conductor layer 121. The patterns H1 to H3 can be insulated from each other by the insulating layer 102. The patterns H1 to H3 can be made of a metal such as Al or Cu. The insulating layer 102 can be made of a material such as SiO ２ Inorganic materials such as the following can be used.

[0041] 2, a ground line HG can be formed around the chip 101. A pattern H3 can be used for the ground line HG. The ground line HG can be connected to pad electrodes PD5 to PD8. Each of the pad electrodes PD5 to PD8 can be arranged at one of the four corners of the chip 101.

[0042] The filter circuits F1 to F6 are arranged inside the ground line HG. The same layout pattern can be used for each of the filter circuits F1 to F6. The filter circuits F1 to F6 can be arranged on an XY plane set on the chip 101. The X axis can be set to the horizontal direction of the chip 101, and the Y axis can be set to the vertical direction of the chip 101. The filter circuits F1, F3, and F5 can be arranged as mirror images of the filter circuits F2, F4, and F6. The filter circuits F1, F3, and F5 can be arranged side by side along the X axis, and the filter circuits F2, F4, and F6 can be arranged side by side along the X axis at positions offset in the Y axis direction from the filter circuits F1, F3, and F5. The inductor L0 can be arranged adjacent to the filter circuits F1 and F2.

[0043] In each of the filter circuits F1 to F6, the inductors L1 and L2 and the capacitor C2 can be formed by patterns H1 to H3. In the inductors L1 and L2, the patterns H1 and H2 can be connected to each other via a via VA2, and the patterns H2 and H3 can be connected to each other via a via VA3, as shown in FIG.

[0044] As shown in FIG. 3 , the opposing electrode of capacitor C1 can be formed by a portion of the patterns H1 and H2 used for inductors L1 and L2. The patterns H1 and H2 used for capacitor C1 can be arranged to overlap each other. In this case, the width W1 of the patterns H1 and H2 used for inductors L1 and L2 can be made different from the width W2 of the patterns H1 and H2 used for capacitor C1. By adjusting the width W2 of the patterns H1 and H2 used for capacitor C1, the capacitance value of capacitor C1 can be adjusted while the patterns H1 and H2 are shared by inductors L1 and L2 and capacitor C1.

[0045] As shown in FIGS. 2 and 6 , the capacitor C2 can be formed with patterns H1 and H3 facing the pattern H2. The patterns H1 and H3 used for the capacitor C2 can be shared by six filter circuits F1 to F6. The patterns H1 and H3 used for the capacitor C2 can be solid patterns, and the patterns H1 and H3 can be connected to each other via a via VA1. The pattern H2 used for the capacitor C2 can be separated for each filter circuit F1 to F6. The patterns H1 and H3 used for the capacitor C2 can be shared by the six filter circuits F1 to F6, connecting the capacitors C2 of the filter circuits F1 to F6. The via VA1 can be disposed between the capacitor C2 of each filter circuit F1, F3, and F5 and the capacitor C2 of each filter circuit F2, F4, and F6.

[0046] As shown in Fig. 4a, the current flowing in from pattern H3 of inductors L1 and L2 is guided to pattern H1 via pattern H2. Then, it flows through pattern H1 via the lower electrode of capacitor C1 and is guided to the intermediate electrode of capacitor C2 via pattern H2. Furthermore, as shown in Fig. 4b, the current guided to the intermediate electrode of capacitor C2 is guided to the upper electrode of capacitor C1 via pattern H2 and flows out via pattern H3.

[0047] 2 and 5, the inductor L0 can be formed by patterns H2 and H3. The pattern H3 of the inductor L0 can be separated in the middle, and the separated portion of the pattern H3 can be connected by the pattern H2. The inductor L0 is connected between the ground line HG and the pattern H3 of the capacitor C2 via the pattern H3.

[0048] Also on the chip 101, a pad electrode PD1 is arranged adjacent to the filter circuit F1, a pad electrode PD2 is arranged adjacent to the filter circuit F2, a pad electrode PD3 is arranged adjacent to the filter circuit F5, and a pad electrode PD4 is arranged adjacent to the filter circuit F6. Differential inputs INA and INB are input to the pad electrodes PD1 and PD2, and differential outputs OTA and OTB are output from the pad electrodes PD3 and PD4. Each of the pad electrodes PD1 to PD8 can be arranged on the top layer of the conductor layer 121.

[0049] Here, by integrating the common mode filter 100 on the chip 101, the parasitic components of the common mode filter 100 can be reduced, and the common mode filter 100 can be made to operate at a higher frequency.

[0050] 7 is a diagram showing an example of implementation of a filter circuit according to the first embodiment. In the figure, "a" is a plan view showing the example of implementation of the filter circuit, and "b" is a cross-sectional view showing the example of implementation of the filter circuit. "b" in the figure shows the configuration cut along line B1-B2 in "a" in the figure.

[0051] In the figure, differential transmission lines DA, DB and a ground line GND are formed on a motherboard 110. The differential transmission lines DA, DB are separated in midstream. A chip 101 on which a common mode filter 100 is formed is mounted at the separation point of the differential transmission lines DA, DB. For example, solder balls 111, 112 can be used to join the chip 101 to the motherboard 110. The solder balls 111, 112 can be disposed on pad electrodes PD1, PD3. In this case, the capacitance value of the capacitor C1 can be set to a value that allows differential signals to pass through the differential transmission lines DA, DB and attenuates common mode noise. The motherboard 110 is an example of a circuit board as defined in the claims.

[0052] The differential transmission lines DA and DB may be compatible with LVDS (Low Voltage Differential Signaling). The differential transmission lines DA and DB may be compatible with MIPI (Mobile Industry Processor Interface), HDMI (High Definition Multimedia Interface) (registered trademark), PCIe (Peripheral Component Interconnect Express), or USB (Universal Serial Bus). A chip 101 on which the common mode filter 100 is formed may be mounted in electronic devices such as communication devices, game devices, imaging devices, smartphones, and personal computers.

[0053] As described above, in the first embodiment, the capacitor C1 is formed on the inductors L1 and L2 that are laminated in the common mode filter 100. This allows the parasitic capacitance of the inductors L1 and L2 of the common mode filter 100 to be allocated to the capacitance of the capacitor C1. This makes it possible to reduce the number of capacitance elements mounted on the common mode filter 100 while suppressing narrowing of the bandwidth of the common mode filter 100 due to the parasitic capacitance of the inductors L1 and L2.

[0054] 2. Second Embodiment In the first embodiment described above, the capacitor C1 of the common mode filter 100 is formed in the inductors L1 and L2 formed based on three conductor layers. In this second embodiment, the capacitor of the filter circuit is formed in an inductor formed based on two conductor layers.

[0055] FIG. 8 is a perspective view showing an example of the configuration of the inductors and capacitors of the filter circuit according to the second embodiment.

[0056] In the figure, this filter circuit 200 can be used in place of the inductors L1 and L2 and the capacitor C1 of each of the filter circuits F1 to F6 in the first embodiment described above. The filter circuit 200 includes patterns H1 and H2. The inductors L1 and L2 and the capacitor C1 can be formed by the patterns H1 and H2. The capacitor C1 can be formed by part of the patterns H1 and H2 used for the inductors L1 and L2. The patterns H1 and H2 used for the capacitor C can be arranged to overlap each other. Vias can be used for interlayer connection between the patterns H1 and H2.

[0057] In this way, in the second embodiment described above, the capacitor C1 of the filter circuit 200 is formed on the inductors L1 and L2 formed based on the patterns H1 and H2. This allows the number of layers of the patterns H1 and H2 to be reduced, while also allocating the parasitic capacitance of the inductors L1 and L2 to the capacitance of the capacitor C1.

[0058] 3. Third Embodiment In the second embodiment described above, the capacitor C1 of the filter circuit 200 is formed on the inductors L1 and L2 formed based on the patterns H1 and H2. In this third embodiment, the capacitor C1 of the filter circuit 200 is formed on the inductors L1 and L2 formed based on the patterns H1 and H2, and the width W1 of the patterns H1 and H2 used for the inductors L1 and L2 and the width W2 of the patterns H1 and H2 used for the capacitor C1 are made different from each other.

[0059] FIG. 9 is a perspective view showing an example of the configuration of inductors and capacitors of a filter circuit according to the third embodiment.

[0060] In the figure, this filter circuit 300 has the same configuration as the filter circuit 200, except that the width W1 of the patterns H1 and H2 used for the inductors L1 and L2 in the first embodiment described above is different from the width W2 of the patterns H1 and H2 used for the capacitor C1.

[0061] As described above, in the third embodiment, the capacitor C1 of the filter circuit 200 is formed on the inductors L1 and L2 formed based on the patterns H1 and H2, and the width W1 of the patterns H1 and H2 used for the inductors L1 and L2 is made different from the width W2 of the patterns H1 and H2 used for the capacitor C1. This makes it possible to allocate the parasitic capacitance of the inductors L1 and L2 to the capacitance of the capacitor C1 while reducing the number of layers of the patterns H1 and H2, and also makes it possible to adjust the capacitance value of the capacitor C1 while sharing the patterns H1 and H2 between the inductors L1 and L2 and the capacitor C1.

[0062] 4. Fourth Embodiment In the second embodiment described above, the capacitor C1 of the filter circuit 200 is formed on the inductors L1 and L2 formed based on the patterns H1 and H2. In this fourth embodiment, the inductors L1 and L2 are formed based on the patterns H1 and H2, and the capacitor C1 of the filter circuit 200 is formed based on a part of the pattern H2.

[0063] FIG. 10 is a perspective view illustrating an example of the configuration of the inductors and capacitors of the filter circuit according to the fourth embodiment.

[0064] In the figure, this filter circuit 400 can be used in place of the inductors L1 and L2 and the capacitor C1 of each of the filter circuits F1 to F6 in the first embodiment described above. The filter circuit 400 includes patterns H1 and H2. The inductors L1 and L2 can be formed by the patterns H1 and H2. The capacitor C1 can be formed by a part of the pattern H2 used for the inductors L1 and L2. The patterns H2 used for the capacitor C1 can be separated from each other. In this case, the patterns H2 used for the capacitor C1 can be arranged adjacent to each other on the same plane, with the side surfaces of the patterns H2 facing each other. The separated portions of the patterns H2 can be connected to each other via the pattern H1. Vias can be used for interlayer connection between the patterns H1 and H2.

[0065] As described above, in the fourth embodiment, the inductors L1 and L2 are formed based on the patterns H1 and H2, and the capacitor C1 of the filter circuit 200 is formed based on a portion of the pattern H2. This allows the portion of the inductors L1 and L2 adjacent to the pattern H2 to be used as the capacitor C1 of the filter circuit 200, and makes it possible to reduce the parasitic capacitance of the inductors L1 and L2 while allocating the parasitic capacitance of the inductors L1 and L2 to the capacitance of the capacitor C1.

[0066] 5. Fifth Embodiment In the above-described first embodiment, the filter circuits F1 to F6 used in the common mode filter 100 have the same layout pattern. In this fifth embodiment, the layout pattern of at least one of the plurality of filter circuits used in the common mode filter is made different.

[0067] FIG. 11 is a perspective view illustrating an example of the configuration of the inductors and capacitors of the filter circuit according to the fifth embodiment.

[0068] In the figure, this common mode filter 500 includes filter circuits F1', F2', F5', and F6' instead of the filter circuits F1, F2, F5, and F6 of the common mode filter 100 of the first embodiment described above. Other configurations of the common mode filter 500 of the fifth embodiment are similar to those of the common mode filter 100 of the first embodiment described above.

[0069] The layout patterns of the filter circuits F1', F2', F5', and F6' are different from the layout patterns of the filter circuits F3 and F4, but the layout patterns of the filter circuits F1', F2', F5', and F6' can be the same as each other.

[0070] Each of the filter circuits F1', F2', F5', and F6' includes inductors L1', L2' and a capacitor C1' instead of the inductors L1, L2 and capacitor C1 of the first embodiment. The capacitor C2 can have the same configuration in each of the filter circuits F1', F2', F5', and F6' and in each of the filter circuits F1, F2, F5, and F6.

[0071] In each of the filter circuits F1', F2', F5', and F6', the inductors L1' and L2' can be formed using patterns H1 to H3. The inductors L1' and L2' are connected in series with each other. The inductors L1' and L2' can have mutual inductance. A capacitor C1' is formed in parallel with the series circuit of the inductors L1' and L2'. One end of the capacitor C2 is connected to the connection point of the inductors L1' and L2'.

[0072] The capacitor C1' of each filter circuit F1', F2', F5', and F6' can be formed based on the capacitive coupling of the inductors L1' and L2'. In this case, the opposing electrode of the capacitor C1' of each filter circuit F1', F2', F5', and F6' can be configured using a part of the pattern H1 or H3 of each inductor L1' or L3'. In this case, the patterns H1 and H3 used for the capacitor C1' can be arranged to overlap each other.

[0073] As described above, in the fifth embodiment, the layout patterns of the filter circuits F1', F2', F5', and F6' of the common mode filter 500 are made different from the layout patterns of the filter circuits F3 and F4. This makes it possible to adjust the filter characteristics of the common mode filter 500 while expanding the band over which the group delay of the common mode filter 500 is constant.

[0074] In the above-described fifth embodiment, an example was shown in which the layout patterns of the filter circuits F1', F2', F5', and F6' were made different from the layout patterns of the filter circuits F3 and F4, but the layout patterns of at least one of the multiple filter circuits used in the common mode filter may be made different. For example, the layout pattern of the first-stage filter circuit, the layout pattern of the second-stage filter circuit, and the layout pattern of the third-stage filter circuit of the common mode filter may be made different from one another. In this case, the layout patterns of the filter circuits 200 to 400 of any of the above-described second to fourth embodiments may be used in combination.

[0075] 6. Sixth Embodiment In the first embodiment described above, the capacitor C1 of the common mode filter 100 is formed on the laminated inductors L1 and L2. In this sixth embodiment, the capacitor C1 of the common mode filter 100 is formed on the laminated inductors L1 and L2, and a DC blocking capacitor is integrated on the chip on which the common mode filter 100 is formed.

[0076] FIG. 12 is a circuit diagram showing an example of the configuration of a filter circuit according to the sixth embodiment.

[0077] In the figure, this common mode filter 600 is obtained by adding DC blocking capacitors DCA and DCB to the common mode filter 100 of the first embodiment described above. Other than that, the configuration of the common mode filter 600 of the sixth embodiment is similar to the configuration of the common mode filter 100 of the first embodiment described above.

[0078] The DC blocking capacitors DCA and DCB output differential outputs OTA' and OTB' by cutting out the DC components contained in the differential outputs OTA and OTB of the common mode filter 100. The DC blocking capacitors DCA and DCB can be connected to the subsequent stage of the common mode filter 100. In this case, the DC blocking capacitors DCA and DCB can be connected to the outputs of the filter circuits F5 and F6, respectively.

[0079] 13 is a plan view showing an example of the layout of a filter circuit according to the sixth embodiment, which corresponds to the circuit of FIG.

[0080] In the figure, the common mode filter 100 and DC blocking capacitors DCA and DCB are formed on a chip 601. Each DC blocking capacitor DCA and DCB can be configured with, for example, patterns H2 and H3. In this case, the patterns H2 and H3 can be opposed to each other at the positions of the DC blocking capacitors DCA and DCB. Note that each DC blocking capacitor DCA and DCB may be configured with patterns H1 and H2, or may be configured with patterns H1 and H3. The DC blocking capacitors DCA and DCB can be arranged in mirror symmetry on the chip 601.

[0081] As described above, in the sixth embodiment, the capacitor C1 of the common mode filter 600 is formed in the stacked inductors L1 and L2, and the DC blocking capacitors DCA and DCB are integrated on the chip 601 on which the common mode filter 600 is formed. This eliminates the need to later attach the DC blocking capacitors DCA and DCB to the motherboard on which the chip 601 is mounted, and makes it possible to suppress an increase in the mounting area for the DC blocking capacitors DCA and DCB.

[0082] In the sixth embodiment described above, an example has been shown in which DC blocking capacitors DCA and DCB are added to the common mode filter 100 of the first embodiment described above. In addition to this, any of the filter circuits 200 to 400 of the second to fourth embodiments described above may be applied to the common mode filter 600, or DC blocking capacitors DCA and DCB may be added to the common mode filter 500 of the fifth embodiment described above.

[0083] 7. Seventh Embodiment In the above-described first embodiment, the electrodes of the capacitor C1 are shared by the patterns H1 and H2 of the inductors L1 and L2 of the common mode filter 100. In this seventh embodiment, the electrodes of the capacitor C1 are shared by the patterns H1 and H2 of the inductors L1 and L2 of a single-ended filter.

[0084] FIG. 14 is a circuit diagram showing an example of the configuration of a filter circuit according to the seventh embodiment.

[0085] In the figure, the single-ended filter 700 is obtained by removing the filter circuits F2, F4, and F6 from the common mode filter 100 of the first embodiment described above. The remaining configuration of the single-ended filter 700 of the seventh embodiment is similar to the configuration of the common mode filter 100 of the first embodiment described above.

[0086] A single-ended input INS is input to the single-ended filter 700, and a single-ended output OTS is output from the single-ended filter 700. At this time, the single-ended filter 700 can attenuate noise contained in the single-ended input INS and output the single-ended output OTS. At this time, the common mode filter 100 of the first embodiment described above can be configured by using a pair of single-ended filters 700.

[0087] 15 is a plan view showing an example of the layout of a filter circuit according to the seventh embodiment, which corresponds to the circuit of FIG.

[0088] In the figure, a common mode filter 700 is formed on a chip 701. This chip 701 is obtained by removing the filter circuits F2, F4, and F6 and the pad electrodes PD2 and PD4 from the chip 101 of the first embodiment described above. Other configurations of the chip 701 of the seventh embodiment are similar to those of the chip 101 of the first embodiment described above.

[0089] As described above, in the seventh embodiment, the electrodes of the capacitor C1 are shared by the patterns H1 and H2 of the inductors L1 and L2 of the single-ended filter 700. This allows the parasitic capacitance of the inductors L1 and L2 of the single-ended filter 700 to be allocated to the capacitance of the capacitor C1, and makes it possible to prevent the band of the single-ended filter 700 from becoming narrower due to the parasitic capacitance of the inductors L1 and L2.

[0090] In the seventh embodiment described above, an example has been shown in which the common mode filter 100 of the first embodiment described above is applied to the single-ended filter 700. In addition to this, the filter circuits 200 to 400 of any of the second to fourth embodiments described above may be applied to a single-ended filter, or the common mode filters 500 and 600 of any of the fifth and sixth embodiments described above may be applied to a single-ended filter.

[0091] 8. Application Examples to Mobile Bodies The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may be realized as a device mounted on any type of mobile body, such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, personal mobility, an airplane, a drone, a ship, or a robot.

[0092] FIG. 16 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile object control system to which the technology according to the present disclosure can be applied.

[0093] The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. In the example shown in Fig. 16, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside-vehicle information detection unit 12030, an inside-vehicle information detection unit 12040, and an integrated control unit 12050. Also shown as functional components of the integrated control unit 12050 are a microcomputer 12051, an audio / video output unit 12052, and an in-vehicle network I / F (interface) 12053.

[0094] The drivetrain control unit 12010 controls the operation of devices related to the drivetrain of the vehicle in accordance with various programs. For example, the drivetrain control unit 12010 functions as a control device for a drive force generating device for generating a drive force of the vehicle, such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating a braking force of the vehicle.

[0095] The body system control unit 12020 controls the operation of various devices equipped in the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as headlamps, backup lamps, brake lamps, turn signals, and fog lamps. In this case, radio waves transmitted from a portable device that serves as a key or signals from various switches can be input to the body system control unit 12020. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door lock device, power window device, lamps, etc.

[0096] The outside-vehicle information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the outside-vehicle information detection unit 12030. The outside-vehicle information detection unit 12030 causes the imaging unit 12031 to capture images outside the vehicle and receives the captured images. The outside-vehicle information detection unit 12030 may perform object detection processing or distance detection processing for people, cars, obstacles, signs, characters on the road surface, etc. based on the received images.

[0097] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0098] The in-vehicle information detection unit 12040 detects information inside the vehicle. For example, a driver state detection unit 12041 that detects the state of the driver is connected to the in-vehicle information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 may calculate the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041, or may determine whether the driver is dozing off.

[0099] The microcomputer 12051 can calculate control target values ​​for the driving force generating device, steering mechanism, or braking device based on the information inside and outside the vehicle acquired by the outside-vehicle information detection unit 12030 or the inside-vehicle information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing the functions of an ADAS (Advanced Driver Assistance System), including vehicle collision avoidance or impact mitigation, following driving based on the distance between vehicles, maintaining vehicle speed, vehicle collision warning, vehicle lane departure warning, etc.

[0100] In addition, the microcomputer 12051 can perform cooperative control for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on driver operation, by controlling the driving force generating device, steering mechanism, braking device, etc. based on information about the surroundings of the vehicle obtained by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040.

[0101] Furthermore, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information outside the vehicle acquired by the outside information detection unit 12030. For example, the microcomputer 12051 can control the headlamps according to the position of a preceding vehicle or an oncoming vehicle detected by the outside information detection unit 12030, and perform cooperative control aimed at preventing glare, such as switching from high beams to low beams.

[0102] The audio / video output unit 12052 transmits at least one of audio and video output signals to an output device capable of visually or audibly notifying the passengers of the vehicle or the outside of the vehicle of information. In the example of Fig. 16, the output devices are exemplified by an audio speaker 12061, a display unit 12062, and an instrument panel 12063. The display unit 12062 may include, for example, at least one of an on-board display and a head-up display.

[0103] FIG. 17 is a diagram showing an example of the installation position of the imaging unit 12031.

[0104] In FIG. 17, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.

[0105] The imaging units 12101, 12102, 12103, 12104, and 12105 are provided, for example, at positions such as the front nose, side mirrors, rear bumper, back door, and the top of the windshield inside the vehicle cabin of the vehicle 12100. The imaging unit 12101 provided on the front nose and the imaging unit 12105 provided on the top of the windshield inside the vehicle cabin mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 provided on the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 provided on the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The imaging unit 12105 provided on the top of the windshield inside the vehicle cabin is mainly used to detect preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, etc.

[0106] 17 shows an example of the imaging ranges of the imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of the imaging unit 12104 provided on the rear bumper or back door. For example, by overlaying the image data captured by the imaging units 12101 to 12104, an overhead image of the vehicle 12100 viewed from above can be obtained.

[0107] At least one of the image capturing units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the image capturing units 12101 to 12104 may be a stereo camera made up of multiple image capturing elements, or may be an image capturing element having pixels for phase difference detection.

[0108] For example, based on the distance information obtained from the imaging units 12101 to 12104, the microcomputer 12051 can calculate the distance to each three-dimensional object within the imaging ranges 12111 to 12114 and the change in this distance over time (relative speed with respect to the vehicle 12100), thereby extracting as a preceding vehicle, in particular, the three-dimensional object that is the closest three-dimensional object on the path of the vehicle 12100 and traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (e.g., 0 km / h or higher). Furthermore, the microcomputer 12051 can set a vehicle-to-vehicle distance to be maintained in advance in front of the preceding vehicle, and perform automatic braking control (including follow-up stop control), automatic acceleration control (including follow-up start control), etc. In this way, cooperative control can be performed for the purpose of autonomous driving, which runs autonomously without relying on driver operation.

[0109] For example, the microcomputer 12051 classifies and extracts three-dimensional object data regarding three-dimensional objects into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on distance information obtained from the imaging units 12101 to 12104, and can use the data for automatic obstacle avoidance. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. The microcomputer 12051 then determines a collision risk that indicates the risk of collision with each obstacle, and when the collision risk is equal to or greater than a set value and a collision is possible, the microcomputer 12051 can provide driving assistance for collision avoidance by outputting an alarm to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or avoidance steering via the drive system control unit 12010.

[0110] At least one of the image capturing units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether a pedestrian is present in the images captured by the image capturing units 12101 to 12104. Such pedestrian recognition is performed, for example, by extracting feature points from the images captured by the image capturing units 12101 to 12104 as infrared cameras and performing pattern matching on a series of feature points that indicate the outline of an object to determine whether the object is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the images captured by the image capturing units 12101 to 12104 and recognizes the pedestrian, the audio / image output unit 12052 controls the display unit 12062 to superimpose a rectangular outline on the recognized pedestrian for emphasis. The audio / image output unit 12052 may also control the display unit 12062 to display an icon or the like indicating the pedestrian at a desired position.

[0111] The above describes an example of a vehicle control system to which the technology according to the present disclosure can be applied. Of the above-described configurations, the technology according to the present disclosure can be applied to the communication network 12001, the drive system control unit 12010, the body system control unit 12020, the outside-vehicle information detection unit 12030, the inside-vehicle information detection unit 12040, the integrated control unit 12050, and the image capture unit 12031. Specifically, for example, each filter circuit according to the above-described embodiment can be applied to the communication network 12001, the drive system control unit 12010, the body system control unit 12020, the outside-vehicle information detection unit 12030, the inside-vehicle information detection unit 12040, the integrated control unit 12050, and the image capture unit 12031. By applying the technology disclosed herein to the vehicle control system 12000, it is possible to reduce noise generated in the transmission paths of the communication network 12001, drive system control unit 12010, body system control unit 12020, outside vehicle information detection unit 12030, inside vehicle information detection unit 12040, integrated control unit 12050, and imaging unit 12031.

[0112] Note that the above-described embodiment shows an example for realizing the present technology, and the matters in the embodiment and the matters specifying the invention in the claims correspond to each other. Similarly, the matters specifying the invention in the claims and the matters in the embodiment of the present technology with the same title correspond to each other. However, the present technology is not limited to the embodiment, and can be realized by applying various modifications to the embodiment within the scope of the gist. Furthermore, the effects described in this specification are merely examples and are not limited, and other effects may also be present.

[0113] The present technology may also be configured as follows: (1) A filter circuit comprising: a first inductor; a second inductor arranged adjacent to the first inductor; and a first capacitor whose counter electrode is shared with patterns of adjacent portions of the first inductor and the second inductor. (2) The filter circuit described in (1), in which the counter electrodes of the first capacitor are arranged on the same layer. (3) The filter circuit described in (1), in which the counter electrodes of the first capacitor are arranged on different layers. (4) The filter circuit described in (3), in which the pattern width of a portion used for the counter electrodes of the first inductor and the second inductor is different from the pattern width of a portion not used for the counter electrodes of the first inductor and the second inductor. (5) The filter circuit described in any of (1) to (4), in which the capacitance value of the first capacitor is set to a value that attenuates common-mode noise. (6) The filter circuit described in any of (1) to (5), in which the first capacitor is formed based on capacitive coupling between the first inductor and the second inductor. (7) The filter circuit according to any one of (1) to (6), further comprising: a second capacitor having one end connected to a connection point between the first inductor and the second inductor. (8) The filter circuit according to (7), further comprising: a conductor layer on which the first inductor, the second inductor, the first capacitor, and the second capacitor are formed; and a semiconductor substrate on which the conductor layer is stacked. (9) The filter circuit according to (8), further comprising: a pad electrode connected to one end of a series circuit of the first inductor and the second inductor and disposed on the uppermost layer of the conductor layer. (10) The filter circuit according to any one of (7) to (9), wherein the first inductor, the second inductor, the first capacitor, and the second capacitor form a single-ended filter. (11) The filter circuit according to (10), wherein a common mode filter is formed by a pair of the single-ended filters. (12) The filter circuit according to (11), wherein the common mode filters are connected in N stages (N is an integer equal to or greater than 1).(13) The filter circuit according to any one of (1) to (12), further comprising: a DC-blocking capacitor connected in series to the series circuit of the first inductor and the second inductor. (14) An electronic device comprising: a circuit board on which a transmission line is formed; and a filter circuit formed on the circuit board and connected to the transmission line, the filter circuit comprising: a first inductor; a second inductor arranged adjacent to the first inductor; and a first capacitor whose opposing electrode is shared with patterns of adjacent portions of the first inductor and the second inductor. (15) The electronic device according to (14), wherein the transmission line supports LVDS (Low Voltage Differential Signaling), and the filter circuit is a common mode filter. (16) The filter circuit according to (15), wherein the capacitance value of the first capacitor is set to a value that passes a differential signal in the transmission line and attenuates common mode noise.

[0114] F1 to F6 Filter circuit L0, L1, L2 Inductors C1, C2 Capacitors

Claims

1. A filter circuit comprising: a first inductor; a second inductor arranged adjacent to the first inductor; and a first capacitor whose opposing electrode is shared with the patterns of the first inductor and the adjacent portions of the second inductor.

2. The filter circuit according to claim 1, wherein the opposing electrodes of the first capacitor are arranged on the same layer.

3. The filter circuit according to claim 1, wherein the opposing electrodes of the first capacitors are arranged on different layers.

4. The filter circuit according to claim 3, wherein the pattern width of the portions of the first inductor and the second inductor used for the opposing electrodes is different from the pattern width of the portions of the first inductor and the second inductor not used for the opposing electrodes.

5. The filter circuit according to claim 1, wherein the capacitance value of the first capacitor is set to a value that attenuates common-mode noise.

6. The filter circuit according to claim 1, wherein the first capacitor is formed based on capacitive coupling between the first inductor and the second inductor.

7. The filter circuit according to claim 1, further comprising: a second capacitor having one end connected to the connection point between the first inductor and the second inductor.

8. The filter circuit according to claim 7, comprising: a conductor layer on which the first inductor, the second inductor, the first capacitor, and the second capacitor are formed; and a semiconductor substrate on which the conductor layer is stacked.

9. The filter circuit according to claim 8, further comprising a pad electrode connected to one end of the series circuit of the first inductor and the second inductor and disposed on the uppermost layer of the conductor layer.

10. The filter circuit according to claim 7, wherein the first inductor, the second inductor, the first capacitor, and the second capacitor form a single-ended filter.

11. The filter circuit according to claim 10, wherein the single-ended filter is paired to form a common mode filter.

12. The filter circuit according to claim 11, wherein the common mode filters are connected in N stages (N is an integer of 1 or more).

13. The filter circuit according to claim 1, further comprising a DC blocking capacitor connected in series with the series circuit of the first inductor and the second inductor.

14. An electronic device comprising: a circuit board on which a transmission line is formed; and a filter circuit formed on the circuit board and connected to the transmission line, wherein the filter circuit comprises: a first inductor; a second inductor disposed adjacent to the first inductor; and a first capacitor whose opposing electrode is shared with the patterns of the first inductor and the adjacent portions of the second inductor.

15. The electronic device according to claim 14, wherein the transmission path supports LVDS (Low Voltage Differential Signaling), and the filter circuit is a common mode filter.

16. The electronic device according to claim 15, wherein the capacitance value of the first capacitor is set to a value that allows a differential signal to pass through the transmission path and attenuates common-mode noise.

Images