Semiconductor diode device and manufacturing method for same

Abstract

A semiconductor diode device according to the present invention comprises a guard ring layer positioned at a first surface side of a semiconductor substrate in a terminus region. The p-type impurity concentration in the guard ring layer is distributed so as to have a first curve for which the slope in a logarithmic scale gradually changes from a first surface to a first depth, a second curve for which the slope in the logarithmic scale gradually changes from the first depth to a second depth, which is the bottom of the guard ring layer, and a second inflection point at which the direction of the slope is reversed at the second depth such that the slope straddles the minimum value of the concentration. The terminus of the first curve and a start end of the second curve are connected at the first depth, and the p-type impurity concentration is distributed so as to have a first inflection point at the first depth at which the curves are bent such that the slope of the start end of the second curve becomes smaller than the slope of the terminus of the first curve.

Description

Semiconductor diode device and method of manufacturing the same

[0001] The present disclosure relates to semiconductor diode devices and methods for fabricating the same.

[0002] Japanese Patent No. 6288315 discloses a semiconductor diode device with improved avalanche resistance.

[0003] a second curve whose slope on a logarithmic scale gradually changes from the first depth to a second depth that is the bottom of the guard ring layer; and a second inflection point at which the direction of the slope reverses across a minimum value of the slope at the second depth; an end of the first curve and a start of the second curve are connected at the first depth; and the p-type impurity concentration is distributed so as to have a first inflection point at the first depth where the slope of the second curve at the first depth is smaller than the slope of the first curve at the end of the first curve.

[0004] The method for manufacturing a semiconductor diode device according to the present disclosure is a method for manufacturing a semiconductor diode device having a semiconductor substrate having a first surface and a second surface opposite to the first surface, a termination region surrounding an active region of the semiconductor substrate in a planar view, and a guard ring layer located in the termination region on the first surface side of the semiconductor substrate, the method including: a first impurity implantation step of implanting impurities at a first ion concentration from the first surface into a pattern of the guard ring; and a second impurity implantation step of implanting impurities at a second ion concentration higher than the first ion concentration from the first surface into a region including the guard ring.

[0005] Fig. 1 is a cross-sectional view showing a semiconductor diode device according to an embodiment of the present disclosure; Fig. 2 is a graph showing a concentration profile of an embodiment and a concentration profile of a comparative example showing the relationship between depth and p-type impurity concentration in a guard ring layer and an n-type layer below the guard ring layer; Fig. 3 is a cross-sectional view illustrating the p-type impurity concentration of a guard ring layer; Fig. 4 is a timing chart showing test results of avalanche energy of a semiconductor diode device of a comparative example; Fig. 5 is a timing chart showing test results of avalanche energy of a semiconductor diode device according to an embodiment; Fig. 6 is a process chart showing an example of a method for manufacturing a semiconductor diode device according to an embodiment of the present disclosure.

[0006] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. Hereinafter, the description may be made using the terms "upper-lower direction" and "planar direction," but the directions in the description may differ from the directions when the semiconductor diode device 1 is in use. The "upper" direction corresponds to a direction perpendicular to the second surface 12 of the semiconductor substrate 10 and facing from the second surface 12 toward the first surface 11. The planar direction corresponds to a direction along the second surface 12.

[0007] 1 is a cross-sectional view showing a semiconductor diode device 1 according to an embodiment of the present disclosure. The semiconductor diode device 1 of this embodiment is a planar diode and may be an FRD (Fast Recovery Diode).

[0008] 1 , the semiconductor diode device 1 may include a semiconductor substrate 10 having a first surface 11 and a second surface 12 located opposite to each other, an active region R0 of the semiconductor substrate 10 that acts to pass a forward current and block a reverse current, and a termination region R1 located closer to the periphery of the semiconductor substrate 10 than the active region R0. The active region R0 may be located at the center or a part of the semiconductor substrate 10 when the semiconductor substrate 10 is viewed in a plan view. The termination region R1 may surround the periphery of the active region R0 when the semiconductor substrate 10 is viewed in a plan view.

[0009] The semiconductor substrate 10 may have, from the second surface 12 side, an n+ type layer 24 and an n- type layer 23. Furthermore, the semiconductor substrate 10 may have a p-type anode layer 22 located on the first surface 11 side of the active region R0. The p-type anode layer 22 may include, from above, a p+ type layer 22a and a p- type layer 22b. Furthermore, the semiconductor substrate 10 may include one or more guard ring layers 25 located on the first surface 11 side of the termination region R1.

[0010] Each guard ring layer 25 may have a pattern that surrounds the entire periphery of the active region R0 in a planar view. Each guard ring layer 25 may be spaced apart from the p-type anode layer 22 in the planar direction. Each guard ring layer 25 may be a layer of a p-type semiconductor containing a p-type impurity. The p-type impurity may be boron (B), red phosphorus (P), arsenic (As), antimony (Sb), gallium (Ga), or a mixture of these components.

[0011] The semiconductor substrate 10 may have, on the first surface 11, an oxide film 31, an interlayer insulating film (e.g., NSG: non-doped SiO2) 32, and an anode electrode 33. The oxide film 31 does not have to be located over most of the active region R0 or above the center of each guard ring layer 25. The interlayer insulating film 32 may be located so as to contact the p-type anode layer 22 in the active region R0 and the multiple guard ring layers 25. The anode electrode 33 may be located so as to contact the p-type anode layer 22 through a contact hole in the interlayer insulating film 32.

[0012] A cathode electrode 35 in contact with the n+ type layer 24 may be located on the second surface 12 of the semiconductor substrate 10 .

[0013] The above configuration enables the semiconductor diode device 1 to function as a diode. That is, when a positive voltage is applied between the anode electrode 33 and the cathode electrode 35, a current flows mainly from the p-type anode layer 22 in the active region R0 through the n-type layer 23 and the n+ type layer 24. On the other hand, when a negative voltage is applied between the anode electrode 33 and the cathode electrode 35, a depletion layer is formed between the p-type anode layer 22 in the active region R0 and the guard ring layer 25 in the termination region R1 and the n+ type layer 24, thereby blocking the reverse current.

[0014] <Impurity Concentration in Guard Ring Layer> Figure 2 is a graph of a concentration profile of an embodiment and a comparative example showing the relationship between depth and p-type impurity concentration in the guard ring layer 25 and the underlying n-type layer 23. The graph is on a logarithmic scale, with the p-type impurity concentration represented on the vertical axis and the distance from the first surface 11 to the second surface 12 (referred to as "depth" in the graph) represented on the horizontal axis. Figure 3 is a cross-sectional view illustrating the p-type impurity concentration in the guard ring layer 25. In Figure 3, the p-type impurity concentration in the vertical cross section of the guard ring layer 25 is represented by dashed-dotted contour lines. The concentration profile graph in Figure 2 shows the concentration profile at the center line B0 (see Figure 3) in the vertical cross section of the guard ring layer 25.

[0015] In this embodiment, the p-type impurity concentration in the guard ring layer 25 may be distributed as follows: a first curve 51 whose slope on a logarithmic scale gradually changes from the first surface 11 to the first depth d1; a second curve 52 whose slope on a logarithmic scale gradually changes from the first depth d1 to a second depth d2, which is the bottom of the guard ring layer 25; and a second inflection point 56 where the direction of the slope reverses across a minimum value of the slope at the second depth d2. Furthermore, the end of the first curve 51 and the start of the second curve 52 may be connected at the first depth d1, and the p-type impurity concentration may be distributed as follows: a first inflection point 55 where the slope of the start of the second curve 52 is smaller at the first depth d1 than the slope of the end of the first curve 51. The gradual change in the slope of the first curve 51 may be continuous from the first surface 11, or may include different slope changes within the first surface 11 and its vicinity. The gradual change in the slope of the second curve 52 may be continuous up to the second depth d2, but may include different slope changes in the range at and near the second depth d2.

[0016] The comparative example is a conventional profile in which the concentration of p-type impurities changes gradually from the first surface 11 side to the second depth d2, which is the bottom of the guard ring layer. The p-type impurity concentration curve 80 of the comparative example does not have the first bending point 55 of the present embodiment, and the gradient gradually increases from the first surface 11 side to the second depth d2.

[0017] P-type impurity concentration curve 50 of this embodiment shows that the p-type impurity concentration of guard ring layer 25 decreases sharply with depth in the high-concentration range close to first surface 11 from first surface 11 to the bottom of guard ring layer 25, while the concentration decreases more gradually with depth in the low-concentration range away from first surface 11. Guard ring layer 25 having this p-type impurity concentration can achieve a semiconductor diode device 1 with a greater avalanche resistance than the configuration of the comparative example.

[0018] <Test Results> Figures 4A and 4B are timing charts showing test results of the avalanche energy of the semiconductor diode devices of the comparative example and this embodiment, respectively. The timing charts show the voltage and current waveforms when an upper limit voltage pulse that does not lead to breakdown is applied to the semiconductor diode device. The timing charts were obtained by the following test: A voltage pulse is applied to the semiconductor diode device, and the voltage and current waveforms are recorded. This operation is repeated while gradually increasing the voltage pulse until the semiconductor diode device breaks down. Then, the voltage and current waveforms when the voltage pulse just before breakdown is applied are extracted as the above timing chart.

[0019] The semiconductor diode device of the comparative example was similar to the semiconductor diode device 1 of the embodiment except for the profile of the p-type impurity concentration of the guard ring layer 25. The concentration profile of the comparative example shown in Figure 2 is the concentration profile of the semiconductor diode device of the comparative example. As described above, the p-type impurity concentration of the guard ring layer of the comparative example has a profile in which the gradient gradually increases from the first surface 11 to the bottom of the guard ring layer 25, and does not have the first bending point 55 of the first embodiment.

[0020] The avalanche energy (E ＡＳ 4A, the avalanche energy (E ＡＳ4B, the avalanche resistance of the semiconductor diode device 1 of this embodiment is improved by the p-type impurity concentration profile of the guard ring layer 25.

[0021] <Details of Impurity Concentration in Guard Ring Layer> The first depth d1, at which the first bending point 55 is located in the p-type impurity concentration curve 50 in FIG. 2, may be located at 20% to 75% of the second depth d2 of the guard ring layer 25. By having the first depth d1 located in the above range, the advantage of improved avalanche resistance can also be obtained. The second depth d2 may be located at 25% to 60% of the first depth d1. The second depth d2 may be located at 30% to 50% of the first depth d1.

[0022] In the p-type impurity concentration curve 50 of FIG. 2 , the difference in p-type impurity concentration on a logarithmic scale between the start point of the first curve 51 and the end point of the first curve 51 (corresponding to the length of the vertical axis of the graph in FIG. 2 ) is denoted as L1, and the difference in p-type impurity concentration on a logarithmic scale between the start point of the first curve 51 and the end point of the second curve 52 (corresponding to the length of the vertical axis of the graph in FIG. 2 ) is denoted as L2. L1 / L2 may be 20% to 75%. Having the ratio of the first curve 51 to the second curve 52 on the vertical axis within the above range similarly provides the advantage of improved avalanche resistance. L1 / L2 may be 25% to 60%. L1 / L2 may be 30% to 50%.

[0023] 5 is a process diagram showing an example of a method for manufacturing the semiconductor diode device 1 according to the embodiment of the present disclosure. The semiconductor diode device 1 of this embodiment can be manufactured by the following process. Note that the method shown below is just an example, and the semiconductor diode device 1 of this embodiment may be manufactured by applying various other methods.

[0024] In the manufacturing method of this embodiment, first, a semiconductor substrate 62 is implanted with n-type impurities and has an oxide film 61 formed on a first surface 71 and a second surface 72. A pattern formation and etching process is then performed on the first surface 71 side of the semiconductor substrate 62. This process removes a portion of the oxide film 61 on the first surface 71 side so as to expose a portion of the first region 63 located in the active region R0 on the first surface 71 side and a portion of the second region 64 located in the termination region R1. The first region 63 is a region where the p-type anode layer 22 is to be formed, and the second region 64 corresponds to a region where the guard ring layer 25 is to be formed.

[0025] 5, a first ion implantation of p-type impurities is performed from the first surface 71 side of the semiconductor substrate 62. By the ion implantation, p-type impurities are implanted into the first region 63 and the second region 64. The first ion implantation is performed, for example, at 30 keV and 3×10 １３ Boron (B) is implanted at a concentration of 1 / cm. After the ion implantation, a heat treatment is performed to thermally diffuse the p-type impurity. Step J1 corresponds to an example of a first impurity implantation step of the present disclosure.

[0026] Next, as shown in step J2, a second ion implantation of p-type impurities is performed on the semiconductor substrate 62 from the first surface 71 side. By the ion implantation, p-type impurities are again implanted into the first region 63 and the second region 64 into which the p-type impurities have already been implanted in step J1. The second ion implantation is performed, for example, at 70 keV and 2×10 １５ Boron (B) is implanted at a concentration of 1 / cm. The second ion implantation may be performed only on the second region 64 out of the first region 63 and the second region 64. Step J2 corresponds to an example of a second impurity implantation step of the present disclosure.

[0027] The concentration of the second ion implantation may be 10 times or more the concentration of the first ion implantation. By these two ion implantations, a guard ring layer 25 having the aforementioned p-type impurity concentration profile is formed in the second region 64. Furthermore, by the single ion implantation in step J1 or the two ion implantations in steps J1 and J2, a p-type anode layer 22 is formed in the first region 63.

[0028] The profile of the p-type impurity concentration of the guard ring layer 25 in the comparative example shown in FIG. 2 is formed by omitting the second ion implantation in this embodiment.

[0029] Next, as shown in step J3, NSG (Non-doped Silicate Glass) or SiO ２ An insulating material such as SiO 2 is deposited, and then annealed to form an interlayer insulating film 65 on the oxide film 61 on the first surface 71 side and on the exposed portions of the first region 63 and the second region 64 .

[0030] Next, as shown in step J4, a mask is formed on the first surface 71 side, and etching is performed on both the first surface 71 side and the second surface 72 side to remove the peripheral portion of the oxide film 61 on the first surface 71 side, the peripheral portion of the interlayer insulating film 65, and the oxide film 61 on the second surface 72 side.

[0031] Subsequently, as shown in step J5, the second surface 72 side of the semiconductor substrate 62 is ground by grinding and spin etching, thereby reducing the semiconductor substrate 62 to a predetermined thickness.

[0032] Subsequently, as shown in step J6, phosphorus is deposited and heat treated to form n+ type layers 66 and 67 on a part of the first surface 71 and the second surface 72 of the semiconductor substrate 62.

[0033] Next, although not shown, a contact window is formed in part of the interlayer insulating film 65 on the first surface 71 side, and the anode electrode 33 (see FIG. 1) is formed so as to contact the first region 63 through the contact window. Furthermore, the cathode electrode 35 (see FIG. 1) is formed so as to contact the n+ type layer on the second surface 72 side.

[0034] The semiconductor diode device 1 of this embodiment can be manufactured by the manufacturing method described above.

[0035] Although the embodiments of the present disclosure have been described above, the semiconductor diode device and the manufacturing method thereof of the present disclosure are not limited to the above embodiments, and the details shown in the embodiments can be modified as appropriate without departing from the spirit of the invention.

[0036] An embodiment of the present disclosure is described below. In the embodiment, (1) a semiconductor diode device includes: a semiconductor substrate having a first surface and a second surface opposite to the first surface; an termination region surrounding an active region on the semiconductor substrate in a plan view; and a guard ring layer located in the termination region on the first surface side of the semiconductor substrate, wherein the p-type impurity concentration in the guard ring layer is distributed so as to have a first curve whose slope on a logarithmic scale gradually changes from the first surface to a first depth; a second curve whose slope on a logarithmic scale gradually changes from the first depth to a second depth that is a bottom of the guard ring layer; and a second inflection point at which the direction of the slope reverses across a minimum value of the concentration at the second depth, an end of the first curve and a start of the second curve are connected at the first depth, and the p-type impurity concentration is distributed so as to have a first inflection point at the first depth where the slope of the starting point of the second curve is smaller than the slope of the ending point of the first curve.

[0037] (2) In the semiconductor diode device of (1) above, the first depth is located at 20% to 75% of the second depth.

[0038] (3) In the semiconductor diode device of (1) or (2) above, when the difference in p-type impurity concentration on a logarithmic scale between the start point of the first curve and the end point of the first curve is denoted as L1 and the difference in p-type impurity concentration on a logarithmic scale between the start point of the first curve and the end point of the second curve is denoted as L2, L1 / L2 is 25% to 75%.

[0039] (4) The semiconductor diode device according to any one of (1) to (3) above is a fast recovery diode.

[0040] In one embodiment, (5) a method for manufacturing a semiconductor diode device is a method for manufacturing a semiconductor diode device having a semiconductor substrate having a first surface and a second surface opposite to the first surface, a termination region surrounding an active region of the semiconductor substrate in a planar view, and a guard ring layer located on the first surface side of the semiconductor substrate in the termination region, the method including: a first impurity implantation step of implanting impurities at a first ion concentration into a pattern of the guard ring layer from the first surface; and a second impurity implantation step of implanting impurities at a second ion concentration higher than the first ion concentration into the pattern of the guard ring layer from the first surface.

[0041] The present disclosure can be used for a semiconductor diode device and a method for manufacturing the same.

[0042] 1 Semiconductor diode device 10 Semiconductor substrate 11 First surface 12 Second surface 22 P-type anode layer 23 N-type layer 24 N+ type layer 25 Guard ring layer 31 Oxide film 32 Interlayer insulating film 33 Anode electrode 35 Cathode electrode 50 P-type impurity concentration curve 51 First curve 52 Second curve 55 First bending point 56 Second bending point J1 Process (first impurity implantation process) J2 Process (second impurity implantation process) R0 Active region R1 Termination region

Claims

1. A semiconductor diode device comprising: a semiconductor substrate having a first surface and a second surface opposite to the first surface; an termination region surrounding an active region on the semiconductor substrate in a planar view; and a guard ring layer located in the termination region on the side of the semiconductor substrate facing the first surface, wherein the p-type impurity concentration in the guard ring layer is distributed so as to have a first curve whose slope on a logarithmic scale gradually changes from the first surface to a first depth; a second curve whose slope on a logarithmic scale gradually changes from the first depth to a second depth which is the bottom of the guard ring layer; and a second inflection point at which the direction of the slope reverses across a minimum value of the concentration at the second depth; the end of the first curve and the start of the second curve are connected at the first depth; and the p-type impurity concentration is distributed so as to have a first inflection point at the first depth where the slope of the start of the second curve is smaller than the slope of the end of the first curve.

2. The semiconductor diode device of claim 1, wherein the first depth is located at 20% to 75% of the second depth.

3. The semiconductor diode device according to claim 1 or 2, wherein, when the difference in p-type impurity concentration on a logarithmic scale between the start point of the first curve and the end point of the first curve is denoted as L1, and the difference in p-type impurity concentration on a logarithmic scale between the start point of the first curve and the end point of the second curve is denoted as L2, L1 / L2 is 25% to 75%.

4. The semiconductor diode device according to any one of claims 1 to 3, which is a fast recovery diode.

5. A method for manufacturing a semiconductor diode device having a semiconductor substrate having a first surface and a second surface opposite to the first surface, a termination region surrounding an active region of the semiconductor substrate in a planar view, and a guard ring layer located in the termination region on the first surface side of the semiconductor substrate, the method comprising: a first impurity implantation step of implanting an impurity at a first ion concentration into a pattern of the guard ring layer from the first surface; and a second impurity implantation step of implanting an impurity at a second ion concentration higher than the first ion concentration into the pattern of the guard ring layer from the first surface.

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