Beamformer integrated circuit and phased array antenna module

Abstract

A beamformer integrated circuit (10) comprises: a memory (13) that stores an intensity setting value that defines the intensity adjustment amount of a high-frequency signal that is a signal to be supplied to each of a plurality of antenna elements (21) or a signal to be supplied from each of the plurality of antenna elements (21); and an analog circuit unit (12) that performs attenuation and amplification of the high-frequency signal on the basis of the intensity setting value stored in the memory (13).

Description

Beamformer integrated circuit and phased array antenna module

[0001] This disclosure relates to a beamformer integrated circuit and a phased array antenna module. This application claims priority to Japanese Patent Application No. 2024-084351, filed May 23, 2024, the contents of which are incorporated herein by reference.

[0002] A phased array antenna is an antenna that can freely change its beam pattern (antenna directivity) by adjusting at least one of the strength and phase of a signal (transmitted signal) supplied to a plurality of antenna elements or a signal (received signal) supplied from a plurality of antenna elements. In recent years, such phased array antennas have been used in various fields, including the automotive and communications fields.

[0003] A phased array antenna module is a module that includes multiple antenna elements and a beamformer integrated circuit. The beamformer integrated circuit includes multiple phase shifters corresponding to the multiple antenna elements and a circuit for setting phase shift amounts for the multiple phase shifters. In addition, the beamformer integrated circuit may also include intensity controllers corresponding to the multiple antenna elements. A required beam pattern is formed by setting appropriate settings for the phase shifters and intensity controllers and adjusting the phases and intensities of multiple signals supplied from (or to) the multiple antenna elements. For details of conventional phased array antenna modules, see, for example, Patent Documents 1 to 3 listed below.

[0004] US Patent Application Publication No. 2023 / 0282976 US Patent No. 8,774,737 US Patent No. 1,112,8041

[0005] In conventional beamformer integrated circuits, a variable gain amplifier (VGA) is mainly used as the intensity controller. To precisely form an arbitrary beam pattern, a wide dynamic range and fine intensity setting resolution are required, but there are limitations to what a variable gain amplifier alone can achieve.

[0006] The present disclosure has been made in consideration of the above circumstances, and aims to provide a beamformer integrated circuit and a phased array antenna module that can form any beam pattern more precisely than ever before.

[0007] In order to solve the above problem, a beamformer integrated circuit (10) according to a first aspect of the present disclosure comprises a memory (13) that stores an intensity setting value that specifies the amount of intensity adjustment of a high-frequency signal that is a signal supplied to a plurality of antenna elements (21) or a signal supplied from a plurality of the antenna elements, and a circuit unit (12) that attenuates and amplifies the high-frequency signal based on the intensity setting value stored in the memory.

[0008] In a beamformer integrated circuit according to a first aspect of the present disclosure, a memory stores intensity setting values ​​that define the intensity adjustment amount of the high-frequency signals that are supplied to or from multiple antenna elements. Then, based on the intensity setting values ​​stored in the memory, the signals that are supplied to or from the multiple antenna elements are attenuated and amplified. This makes it possible to achieve a wide dynamic range and fine resolution in beamforming, thereby enabling more precise formation of any beam pattern than ever before.

[0009] Furthermore, a beamformer integrated circuit according to a second aspect of the present disclosure is a beamformer integrated circuit according to the first aspect of the present disclosure, wherein the circuit section comprises a variable gain amplifier (63, 69) that amplifies the high-frequency signal based on the intensity setting value stored in the memory, and a variable attenuator (64, 70) that attenuates the high-frequency signal based on the intensity setting value stored in the memory.

[0010] Furthermore, a beamformer integrated circuit according to a third aspect of the present disclosure is a beamformer integrated circuit according to the second aspect of the present disclosure, wherein the upper bits of the intensity setting value are a first setting value that specifies the attenuation rate of the variable attenuator, and the lower bits of the intensity setting value are a second setting value that specifies the amplification rate of the variable gain amplifier.

[0011] Furthermore, a beamformer integrated circuit according to a fourth aspect of the present disclosure is a beamformer integrated circuit according to the third aspect of the present disclosure, which includes a conversion circuit (15, 16) that converts the first setting value into a control value for controlling the variable attenuator.

[0012] Furthermore, a beamformer integrated circuit according to a fifth aspect of the present disclosure is a beamformer integrated circuit according to the fourth aspect of the present disclosure, wherein the number of bits of the control value is 3 or more, the number of bits of the first setting value is 2 or more, and the number of bits of the first setting value is less than the number of bits of the control value.

[0013] Furthermore, a beamformer integrated circuit according to a sixth aspect of the present disclosure is a beamformer integrated circuit according to any one of the first to fifth aspects of the present disclosure, wherein the memory further stores a phase shift amount setting value that specifies the phase shift amount of the high-frequency signal, and the circuit unit further includes a phase shifter (61) that adjusts the phase shift amount of the high-frequency signal based on the phase shift amount setting value stored in the memory.

[0014] Furthermore, in a beamformer integrated circuit according to a seventh aspect of the present disclosure, in the beamformer integrated circuit according to the sixth aspect of the present disclosure, the intensity setting value and the phase shift setting value are set in combination according to the beam pattern to be controlled, and the memory stores beam tables (BT, BT1) in which multiple combinations of the intensity setting value and the phase shift setting value are stored.

[0015] A phased array antenna module (1) according to an eighth aspect of the present disclosure comprises a plurality of antenna elements (21) and a beamformer integrated circuit (10) according to any one of the first to seventh aspects of the present disclosure connected to the plurality of antenna elements.

[0016] According to the present disclosure, there is an effect that any beam pattern can be formed more precisely than before.

[0017] FIG. 1 is a system configuration diagram showing the configuration of a phased array antenna module according to a first embodiment of the present disclosure. FIG. 2 is a block diagram showing the configuration of a main part of a beamformer integrated circuit according to the first embodiment of the present disclosure. FIG. 3 is a diagram showing the connection relationship between a digital circuit unit and an analog circuit unit provided in the RF front end of the beamformer integrated circuit according to the first embodiment of the present disclosure. FIG. 4 is a diagram for explaining a beam table used in the first embodiment of the present disclosure. FIG. 5 is a diagram for explaining a beam pattern setting method according to the first embodiment of the present disclosure. FIG. 6 is a diagram showing intensity control characteristics in a transmit path of the beamformer integrated circuit according to the first embodiment of the present disclosure. FIG. 7 is a diagram showing intensity control characteristics in a receive path of the beamformer integrated circuit according to the first embodiment of the present disclosure. FIG. 8 is a diagram for explaining a beam table used in a second embodiment of the present disclosure. FIG. 9 is a diagram for explaining a beam pattern setting method according to the second embodiment of the present disclosure. FIG. 10 is a diagram showing intensity control characteristics in a transmit path of the beamformer integrated circuit according to the second embodiment of the present disclosure. FIG. 11 is a diagram showing intensity control characteristics in a receive path of the beamformer integrated circuit according to the second embodiment of the present disclosure. FIG. 12 is a diagram showing intensity control characteristics in a transmit path of a beamformer integrated circuit according to a comparative example.

[0018] Hereinafter, beamformer integrated circuits and phased array antenna modules according to embodiments of the present disclosure will be described in detail with reference to the drawings.

[0019] A phased array antenna module according to a first embodiment of the present disclosure is provided in, for example, a wireless communication device that uses millimeter waves and is capable of beamforming, which allows the beam pattern to be freely changed. The phased array antenna module includes, for example, a plurality of integrated circuits (ICs) mounted on one side of a substrate such as a known printed circuit board, and an antenna array mounted on the other side.

[0020] The integrated circuits and antenna array constituting the phased array antenna module are formed using known materials and methods. Furthermore, the electrical connection structures between the integrated circuits and between the integrated circuits and the antenna array are not particularly limited. Known connection structures may be used as the electrical connection structures.

[0021] 1 is a system configuration diagram showing the configuration of a phased array antenna module according to a first embodiment of the present disclosure. As shown in Fig. 1, the phased array antenna module 1 includes eight beamformer integrated circuits 10A, 10B, 10C, 10D, 10E, 10F, 10G, and 10H (hereinafter referred to as beamformer integrated circuits 10A to 10H), an antenna array 20, a frequency conversion integrated circuit 30, and an RF signal coupler / splitter 40.

[0022] The phased array antenna module 1 is connected to the control device 50 via a signal line 51, a control line 52, and a power line 53. An RF signal at an IF (intermediate frequency) signal frequency is transmitted and received between the control device 50 and the phased array antenna module 1 via the signal line 51. Communication messages related to control are transmitted and received between the control device 50 and the phased array antenna module 1 via the control line 52. Power is supplied from the control device 50 to the phased array antenna module 1 via the power line 53.

[0023] The beamformer integrated circuits 10A to 10H are integrated circuits that control the beam pattern of the antenna array 20. A plurality of antenna elements 21 that constitute the antenna array 20 are connected to each of the beamformer integrated circuits 10A to 10H. For example, eight antenna elements 21 for horizontal polarization and eight antenna elements 21 for vertical polarization are connected to each of the beamformer integrated circuits 10A to 10H. In other words, the antenna array 20 is composed of a total of 128 antenna elements 21, including 64 antenna elements 21 for horizontal polarization and 64 antenna elements 21 for vertical polarization. The beamformer integrated circuits 10A to 10H will be described in detail later.

[0024] The frequency conversion integrated circuit 30 is an integrated circuit that performs frequency conversion between an RF signal at an IF signal frequency and an RF signal at a frequency that is transmitted and received by the beamformer integrated circuits 10A to 10H and the antenna array 20.

[0025] The RF signal coupler / splitter 40 distributes the RF signal output from the frequency conversion integrated circuit 30 to each of the beamformer integrated circuits 10A to 10H. The RF signal coupler / splitter 40 also combines the RF signals received by each of the beamformer integrated circuits 10A to 10H and inputs the combined signals to the frequency conversion integrated circuit 30.

[0026] <Beamformer Integrated Circuit> Figure 2 is a block diagram showing the configuration of the main parts of a beamformer integrated circuit according to the first embodiment of the present disclosure. The eight beamformer integrated circuits 10A to 10H have the same configuration. Therefore, in the following description, only one of the beamformer integrated circuits 10A to 10H, i.e., the beamformer integrated circuit 10, may be described. Description of the other seven beamformer integrated circuits may be omitted.

[0027] The beamformer integrated circuit 10 includes 16 RF front ends (RFFEs) 5A to 5P, a digital circuit 6, an analog circuit 7, and an RF signal coupler / splitter 8. The 16 RF front ends 5A to 5P have the same configuration. Therefore, in the following description, one of the 16 RF front ends 5A to 5P, i.e., the RF front end 5, may be described. Description of the other 15 RF front ends may be omitted.

[0028] 2, each of the 16 RF front ends 5A to 5P is connected to each of the 16 antenna elements 21A to 21P so that there is a one-to-one correspondence between one antenna element 21 and one RF front end 5. Of the 16 RF front ends 5A to 5P and the 16 antenna elements 21A to 21P, eight RF front ends (e.g., RF front ends 5A to 5H) and eight antenna elements (e.g., antenna elements 21A to 21H) are for horizontal polarization, and the remaining eight RF front ends (e.g., RF front ends 5I to 5P) and eight antenna elements (e.g., antenna elements 21I to 21P) are for vertical polarization.

[0029] The 16 antenna elements 21A to 21P have the same or similar configurations. Therefore, in the following description, one of the 16 antenna elements 21A to 21P, i.e., antenna element 21, may be described. Description of the other 15 antenna elements may be omitted. The antenna elements 21A to 21P may have the same configuration. Regarding the configuration of each of the antenna elements 21A to 21P, the configuration of the antenna element for horizontal polarization and the configuration of the antenna element for vertical polarization may be slightly different.

[0030] In this way, in one beamformer integrated circuit 10, each of the 16 RF front ends 5A to 5P is connected to each of the 16 antenna elements 21A to 21P in a one-to-one correspondence. Therefore, in the entire phased array antenna module 1 having eight beamformer integrated circuits 10A to 10H, each of the 128 antenna elements 21 constituting the antenna array 20 is connected to each of the 16 RF front ends 5A to 5P in each of the eight beamformer integrated circuits 10A to 10H.

[0031] The 128 antenna elements 21 that make up the antenna array 20 are divided into 64 antenna elements 21 that transmit and receive horizontally polarized radio waves and 64 antenna elements 21 that transmit and receive vertically polarized radio waves. The eight beamformer integrated circuits 10A-10H control the transmission and reception of horizontally polarized radio waves in the 64 antenna elements 21, and also control the transmission and reception of vertically polarized radio waves in the 64 antenna elements 21. For each of the horizontally polarized radio waves and vertically polarized radio waves, the beamformer integrated circuits 10A-10H set the phase and intensity of each of the 64 antenna elements so that the direction of the composite radio waves transmitted or received from the 64 antenna elements 21 is a predetermined direction.

[0032] 2, the RF front end 5 includes a digital circuit unit 11 and an analog circuit unit 12 (circuit unit). The digital circuit unit 11 transmits and receives control-related communication messages to and from the control device 50 via the control line 52 shown in FIG. 1. The digital circuit unit 11 controls the RF front end 5 based on the communication messages transmitted from the control device 50.

[0033] In this embodiment, communication messages related to control are transmitted and received between the phased array antenna module 1 and the control device 50 through parallel communication. That is, the digital circuit unit 11 transmits and receives communication messages related to control with the control device 50 through parallel communication. Note that the communication between the phased array antenna module 1 and the control device 50 is not limited to parallel communication. It may be serial communication such as SPI (Serial Peripheral Interface) or I2C (Inter-Integrated Circuit).

[0034] The digital circuit unit 11 is connected to the digital circuit 6 by wiring (not shown) inside the beamformer integrated circuit 10. The digital circuit 6 relays communication between the digital circuit unit 11 and the control device 50. Alternatively, the digital circuit 6 communicates with the digital circuit unit 11 based on the contents of a communication message transmitted from the control device 50.

[0035] Each communication transaction sent from the control device 50 to the phased array antenna module 1 includes additional information, a command, and data. The communication transaction has a fixed bit length. The command is a register address when instructing writing to or reading from a register. Alternatively, the command is a numerical value indicating an operation instruction to the beamformer integrated circuit 10 or the RF front end 5. The command and data have a fixed length. In this embodiment, the command is 8 bits and the data is 16 bits.

[0036] The digital circuit unit 11 includes a memory 13 that is a storage area for storing a beam table BT (see FIG. 4) used for beamforming. The beam table BT is a lookup table that stores a plurality of combinations of phase-shift setting values ​​and intensity setting values ​​that are set according to the beam pattern of the antenna array 20 to be controlled. In this embodiment, a beam table (a beam table with 1024 items) that defines 1024 combinations of phase-shift setting values ​​and intensity setting values ​​is stored in the memory 13. The beam table BT is written to or read from the memory 13 using a 10-bit address. Details of the beam table BT will be described later.

[0037] The memory 13 is realized using, for example, a static random access memory (SRAM). Although it is preferable that the memory 13 be realized using an SRAM, the memory 13 may also be realized using a register, a dynamic random access memory (DRAM), a flash memory, or a read only memory (ROM).

[0038] The analog circuit unit 12 is a circuit that outputs an RF signal to the antenna element 21 connected to the RF front end 5 and receives an RF signal output from the antenna element 21. Under the control of the digital circuit unit 11, the analog circuit unit 12 adjusts the phase and intensity of the RF signal transmitted and received by the antenna element 21 connected to the RF front end 5.

[0039] The analog circuit unit 12 is connected to the analog circuit 7 via an RF signal coupler / splitter 8. The RF signal coupler / splitter 8 distributes the RF signal output from the analog circuit 7 to the analog circuit units 12 provided in each of the RF front ends 5A to 5P. The RF signal coupler / splitter 8 also combines the RF signals output from the analog circuit units 12 provided in each of the RF front ends 5A to 5H and outputs the combined signal to the analog circuit 7.

[0040] As shown in FIG. 2 , the analog circuit unit 12 includes a phase shifter (PS) 61, a changeover switch (SW) 62, a variable gain amplifier (VGA) 63, a variable attenuator (ATT) 64, a phase inverter (PI) 65, a power amplifier (PA) 66, a changeover switch (SW) 67, a low noise amplifier (LNA) 68, a variable gain amplifier (VGA) 69, a variable attenuator (ATT) 70, and a phase inverter (PI) 71.

[0041] The variable gain amplifier 63, variable attenuator 64, phase inverter 65, and power amplifier 66 are provided on the transmission path R1, while the low-noise amplifier 68, variable gain amplifier 69, variable attenuator 70, and phase inverter 71 are provided on the reception path R2. The transmission path R1 is a path through which an RF signal (high-frequency signal) output to the antenna element 21 passes, and the reception path R2 is a path through which an RF signal (high-frequency signal) input from the antenna element 21 passes. The changeover switches 62 and 67 switch between connecting the transmission path R1 or the reception path R2 between the phase shifter 61 and the antenna element 21 at specified time intervals. This allows the phased array antenna module 1 to transmit and receive high-frequency signals as a time-division multiplexing system.

[0042] The phase shifter 61 adjusts the phase shift of the RF signal passing through the transmission path R1 or the RF signal passing through the reception path R2 in accordance with the phase shift setting value of the beam table BT read from the memory 13 of the digital circuit unit 11. In other words, the phase shifter 61 is provided in common to the transmission path R1 and the reception path R2. Note that the phase shifter 61 common to the transmission path R1 and the reception path R2 may be omitted, and a phase shifter may be provided separately for the transmission path R1 and the reception path R2.

[0043] The variable gain amplifier 63 amplifies the RF signal passing through the transmission path R1 in accordance with the intensity setting value of the beam table BT read from the memory 13. The variable attenuator 64 attenuates the RF signal passing through the transmission path R1 in accordance with the intensity setting value of the beam table BT read from the memory 13. The phase inverter 65 inverts the phase of the RF signal passing through the transmission path R1 in accordance with the phase shift setting value of the beam table BT read from the memory 13. The power amplifier 66 amplifies the RF signal passing through the transmission path R1 by a predetermined amplification factor. By adjusting the phase shift and intensity of the RF signal passing through the transmission path R1, the beam pattern of the radio waves transmitted from the phased array antenna module 1 can be changed.

[0044] The low-noise amplifier 68 amplifies the RF signal output from the selector switch 67 at a predetermined gain. The variable gain amplifier 69 amplifies the RF signal passing through the receiving path R2 in accordance with the intensity setting value of the beam table BT read from the memory 13. The variable attenuator 70 attenuates the RF signal passing through the receiving path R2 in accordance with the intensity setting value of the beam table BT read from the memory 13. The phase inverter 71 inverts the phase of the RF signal passing through the receiving path R2 in accordance with the phase shift setting value of the beam table BT read from the memory 13. By adjusting the phase shift and intensity of the RF signal passing through the receiving path R2, the beam pattern of the radio waves received by the phased array antenna module 1 can be changed.

[0045] 3 is a diagram showing the connection relationship between a digital circuit unit and an analog circuit unit provided in the RF front end of the beamformer integrated circuit according to the first embodiment of the present disclosure. As shown in FIG. 3, the phase shifter 61, variable gain amplifiers 63 and 69, variable attenuators 64 and 70, and phase inverters 65 and 71 provided in the analog circuit unit 12 are controlled according to the contents of the beam table BT stored in the memory 13. In contrast, the selector switches 62 and 67, power amplifier 66, and low-noise amplifier 68 provided in the analog circuit unit 12 are controlled by logic circuits (not shown), such as registers, provided in the digital circuit unit 11.

[0046] 3 , the digital circuit unit 11 includes, in addition to the memory 13, an expansion circuit 14, a conversion circuit 15, and a conversion circuit 16. The expansion circuit 14 expands the bit string of the phase-shift amount setting value of the beam table BT read from the memory 13 into a bit string of a control value (phase-shifter control value) for controlling the phase shifter 61. For example, the expansion circuit 14 expands a bit string of 6 bits of the 7-bit phase-shift amount setting value into a bit string of a 52-bit control value. The remaining 1 bit of the phase-shift amount setting value is used to control the phase inverters 65 and 71. As will be described in detail later, the number of bits of the phase-shift amount setting value is set according to the resolution of the phase shift amount, and the number of bits of the control value is set according to the number of division units constituting the phase shifter 61.

[0047] The conversion circuit 15 converts a portion of the intensity setting value of the beam table BT read from the memory 13 into a control value (attenuation rate control value) for controlling the variable attenuator 64. The conversion circuit 16 converts a portion of the intensity setting value of the beam table BT read from the memory 13 into a control value (attenuation rate control value) for controlling the variable attenuator 70. Note that, as will be described in detail later, the upper bits of the intensity setting value of the beam table BT read from the memory 13 are attenuation rate setting values ​​(first setting values) that define the attenuation rates of the variable attenuators 64 and 70, and the lower bits are amplification rate setting values ​​(second setting values) that define the amplification rates of the variable gain amplifiers 63 and 69. The conversion circuits 15 and 16 convert the upper bits of the intensity setting value of the beam table BT read from the memory 13 into control values ​​(attenuation rate control values) that control the variable attenuators 64 and 70.

[0048] The conversion circuits 15 and 16 are, for example, logic circuits that convert the upper bits of the intensity setting value of the beam table BT read from the memory 13 into a control value (attenuation rate control value) for controlling the variable attenuators 64 and 70. The conversion circuits 15 and 16 may be circuits that perform the conversion using a lookup table stored in a memory or a register. Alternatively, the conversion circuits 15 and 16 may store the correspondence between the upper bits of the intensity setting value and the control value of the variable attenuators 64 and 70 in a register and use a method of selecting between them using conditional branching or the like. There are no particular limitations on the implementation method of the conversion circuits 15 and 16, and any implementation method may be used.

[0049] <Beam Table> Fig. 4 is a diagram for explaining the beam table used in the first embodiment of the present disclosure. Note that Fig. 4 shows the beam table BT stored in the memory 13, in association with a parameter P1 for specifying an address in the memory 13 and a parameter P2 for specifying a beam pattern.

[0050] 4, the beam table BT stored in the memory 13 defines 1024 combinations of phase-shift setting values ​​and intensity setting values ​​(a beam table with 1024 items). For example, a phase-shift setting value indicated as "RFFE00Phase0000" and an intensity setting value indicated as "RFFE00Gain0000" are stored at address "0" of the memory 13. Also, a phase-shift setting value indicated as "RFFE00Phase1023" and an intensity setting value indicated as "RFFE00Gain1023" are stored at address "1023" of the memory 13.

[0051] 4, the phase shift amount setting value is 7 bits, and the intensity setting value is 8 bits. That is, 15 bits of information are stored in each address of the memory 13. Of the 7 bits of the phase shift amount setting value, the most significant bit (MSB) is used to control the phase inverters 65 and 71, and the remaining 6 bits are used to control the phase shifter 61.

[0052] When the most significant bit of the phase shift amount setting value is "1", phase inversion is instructed to the phase inverters 65 and 71. This corresponds to setting a phase shift amount of 180 degrees. The lowest 6 bits of the phase shift amount setting value are used to specify which of the 52 divided units constituting the phase shifter 61 should have its state changed. When the value of the lowest 6 bits of the phase shift amount setting value is "0", all of the 52 divided units constituting the phase shifter 61 are in the reference state. When the value is "1" to "52", the divided units corresponding to that value are set to the phase-shifted state. Note that when the value of the lowest 6 bits of the phase shift amount setting value is "52", all of the 52 divided units constituting the phase shifter 61 are set to the phase-shifted state. In other words, when the phase shifter 61 is composed of 52 divided units, the phase shift state of the phase shifter 61 can be set to 53 stages.

[0053] The phase shifter 61 is designed so that the phase shift amount exceeds 180 degrees when all 52 divided units are set to a phase-shifted state in the frequency range used by the phased array antenna module 1. Note that, in this embodiment, a configuration is described as an example in which the phase shift amount of the RF signal passing through the transmission path R1 or the reception path R2 is adjusted by combining the phase inverters 65, 71 with the phase shifter 61 capable of setting a phase shift amount exceeding 180 degrees, but this configuration is not limited to this. A configuration may also be used in which only a phase shifter capable of setting a phase shift amount exceeding 360 degrees is used without using the phase inverters 65, 71.

[0054] As described above, the least significant 6 bits of the phase shift amount setting value are expanded by the expansion circuit 14 shown in Fig. 3 into a bit string (52 bits) of a control value (phase shifter control value) for controlling the phase shifter 61. That is, the least significant 6 bits of the phase shift amount setting value are expanded into a bit string having the same number of bits as the number of division units constituting the phase shifter 61. The number of division units constituting the phase shifter 61 is not limited to 52, and any number may be used.

[0055] Of the eight bits of the intensity setting value, the most significant three bits are an attenuation factor setting value (first setting value) that defines the attenuation factor of the variable attenuators 64 and 70, and the remaining least significant five bits are an amplification factor setting value (second setting value) that defines the amplification factor of the variable gain amplifiers 63 and 69. In this embodiment, the variable attenuators 64 and 70 have a wide dynamic range, and the variable gain amplifiers 63 and 69 have fine resolution, and the most significant three bits of the intensity setting value are assigned to the variable attenuators 64 and 70, and the least significant five bits are assigned to the variable gain amplifiers 63 and 69. This makes it possible to design an intensity setting device that has a good balance between a wide dynamic range and fine resolution, and that is suitable for wideband communications with little wavelength dependency and little amplification distortion.

[0056] Alternatively, the upper three bits of the intensity setting value may be assigned to the variable gain amplifiers 63, 69, and the lower five bits to the variable attenuators 64, 70. However, it is not easy to design variable gain amplifiers 63, 69 that have a wide dynamic range and small wavelength dependency and amplification distortion. Furthermore, if variable attenuators 64, 70 are designed with fine resolution and a narrow dynamic range, the characteristics of the variable attenuators 64, 70 cannot be fully utilized. For this reason, it is desirable to assign the upper three bits of the intensity setting value to the variable attenuators 64, 70, and the lower five bits to the variable gain amplifiers 63, 69.

[0057] The attenuation rate setting value of the upper three bits of the eight bits of the intensity setting value is defined, for example, as "7" for maximum signal strength (minimum attenuation rate) and "0" for minimum signal strength (maximum attenuation rate. As described above, this attenuation rate setting value is converted into a control value (attenuation rate control value) for controlling the variable attenuators 64 and 70 by the conversion circuits 15 and 16 shown in FIG. 3.

[0058] <Beam Pattern Setting Method> FIG. 5 is a diagram for explaining a beam pattern setting method according to the first embodiment of the present disclosure.

[0059] <<First Step>> In the first step S11, the control device 50 transmits a communication message having a fixed bit length to the phased array antenna module 1 via the control line 52 in a communication transaction specifying a beam index. This communication message includes a command indicating beam selection and data specifying the beam index. In the examples shown in Figures 4 and 5, the data specifying the beam index is a numerical value ranging from "0" to "1023," and this numerical value is used to specify an address in the memory 13.

[0060] The communication message transmitted from the control device 50 to the phased array antenna module 1 via the control line 52 is input to the beamformer integrated circuit 10 shown in Fig. 2. Then, in the beamformer integrated circuit 10, the communication message is input to the digital circuit section 11 of the RF front end 5 via the digital circuit 6.

[0061] In the second step S12, the digital circuit unit 11 of the RF front end 5 reads the beam table BT from the memory 13 based on the contents of the communication message transmitted from the control device 50. Specifically, the digital circuit unit 11 uses the beam index included in the communication message as a read address, and reads the 15-bit data DT stored at that address.

[0062] 5, the 15-bit data DT read from the memory 13 includes a 7-bit phase shift amount setting value and an 8-bit intensity setting value. The 7-bit phase shift amount setting value includes a 1-bit phase inverter setting value and a 6-bit phase shifter setting value. The 8-bit intensity setting value includes a 3-bit attenuation rate setting value and a 5-bit amplification rate setting value.

[0063] <<Third Step>> In the third step S13, the conversion circuit 15 or the conversion circuit 16 shown in FIG. 3 converts the 3-bit attenuation factor setting value read out in the second step into a 3-bit control value (attenuation factor control value) for controlling the variable attenuator 64 or the variable attenuator 70.

[0064] <<Fourth Step>> In the fourth step S14, the digital circuit unit 11 converts the setting values ​​read out in the second step, except for the 3-bit attenuation rate setting value, into control values ​​and outputs them to the analog circuit unit 12. Specifically, the digital circuit unit 11 outputs the 1-bit phase inverter setting value read out in the second step as a 1-bit phase inverter control value to the phase inverter 65 or the phase inverter 71. The expansion circuit 14 of the digital circuit unit 11 expands the 6-bit phase shifter setting value into a 52-bit phase shifter control value and outputs it to the phase shifter 61. The digital circuit unit 11 also converts the 5-bit gain setting value into a 5-bit gain control value and outputs it to the variable gain amplifier 63 or the variable gain amplifier 69. In this way, the beam pattern of the phased array antenna module 1 is set.

[0065] In this embodiment, the variable gain amplifiers 63 and 69 are designed so that when the gain setting value is "0," the gain is minimum, and when the gain setting value is "31," the gain is maximum. Therefore, the 5-bit gain setting value is output as is as the gain control value to the variable gain amplifier 63 or the variable gain amplifier 69. If the magnitude relationship between the gain setting values ​​for the variable gain amplifiers 63 and 69 and the magnitude relationship between the gain control values ​​do not correspond, the variable gain amplifiers 63 and 69 may also be provided with a logic circuit that converts the gain setting value into the gain control value, as with the variable attenuators 64 and 70.

[0066] Fig. 6 is a diagram showing the intensity control characteristics in the transmit path of the beamformer integrated circuit according to the first embodiment of the present disclosure. Fig. 7 is a diagram showing the intensity control characteristics in the receive path of the beamformer integrated circuit according to the first embodiment of the present disclosure. The graphs shown in Figs. 6 and 7 have the intensity setting value on the horizontal axis and the relative signal intensity on the vertical axis. The intensity control characteristics shown in Figs. 6 and 7 are simulation results when the frequency of the RF signals passing through the transmit path R1 and the receive path R2 of the beamformer integrated circuit 10 is 38 GHz.

[0067] 6, in the transmission path R1, the correspondence relationship between the attenuation rate setting value and the attenuation rate control value is set as follows: Attenuation rate setting value "7"...attenuation rate control value "1" (binary notation "001") Attenuation rate setting value "6"...attenuation rate control value "3" (binary notation "011") Attenuation rate setting value "5"...attenuation rate control value "5" (binary notation "101") Attenuation rate setting value "4"...attenuation rate control value "7" (binary notation "111") Attenuation rate setting value "3"...attenuation rate control value "2" (binary notation "010") Attenuation rate setting value "2"...attenuation rate control value "6" (binary notation "110") Attenuation rate setting value "1"...attenuation rate control value "4" (binary notation "100")

[0068] 7, in the reception path R2, the correspondence relationship between the attenuation rate setting value and the attenuation rate control value is set as follows: Attenuation rate setting value "7"...attenuation rate control value "1" (binary notation "001") Attenuation rate setting value "6"...attenuation rate control value "3" (binary notation "011") Attenuation rate setting value "5"...attenuation rate control value "5" (binary notation "101") Attenuation rate setting value "4"...attenuation rate control value "7" (binary notation "111") Attenuation rate setting value "3"...attenuation rate control value "2" (binary notation "010") Attenuation rate setting value "2"...attenuation rate control value "4" (binary notation "100") Attenuation rate setting value "1"...attenuation rate control value "6" (binary notation "110")

[0069] The correspondence relationship between the attenuation factor setting value and the attenuation factor control value in the transmission path R1 differs from the correspondence relationship between the attenuation factor setting value and the attenuation factor control value in the reception path R2 in that the attenuation factor control value corresponding to the attenuation factor setting value "2" is reversed from the attenuation factor control value corresponding to the attenuation factor setting value "1." Note that, in both the transmission path R1 and the reception path R2, an attenuation factor control value of "0" (binary notation "000") is not used for the variable attenuators 64, 70 due to impedance matching issues.

[0070] An unused attenuation rate control value of "0" (binary notation "000") corresponds to an attenuation rate setting value of "0", and therefore valid intensity setting values ​​are "32" to "255", as shown in Figs. 6 and 7. The relative signal strength on the vertical axis is an intensity based on the intensity of the RF signal output from the RF front end 5 when the intensity setting value is set to "255". In the examples shown in Figs. 6 and 7, when the intensity setting value is set to "255", the intensity of the RF signal output from the RF front end 5 is 0 dB.

[0071] As shown in Figure 6, in the transmission path R1, when the intensity setting value is "32," the signal intensity reaches its minimum of -33.4 dB. In other words, the dynamic range in the transmission path R1 is 33.4 dB, which is a wide dynamic range that could not be achieved with conventional technology. Furthermore, it can be seen that the resolution is sufficiently small, at 0.17 dB or less, in the high-power range where the relative signal intensity is 0 to -5 dB.

[0072] 6, there are regions where the magnitude relationship between the intensity setting value and the relative signal strength is reversed before and after the attenuation rate control value is changed. For example, this occurs when the intensity setting value is changed from "63" to "64," when the intensity setting value is changed from "95" to "96," when the intensity setting value is changed from "127" to "128," and so on. However, beamforming can generally be used without any problems. Note that when creating a beam table, it is sufficient to consider the intensity setting value so that reversal does not occur in the reversed region.

[0073] As shown in Figure 7, when the intensity setting value is "32" for the receiving path R2, the signal intensity reaches its minimum of -29.2 dB. In other words, the dynamic range for the receiving path R2 is 29.2 dB, which is a wide dynamic range that would not be possible with conventional technology. Furthermore, the resolution is sufficiently small, at 0.18 dB or less, in the high-power range where the relative signal intensity is 0 to -5 dB.

[0074] 7, there are areas where the magnitude relationship between the intensity setting value and the relative signal strength is reversed before and after the attenuation rate control value is changed, as in Fig. 6. However, the beamforming can generally be used without any problems, and it is sufficient to take care to set the intensity setting value so that the reversal does not occur in the reversed areas when creating the beam table.

[0075] As described above, in this embodiment, intensity setting values ​​that define the intensity of the RF signals supplied from the transmission path R1 to the plurality of antenna elements 21 or the RF signals supplied from the plurality of antenna elements 21 to the reception path R2 are stored in the memory 13, and the RF signals are attenuated and amplified by the analog circuit unit 12 based on the intensity setting values ​​stored in the memory 13. Specifically, a variable gain amplifier 63 and a variable attenuator 64 are provided in the transmission path R1, and a variable gain amplifier 69 and a variable attenuator 70 are provided in the reception path R2 to attenuate and amplify the RF signals. This makes it possible to achieve a wide dynamic range and finer resolution in beamforming, and to form any beam pattern more precisely than ever before.

[0076] In this embodiment, the attenuation factor setting values ​​of the variable attenuators 64 and 70 are stored as part of the beam table BT, enabling high-speed beamforming. Furthermore, since the upper bits of the intensity setting value are used as the attenuation factor setting value and the lower bits are used as the amplification factor setting value, a well-balanced dynamic range and resolution can be achieved. Furthermore, the conversion circuits 15 and 16 can easily convert the attenuation factor setting value into the attenuation factor control value.

[0077] Second Embodiment Next, a second embodiment of the present disclosure will be described. The phased array antenna module and beamformer integrated circuit of this embodiment have substantially the same configurations as the phased array antenna module 1 of the first embodiment shown in Fig. 1 and the beamformer integrated circuit 10 shown in Fig. 2, but the beam table BT stored in the memory 13 is slightly different. The following mainly describes the differences from the first embodiment.

[0078] <Beam Table> Fig. 8 is a diagram for explaining a beam table used in the second embodiment of the present disclosure. Note that Fig. 8, like Fig. 4, shows a beam table BT1 stored in the memory 13, in association with a parameter P1 for specifying an address in the memory 13 and a parameter P2 for specifying a beam pattern.

[0079] As shown in Fig. 8, the beam table BT1 used in this embodiment, like the beam table BT in the first embodiment, defines 1024 combinations of phase shift amount setting values ​​and intensity setting values ​​(a beam table with 1024 items). In the beam table BT shown in Fig. 4, the phase shift amount setting values ​​stored in each address of the memory 13 are 7 bits and the intensity setting values ​​are 8 bits. In contrast, the beam table BT1 used in this embodiment differs from the beam table BT shown in Fig. 4 in that both the phase shift amount setting values ​​and the intensity setting values ​​stored in each address of the memory 13 are 7 bits.

[0080] In this embodiment, the number of bits of the intensity setting value is smaller than in the first embodiment, so the capacity of the beam table BT1 can be made smaller than the capacity of the beam table BT. This reduces the capacity of the memory 13 required to store the beam table BT1, and reduces the cost of the beamformer integrated circuit 10.

[0081] In this embodiment, the phase shift amount set values ​​stored in each address of the memory 13 are the same as those stored in each address of the memory 13 in the first embodiment. That is, of the seven bits of the phase shift amount set value, the most significant bit (MSB) is used to control the phase inverters 65 and 71, and the remaining six bits are used to control the phase shifter 61.

[0082] In contrast, in this embodiment, the number of bits of the intensity setting value is reduced to 7 bits, and therefore, of the 7 bits of the intensity setting value, the most significant 2 bits are used as an attenuation factor setting value (first setting value) that defines the attenuation factor of the variable attenuators 64 and 70. The least significant 5 bits (amplification factor setting value) of the intensity setting value in this embodiment are the same as those in the first embodiment.

[0083] In this embodiment, as in the first embodiment, the most significant bits (the most significant two bits) of the intensity setting value are assigned to the variable attenuators 64 and 70, and the least significant five bits are assigned to the variable gain amplifiers 63 and 69. This allows a well-balanced design between a wide dynamic range and fine resolution, and also makes it possible to configure an intensity setting device that is suitable for wideband communications with little wavelength dependency and little amplification distortion.

[0084] The attenuation rate setting value, which is the two most significant bits of the seven bits of the intensity setting value, is defined as, for example, "3" for maximum signal strength (minimum attenuation rate) and "0" for minimum signal strength (maximum attenuation rate. As in the first embodiment, this attenuation rate setting value is converted into a control value (attenuation rate control value) for controlling the variable attenuators 64 and 70 by the conversion circuits 15 and 16 shown in FIG. 3.

[0085] <Beam Pattern Setting Method> Fig. 9 is a diagram for explaining a beam pattern setting method according to the second embodiment of the present disclosure. As shown in Fig. 9, in this embodiment, the first step S11 to the fourth step S14 are also performed to set the beam pattern of the phased array antenna module 1.

[0086] <<First Step>> In the first step S11, similar to the first embodiment, the control device 50 transmits a communication message having a fixed bit length to the phased array antenna module 1 via the control line 52 in a communication transaction that specifies a beam index.

[0087] <<Second Step>> In the second step S12, the digital circuit unit 11 of the RF front end 5 uses the beam index included in the communication message as a read address and reads out the 14-bit data DT1 stored at that address.

[0088] 9, the 14-bit data DT read from the memory 13 includes a 7-bit phase shift amount setting value and a 7-bit intensity setting value. The 7-bit phase shift amount setting value includes a 1-bit phase inverter setting value and a 6-bit phase shifter setting value. The 7-bit intensity setting value includes a 2-bit attenuation factor setting value and a 5-bit amplification factor setting value.

[0089] 3 converts the 2-bit attenuation factor setting value read out in the second step into a 3-bit control value (attenuation factor control value) for controlling the variable attenuator 64 or 70. In this manner, in this embodiment, the number of bits of the attenuation factor control value is 3 or more, the number of bits of the attenuation factor setting value (first setting value) is 2 or more, and the number of bits of the attenuation factor setting value is less than the number of bits of the attenuation factor control value.

[0090] <<Fourth Step>> In the fourth step S14, similarly to the first embodiment, the digital circuit unit 11 outputs the 1-bit phase inverter setting value read out in the second step as a 1-bit phase inverter control value to the phase inverter 65 or the phase inverter 71. Furthermore, the expansion circuit 14 of the digital circuit unit 11 expands the 6-bit phase shifter setting value into a 52-bit phase shifter control value and outputs it to the phase shifter 61. Furthermore, the digital circuit unit 11 converts the 5-bit gain setting value into a 5-bit gain control value and outputs it to the variable gain amplifier 63 or the variable gain amplifier 69. In this way, the beam pattern of the phased array antenna module 1 is set.

[0091] FIG. 10 is a diagram showing the intensity control characteristics of the transmit path R1 of the beamformer integrated circuit according to the second embodiment of the present disclosure. Also, FIG. 11 is a diagram showing the intensity control characteristics of the receive path R2 of the beamformer integrated circuit according to the second embodiment of the present disclosure. Note that, like the graphs shown in FIGS. 6 and 7 , the graphs shown in FIGS. 10 and 11 have the intensity setting value on the horizontal axis and the relative signal intensity on the vertical axis. Also, like the intensity control characteristics shown in FIGS. 6 and 7 , the intensity control characteristics shown in FIGS. 10 and 11 are simulation results for the case where the frequency of the RF signal passing through the transmit path R1 and the receive path R2 of the beamformer integrated circuit 10 is 38 GHz.

[0092] 10, in the transmission path R1, the correspondence relationship between the attenuation rate setting value and the attenuation rate control value is set as follows: Attenuation rate setting value "3"...attenuation rate control value "1" (binary notation "001") Attenuation rate setting value "2"...attenuation rate control value "5" (binary notation "101") Attenuation rate setting value "1"...attenuation rate control value "2" (binary notation "010") Attenuation rate setting value "0"...attenuation rate control value "4" (binary notation "100")

[0093] 11, in the receiving path R2, the correspondence relationship between the attenuation rate setting value and the attenuation rate control value is set as follows: Attenuation rate setting value "3"...attenuation rate control value "1" (binary notation "001") Attenuation rate setting value "2"...attenuation rate control value "5" (binary notation "101") Attenuation rate setting value "1"...attenuation rate control value "2" (binary notation "010") Attenuation rate setting value "0"...attenuation rate control value "6" (binary notation "110")

[0094] The correspondence relationship between the attenuation factor setting value and the attenuation factor control value in the transmission path R1 differs from the correspondence relationship between the attenuation factor setting value and the attenuation factor control value in the reception path R2 in that the attenuation factor control value corresponding to the attenuation factor setting value "0" is different. Also, in the first embodiment, as shown in Figures 6 and 7, valid intensity setting values ​​were "32" to "255", but in this embodiment, as shown in Figures 10 and 11, valid intensity setting values ​​are "0" to "127". In the example shown in Figures 10 and 11, when the intensity setting value is set to "127", the intensity of the RF signal output from the RF front end 5 is 0 dB.

[0095] As shown in FIG. 10 , in the transmission path R1, when the intensity setting value is "0," the signal intensity is at its minimum of -33.4 dB. That is, the dynamic range in the transmission path R1 is 33.4 dB, as in the first embodiment. Also, as in the first embodiment, the resolution is 0.17 dB or less in the high-power range where the relative signal intensity is 0 to -5 dB. As shown in FIG. 11 , in the reception path R2, when the intensity setting value is "0," the signal intensity is at its minimum of -29.2 dB. That is, the dynamic range in the reception path R2 is 29.2 dB, as in the first embodiment. Also, as in the first embodiment, the resolution is 0.18 dB or less in the high-power range where the relative signal intensity is 0 to -5 dB.

[0096] 10 and 11 with those of FIGS. 6 and 7, it can be seen that in this embodiment, there is almost no region in which the magnitude relationship between the intensity setting value and the relative signal strength is reversed before and after the attenuation rate control value is changed. For example, in the graph shown in FIG. 10, when the intensity setting value is changed from "63" to "64," the magnitude relationship between the intensity setting value and the relative signal strength is only slightly reversed. Furthermore, in the graph shown in FIG. 11, when the intensity setting value is changed from "31" to "32" and when the intensity setting value is changed from "95" to "96," the magnitude relationship between the intensity setting value and the relative signal strength is only slightly reversed.

[0097] As described above, in this embodiment as well, an intensity setting value that defines the intensity of the RF signal supplied from the transmission path R1 to the plurality of antenna elements 21 or the RF signal supplied from the plurality of antenna elements 21 to the reception path R2 is stored in the memory 13, and the RF signal is attenuated and amplified by the analog circuit unit 12 based on the intensity setting value stored in the memory 13. Specifically, a variable gain amplifier 63 and a variable attenuator 64 are provided in the transmission path R1, and a variable gain amplifier 69 and a variable attenuator 70 are provided in the reception path R2 to attenuate and amplify the RF signal. This makes it possible to achieve a wide dynamic range and finer resolution in beamforming, and to form any beam pattern more precisely than before.

[0098] In this embodiment, the attenuation factor setting values ​​of the variable attenuators 64 and 70 are stored as part of the beam table BT, enabling high-speed beamforming. Furthermore, since the upper bits of the intensity setting value are used as the attenuation factor setting value and the lower bits are used as the amplification factor setting value, a well-balanced dynamic range and resolution can be achieved. Furthermore, the conversion circuits 15 and 16 can easily convert the attenuation factor setting value into the attenuation factor control value.

[0099] Additionally, in this embodiment, the capacity of the beam table BT1 can be made smaller than that of the beam table BT in the first embodiment, which reduces the capacity of the memory 13 required to store the beam table BT1 and reduces the cost of the beamformer integrated circuit 10.

[0100] Furthermore, the area of ​​the SRAM required to store the beam table BT1 shown in Figure 8 is smaller than the area of ​​the SRAM required to store the beam table BT shown in Figure 4. For example, in an SRAM IP of a 130 nm semiconductor process, the area of ​​the SRAM required to store the beam table BT1 is 6% smaller than the area of ​​the SRAM required to store the beam table BT. This makes it possible to reduce the overall size of the chip and reduce costs.

[0101] [Comparative Example] The inventors of the present application also conducted a simulation of a comparative example to confirm the effects of the beamformer integrated circuit 10 according to the first and second embodiments. In the comparative example, the variable attenuator 64 and the variable attenuator 70 of the beamformer integrated circuit 10 shown in FIG. 2 are omitted. That is, the beamformer integrated circuit 10 according to the first and second embodiments is configured such that the variable gain amplifier 63 and the variable attenuator 64 are provided in the transmission path R1, and the variable gain amplifier 69 and the variable attenuator 70 are provided in the reception path R2 to attenuate and amplify the RF signal. In contrast, the comparative example is configured such that the variable gain amplifier 63 is provided in the transmission path R1, and the variable gain amplifier 69 is provided in the reception path R2 to amplify only the RF signal.

[0102] In the comparative example, similar to the first embodiment, the phase shift amount setting value is 7 bits and the intensity setting value is 8 bits. That is, 15 bits of information are stored in each address of the memory 13. However, unlike the first embodiment, in the comparative example, all 8 bits of the intensity setting value are used as the amplification factor setting value that defines the amplification factor of the variable gain amplifiers 63 and 69.

[0103] FIG. 12 is a diagram showing the intensity control characteristics of the transmit path of the beamformer integrated circuit according to the comparative example. In the comparative example, the intensity setting value is 8 bits, allowing for precise setting of the intensity setting value, thereby enabling precise control of the gain of the variable gain amplifier 63. However, in the comparative example, since the variable gain amplifier 63 simply amplifies the RF signal, the dynamic range is insufficient at 7.5 dB, as shown in FIG. 12 . Furthermore, even if the design of the variable gain amplifier 63 in the comparative example is modified to expand the dynamic range, it is difficult to achieve 20 dB. Furthermore, such a design modification results in coarse resolution. In contrast, in the first and second embodiments, as shown in FIGS. 6 and 10 , a wide dynamic range of 33.4 dB is achieved, demonstrating significantly superior results compared to the comparative example.

[0104] Although the beamformer integrated circuit and the phased array antenna module according to the embodiments of the present disclosure have been described above, the present disclosure is not limited to the above embodiments and can be freely modified within the scope of the present disclosure. For example, the phased array antenna module described in the above embodiments is for a time division multiplexing system. However, the phased array antenna module of the present disclosure may be for a frequency division multiplexing system.

[0105] In the above-described embodiment, an example has been described in which one antenna element 21 is connected to one RF front end 5 in a one-to-one correspondence. However, in the present disclosure, two front ends may be connected to a dual-polarized antenna element having a connection terminal for horizontal polarization and a connection terminal for vertical polarization.

[0106] In the above-described embodiment, the beamformer integrated circuit 10 includes a memory 13 that stores an intensity setting value that specifies the intensity adjustment amount of a high-frequency signal that is a signal supplied to or from a plurality of antenna elements 21, and an analog circuit unit 12 (circuit unit) that attenuates and amplifies the high-frequency signal based on the intensity setting value stored in the memory 13.

[0107] In addition, in the beamformer integrated circuit 10, the analog circuit unit 12 includes a variable gain amplifier (e.g., variable gain amplifiers 63, 69) that amplifies the high-frequency signal based on the intensity setting value stored in the memory 13, and a variable attenuator (e.g., variable attenuator 64, 70) that attenuates the high-frequency signal based on the intensity setting value stored in the memory 13.

[0108] Furthermore, in the beamformer integrated circuit 10, the upper bits of the intensity setting value are a first setting value that specifies the attenuation rate of the variable attenuator, and the lower bits of the intensity setting value are a second setting value that specifies the amplification rate of the variable gain amplifier.

[0109] The beamformer integrated circuit 10 also includes a conversion circuit (for example, conversion circuits 15 and 16) that converts the first setting value into a control value for controlling the variable attenuator.

[0110] In addition, in the beamformer integrated circuit 10, the number of bits of the control value is 3 bits or more, the number of bits of the first setting value is 2 bits or more, and the number of bits of the first setting value is less than the number of bits of the control value.

[0111] In addition, in the beamformer integrated circuit 10, the memory 13 further stores a phase shift amount setting value that defines the phase shift amount of the high-frequency signal, and the analog circuit unit 12 further includes a phase shifter 61 that adjusts the phase shift amount of the high-frequency signal based on the phase shift amount setting value stored in the memory 13.

[0112] In addition, in the beamformer integrated circuit 10, the intensity setting value and the phase shift setting value are set in combination according to the beam pattern to be controlled, and the memory 13 stores a beam table (e.g., beam table BT, BT1) in which multiple combinations of the intensity setting value and the phase shift setting value are stored.

[0113] In the above-described embodiment, the phased array antenna module 1 includes a plurality of antenna elements 21 and a beamformer integrated circuit 10 connected to the plurality of antenna elements 21 .

[0114] 1...phased array antenna module, 10...beam former integrated circuit, 12...analog circuit section (circuit section), 13...memory, 15, 16...conversion circuit, 21...antenna element, 61...phase shifter, 63, 69...variable gain amplifier, 64, 70...variable attenuator, BT, BT1...beam table

Claims

1. A beamformer integrated circuit comprising: a memory that stores intensity setting values ​​that define the intensity adjustment amount of a high-frequency signal that is a signal supplied to a plurality of antenna elements or a signal supplied from a plurality of said antenna elements; and a circuit unit that attenuates and amplifies said high-frequency signal based on said intensity setting values ​​stored in said memory.

2. A beamformer integrated circuit according to claim 1, wherein the circuit section comprises: a variable gain amplifier that amplifies the high frequency signal based on the intensity setting value stored in the memory; and a variable attenuator that attenuates the high frequency signal based on the intensity setting value stored in the memory.

3. The beamformer integrated circuit according to claim 2, wherein the most significant bits of the intensity setting value are a first setting value that defines the attenuation rate of the variable attenuator, and the least significant bits of the intensity setting value are a second setting value that defines the amplification rate of the variable gain amplifier.

4. The beamformer integrated circuit according to claim 3, further comprising a conversion circuit for converting said first setting value into a control value for controlling said variable attenuator.

5. The beamformer integrated circuit according to claim 4, wherein the number of bits of the control value is 3 or more, and the number of bits of the first setting value is 2 or more, and the number of bits of the first setting value is less than the number of bits of the control value.

6. A beamformer integrated circuit as claimed in any one of claims 1 to 5, wherein the memory further stores a phase shift amount setting value that defines the phase shift amount of the high frequency signal, and the circuit section further comprises a phase shifter that adjusts the phase shift amount of the high frequency signal based on the phase shift amount setting value stored in the memory.

7. A beamformer integrated circuit as claimed in claim 6, wherein the intensity setting value and the phase shift setting value are set in combination according to the beam pattern to be controlled, and the memory stores a beam table in which a plurality of combinations of the intensity setting value and the phase shift setting value are stored.

8. A phased array antenna module comprising: a plurality of antenna elements; and a beamformer integrated circuit according to any one of claims 1 to 7 connected to the plurality of antenna elements.

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