Embedded flash memory device of single poly structure, manufacturing method therefor, and neuromorphic hardware device using same

Abstract

According to an embodiment of the present application, provided are an embedded flash memory device of a single poly structure, a manufacturing method therefor, and a neuromorphic hardware device using same. The embedded flash memory device includes a plurality of unit memory cells. Each unit memory cell includes: a coupling transistor including a source region and a drain region which are connected to a word line, and a floating gate region; and a read-out transistor which includes a source region connected to a source line and a drain region connected to a bit line, and shares, with the coupling transistor, the floating gate region, and the coupling transistor and the read-out transistor may be configured in a gated-p-i-n diode structure.

Description

Embedded flash memory device with single poly structure, method for manufacturing the same, and neuromorphic hardware device using the same

[0001] The present application relates to an embedded flash memory device having a single poly structure, a method for manufacturing the same, and a neuromorphic hardware device using the same.

[0002] With the rapid advancement of artificial intelligence technologies like deep learning, computational processing and data demands are rapidly increasing. For example, the number of parameters and layers required to operate neural networks, essential for implementing artificial intelligence, are rapidly increasing.

[0003] To handle massive data processing workloads, product development has been steadily progressing on high-speed memory devices such as SRAM and HBM (High Bandwidth Memory). However, SRAM and HBM are volatile memories, which lead to power consumption and wasted operating time due to additional refresh operations. Consequently, demand for memory devices with non-volatile characteristics and extremely high bandwidth is continuously increasing.

[0004] Recently, an embedded flash implemented using five transistors (5T) has been proposed (S. Song, J. Kim, and CH Kim, "Program / erase speed, endurance, retention, disturbance characteristics of single-poly embedded flash cells," in Proc. IEEE Int. Reliability Physics Symp., 2013, pp. MY.4.1-MY4.6).

[0005] Specifically, this embedded flash implements a floating gate using a single poly-gate structure, and fabricates a non-volatile embedded flash using a total of five transistors: a read-out transistor, two coupling transistors, and two additional transistors for tunneling operation.

[0006] This embedded flash has the advantage of being applicable to automotive semiconductors and artificial intelligence implementations by utilizing existing CMOS processes, but it has the disadvantage of requiring a very high voltage supply because it performs programming / erasing using tunneling operations, and it has the problem of occupying a very large area per device because it uses five transistors, one of which is a very large coupling transistor. In addition, there is also the disadvantage of making large-area, low-power neuromorphic operation difficult due to the generation of high read current.

[0007] The purpose of this application is to provide an embedded flash memory device having a single poly structure, a method for manufacturing the same, and a neuromorphic hardware device using the same.

[0008] According to an embodiment of the present application, an embedded flash memory device having a single poly structure is provided. The embedded flash memory device includes a plurality of unit memory cells, wherein the unit memory cells include a coupling transistor having a source region and a drain region connected to a word line and a floating gate region; and a read-out transistor having a source region connected to the source line and a drain region connected to a bit line, and sharing the floating gate region with the coupling transistor, wherein the coupling transistor and the read-out transistor may be configured in a gated-pin diode structure.

[0009] Additionally, the coupling transistor and the read-out transistor can perform a coupling operation so that when a predetermined voltage is applied to the word line, a predetermined ratio of voltage is distributed to the floating gate region.

[0010] Additionally, the coupling transistor and the lead-out transistor may be configured as a gated-pin diode structure having the same area.

[0011] Additionally, when voltage is applied to the word line, the coupling transistor and the read-out transistor may have the same capacitance characteristics.

[0012] Additionally, the embedded flash memory device can be manufactured through a CMOS (Complementary Metal-Oxide-Semiconductor) process.

[0013] In addition, the plurality of unit memory cells are configured as a NOR type array, and the unit memory cells can perform a program operation or an erase operation by injecting electrons or holes into the floating gate region through hot carrier injection (HCI) according to voltage application to the word line and the bit line.

[0014] In addition, the unit memory cell can perform a program operation by injecting electrons into the floating gate region through BBHE (Band-to-band hot electron) when a positive voltage is applied to the word line and the bit line, and can perform an erase operation by injecting holes into the floating gate region through BBHH (Band-to-band hot hole) when a negative voltage is applied to the word line and a positive voltage is applied to the bit line.

[0015] According to an embodiment of the present application, a neuromorphic hardware device using the embedded flash memory device is provided.

[0016] In addition, the neuromorphic hardware device can implement multi-level weighting by adjusting the capacitance of each of the plurality of unit memory cells by changing the threshold voltage of the unit memory cell based on the program and erase operations of the unit memory cell.

[0017] In addition, the neuromorphic hardware device can implement multi-level weighting by controlling the transconductance of each of the plurality of unit memory cells by changing the threshold voltage of the unit memory cell based on the program and erase operations of the unit memory cell.

[0018] According to an embodiment of the present application, a method for manufacturing an embedded flash memory device having a single poly structure is provided. The method comprises the steps of: preparing a wafer substrate; isolating and forming first active regions and second active regions corresponding to a coupling transistor and a read-out transistor, respectively, with the same area; forming a gate stack on upper sides of the first active region and the second active region to form a floating gate region, and patterning the gate stack into a predetermined shape; forming a source region by implanting P+ ions into one region of the first active region and the second active region; forming a drain region by implanting N+ ions into another region of the first active region and the second active region, thereby forming the coupling transistor and the read-out transistor sharing the floating gate region; forming a metal bonding surface in the source region and the drain region of the coupling transistor and the read-out transistor, and depositing a first layer metal connected to the metal bonding surface of the coupling transistor; And a step of forming a metal via for connecting the first layer metal and the second layer metal, and depositing the second layer metal connected to the first layer metal through the metal via; wherein the coupling transistor and the read-out transistor may be configured as a gated-pin diode structure.

[0019] According to embodiments of the present application, since a unit memory cell is implemented using two transistors, it can be configured with a smaller area and have a high bit density.

[0020] Additionally, low-power operation is possible because efficient program / erase operation is possible through the characteristics of the read-out transistor, and various array configurations are possible.

[0021] Additionally, since it is co-integrated with CMOS logic circuits, it can provide very high bandwidth, high yield, and high reliability, and enables ultra-high-speed neuromorphic hardware computation operations.

[0022] Additionally, the current mode and capacitive mode of the lead-out transistor allow for a variety of on-chip or off-chip applications.

[0023] The effects that can be obtained from the embodiments of the present application are not limited to the effects mentioned above, and other effects not mentioned can be clearly understood by a person having ordinary skill in the technical field to which the present application belongs from the description below.

[0024] To facilitate a more thorough understanding of the drawings cited in this application, a brief description of each drawing is provided.

[0025] FIG. 1 is a circuit diagram of an embedded flash memory device having a single poly structure according to an embodiment of the present application.

[0026] FIG. 2 and FIG. 3 are drawings for explaining the structure of an embedded flash memory device having a single poly structure according to an embodiment of the present application.

[0027] FIG. 4 and FIG. 5 are drawings for explaining the coupling operation of a coupling transistor and a lead-out transistor according to an embodiment of the present application.

[0028] FIG. 6 is a diagram for explaining program and erase operations of an embedded flash memory device having a single poly structure according to an embodiment of the present application.

[0029] FIG. 7a and FIG. 7b are drawings for explaining a method for manufacturing an embedded flash memory device having a single poly structure according to an embodiment of the present application.

[0030] FIG. 8 and FIG. 9 are drawings for explaining an array of embedded flash memory elements of a single poly structure according to an embodiment of the present application.

[0031] FIGS. 10 to 13 are drawings for explaining a neuromorphic hardware device using an embedded flash memory device with a single poly structure according to an embodiment of the present application.

[0032] Hereinafter, embodiments of the present application will be described in detail with reference to the accompanying drawings. The same reference numbers or symbols used in each drawing represent components or elements that perform substantially the same functions. For convenience, the directions of up, down, left, and right described below are based on the drawings, and the scope of the present application is not limited to these directions.

[0033] When explaining the technical concepts of this application, detailed descriptions of related known technologies will be omitted if they are deemed to unnecessarily obscure the gist of this application. Furthermore, numbers (e.g., "first," "second," etc.) used throughout the description of this application are merely identifiers used to distinguish one component from another.

[0034] The terminology used herein is for the purpose of describing embodiments and is not intended to limit and / or restrict the present application. The singular expression "a" includes the plural expression unless the context clearly dictates otherwise. When a part is said to be connected to another part in this specification, this includes not only direct connections but also indirect connections with other components intervening. Furthermore, when a part is said to include a component, this does not exclude other components unless otherwise specifically stated, but rather includes other components as well.

[0035] Furthermore, the term "or" in this application is intended to mean an inclusive "or" rather than an exclusive "or." That is, unless otherwise specified or clear from context, "X utilizes A or B" is intended to mean either of the natural inclusive permutations. That is, if X utilizes A; X utilizes B; or X utilizes both A and B, "X utilizes A or B" can apply to any of the above cases. Furthermore, the term "and / or" as used herein should be understood to refer to and encompass all possible combinations of one or more of the associated configurations listed.

[0036] In addition, when it is said in the present application that a member is located “on”, “above”, “upper”, “upper side”, “below”, “lower side”, “lower side”, or “lower side” of another member, this includes not only a case where a member is in contact with another member, but also a case where another member exists between the two members.

[0037] Additionally, in this application, when a part is said to "include" a certain component, this does not mean that other components are excluded, but rather that other components may be included, unless specifically stated otherwise.

[0038] Additionally, the terms "about," "substantially," and the like used in this application are used to mean at or near the numerical value when manufacturing and material tolerances inherent to the meanings mentioned are presented, and are used to prevent unscrupulous infringers from unfairly exploiting disclosures that mention precise or absolute values ​​to aid understanding of this application. Furthermore, in this application, the terms "step of ~" or "step of ~" do not mean "step for ~."

[0039] It should be noted that the distinction between components in this application is merely a distinction based on the primary function of each component. In other words, two or more components described below may be combined into a single component, or a single component may be further subdivided into two or more components with more detailed functions. Furthermore, each component described below may, in addition to its own primary function, additionally perform some or all of the functions of other components. It should also be noted that some of the primary functions of each component may be dedicated to other components.

[0040]

[0041] Hereinafter, embodiments of the present application will be described in detail one by one.

[0042]

[0043] FIG. 1 is a circuit diagram of an embedded flash memory device having a single poly structure according to an embodiment of the present application.

[0044] Referring to Figure 1, one unit memory cell including two transistors (10, 20) is shown. An embedded flash memory device can be configured by arranging a plurality of memory cells in a certain shape of an array.

[0045] Here, the two transistors are a coupling transistor (10) and a lead-out transistor (20), respectively, and the coupling transistor (10) and the lead-out transistor (20) may be field effect transistors.

[0046] The coupling transistor (10) performs a coupling operation with the read-out transistor (20), and can distribute the voltage applied to the word line and transmit it to the floating gate region (FG).

[0047] The coupling transistor (10) includes a source region, a drain region, and a floating gate region (FG), and the source region and the drain region are connected to the same electrode and can be connected to a word line.

[0048] The read-out transistor (20) shares a floating gate region (FG) with the coupling transistor (10) and can be formed to have the same structure as the coupling transistor (10). A source line can be connected to the source region of the read-out transistor (20), and a bit line can be connected to the drain region. The read-out transistor (20) can perform a function of reading stored data (i.e., determining a 1 or 0 state) by detecting an increase or decrease in conductivity according to a change in threshold voltage according to charges accumulated in the floating gate region.

[0049] The coupling transistor (10) and the read-out transistor (20) can perform a program operation (write operation) and an erase operation (erase operation) that inject or remove charges into or from the floating gate region (FG) according to the voltage applied to the word line, drain line, and source line.

[0050] The program and erase operations of the coupling transistor (10) and the lead-out transistor (20) will be described in detail with reference to FIG. 6.

[0051] In an embodiment, the coupling transistor (10) and the read-out transistor (20) may be configured as gated pin diode structures having the same area. Specifically, the coupling transistor (10) and the read-out transistor (20) may be formed as gated pin diode structures having the same area by forming a source region with P+ and a drain region with N+. According to the present application, through this pin structure, a strong junction electric field is formed at the source-channel and channel-drain, thereby enabling injection of electrons or holes into the floating gate region at low voltage and high speed.

[0052]

[0053] FIG. 2 and FIG. 3 are drawings for explaining the structure of an embedded flash memory device having a single poly structure according to an embodiment of the present application.

[0054] Figures 2 and 3 show the planar layout and cross-sectional layout of one unit memory cell.

[0055] The coupling transistor (10) and the lead-out transistor (20) are arranged such that a first active region (ACT1) and a second active region (ACT2) forming a channel are arranged, a BP (Boron implant mask) is used for P+ implant, and an N+ implant is performed in an area where BP is not used, so that the source region is formed as P+ and the drain region is formed as N+, ultimately forming a gated pin diode structure.

[0056] In the embodiment, various materials such as Si (silicon), SiGe (silicon-germanium), SiC (silicon carbide), GaN (gallium nitride), Poly-Si (polysilicon), IGZO (indium gallium zinc oxide), and TMD (transition metal dichalcogenide) can be used as the material of the active region (ACT1, ACT2).

[0057] A poly-gate region, i.e., a floating gate region (FG), is formed on the upper side of the active region (ACT1, ACT2). The coupling transistor (10) and the lead-out transistor (20) can be configured to share one floating gate region (FG).

[0058] The first layer metal (M1) is a metal line that applies the voltage of the word line (WL) to the source region and drain region of the coupling transistor (10), and is connected to the metal junction surface (CA) formed in the source region and drain region of the coupling transistor (10), respectively. Meanwhile, the second layer metal (M2) is a metal line that applies the voltage of the bit line (BL) to the drain region of the read-out transistor (20), and applies the voltage of the source line (SL) to the source region, and is connected to the metal junction surface (CA) formed in the source region and drain region of the read-out transistor (20), respectively, through a metal via (M1V1M2).

[0059] Therefore, the word line (WL) is controlled by being horizontally connected to the first layer using the first layer metal (M1) so that the word line (WL), bit line (BL), and source line (SL) do not affect each other, and the bit line (BL) and source line (SL) are controlled by being vertically connected to the second layer using the second layer metal (M2).

[0060] These layers that make up the embedded flash memory device with a single poly structure are layers utilized in the existing CMOS process, so it is possible to manufacture the embedded flash memory device through the CMOS process without additional masks or layers.

[0061] At this time, as with conventional embedded flash memory, the poly gate is not connected to other metals and functions as a floating gate region. Therefore, a 2-T single poly embedded flash memory element is formed with a two-gate pin diode structure.

[0062]

[0063] FIGS. 4 and 5 are diagrams for explaining the coupling operation of a coupling transistor and a read-out transistor according to an embodiment of the present application. Specifically, FIG. 4 shows an equivalent capacitor circuit diagram of an embedded flash device according to an embodiment of the present application, and FIG. 5 shows the results of voltage transmission to a floating gate region through voltage application to a word line and the coupling ratio.

[0064] As described above, the coupling transistor (10) is configured with the same structure and area as the read-out transistor (20), and the source region and drain region are connected to the same electrode and are connected to the word line (WL).

[0065] At this time, voltage (V) is applied to the word line (WL). WL ) is given, voltage distribution occurs and voltage (V) is applied to the floating gate region (FG). FG ) is formed. That is, the two transistors can be expressed as the equivalent capacitor circuit diagram of Fig. 4, and have the same capacitance characteristics, as in (a) of Fig. 5. Therefore, the coupling transistor (10) and the read-out transistor (20) can operate by generating a coupling phenomenon due to capacitances of the same characteristics, and when voltage is applied to the word line (WL), it is transmitted as voltage to the gate of the read-out transistor (20).

[0066] Figure 5 (b) shows the voltage results transmitted to the floating gate region (FG) when voltage is applied to the word line (WL). Due to the capacitance characteristics of the two transistors, the same voltage is typically distributed, resulting in a coupling result close to 0.5.

[0067]

[0068] FIG. 6 is a diagram for explaining program and erase operations of an embedded flash memory device having a single poly structure according to an embodiment of the present application.

[0069] The embedded flash memory device of a single poly structure according to an embodiment of the present application can be configured with a plurality of memory cells as an AND type array, and can also be configured as a NOR type, which is a representative array type capable of low-power operation, and can thus be used in various array structures.

[0070] Fig. 6 (a) shows the operation of a NOR type embedded flash memory device, and Fig. 6 (b) shows the operation of an AND type embedded flash memory device.

[0071] When configured as a NOR type array, program and erase operations can be performed by injecting electrons and holes into the floating gate region (FG) via hot carrier injection (HCI). At this time, due to the pin structure, a strong junction electric field is formed at the source-channel and channel-drain, allowing electrons or holes to be injected into the floating gate region at low voltage and high speed.

[0072] First, when a positive voltage is applied to the word line (WL) connected to the coupling transistor (10) and the bit line (BL) connected to the read-out transistor (20), a program (write) operation is performed by injecting electrons into the floating gate region (FG) through BBHE (Band-to-band hot electron).

[0073] Next, when a negative voltage is applied to the word line (WL) connected to the coupling transistor (10) and a positive voltage is applied to the bit line (BL) connected to the read-out transistor (20), an erase operation is performed by injecting positive holes into the floating gate region (FG) through the band-to-band hot hole (BBHH).

[0074] At this time, the stored charge / positive charge is the threshold voltage (V) of the read-out transistor (20). th) will increase / decrease.

[0075] The operation of such a NOR type array can be implemented at a lower voltage than tunneling injection, enabling low-power operation and eliminating the need for additional high-voltage supply circuit design, thereby improving the overall memory chip area and power efficiency compared to conventional embedded flash memory devices.

[0076] Meanwhile, when configured as an AND-type array, program operations can be performed using the Folwer-Nordheim (FN) tunneling method, similar to conventional embedded flash memory. While this requires a higher word line (WL) voltage than a NOR-type configuration, the tunneling characteristics enable lower power operation compared to conventional memory.

[0077]

[0078] FIG. 7a and FIG. 7b are drawings for explaining a method for manufacturing an embedded flash memory device having a single poly structure according to an embodiment of the present application.

[0079] First, a semiconductor wafer substrate can be prepared ((a) of Fig. 7a).

[0080] Next, the first active region (ACT1) and the second active region (ACT2) corresponding to the coupling transistor (10) and the lead-out transistor (20) respectively can be formed in isolation with the same area ((b) of FIG. 7a).

[0081] In the embodiment, various materials such as Si (silicon), SiGe (silicon-germanium), SiC (silicon carbide), GaN (gallium nitride), Poly-Si (polycrystalline silicon), IGZO (indium gallium zinc oxide), and TMD (transition metal dichalcogenide) can be used as materials of the active region (ACT1, ACT2).

[0082] Next, to form a floating gate region (FG), a gate stack can be formed on the upper side of the first active region (ACT1) and the second active region (ACT2) and patterned into a predetermined shape ((c) of FIG. 7a).

[0083] Here, the gate stack may include gate oxide (metal) and polysilicon (poly-Si). The gate oxide is composed of an insulating material, and a metal material is deposited thereon to control electrical signals. The polysilicon is not connected to the first layer metal and the second layer metal described below, and forms a floating gate region (FG).

[0084] In the embodiment, various insulating materials such as SiO2 (silicon dioxide), SiON (silicon nitride), HfO2 (hafnium oxide), ZrO2 (zirconium oxide), La2O3 (lanthanum oxide), and TiO2 (titanium dioxide) can be used as the gate oxide, and various materials such as TiN (titanium nitride), W (tungsten), and TaN (tantalum nitride) can be used as the material forming the floating gate region in addition to polysilicon.

[0085] A source region can be formed by implanting P+ ions (P+ implantation) into one region of the first active region (ACT1) and the second active region (ACT2), and a drain region can be formed by implanting N+ ions (N+ implantation) into another region, and then rapid heat treatment can be performed (Fig. 7a (d) and Fig. 7b (e)).

[0086] Through this, a coupling transistor (10) and a read-out transistor (20) of the same gated pin diode structure sharing a floating gate area can be formed.

[0087] Next, a metal junction surface can be formed in the source region and drain region of the coupling transistor (10) and the lead-out transistor (20), and a first layer metal (M1) connected to the metal junction surface can be deposited ((f) of FIG. 7b).

[0088] The source region and drain region of the coupling transistor (10) can be connected to the word line (WL) with the same electrode through the first layer metal (M1).

[0089] Next, a metal via can be formed to connect the first layer metal (M1) and the second layer metal (M2), and the second layer metal (M2) connected to the first layer metal (M1) can be deposited through the metal via ((e) of FIG. 7b).

[0090] The source region and drain region of the read-out transistor (20) can be connected to the source line (SL) and the bit line (BL), respectively, through the second layer metal (M2).

[0091] Accordingly, the word line (WL) is controlled by being horizontally connected to the first layer using the first layer metal (M1) so that the word line (WL), bit line (BL), and source line (SL) do not affect each other, and the bit line (BL) and source line (SL) are controlled by being vertically connected to the second layer using the second layer metal (M2).

[0092] However, the manufacturing method described with reference to FIGS. 7a and 7b is exemplary, and various process methods known in the technical field to which the present application belongs can be applied.

[0093]

[0094] FIG. 8 and FIG. 9 are drawings for explaining an array of embedded flash memory elements of a single poly structure according to an embodiment of the present application.

[0095] The embedded flash memory device according to the embodiment of the present application sets the areas of the coupling transistor (10) and the read-out transistor (20) to be the same, and uses only two transistors in each unit memory cell, so that, as shown in FIG. 8, the feature size is 16F, which is smaller than the existing embedded flash (52F²). 2 It can have high density characteristics that can be designed.

[0096] In addition, as illustrated in FIG. 9, the embedded flash memory device according to the embodiment of the present application can be configured as a representative AND type array. In addition, as described above, it can also be configured as a NOR type array capable of low-power operation, thus having the advantage of being usable in various array structures.

[0097]

[0098] FIGS. 10 to 13 are drawings for explaining a neuromorphic hardware device using an embedded flash memory device with a single poly structure according to an embodiment of the present application.

[0099] Figures 10 and 11 show two types of neuromorphic hardware structures utilizing embedded flash memory devices according to embodiments of the present application. The threshold voltage (V) of each unit memory cell is determined by utilizing the program / erase operation described above. th ) can be adjusted, allowing for various multi-level weight expressions.

[0100] First, Fig. 10 shows a structure of a capacitive mode. Fig. 10 (a) shows an example using an AND type array configuration, and Fig. 10 (b) shows an example using an array configuration in the form of a crossbar array implemented in a manner that does not use a source line (SL).

[0101] When operating in capacitive mode, as shown in Fig. 12, the threshold voltage (V th ) can be changed to change the capacitance values ​​of multiple unit memory cells, so that various weights can be expressed using this.

[0102] Next, Fig. 11 shows the structure of the current mode, which is a vector-matrix multiplication operation method through the summation of the current output through the applied gate voltage and the transmitted transconductance value, similar to the existing flash and embedded flash memories.

[0103] In current mode operation, as shown in Fig. 13, the threshold voltage (V th ) can be changed similarly to the capacitance mode, so that various weight expressions are possible.

[0104]

[0105] Although the embodiments have been described in detail above, the scope of the present application is not limited thereto, and various modifications and improvements made by those skilled in the art using the basic concept of the present application defined in the following claims also fall within the scope of the present application.

Claims

1. As an embedded flash memory device with a single poly structure, Contains multiple unit memory cells, The above unit memory cell is, A coupling transistor including a source region and a drain region connected to a word line, and a floating gate region; and A source region connected to a source line and a drain region connected to a bit line, and a lead-out transistor sharing the floating gate region with the coupling transistor, An embedded flash memory device, wherein the coupling transistor and the read-out transistor are configured as a gated-pin diode structure.

2. In paragraph 1, An embedded flash memory device in which the coupling transistor and the read-out transistor operate in a coupling manner so that when a predetermined voltage is applied to the word line, a predetermined ratio of voltage is distributed to the floating gate region.

3. In paragraph 2, An embedded flash memory device, wherein the coupling transistor and the read-out transistor are configured as gated-pin diode structures having the same area.

4. In paragraph 2, An embedded flash memory device, wherein when voltage is applied to the word line, the coupling transistor and the read-out transistor have the same capacitance characteristics.

5. In paragraph 1, The above embedded flash memory device, An embedded flash memory device manufactured using the CMOS (Complementary Metal-Oxide-Semiconductor) process.

6. In paragraph 1, The plurality of above unit memory cells are configured as a NOR type array, The above unit memory cell is, An embedded flash memory device that performs a program operation or an erase operation by injecting electrons or holes into the floating gate region through hot carrier injection (HCI) according to voltage application to the word line and the bit line.

7. In paragraph 6, The above unit memory cell is, When a positive voltage is applied to the word line and the bit line, electrons are injected into the floating gate region through BBHE (Band-to-band hot electron), thereby performing a program operation. An embedded flash memory device that performs an erase operation by injecting holes into the floating gate region through a band-to-band hot hole (BBHH) when a negative voltage is applied to the word line and a positive voltage is applied to the bit line.

8. A neuromorphic hardware device using an embedded flash memory device according to any one of claims 1 to 7.

9. In paragraph 8, The neuromorphic hardware device implements multi-level weighting by adjusting the capacitance of each of the plurality of unit memory cells by changing the threshold voltage of the unit memory cell based on the program and erase operations of the unit memory cell.

10. In paragraph 8, The neuromorphic hardware device implements multi-level weighting by controlling the transconductance of each of the plurality of unit memory cells by changing the threshold voltage of the unit memory cell based on the program and erase operations of the unit memory cell.

11. A method for manufacturing an embedded flash memory device having a single poly structure, Step of preparing a wafer substrate; A step of isolating and forming a first active region and a second active region corresponding to each of a coupling transistor and a lead-out transistor with the same area; A step of forming a gate stack on the upper side of the first active region and the second active region to form a floating gate region and patterning it into a predetermined shape; A step of forming a source region by injecting P+ ions into one region of the first active region and the second active region; A step of forming the coupling transistor and the read-out transistor that share the floating gate region by forming a drain region by injecting N+ ions into another region of the first active region and the second active region; A step of forming a metal junction surface in the source region and the drain region of the coupling transistor and the lead-out transistor, and depositing a first layer metal connected to the metal junction surface of the coupling transistor; and A step of forming a metal via for connecting the first layer metal and the second layer metal, and depositing the second layer metal connected to the first layer metal through the metal via; A manufacturing method wherein the coupling transistor and the lead-out transistor are configured as a gated-pin diode structure.

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