Front console with adapter

Abstract

The invention relates to a front console with adapter (10) for use on frailer vehicles without a roof lifting, which enables the height of the front bollard pillar (B) to be the same for trailer vehicles with and without a roof lifting, so that the front bollard cut length (BB) and the front bollard cutting axis (BKE) are common.

Description

Atty. Ref. No. 0073605-000982 A DESIGN STRATEGY FOR HIGH-PERFORMANCE P-TYPE TWO-DIMENSIONAL FIELD EFFECT TRANSISTORS CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This patent application is related to and claims the benefit of priority of U.S. provisional patent application no. 63 / 649,715, filed on May 20, 2024, the entire contents of which is incorporated herein by reference. STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT

[0002] This invention was made with government support under Grant No. ECCS-2042154 awarded by the National Science Foundation. The Government has certain rights in the invention. FIELD OF THE INVENTION

[0003] Embodiments can relate to a Field Effect Transistor (FET) including a substrate having a 2D material formed on a surface thereof, wherein a channel region includes one to three monolayers of the 2D material. BACKGROUND OF THE INVENTION

[0004] The rise of two-dimensional (2D) semiconductors as potential alternatives to silicon in CMOS technology, especially at scaled process nodes, is promising due to their atomically thin nature. Semiconducting transition metal dichalcogenides (TMDs) like MoS2, MoSe2, and WSe2, with thicknesses as thin as ~0.6 nm at the monolayer level, offer atomically smooth surfaces and hold significant potential for high-performance field-effect transistors (FETs). Notable progress has been made in n-type FETs based on 2D materials such as MoS2and WS2, driven by advancements in material growth, contact engineering, channel length scaling, and high-k dielectric integration bringing them closer to meeting the requirements set by International Roadmap for Devices and Systems (IRDS). However, achieving high-performance p-type FETs has been slower due to challenges related to Fermi level pinning at metal / 2D interfaces.

[0005] In 2D TMDs like MoS2and WS2, Fermi level pinning near the conduction band edge can be overcome by using low work-function metals as contact electrodes to realize high-Atty. Ref. No. 0073605-000982 performance n-type FETs. However, it results in significant contact resistance (RC) for hole injection.

[0006] Additionally, the challenge is exacerbated in monolayers due to larger bandgap values. In contrast, transition metal selenides like MoSe2and WSe2facilitate relatively easier hole injection due to Fermi level pinning near the middle of the bandgap. Here however tunneling injection across the Schottky barrier leads to diminished ON-state performance (ION). Reducing RCby cutting short the tunneling distance is imperative by degenerate doping underneath the contacts, a strategy long adopted in the semiconductor industry for both n- and p-type FETs. Applying this approach to 2D FETs presents its own challenges.

[0007] On examining 2D FETs based on pristine and doped MoSe2and WSe2single crystal flakes it was observed that while n-type transport dominates in pristine flakes, thick doped flakes demonstrate degenerate p-type doping, resulting in improved FET characteristics. However, thick flakes lack electrostatic gate control, leading to a poor on / off current ratio. As the flake thickness decreases, doping effectiveness diminishes due to quantum confinement effects. This underscores the importance of degenerate doping to decrease RCand the necessity of maintaining a thin channel for improved electrostatics. SUMMARY OF THE INVENTION

[0008] Embodiments can relate to a novel FET structure comprising thin channel layers and degenerately doped multilayer contact regions, to achieve high performance (ION~85μA / μm) with low RC(~2 kΩ-μm) and high ON / OFF current ratio (104). Furthermore, applying the novel FET design on a scaled dual-gated FET is demonstrated, showcased improved performance (ION~212μA / μm). This design approach can be extended to various 2D materials, facilitating advancements in both n- and p-type doping for 2D FET technology and underscoring the significance of doped multilayer 2D materials on a wafer scale.

[0009] Doping is crucial for shaping semiconductors and electronic devices, particularly in field- effect transistors (FETs). Degenerate doping in the silicon channel beneath the source and drain regions is vital for high-performance n- and p-type devices as it reduces contact resistance (RC). In contrast, 2D semiconductors mainly rely on metal work-function engineering to lower RC. While successful for n-type 2D FETs, achieving the same for p-type ones has been challenging. To address this, the present disclosure demonstrates degenerate p-type doping in thick MoSe2Atty. Ref. No. 0073605-000982 and WSe2FETs 4-6 monolayers) via transition metal substitution (V, Nb, Ta) and an observation of weakened gate control and a poor on / off current ratio. Interestingly, thinner flakes ( 1-3 monolayers) show reduced doping effectiveness due to quantum confinement effects, restoring gate control. Based on this observation, the present disclosure provides for designed a FET structure where the channel is fabricated using thinner 2D material which are relatively less doped, while the contact regions consist of degenerately doped thicker layers, allowing us to achieve both low RCand high on / off current ratio. The doping and device design approach are relevant for synthetic 2D materials and n-type 2D FETs.

[0010] Embodiments can relate to a Field Effect Transistor (FET) including a substrate having a 2D material formed on a surface thereof. The 2D material can have a source contact region, a drain contact region, and a channel region. The channel region can include one to three monolayers of the 2D material. The source contact region can include three to six monolayers of the 2D material. The drain contact region can include three to six monolayers of the 2D material.

[0011] In some embodiments, the channel region can consist essentially of one to three monolayers of the 2D material. The source contact region can consist essentially of three to six monolayers of the 2D material. The drain contact region can consist essentially of three to six monolayers of the 2D material.

[0012] In some embodiments, the channel region can consist of one to three monolayers of the 2D material. The source contact region can consist of three to six monolayers of the 2D material. The drain contact region can consist of three to six monolayers of the 2D material.

[0013] In some embodiments, the source contact region can include degenerately doped 2D material. The drain contact region can include degenerately doped 2D material.

[0014] In some embodiments, the FET can include a source contact formed on the source contact region. A drain contact can be formed on the drain contact region.

[0015] In some embodiments, the channel region can be formed between the source contact region and the drain contact region.

[0016] In some embodiments, the 2D material can include one or more types of 2D material.

[0017] In some embodiments, the 2D material of the channel region can be the same as or different from the 2D material of the source contact region. The 2D material of the channelAtty. Ref. No. 0073605-000982 region can be the same as or different from the 2D material of the drain contact region. The 2D material of the source contact region can be the same as or different from the 2D material of the drain contact region.

[0018] In some embodiments, the 2D material of one monolayer of the channel region can be the same as or different from the 2D material of another monolayer of the channel region. The 2D material of one monolayer of the source contact region can be the same as or different from the 2D material of another monolayer of the source contact region. The 2D material of one monolayer of the drain contact region can be the same as or different from the 2D material of another monolayer of the drain contact region.

[0019] In some embodiments, the substrate can be a p-type doped substrate. The substrate can be a n-type doped substrate.

[0020] In some embodiments, the FET can yield a performance of at least ION= 85μA / μm. The FET can exhibit a contact resistance (RC) of less than 2 kΩ-μm. The FET can exhibit an ON / OFF current ratio > 104.

[0021] Embodiments can relate to a method for generated a FET structure. The method can involve forming three to six monolayers of 2D material on a surface of a substrate. The method can involve removing three to five monolayers of the 2D material to generate a channel region. The channel region can be between a source contact region and a drain contact region. The source contact region can include three to six monolayers of the 2D material. The drain contact region can include three to six monolayers of the 2D material.

[0022] In some embodiments, removing three to five monolayers can involve a self-limiting etching technique.

[0023] In some embodiments, the self-limiting etching technique can involve radio frequency (RF) plasma-based oxidation.

[0024] In some embodiments, RF plasma-based oxidation can remove three to five monolayers in a layer-by-layer fashion.

[0025] In some embodiments, the forming three to six monolayers of 2D material on a surface of a substrate can involve forming a first layer on the substrate, a second layer on the first layer, a third layer on the second layer, a fourth layer on the third layer, a fifth layer on the fourth layer, and a sixth layer on the fifth layer. RF plasma-based oxidation can be used on the sixth layer toAtty. Ref. No. 0073605-000982 generate a passivating and sub-stoichiometric sixth layer, wherein the passivating and sub- stoichiometric sixth layer is dissolved. RF plasma-based oxidation can be used on the fifth layer to generate a passivating and sub-stoichiometric fifth layer, wherein the passivating and sub- stoichiometric fifth layer is dissolved. RF plasma-based oxidation can be used on the fourth layer to generate a passivating and sub-stoichiometric fourth layer, wherein the passivating and sub-stoichiometric fourth layer is dissolved.

[0026] In some embodiments, the 2D material can be doped single crystals.

[0027] In some embodiments, the 2D material can be doped using a chemical vapor transport technique.

[0028] In some embodiments, the 2D material can be formed on the surface of the substrate via a chemical vapor transport technique.

[0029] Exemplary embodiments can relate to a Field Effect Transistor (FET). The FET can include a substrate having a 2D material formed on a surface thereof, the 2D material having a source contact region, a drain contact region, and a channel region. The channel region can have less than four monolayers of the 2D material. The source contact region can include more than four monolayers of the 2D material. The drain contact region can include more than four monolayers of the 2D material.

[0030] In some embodiments, the source contact region can include heavily / degenerately doped 2D material. The drain contact region can include heavily / degenerately doped 2D material. The channel region can include include pristine / lightly / moderately doped 2D material.

[0031] In some embodiments, the 2D material can include one or more types of 2D material. The 2D material of the channel region can be the same as or different from the 2D material of the source contact region. The 2D material of the channel region can be the same as or different from the 2D material of the drain contact region. The 2D material of the source contact region can be the same as or different from the 2D material of the drain contact region.

[0032] In some embodiments, the 2D material of one monolayer of the channel region can be the same as or different from the 2D material of another monolayer of the channel region. The 2D material of one monolayer of the source contact region can be the same as or different from the 2D material of another monolayer of the source contact region. The 2D material of one

Claims

Atty. Ref. No. 0073605-000982 monolayer of the drain contact region can be the same as or different from the 2D material of another monolayer of the drain contact region. [0033] Further features, aspects, objects, advantages, and possible applications of the present invention will become apparent from a study of the exemplary embodiments and examples described below, in combination with the Figures, and the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS [0034] The above and other objects, aspects, features, advantages and possible applications of the present innovation will be more apparent from the following more particular description thereof, presented in conjunction with the following drawings. Like reference numbers used in the drawings may identify like components. [0035] FIG. 1 shows an exemplary architecture of an embodiment of the 2D FET. [0036] FIG. 2 show an exemplary process of forming an embodiment of te 2D FET. [0037] FIG. 3 shows substitutionally doped p-type MoSe2FETs. [0038] FIG. 4 shows electronic band structure of pristine and doped MoSe2, wherein the band structure of pristine (panel a) and V- (panel b), Nb- (panel c), and Ta- (panel d) doped 2H-phase MoSe2for single-layer (1L), double-layer (2L), and eight-layer (8L) optimized structure is shown. A bar plot showing the relative position of Fermi level (E�) with respect to the valenceband (E�), i.e., E� − E� for 1L, 2L and 8L-MoSe2 for each of the group VB dopants is shown inpanel e. A bar plot showing band gap (E�) for pristine as well as V-, Nb- and Ta-doped MoSe2for each thicknesses is shown in panel f. [0039] FIG. 5 shows impact of degenerate doping on contact resistance, wherein transfer characteristics of V-, Nb-, and Ta-doped thick MoSe2flakes for different L(panel a), corresponding TLM data, i.e., R�versus Lobtained at V= -8 V along with the linear fits to extract the 2R�values from the y-intercepts (panel b), and R�values obtained from TLM measurements for V-, Nb-, and Ta-doped MoSe2flakes with different thicknesses (panel c) are shown. [0040] FIG. 6 shows an exemplary embodiment of a 2D FET design. [0041] FIG. 7 shows an exemplary high performance p-type dual-gated 2D FET. [0042] FIG. 8 shows electrical characterization of Nb-doped CVD-grown large-area MoSe2FETs.

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