Data scaling

Abstract

Apparatuses, systems, and techniques to scale values. In at least one embodiment, a processor comprising one or more circuits to cause a largest value of each portion of two or more portions of an array to be identified and to use the largest value of each portion to scale one or more values within each portion sequentially.

Description

DATA SCALINGTECHNICAL FIELD

[0001] At least one embodiment pertains to scaling data values. For example, at least one embodiment pertains to one or more circuits to cause a largest value in each portion of two or more portions of an array to be identified and to use a largest value of each portion to scale one or more values within each portion sequentially.BACKGROUND

[0002] Processors use data represented using a multitude of data formats to perform operations and may manage data to reduce total processing impact by scaling data inputs to be represented in another data format. Techniques for reducing memory access overheads through scaling data inputs can be improved.BRIEF DESCRIPTION OF DRAWINGS

[0003] FIG. 1 illustrates an example data scaling system, according to at least one embodiment;

[0004] FIG. 2 illustrates an example of tensor scaling, according to at least one embodiment;

[0005] FIG. 3 illustrates an example of data format conversion, according to at least one embodiment;

[0006] FIG. 4 illustrates an example of scaling operations, according to at least one embodiment;

[0007] FIG. 5 illustrates an example of operations of one or more scaling modules, according to at least one embodiment;

[0008] FIG. 6 illustrates a flow diagram of a method to scale values, according to at least one embodiment;

[0009] FIG. 7 illustrates a flow diagram of a method to scale values, according to at least one embodiment;

[0010] FIG. 8 illustrates an example of a processor, according to at least one embodiment;

[0011] FIG. 9A illustrates logic, according to at least one embodiment;

[0012] FIGS. 9B illustrates logic, according to at least one embodiment;

[0013] FIG. 10 illustrates training and deployment of a neural network, according to at least one embodiment;

[0014] FIG. 11 illustrates an example data center system, according to at least one embodiment;

[0015] FIG. 12A illustrates an example of an autonomous vehicle, according to at least one embodiment;

[0016] FIG. 12B illustrates an example of camera locations and fields of view for the autonomous vehicle of FIG. 12A, according to at least one embodiment;

[0017] FIG. 12C is a block diagram illustrating an example system architecture for the autonomous vehicle of FIG. 12A, according to at least one embodiment;

[0018] FIG. 12D is a diagram illustrating a system for communication between cloud-based server(s) and the autonomous vehicle of FIG. 12 A, according to at least one embodiment;

[0019] FIG. 13 is a block diagram illustrating a computer system, according to at least one embodiment;

[0020] FIG. 14 is a block diagram illustrating a computer system, according to at least one embodiment;

[0021] FIG. 15 illustrates a computer system, according to at least one embodiment;

[0022] FIG. 16 illustrates a computer system, according to at least one embodiment;

[0023] FIG. 17A illustrates a computer system, according to at least one embodiment;

[0024] FIG. 17B illustrates a computer system, according to at least one embodiment;

[0025] FIG. 17C illustrates a computer system, according to at least one embodiment;

[0026] FIG. 17D illustrates a computer system, according to at least one embodiment;

[0027] FIG. 17E and 17F illustrate a shared programming model, according to at least one embodiment;

[0028] FIG. 18 illustrates exemplary integrated circuits and associated graphics processors, according to at least one embodiment;

[0029] FIGS. 19A-19B illustrate exemplary integrated circuits and associated graphics processors, according to at least one embodiment;

[0030] FIGS. 20A-20B illustrate additional exemplary graphics processor logic according to at least one embodiment;

[0031] FIG. 21 illustrates a computer system, according to at least one embodiment;

[0032] FIG. 22A illustrates a parallel processor, according to at least one embodiment;

[0033] FIG. 22B illustrates a partition unit, according to at least one embodiment;

[0034] FIG. 22C illustrates a processing cluster, according to at least one embodiment;

[0035] FIG. 22D illustrates a graphics multiprocessor, according to at least one embodiment;

[0036] FIG. 23 illustrates a multi-graphics processing unit (GPU) system, according to at least one embodiment;

[0037] FIG. 24 illustrates a graphics processor, according to at least one embodiment;

[0038] FIG. 25 is a block diagram illustrating a processor micro-architecture for a processor, according to at least one embodiment;

[0039] FIG. 26 illustrates a deep learning application processor, according to at least one embodiment;

[0040] FIG. 27 is a block diagram illustrating an example neuromorphic processor, according to at least one embodiment;

[0041] FIG. 28 illustrates at least portions of a graphics processor, according to one or more embodiments;

[0042] FIG. 29 illustrates at least portions of a graphics processor, according to one or more embodiments;

[0043] FIG. 30 illustrates at least portions of a graphics processor, according to one or more embodiments;

[0044] FIG. 31 is a block diagram of a graphics processing engine of a graphics processor in accordance with at least one embodiment;

[0045] FIG. 32 is a block diagram of at least portions of a graphics processor core, according to at least one embodiment;

[0046] FIGS. 33A-33B illustrate thread execution logic including an array of processing elements of a graphics processor core according to at least one embodiment;

[0047] FIG. 34 illustrates a parallel processing unit (“PPU”), according to at least one embodiment;

[0048] FIG. 35 illustrates a general processing cluster (“GPC”), according to at least one embodiment;

[0049] FIG. 36 illustrates a memory partition unit of a parallel processing unit (“PPU”), according to at least one embodiment;

[0050] FIG. 37 illustrates a streaming multi-processor, according to at least one embodiment;

[0051] FIG. 38 is an example data flow diagram for an advanced computing pipeline, in accordance with at least one embodiment;

[0052] FIG. 39 is a system diagram for an example system for training, adapting, instantiating, and deploying machine learning models in an advanced computing pipeline, in accordance with at least one embodiment;

[0053] FIG. 40 includes an example illustration of an advanced computing pipeline 3910A for processing imaging data, in accordance with at least one embodiment;

[0054] FIG. 41 A includes an example data flow diagram of a virtual instrument supporting an ultrasound device, in accordance with at least one embodiment;

[0055] FIG. 4 IB includes an example data flow diagram of a virtual instrument supporting an CT scanner, in accordance with at least one embodiment;

[0056] FIG. 42A illustrates a data flow diagram for a process to train a machine learning model, in accordance with at least one embodiment;

[0057] FIG. 42B is an example illustration of a client-server architecture to enhance annotation tools with pre-trained annotation models, in accordance with at least one embodiment; and

[0058] FIG. 43 illustrates components of a system to access a large language model, according to at least one embodiment.DETAILED DESCRIPTION

[0059] FIG. 1 illustrates an example of a data scaling system 100 (“system 100”), in accordance with some embodiments of the present disclosure. It should be understood that this and other arrangements described herein are set forth only as examples. Other arrangements and elements (e.g., machines, interfaces, functions, orders, groupings of functions, etc.) may be used in addition to or instead of those shown, and some elements may be omitted altogether. Further, many of the elements described herein are functional entities that may be implemented as discrete or distributed components or in conjunction with other components, and in any suitable combination and location. Various functions described herein as being performed by entities may be carried out by hardware, firmware, and / or software. For instance, various functions may be carried out by a processor executing instructions stored in memory.

[0060] In at least one embodiment, a module includes any combination of any type of logic (e.g., software, hardware, firmware) and / or circuitry configured to perform a function as described. In at least one embodiment, a module includes one or more circuits that form part of a larger system (e.g., an integrated circuit (IC), system on-chip (SoC), central processing unit (CPU), graphics processing unit (GPU), data processing unit (DPU), etc.). In at least one embodiment, a controller includes any combination of any type of logic (e.g., software, hardware, firmware) and / or circuitry configured to perform a function as described. In at least one embodiment, software includes software packages, code, programming language, drivers, instructions, instruction sets, or some combination thereof. In at least one embodiment, hardware includes hardwired circuits, programmable circuits, state machine circuits, fixed function circuits, execution unit circuits, firmware with stored instructions executed by programmable circuits, or some combination thereof.

[0061] In at least one embodiment, system 100 includes one or more devices 102 and / or one or more device(s) 116. In at least one embodiment, device 102 includes one or more of a data conversion manager 104, one or more machine learning model(s) 108, one more processors 110, one or more communication managers 112, and / or one or more storage devices 114. In at least one embodiment, data conversion manager 104 includes one or more scaling modules 106. In at least one embodiment, device 102 is implemented, for example, using a main central processing unit (“CPU”) complex, one or more microprocessors, one or more microcontrollers, one or more graphics processing units (“GPU(s)”), one or more data processing units (“DPU(s)”), hardware, software, logic, processors, one or more transformer engines, and / or other components.

[0062] In at least one embodiment, device(s) 116 includes one or more processors 122, a storage device 120, and / or communication manager 124. In at least one embodiment, processors 122 include one or more processing cores, such as core 118A, core 118B, core 118Y, and / or core 118Z (referred to individually and / or collectively herein as “cores 118”). In at least one embodiment, device(s) 116 are implemented, for example, using a main central processing unit (“CPU”) complex, one or more microprocessors, one or more microcontrollers, one or more graphics processing units (“GPU(s)”), one or more data processing units (“DPU(s)”), hardware, software, logic, processors, one or more transformer engines, and / or other components. In at least one embodiment, one or more components of device 102 may be include with one or more components of device(s) 116 within a single device.

[0063] In at least one embodiment, system 100 comprises one or more component configured to scale one or more data values. In at least one embodiment, one or more components (e.g., processor 110 and / or processors 122) of system 100 is used to cause a largest value in each portion of two or more portions of an array to be identified and to use said largest value of each portion to scale one or more values within each portion sequentially. In at least one embodiment, system 100 is to perform a method to cause a largest value in each portion of two or more portions of an array to be identified and to use said largest value of each portion to scale one or more values within each portion sequentially. In at least one embodiment, for example, system 100 is to identify a largest value in one or more values of one or more portions of a tensor, to identify a scaling factor to be used to scale one or more values of said tensor.

[0064] In at least one embodiment, data values (e.g., used by machine learning model(s) 108) may be represented using one or more data formats. In at least one embodiment, a data format instructs system 100 of how one or more numerical data values are to be expressed. In at least one embodiment, a data format may indicate how values having decimal components are represented. In at least one embodiment, for example, a floating point (FP) data format may specify a fixed precision of a value. In at least one embodiment, a floating point data format may specify a fixed precision (a significand) that is scaled by an integer exponent. In at least one embodiment, data formats may specify that a value be represented using a particular number of bits (e.g., bit width). In at least one embodiment, for example, a value in a FP32 data format uses 32 bits, while a value in a FP8 data format uses 8 bits to represent said values. In at least one embodiment, a value represented in a first format (e.g., FP32) may be converted as to be represented in a second format (e.g., FP8). In at least one embodiment, converting a value from one data format to another may include scaling said value such that it can be representedin a desired format. In at least one embodiment, scaling a value comprises multiplying said value by a scaling factor. In at least one embodiment, a scaling factor is a value representing how much a data value is to be scaled. In at least one embodiment, a scaling factor may be identified based on a desired data format that a value is to be converted to. In at least one embodiment, for example, a scaling factor may be identified such that a value scaled using said scaling factor is able to be represented in a range of values that is able to be represented using a particular data format.

[0065] In at least one embodiment, one or more scaling factors may be identified, or otherwise calculated, based on values within an array that is to be scaled. In at least one embodiment, a magnitude of one or more values within an array are used to identify a scaling factor to be used to scale said array. In at least one embodiment, for example, A and B are input matrices for which scaling factors sBand sBmay be calculated based on current values within A and B to quantize these matrices. In at least one embodiment, in such an example:Where qmaxrepresents a largest value that can be represented in a quantized format, and Aqand Bqdenote these matrices in their quantized form. In at least one embodiment, when performing a matrix multiplication operation of A and B, an inner product operation AqBqis calculated using a quantized operation (e.g., an FP8 GEMM) and applying outer product scaling factorsand sBgenerates an output matrix C, where C = sAsB(AqBq).

[0066] In at least one embodiment, data values may be associated with one or more arrays of data, where said arrays comprise one or more elements associated with said data values. In at least one embodiment, an array of data may comprise one or more dimensions of elements. In at least one embodiment, for example, an array of data may be a one dimensional array and / or a multidimensional tensor.

[0067] In at least one embodiment, data conversion manager 104 comprises one or more components configured to covert one or more data values. In at least one embodiment, data conversion manager 104 is to convert (e.g., using processor 110 and / or processors 122) one or more data values represented in a first format to a second format. In at least one embodiment,for example, conversion manager 104 is to convert (e.g., using processor 110 and / or processors 122) one or more values in one or more arrays from a data format (e.g., FP32) to another data format (e.g., FP8) having a lower precision representation and / or fewer number of bits. In at least one embodiment, conversion manager 104 is to perform one or more quantization operations (e.g., using processor 110 and / or processors 122) to transform one or more values from one data format into another format. In at least one embodiment, data conversion manager 104 is to use scaling module 106 to scale one or more data values. In at least one embodiment, scaling may be performed before converting (e.g., by quantizing) a value to a data format. In at least one embodiment, scaling may be performed subsequent to converting (e.g., by quantizing) a value to a data format.

[0068] In at least one embodiment, converting one or more values from one format to another format may be performed subsequent to an operation using these one or more values. In at least one embodiment, for example, one or more values may be organized in an array (e.g., a tensor generated as a result of a matrix multiplication operation) that are transformed (e.g., converted) from a first data format to another format. In at least one embodiment, converting one or more values from a first data format to a second data format (e.g., using data conversion manager 104) may be performed subsequent to performing an operation using these one or more values but before these one or more values have been stored (e.g., written to memory). In at least one embodiment, for example, one or more values may be transformed from a first data format to a second data format while values are in one or more registers (e.g., result registers) used by one or more operations, such as matrix multiplication.

[0069] In at least one embodiment, data conversion manager 104 is to partition an input array, into one or more portions. In at least one embodiment, for example, data conversion manager 104 is to partition an input matrix into n sub-matrices. In at least one embodiment, data conversion manager 104 may partition an input array into one or more portions, where a size and / or number of theses portions is selected, or otherwise calculated, based on a size and / or amount of data that is able to be stored within a particular device, such as cores 118, storage device 120, and / or storage device 114. In at least one embodiment, data conversion manger 104 may store (e.g., buffer) a portion of an input array of values. In at least one embodiment, for example, data conversion manger 104 may store (e.g., buffer) a portion of an input array of values that is produced from a preceding operator (e.g., an output of a layernorm layer of machine learning model(s) 108). In at least one embodiment, data conversion manager 104 may identify a scale value (e.g., using scaling module 106) for a portion of an array of values.In at least one embodiment, data conversion manager 104 may calculate a scaling factor to be used to scale one or more values of a sub-matrix of an input matrix based on these values in said sub-matrix. In at least one embodiment, for example, data conversion manager 104 may use scaling module 106 to identify a largest value of one or more values in a sub-matrix of an input matrix and use this largest value (“local maximum”) to calculate a scale factor (“local scale factor”) that is to be used to scale these values of this sub-matrix. In at least one embodiment, for example, data conversion manager 104 may use scaling module 106 to identify a smallest value, mean, average, median, mode, or other value of one or more values in a sub-matrix of an input matrix and use such value (“local maximum”) to calculate a scale factor (“local scale factor”) that is to be used to scale these values of this sub-matrix. In at least one embodiment, for example, data conversion manager 104 may use scaling module 106 to combine one or more scaling values with one or more offset values, constant values, adjustment values, threshold values, and / or other suitable value that is to be used to scale the values of a sub-matrix. In at least one embodiment, for example, data conversion manager 104 may use scaling module 106 to identify a largest observed value of one or more values in a sub-matrix of an input matrix and use this largest observed value (“running maximum”) to calculate a scale factor (“local scale factor”) that is to be used to scale these values of this sub-matrix. In at least one embodiment, for example, data conversion manager 104 may use scaling module 106 to identify a largest observed value of one or more values in a first sub-matrix of an input matrix and use this largest value to estimate one or more largest values corresponding to one or more other sub-matrices of said input matrix that can then be used to calculate a scale factor that is to be used to scale these values of these other sub-matrices. In at least one embodiment, data conversion manager 104 may use scaling module 106 to scale one or more values of a portion of an array based on a scaling factor identified in association with said portion. In at least one embodiment, data conversion manager 104, after scaling values in a sub-matrix by a local scale factor, may cause these partially quantized values in this sub-matrix to be stored in memory (e.g., storage device 114 and / or storage device 120) in a quantized format, such as FP8. In at least one embodiment, once one or more sub-matrices have been scaled using respective scaling factors (local scaling factors), one or more of these sub-matrices may be rescaled using a different scaling factor. In at least one embodiment, for example, once one or more submatrices have been scaled, quantized, and / or stored to memory, these sub-matrices may be read from memory in their quantized form (e.g., FP8), scaled again using an adjust scale factor, and written back to memory in their quantized form. In at least one embodiment, an adjusted scale factor may be calculated based on values in an input matrix that is to be scaled. In at least oneembodiment, for example, based on a maximum data value in a matrix (“global maximum”), and adjusted scaled factor may be identified and used to rescale one or more values of this matrix.

[0070] In at least one embodiment, scaling module 106 comprises one or more components configured to identify one or more scaling values with which to scale one or more data values and / or scale one or more data values. In at least one embodiment, scaling module 106 is to access one or more portions (sub-matrix) of an input array of values (e.g., matrix), calculate (e.g., using processor 110 and / or processors 122) one or more scaling factors, and / or apply one or more scaling factors to scale one or more values in an input array. In at least one embodiment, for example, an input matrix A is partitioned into n disjoint sub-matrices, A =(e.g., using data conversion manager 104), for while one or more scale factors may be calculated. In at least one embodiment, for each sub-matrix in^, a local scaling factor can be calculated:is a scaling factor to be applied to scale sub-matrix d^andis a scaling factor to be applied to scale sub-matrix ^4^:where A is a partially quantized sub-matrix d^and A^ is a partially quantized sub-matrix

[0071] In at least one embodiment, scaling module 106 may rescale one or more portions of a matrix that have previously been scaled (e.g., using a local scaling factor). In at least one embodiment, scaling module 106 may rescaled one or more sub-matrices that have previously been scaled. In at least one embodiment, scaling module 106 calculates a global scale factor, sA, by identifying a maximum of all sub-matrix scales factors: sA= max (s^\ , s^\ In at least one embodiment, using both global and local scale factors, matrix^ can be expressed:

[0072] In at least one embodiment, scaling module 106 is to define adjusted scale factors for each portion of an array. In at least one embodiment, for example, scaling module 106 is to define adjusted scale factors for each sub-matrix of matrix 4. In at least one embodiment, an adjusted scaling factor allows a matrix to be rewritten in a form to be efficiently stored and / or operated upon. In at least one embodiment, adjusted scaling factors,may be calculated as:„(1) „(n)„'(1) _ ,(n) _SA A ~ A ~ > sASAallowing matrix A to be rewritten as:

[0073] In at least one embodiment, scaling module 106 is to apply one or more adjusted scale factors to one or more partially-quantized sub-matrices to generate a fully quantized matrix Aq:

[0074] In at least one embodiment, scaling module 106 is to apply two mor more levels of scaling to an array of values, where a first level scales values in said array using scale factors computed locally with respect to each portion of said array, and a second level scales said values to restore an effective global scale factor.

[0075] In at least one embodiment, device 116 includes one or more processing cores 118A- 118Z. In at least one embodiment, cores 118A-118Z are any number of processing cores that suitable for executing parallel processing (e.g., to perform machine learning model(s) 108). In at least one embodiment, cores 118A-118Z are tensor cores. In at least one embodiment, cores 118A-118Z include one or more tensor cores that are further divided into sub-processing units. In at least one embodiment, cores 118A-118Z are further divided into one or more tiles. In at least one embodiment, tiles include one or more vectors of values. In at least one embodiment,one or more tiles making up one or more cores 118 A- 118Z can be operated on single instruction multiple date (SIMD) instructions. In at least one embodiment, cores 118A-118Z include one or more on-chip memories. In at least one embodiment, on-chip memories of cores 118A-118Z are tile sized. In at least one embodiment, on-chip memories of cores 118A-118Z can hold one or more values represented by one or more formats. In at least one embodiment, for example, on-chip memory of one or more of cores 118A-118Z can store values in floating point (FP) 8, FP16, and / or FP32. In at least one embodiment, on-chip memories of one or more cores 11 SA- 118Z can store values in integer (INT) 8, INT 16, and / or INT 32.

[0076] In at least one embodiment, device 102 receives one or more values from storage device 120 as instructed by processors 122 for computation by one or more cores 118A-118Z of device 116. In at least one embodiment, values received by device 102 include one or more vectors, matrices, or tensors. In at least one embodiment, device 102 transmits received values to data conversion manager 104. In at least one embodiment, data conversion manager 104 may directly store one or more values in storage device 114 and / or storage device 120. In at least one embodiment, device 102 may store one or more values in storage device 114 and / or storage device 120. In at least one embodiment, date conversion manager 104 retrieves and / or transmits one or more values to scaling module 106.

[0077] In at least one embodiment, a logic unit includes firmware logic, hardware logic, or some combination thereof configured to provide any function as described further herein. In at least one embodiment, a logic unit includes circuitry that forms part of a larger system (e.g., IC, SoC, CPU, GPU, DPU). In at least one embodiment, a logic unit includes logic circuitry for implementation of firmware and / or hardware.

[0078] In at least one embodiment, an engine includes a module and / or logic unit as described further herein. In at least one embodiment, a component includes a module and / or logic unit as described further herein. In at least one embodiment, an engine includes software logic, firmware logic, hardware logic, or some combination thereof configured to provide any function as described further herein. In at least one embodiment, a component includes software logic, firmware logic, hardware logic, or some combination thereof configured to provide any function as described further herein. In at least one embodiment, operations performed by hardware and / or firmware may alternatively be implemented via a software module, which may be embodied as a software package, code and / or instruction set. In at least one embodiment, a logic unit may also utilize a portion of software to implement its function.

[0079] In at least one embodiment, system 100 is implemented, for example, using one or more parallel computing platforms. In at least one embodiment, system 100 is implemented, for example, using NVIDIA CUDA, OpenCL, OpenGL, TensorFlow, JavaScript, Git, and / or one or more other parallel computing platforms.

[0080] In at least one embodiment, system 100 includes one or more processors, such as processor 110 and / or processors 122. In at least one embodiment system 100 includes a different number of processors (e.g., more than one processor 122 and / or processor 110), not shown for clarity. In at least one embodiment, a processor, such as processor 110 and / or processors 122 is a processor as described below.

[0081] In at least one embodiment, one or more components of system 100 (e.g., device 102, device(s) 116, data conversion manager 104, machine learning model(s) 108, communication manager 112, communication manager 112, storage device 114, storage device 120, processor 110, and / or processors 122) is implemented, for example, using one or more circuits that form part of a larger system (e.g., an integrated circuit (IC), system on-chip (SoC), central processing unit (CPU), graphics processing unit (GPU), data processing unit (DPU), etc.). In at least one embodiment, data conversion manager 104 includes any combination of any type of logic (e.g., software, hardware, firmware) and / or circuitry configured to perform a function as described. In at least one embodiment, software includes software packages, code, programming language, drivers, instructions, instruction sets, or some combination thereof. In at least one embodiment, hardware includes hardwired circuits, programmable circuits, state machine circuits, fixed function circuits, execution unit circuits, firmware with stored instructions executed by programmable circuits, or some combination thereof. In at least one embodiment, one or more components of system 100 (e.g., device 102, device(s) 116, data conversion manager 104, machine learning model(s) 108, communication manager 112, communication manager 112, storage device 114, storage device 120, processor 110, and / or processors 122) includes a logic unit that includes firmware logic, hardware logic, or some combination thereof configured to provide any function as described further herein. In at least one embodiment, a logic unit includes circuitry that forms part of a larger system (e.g., IC, SoC, CPU, GPU, DPU). In at least one embodiment, a logic unit includes logic circuitry for implementation of firmware and / or hardware.

[0082] In at least one embodiment, one or more storage devices, such as storage device 114 and / or storage device 120, is implemented, for example using may cache memory, dynamicrandomly addressable memory (“DRAM”), static randomly addressable memory (“SRAM”), non-volatile memory (e.g., flash memory), or other type of memory storage. In at least one embodiment, storage device 114 and / or storage device 120 is implemented as any form of computer memory suitable for executing embodiments described herein.

[0083] In at least one embodiment, various components of system 100 are interconnected by one or more buses, pipelines, or other communication links. In at least one embodiment, device 102, device(s) 116, storage device 114, storage device 120, processor 110, and / or processors 122 communicates with one another over a connection (not shown), such as a bus. In at least one embodiment, processors 122 is implemented, for example, using a main central processing unit (“CPU”) complex, one or more microprocessors, one or more microcontrollers, one or more graphics processing units (“GPU(s)”), one or more data processing units (“DPU(s)”), and / or other components. In at least one embodiment, a storage device, such as storage device 114 and / or storage device 120, includes memory (e.g., one or more non-transitory processor- readable medium) storing processor executable instructions that when executed using one or more processors, such as processor 110 and / or processors 122, implements data conversion manager 104, scaling module 106, machine learning model(s) 108, communication manager 124, and / or communication manager 112. In at least one embodiment, by way of additional non-limiting examples, memory (e.g., one or more non-transitory processor-readable medium) are implemented, for example, using volatile memory (e.g., dynamic random-access memory (“DRAM”)) and / or nonvolatile memory (e.g., a hard drive, a solid-state device (“SSD”), and / or other component).

[0084] In at least one embodiment, as used in any implementation described herein, unless otherwise clear from context or stated explicitly to contrary, terms such as “module” and nominalized verbs (e.g., data conversion manager 104, scaling module 106, machine learning model(s)108, communication manager 112, and / or communication manager 124) each refers to any combination of software logic, firmware logic, hardware logic, and / or circuitry configured to provide functionality described herein. In at least one embodiment, software may be embodied as a software package, code and / or instruction set or instructions, and “hardware”, as used in any implementation described herein, may include, for example, singly or in any combination, hardwired circuitry, programmable circuitry, state machine circuitry, fixed function circuitry, execution unit circuitry, and / or firmware that stores instructions executed by programmable circuitry. In at least one embodiment, modules may, collectively orindividually, be embodied as circuitry that forms part of a larger system, for example, an integrated circuit (IC), system on-chip (SoC), and so forth.

[0085] In at least one embodiment, machine learning model(s) 108 comprise one or more components configured to perform one or more tasks. In at least one embodiment, machine learning model(s) 108 include one or more models, such as a deep neural network, to perform one or more tasks. In at least one embodiment, machine learning model(s) 108 may include one or more neural network modules that represent portions of a neural network. In at least one embodiment, for example, machine learning model(s) 108 may include a neural network comprising modules that are to cause on or more operations to be performed. In at least one embodiment, a neural network module may be a convolution operations (e.g., ID, 2D, and / or 3D convolution). In at least one embodiment, a neural network module may be an addition module. In at least one embodiment, a neural network module may include one or more fully connected layers of one or more neurons. In at least one embodiment, a neural network module may include one or more functions and / or calculations. In at least one embodiment, a neural network module includes a concatenation operation. In at least one embodiment, machine learning model(s) 108 will accept an input and generate one or more output values, representing a prediction and / or classification. In at least one embodiment, machine learning model(s) 108 may be used in one or more large language models (LLMs).

[0086] In at least one embodiment, components of system 100 communicates (e.g., using a communication manager, such as communication manager 112 and / or communication manager 124) across one or more networks (not depicted) described herein. In at least one embodiment, networks includes a cellular network and / or Internet.

[0087] In at least one embodiment, a communication manager, such as communication manager 112 and / or communication manager 124, may include one or more components and features for communicating across one or more networks, devices, and / or elements of system 100. In at least one embodiment, a communication manager, such as communication manager 112 and / or communication manager 124, is configured to communicate via any number of networks, described herein. In at least one embodiment, a communication manager, such as communication manager 112 and / or communication manager 124, is configured to manage communications received by its respective system (e.g., parameter values, tensors, etc.) and / or provided by a respective system (e.g., parameter values, tensors, etc.), such as amongst any of device 102, device(s) 116, storage device 114, storage device 120, processors 122, and / or othercomponents that may be included in system 100. In at least one embodiment, a communication manager, such as communication manager 112 and / or communication manager 124, may manage communications within a respective system 100.

[0088] FIG. 2 illustrates, in at least one embodiment, an example of tensor scaling 200, according to at least one embodiment. In at least one embodiment, tensor scaling 200 is described in conjunction with FIG. 1. In at least one embodiment, one or more components of system 100 of FIG. 1 are used to perform one or more operations of tensor scaling 200. In at least one embodiment, an input tensor 202 is accessed (e.g., using data conversion manager 104 of FIG. 1). In at least one embodiment, one or more sub-tensors 206A-206N (referred to individually and / or collectively herein as “sub-tensors 206”) are generated 204 using input tensor 202. In at least one embodiment, a number of sub-tensors 206A-208A is generated 204 based on a number of tiles of one or more of cores (e.g., cores 118 of FIG. 1). In at least one embodiment, one or more sub-tensors 206A-208N are generated sequentially. In at least one embodiment, one or more sub-tensors 206A-206N are generated in parallel. In at least one embodiment, a threshold number of sub-tensors 206A-206N are generated. In at least one embodiment, a threshold number of sub-tensors 206A-206N includes a tile size of one or more processors (e.g., cores 118) divided into a size of input tensor 202.

[0089] In at least one embodiment, local maximum values 208A-208N (referred to individually and / or collectively herein as “local maximum values 208”) are identified (e.g., using scaling module 106 of FIG. 1) for each of sub-tensors 206A-208N. In at least one embodiment, local maximum value 208A-208N are written to memory (e.g., storage device 120, storage device 114, and / or on-chip memory of one or more of cores 118A-118Z).

[0090] In at least one embodiment, one or more sub-tensors 206 are scaled to generated scaled sub-tensors 210A-210N (referred to individually and / or collectively herein as “scaled sub-tensors 210”). In at least one embodiment, scaled sub-tensors 206A-206N are scaled using a respective local maximum 208A-208N. In at least one embodiment, scaled sub -tensor 210A- 210N are written to memory such as, storage device 120, storage device 114, and / or on-chip memory of one or more of cores 118A-118Z of FIG. 1.

[0091] In at least one embodiment, one or more scaled sub-tensor 210A-210N are converted (e.g., using data conversion manager 104 of FIG. 1) to converted sub-tensors 212A-212N (referred to individually and / or collectively herein as “converted sub-tensors 212”). In at least one embodiment, converting scaled sub-tensors 210 to converted sub-tensors 212 comprisestransforming scaled sub-tensors 210 from a first data format to a second data format. In at least one embodiment, for example, generating converted sub-tensor 212A-212N includes converting scaled sub-tensor 210A-210N from FP32 to FP8 and / or FP4. In at least one embodiment, for example, generating converted sub-tensor 212A-212N includes converting scaled sub-tensor 210A-210N from FP32 to FP16. In at least one embodiment, converted subtensor 212A-212N is written to memory, such as storage device 120, storage device 114, and / or on-chip memory of one or more of cores 118A-118Z.

[0092] In at least one embodiment, tensor scaling 200 comprises identifying a global maximum 214 value of input tensor 202. In at least one embodiment, a global maximum value is a highest value (greatest magnitude) of all values within input tensor 202. In at least one embodiment, a global maximum value is identified using local maximum values 208A-208N. In at least one embodiment, global maximum value is identified as a highest value of all values of identified local maximum values 208A-208N of sub-tensors 206A-206N.

[0093] In at least one embodiment, converted sub-tensors 212A-212N are read from one or more memory locations, such as storage device 120, storage device 114, and / or on-chip memory of one or more of cores 118A-118Z. In at least one embodiment, one or more converted sub-tensors 212A-212N are scaled and / or rescaled using a global maximum value.

[0094] In at least one embodiment, scaled converted sub-tensors 212A-212N are written to memory, such as storage device 120, storage device 114, and / or on-chip memory of one or more of cores 118A-118Z. In at least one embodiment, scaled converted sub-tensors 212A- 212N are used by one or more of one or more of cores 118A-118Z to use and / or train one or more machine learning model(s) 108.

[0095] In at least one embodiment, one or more machine learning model(s) 108 are used to perform one or more tasks including inference or prediction operations as set forth herein with regards to FIGs 1-43.

[0096] FIG. 3 illustrates, in at least one embodiment, an example of data format conversion 300, according to at least one embodiment. In at least one embodiment, data format conversion 300 is described in conjunction with FIG. 1 and / or FIG. 2. In at least one embodiment, one or more components of system 100 of FIG. 1 are used to perform one or more operations of data format conversion 300. In at least one embodiment, one or more values in a first data format 302 are received, or otherwise accessed (e.g., using data conversion manager 104 of FIG. 1). In at least one embodiment, one or more values in a first data format 302 are accessed usingdata conversion manager 104, device 102, device 116, processor 122, and / or storage device 120 of FIG. 1. In at least one embodiment, values in a first data format include values of input tensor 202 and / or sub-tensors 206A-206N of FIG. 2. In at least one embodiment, scaling module receives value in a first data format 302 and determines a format of received values. In at least one embodiment, a first data format includes but is not limited to FP32, FP16, FP 8, INT32, INTI 6, INT8, and / or one or more mixed precision data formats. In at least one embodiment, for example, in at least one embodiment, scaling module receives sub-tensor 206A. In at least one embodiment, scaling module 106 determines a format of values in subtensor 206A is FP32.

[0097] In at least one embodiment, scaling module 106 performs scaling 304 on one or more values in a first data format 302. In at least one embodiment, scaling module 106 performs scaling using device 102. In at least one embodiment, scaling 304 includes determining a highest value of values of one or more sub-tensors 206A-206N. In at least one embodiment, scaling module 106 scales values of a sub-tensor (e.g., sub-tensors 206A-206N) by dividing all values of this sub-tensor by a highest value of this sub-tensor. For example, in at least one embodiment, scaling module 106 determines sub-tensor 206 A includes ten values and a highest value is 100. In at least one embodiment, scaling module 106 then divides all ten values of a sub tensor by a highest value (e.g., 100). In at least one embodiment, scaling module reads each value, divides each value by a highest value, and writes each scaled value to one or more of storage device 120, storage device 114, and / or on-chip memory of one or more of cores 11 SA- 118Z. In at least one embodiment, sub-tensor values (e.g., sub-tensors 206A-206N) are values in a first data format, scaling module 106 reads sub-tensor values in a first data format, scaling module 106 conducts one or more scaling operations in a first data format, and scaling module 106 writes scaled values in this first data format.

[0098] In at least one embodiment, a scaling operation centers a range of values of a subtensor around a highest value. In at least one embodiment, for example, in a at least one embodiment, if ten values of sub-tensor 206A are 100, 90, 80, 70, 60, 0, 0, 0, 0.1, 0. In at least one embodiment, scaling module 106 will determine a highest value is 100 and will divide all values by a highest value. In at least one embodiment, for example, scaled values are 1, 0.9, 0.8, 0.7, 0.6, 0, 0, 0, 0.001, and 0. In at least one embodiment, for example, an effect of a scaling operation is to center values around a number 1, decreasing a range of values needed to be stored.

[0099] In at least one embodiment, scaling module 106 writes a highest value during a scaling operation to one or more of storage device 120, storage device 114, and / or on-chip memory of one or more of cores 118A-118Z. In at least one embodiment, a highest value used by scaling module 106 as described above is labeled and stored as a local maximum value by scaling module 106.

[0100] In at least one embodiment, scaling module 106 performs one or more data conversions 306. In at least one embodiment, scaling module 106 converts an output of a scaling operation (e.g., scaled values) from a first data format to a second data format. In at least one embodiment, a second data format includes but is not limited to FP32, FP16, FP8, FP4, INT32, INTI 6, INT8 and / or one or more mixed precision data formats. In at least one embodiment, scaling module converts from a first data format to a second data format by reading one or more scaled values in a first data format and writing one or more scaled values in a first data format to a different memory. In at least one embodiment, for example, scaling module 106 receives values of sub-tensor 206A in FP32. In at least one embodiment, for example, scaling module scales values of sub-tensor 206A in FP32 by dividing tensor values by a highest value. In at least one embodiment, for example, scaling module reads a scaled values of sub-tensor 206A and writes them to one or more FP8 memories. In at least one embodiment, scaling module 106 writes a scaled values into one or more FP8 memories located in one or more of storage device 120, storage device 114, and / or on-chip memory of one or more of cores 118 A- 118Z .

[0101] In at least one embodiment, scaling module 106 outputs one or more values in a second data format 308. In at least one embodiment, writing values of one or more subtensor (e.g., sub-tensor 206A) into a lower precision memory (e.g., FP8) generates one or more values in a second data format 308. In at least one embodiment, scaling module 106 converts data from a higher precision format (e.g., FP32) to a less precise format (e.g., FP8 and / or FP4) as described above. In at least one embodiment, scaling module 106 when converting data from a first data format 302 to a second data format 308 speeds up an ability of device 116 to process tensor values by allowing utilization of smaller and faster memories located closer to one or more of cores 118A-118Z. In at least one embodiment, conversion of data by scaling module 106 reduces a size of a data footprint. In at least one embodiment, for example, when a values is in a first data format (e.g., FP32) such format requires 32-bit sized floating point values to be stored in memories capable of holding 32 bit sized data. In at least one embodiment, for example, after conversion by scaling module 106 one or more values now in a second dataformat (e.g., FP8) only require 8 bits. In at least one embodiment, for example, data conversions performed by scaling module 106 reduced a size of memory needed to store one or more tensor values, permits moving data from large but slower memories to smaller and fast memories, and permits movement of data from memories distant from one or more processing cores (e.g., storage device 120) to memories close to one or more processing cores 118A-118Z (e.g., one or more on-chip memories of processing cores 118A-118Z).

[0102] FIG. 4 illustrates, in at least one embodiment, an example of scaling operations 400, according to at least one embodiment. In at least one embodiment, scaling operations 400 are described in conjunction with FIG. 1 and / or FIG. 2. In at least one embodiment, one or more components of system 100 of FIG. 1 are used to perform one or more operations of scaling operations 400. In at least one embodiment, scaling module 106 writes one or more values in a second data format 402 to one or more of storage device 120, storage device 114, and / or on- chip memory of one or more of cores 118A-118Z. In at least one embodiment, scaling module 106 generates one or more values in a second data format as set forth above with regards to FIG. 3.

[0103] In at least one embodiment, scaling module 106 performs data evaluation 403 to identify local maxima data corresponding to values of one or more portions of an array. In at least one embodiment, data evaluation 403 includes reading one or more or all of local maximum values (e.g., local maximum data 208A-208N) written to one or more of storage device 120, storage device 114, and / or on-chip memory of one or more of cores 118A-118Z. In at least one embodiment, scaling module 106 reads one or more of local maximum values as set forth in FIG. 3.

[0104] In at least one embodiment, scaling module 106 reads each local maximum value sequentially. In at least one embodiment, scaling module 106 reads a first local maximum and performs a data comparison 404 between a first local maximum against a next local maximum. If a next local maximum is greater than a first local maximum, then a next local maximum is written to memory and stored as a global maximum value. In at least one embodiment, data comparison 404 comprises comparing each local maximum with a current global maximum, updating a global maximum value whenever a local maximum is greater than a current global maximum.

[0105] In at least one embodiment, scaling module 106 determines one or more global maxima in parallel. In at least one embodiment, data comparison 404 occurs in parallel wherescaling module 106 determines a global maximum as a highest value of one or more of input tensor 202, sub-tensors 206A-206N, scale sub-tensors 210A-210N, and / or converted subtensor 212 A-212N.

[0106] In at least one embodiment, scaling module 106 writes a highest value of input tensor 202 to on one or more of storage device 120, storage device 114, and / or on-chip memory of one or more of cores 118A-118Z. In at least one embodiment, scaling module 106 identifies a largest value of input tensor 202 as a global maximum value.

[0107] In at least one embodiment, scaling module 106 writes a highest value of sub-tensors 206A-206N to on one or more of storage device 120, storage device 114, and / or on-chip memory of one or more of cores 118A-118Z. In at least one embodiment, scaling module 106 identifies a largest value of sub-tensors 206A-206N as a global maximum value.

[0108] In at least one embodiment, scaling module 106 writes a highest value of scale subtensor 21 OA-210N to on one or more of storage device 120, storage device 114, and / or on-chip memory of one or more of cores 118A-118Z. In at least one embodiment, scaling module 106 identifies a largest value of scale sub-tensor 21 OA-210N as a global maximum value.

[0109] In at least one embodiment, scaling module 106 writes a highest value of converted sub-tensor 212 A-212N to on one or more of storage device 120, storage device 114, and / or on- chip memory of one or more of cores 118A-118Z. In at least one embodiment, scaling module 106 identifies a largest value of converted sub-tensor 212A-212N as a global maximum value.

[0110] In at least one embodiment, scaling module 106 determines 405 whether a local maximum value is different from a global maximum value. For each sub-tensor (e.g., subtensors 206A-206N, converted sub-tensor 212A-212N, and / or scale sub-tensor 210A-210N) with a local maximum that is identical to a current global maximum, scaling module 106 identifies that tensor as a tensor that should not be re-scaled (“No” in 405). In at least one embodiment, for tensors that should not be re-scaled 406, scaling module 106 saves these tensor to memory (e.g., one or more of one or more of storage device 120, storage device 114, and / or on-chip memory of one or more of cores 118A-118Z). In at least one embodiment, a saved tensor (e.g., scale with global maximum 216) is used by one or more of one or more of cores 118A-118Z to train one or more machine learning model(s) 108.

[0111] In at least one embodiment, one or more machine learning model(s) 108 are used to perform one or more tasks including inference or prediction operations as set forth herein with regards to FIGs 1-43.

[0112] In at least one embodiment, for each sub-tensor (e.g., sub-tensors 206A-206N, converted sub-tensor 212A-212N, and / or scale sub -tensor 21 OA-2 ION) with a local maximum different from a current global maximum, scaling module 106 identifies that tensor as a tensor to be re-scaled (“Yes” in 405). In at least one embodiment, scaling module 106 re-scales one or more tensors by retrieving a local maximum value from memory, retrieving a global maximum value from memory, generating a global scaling value by dividing a global maximum value by a local maximum value, and dividing values of one or more of these scaled sub-tensors 210A-210N and / or converted sub-tensors 212A-212N by global scaling value.

[0113] In at least one embodiment, scaling module 106 writes re-scaled data 408 to one or more of storage device 120, storage device 114, and / or on-chip memory of one or more of cores 118A-118Z. In at least one embodiment, a saved re-scaled tensor 408 (e.g., scale with global maximum 216) is used by one or more of one or more of cores 118A-118Z to train one or more machine learning model(s) 108. In at least one embodiment, one or more trained machine learning model(s) 108 are used to perform one or more tasks including inference or prediction operations as set forth herein with regards to FIGs 1-43. In at least one embodiment, re-scale tensor 408 is used by one or more of cores 118A-118Z to execute one or more processing tasks, for example, one or more parallel processing operations, one or more general matrix multiply (GEMM) operations, and / or one or more matrix operations.

[0114] FIG. 5 illustrates, in at least one embodiment, an example of operations 500 of one or more scaling modules, according to at least one embodiment. In at least one embodiment, operations 500 are described in conjunction with FIG. 1 and / or FIG. 2. In at least one embodiment, one or more components of system 100 of FIG. 1 are used to perform one or more operations 500. In at least one embodiment, input tensor 502 (e.g., input tensor 202) includes one or more values. In at least one embodiment, input tensor includes four values 5, 100, 10, and 20. In at least one embodiment, although only four values are depicted in input tensor 502, input tensor 502 can include any finite number of values. In at least one embodiment, input tensor 502 values are in a first data format. In at least one embodiment, for example, input tensor 502 values are in FP32 format.

[0115] In at least one embodiment, scaling module 106 receive input tensor 502. In at least one embodiment, scaling module generates one or more sub tenors 504 (e.g., generate subtensors 204). In at least one embodiment, scaling module generates two sub-tensors 504, 506. In at least one embodiment, first generated sub-tensor 504 (e.g., sub-tensor 206A) includes values 5 and 100. In at least one embodiment, scaling module generates second sub-tensor 506 (e.g., sub-tensor 206B) that includes values 10 and 20.

[0116] In at least one embodiment, scaling module 106 identifies a local maximum (e.g., identify local maximum 208A-208N) of sub-tensor 504 as a greatest value of all tensor values of tensor 504. In at least one embodiment, scaling module 106 identifies a local maximum of sub-tensor 504 as 100. In at least one embodiment, scaling module 106 writes local maximum 100 to memory.

[0117] In at least one embodiment, scaling module 106 identifies a local maximum (e.g., identify local maximum 208A-208N) of sub-tensor 506 as a greatest value of all tensor values of tensor 506. In at least one embodiment, scaling module 106 identifies a local maximum of sub-tensor 506 as 20. In at least one embodiment, scaling module 106 writes local maximum 100 to memory.

[0118] In at least one embodiment, scaling module 106 scales sub-tensor 504 (e.g., scale subtensor 210A-210N) by dividing values of sub-tensor 504 by a local maximum value of 100. In at least one embodiment, scaling sub-tensor 504 by scaling module 106 generates a scaled subtensor 508 including values 0.05 and 1.

[0119] In at least one embodiment, scaling module 106 scales sub-tensor 506 (e.g., scale subtensor 210A-210N) by dividing values of sub-tensor 506 by a local maximum value of 20. In at least one embodiment, scaling sub-tensor 506 by scaling module 106 generates a scaled subtensor 510 including values 0.5 and 1.

[0120] In at least one embodiment, scaling module converts (e.g., convert sub-tensor 212A- 212N) scaled sub-tensors 508, 510 to one or more converted sub-tensors 512, 514. In at least one embodiment, scaling module converts scaled sub-tensors 508, 510 to converted sub-tensor 512, 514 by writing scaled sub-tensors 508, 510 to one or more values in a second data format 308. In at least one embodiment, scaling module 106 converts scaled sub-tensors 508, 510 by writing sub-tensors 508, 510 to one or more FP8 memories (e.g., one or more of one or more of storage device 120, storage device 114, and / or on-chip memory of one or more of cores118A-118Z). In at least one embodiment, scaling module converts sub-tensors 508, 510 by writing sub-tensors 508, 510 to one or more on-chip memories.

[0121] In at least one embodiment, scaling module 106 identifies a global maximum value 516 (e.g., identify global maximum 214). In at least one embodiment, scaling module 106 identifies a global maximum as set forth with reference to FIGs 1-4. In at least one embodiment, scaling module 106 compares a local maximum of sub-tensors 504 and 506 and determines a global maximum should be 100.

[0122] In at least one embodiment, scaling module 106 re-scales one or more sub-tensors as set forth with reference to FIGs 1-4. In at least one embodiment, scaling module 106 evaluates sub-tensor 504, determines a local maximum of sub-tensor 504 is not different from a global maximum, and determines sub-tensor 504 should not be re-scaled 516. In at least one embodiment, scaling module 106 evaluates sub-tensor 506, determines a local maximum of sub-tensor 506 is different from a global maximum, and determines sub-tensor 504 should be re-scaled 518.

[0123] In at least one embodiment, scaling module 106 transmits sub-tensor 520 to one or more of data conversion manager 104, storage device 120, processor 122, device 116, and / or cores 118A-118Z.

[0124] In at least one embodiment, scaling module re-scales sub-tensor 514 with a global maximum. In at least one embodiment, scaling module re-scales sub-tensor as set forth above with reference to FIGS. 1-4. In at least one embodiment, scaling module 106 re-scales subtensor 514 by retrieving a local maximum value from memory, retrieving a global maximum value from memory, generating a global scaling value by dividing a global maximum value by a local maximum value, and dividing values of sub-tensor 514 by global scaling value. In at least one embodiment, scaling module re-scales sub-tensor 514 as set forth above and generates sub-tensor 520. In at least one embodiment, scaling module 106 transmits sub-tensor 520 to one or more of data conversion manager 104, storage device 120, processor 122, device 116, and / or cores 118A-118Z.

[0125] In at least one embodiment, each block of method 600, described herein, includes a computing process that may be performed using any combination of hardware, firmware, and / or software. In at least one embodiment, for instance, various functions may be carried out by a processor executing instructions stored in memory. In at least one embodiment, method 600 may also be embodied as computer-usable instructions stored on computer storage media.In at least one embodiment, method 600 may be provided by a standalone application, a service or hosted service (standalone or in combination with another hosted service), or a plug-in to another product, to name a few. In at least one embodiment, in addition, method 600 is described, by way of example, with respect to system 100 of FIG. 1. In at least one embodiment, these methods may additionally or alternatively be executed by any one system, or any combination of systems, including, but not limited to, those described herein.

[0126] FIG. 6 is a flow diagram showing a method 600 to scale values, according to at least one embodiment. In at least one embodiment, method 600, at block 602, includes receiving a threshold number of values into on-chip memory. In at least one embodiment, a threshold number of values is determined by one or more of device 102, scaling module 106, device 116, processors 122, and / or hard coded into system 100. In at least one embodiment, a threshold number of values includes a number of values that can be stored in a tile of one or more of cores 118A-118Z. In at least one embodiment, for example, application of FIG. 1 is to receive, or otherwise access, one or more tensors (e.g., input tensor 202 of FIG. 2) defined by one or more users, device 102, scaling module 106, device 116, and / or processors 122.

[0127] In at least one embodiment, method 600, at block 604, includes determining local maximum values of values stored in on-chip memory. In at least one embodiment, determining local maximum values includes receiving by scaling module 106 one or more sub-tensors containing a threshold number of values as set forth above in reference to FIGs 1-5. In at least one embodiment, scaling module 106 receives one or more sub-tensors 206A-206N and identifies local maximum values (e.g., 208A-208N) as set forth above in reference to FIGS. 1- 5.

[0128] In at least one embodiment, method 600, at block 606, writing local maximum value to memory. In at least one embodiment, writing local maximum value to memory includes scaling one or more sub-tensors by one or more local maximum values. In at least one embodiment, scaling one or more sub-tensors by one or more local maximum values includes identifying a largest value of a sub-tensor, writing a largest value to one or more memories, and dividing each value of this sub-tensor by a maximum value. In at least one embodiment, scaling one or more sub-tensors is set forth above with reference to FIGs 1-5. In at least one embodiment, writing local maximum values to memory includes writing one or more local maximum values to one or more of storage device 120, storage device 114, and / or on-chip memory of one or more of cores 118A-118Z.

[0129] In at least one embodiment, method 600, at block 608, includes determining a global maximum value. In at least one embodiment, determining a global maximum value includes determining a largest value of one or more local maximum values and identifying a largest local maximum value as a global maximum value (e.g., identify global maximum 214). In at least one embodiment, determining a global maximum value is set forth above with reference to FIGs 1-5. In at least one embodiment, scaling module 106 reads one or more local maximum values for one or more sub-tensors, determines a largest local maximum value, and identifies a largest local maximum value as a global maximum value.

[0130] In at least one embodiment, method 600, at block 610, includes re-scaling local maximum values by global maximum value. In at least one embodiment, re-scaling local maximum values includes re-scaling one or more tensors by retrieving a local maximum value from memory, retrieving a global maximum value from memory, generating a global scaling value by dividing a global maximum value by a local maximum value, and dividing values of one or more of scale sub-tensors 210A-210N and / or converted sub-tensors 212A-212N by global scaling value. In at least one embodiment, re-scaling local maximum values is set forth in reference to FIGs 1-5.

[0131] In at least one embodiment, method 600, at block 612, includes writing re-scale values to memory. In at least one embodiment, writing re-scale values to memory includes writing any re-scaled tensors to memory. In at least one embodiment, writing re-scale values to memory is set forth in reference to FIGs 1-5. In at least one embodiment, upon writing re-scale values to memory method 600 may terminate 614.

[0132] In at least one embodiment, each block of method 700, described herein, includes a computing process that may be performed using any combination of hardware, firmware, and / or software. In at least one embodiment, for instance, various functions may be carried out by a processor executing instructions stored in memory. In at least one embodiment, method 700 may also be embodied as computer-usable instructions stored on computer storage media. In at least one embodiment, method 600 may be provided by a standalone application, a service or hosted service (standalone or in combination with another hosted service), or a plug-in to another product, to name a few. In at least one embodiment, in addition, method 700 is described, by way of example, with respect to system 100 of FIG. 1. In at least one embodiment, these methods may additionally or alternatively be executed by any one system, or any combination of systems, including, but not limited to, those described herein.

[0133] FIG. 7 is a flow diagram showing a method 700 to scale values, according to at least one embodiment. In at least one embodiment, method 700, at block 702, includes receiving a threshold number of values into on-chip memory. In at least one embodiment, a threshold number of values is determined by one or more of device 102, scaling module 106, device 116, processors 122, and / or hard coded into system 100. In at least one embodiment, a threshold number of values includes a number of values that can be stored in a tile of one or more of cores 118A-118Z. In at least one embodiment, for example, application of FIG. 1 is to receive, or otherwise access, one or more tensors (e.g., input tensor 202 of FIG. 2) defined by one or more users, device 102, scaling module 106, device 116, and / or processors 122.

[0134] In at least one embodiment, method 700, at block 704, includes determining local maximum values of values stored in on-chip memory. In at least one embodiment, determining local maximum values includes receiving by scaling module 106 one or more sub-tensors containing a threshold number of values as set forth above in reference to FIGs 1-5. In at least one embodiment, scaling module 106 receives one or more sub-tensors 206A-206N and identifies local maximum values (e.g., 208A-208N) as set forth above in reference to FIGS. 1- 6.

[0135] In at least one embodiment, method 700, at block 706, writing local maximum value to memory. In at least one embodiment, writing local maximum value to memory includes scaling one or more sub-tensors by one or more local maximum values. In at least one embodiment, scaling one or more sub-tensors by one or more local maximum values includes identifying a largest value of a sub-tensor, writing a largest value to one or more memories, and dividing each value of a sub-tensor by a maximum value. In at least one embodiment, scaling one or more sub-tensors is set forth above with reference to FIGs 1-6. In at least one embodiment, writing local maximum values to memory includes writing one or more local maximum values to one or more of storage device 120, storage device 114, and / or on-chip memory of one or more of cores 118A-118Z.

[0136] In at least one embodiment, method 700, at block 708, includes determining a global maximum value. In at least one embodiment, determining a global maximum value includes determining a largest value of one or more local maximum values and identifying a largest local maximum value as a global maximum value (e.g., identify global maximum 214). In at least one embodiment, determining a global maximum value is set forth above with reference to FIGs 1-6. In at least one embodiment, scaling module 106 reads one or more local maximumvalues for one or more sub-tensors, determines a largest local maximum value, and identifies a largest local maximum value as a global maximum value.

[0137] In at least one embodiment, method 700, at block 710, execute consuming operation. In at least one embodiment, execute consuming operation includes using one or more subtensors by one or more one or more of cores 118 A- 118Z and re-scaling one or more sub-tensors in a same operation. In at least one embodiment, scaling module 106 identifies one or more sub-tensors to be transmitted to one or more cores 118A-118Z, generates a global scaling value by dividing a global maximum value by a local maximum value for an identified sub-tensor, and transmits said identified sub-tensor and global scaling value to one or more cores 1 ISA- 118Z. In at least one embodiment, execute consuming operation is set forth above with reference to FIGs 1-6.

[0138] In at least one embodiment, cores 118A-118Z re-scales a transmitted sub-tensor by a transmitted global scaling value and uses this re-scaled sub-tensor to carry out one or more operations. In at least one embodiment, cores 118A-118Z carry out one or more operations as set forth with reference to FIGS. 1-6 and / or 8-43. In at least one embodiment, method 700 is terminated 712.

[0139] FIG. 8 illustrates an example 800 of a processor, according to at least one embodiment. In at least one embodiment, a processor 802 performs one or more processes such as those described with reference to FIGS. 1-7 to generate one or more scaled values using one or more circuits to cause a largest value in each portion of two or more portions of an array to be identified and to use said largest value of each portion to scale one or more values within each portion sequentially.

[0140] In at least one embodiment, processor 802 comprises one or more processors such as those described in connection with FIGS. 1-7 and / or 8-43. In at least one embodiment, processor 800 is any suitable processing unit or combination of processing units, such as one or more CPUs, GPUs, GPGPUs, or PPUs. In at least one embodiment, processor 802 comprises one or more software program(s), a conversion module 822, and / or scaling module 824. In at least one embodiment, conversion module 822, and / or scaling module 824, are part of one or more other processors. In at least one embodiment, conversion module 822, and / or scaling module 824 are distributed among multiple processors that communicate over a bus, network, by writing to shared memory, or any suitable communication process such as, for example, those described with reference to FIGS. 1-7 and / or 8-43.

[0141] In at least one embodiment, conversion module 822 comprises circuits to cause one or more data vales to be transformed from a first data format into a second data format, e.g., as illustrated in FIGS. 1-7.

[0142] In at least one embodiment, scaling module 824 comprises circuits to cause one or more data vales to be scaled using one or more calculated scaling factors, e.g., as illustrated in FIGS. 1-7.LOGIC

[0143] FIG. 9A illustrates logic 915 which, as described elsewhere herein, can be used in one or more devices to perform operations such as those discussed herein in accordance with at least one embodiment. In at least one embodiment, logic 915 is used to perform inferencing and / or training operations associated with one or more embodiments. In at least one embodiment, logic 915 is inference and / or training logic. Details regarding logic 915 are provided below in conjunction with FIGS. 9A and / or 9B. In at least one embodiment, logic refers to any combination of software logic, hardware logic, and / or firmware logic to provide functionality or operations described herein, wherein logic may be, collectively or individually, embodied as circuitry that forms part of a larger system, for example, an integrated circuit (IC), system-on-chip (SoC), or one or processors (e.g., CPU, GPU).

[0144] In at least one embodiment, logic 915 may include, without limitation, code and / or data storage 901 to store forward and / or output weight and / or input / output data, and / or other parameters to configure neurons or layers of a neural network trained and / or used for inferencing in aspects of one or more embodiments. In at least one embodiment, logic 915 may include, or be coupled to code and / or data storage 901 to store graph code or other software to control timing and / or order, in which weight and / or other parameter information is to be loaded to configure, logic, including integer and / or floating point units (collectively, arithmetic logic units (ALUs)). In at least one embodiment, code, such as graph code, loads weight or other parameter information into processor ALUs based on an architecture of a neural network to which such code corresponds. In at least one embodiment, code and / or data storage 901 stores weight parameters and / or input / output data of each layer of a neural network trained or used in conjunction with one or more embodiments during forward propagation of input / output data and / or weight parameters during training and / or inferencing using aspects of one or more embodiments. In at least one embodiment, any portion of code and / or data storage 901 may beincluded with other on-chip or off-chip data storage, including a processor’s LI, L2, or L3 cache or system memory.

[0145] In at least one embodiment, any portion of code and / or data storage 901 may be internal or external to one or more processors or other hardware logic devices or circuits. In at least one embodiment, code and / or code and / or data storage 901 may be cache memory, dynamic randomly addressable memory (“DRAM”), static randomly addressable memory (“SRAM”), non-volatile memory (e.g., flash memory), or other storage. In at least one embodiment, a choice of whether code and / or code and / or data storage 901 is internal or external to a processor, for example, or comprising DRAM, SRAM, flash or some other storage type may depend on available storage on-chip versus off-chip, latency requirements of training and / or inferencing functions being performed, batch size of data used in inferencing and / or training of a neural network, or some combination of these factors.

[0146] In at least one embodiment, logic 915 may include, without limitation, a code and / or data storage 905 to store backward and / or output weight and / or input / output data corresponding to neurons or layers of a neural network trained and / or used for inferencing in aspects of one or more embodiments. In at least one embodiment, code and / or data storage 905 stores weight parameters and / or input / output data of each layer of a neural network trained or used in conjunction with one or more embodiments during backward propagation of input / output data and / or weight parameters during training and / or inferencing using aspects of one or more embodiments. In at least one embodiment, logic 915 may include, or be coupled to code and / or data storage 905 to store graph code or other software to control timing and / or order, in which weight and / or other parameter information is to be loaded to configure, logic, including integer and / or floating point units (collectively, arithmetic logic units (ALUs)).

[0147] In at least one embodiment, code, such as graph code, causes the loading of weight or other parameter information into processor ALUs based on an architecture of a neural network to which such code corresponds. In at least one embodiment, any portion of code and / or data storage 905 may be included with other on-chip or off-chip data storage, including a processor’s LI, L2, or L3 cache or system memory. In at least one embodiment, any portion of code and / or data storage 905 may be internal or external to one or more processors or other hardware logic devices or circuits. In at least one embodiment, code and / or data storage 905 may be cache memory, DRAM, SRAM, non-volatile memory (e.g., flash memory), or other storage. In at least one embodiment, a choice of whether code and / or data storage 905 is internalor external to a processor, for example, or comprising DRAM, SRAM, flash memory or some other storage type may depend on available storage on-chip versus off-chip, latency requirements of training and / or inferencing functions being performed, batch size of data used in inferencing and / or training of a neural network, or some combination of these factors.

[0148] In at least one embodiment, code and / or data storage 901 and code and / or data storage 905 may be separate storage structures. In at least one embodiment, code and / or data storage 901 and code and / or data storage 905 may be a combined storage structure. In at least one embodiment, code and / or data storage 901 and code and / or data storage 905 may be partially combined and partially separate. In at least one embodiment, any portion of code and / or data storage 901 and code and / or data storage 905 may be included with other on-chip or off-chip data storage, including a processor’s LI, L2, or L3 cache or system memory.

[0149] In at least one embodiment, logic 915 may include, without limitation, one or more arithmetic logic unit(s) (“ALU(s)”) 910, including integer and / or floating point units, to perform logical and / or mathematical operations based, at least in part on, or indicated by, training and / or inference code (e.g., graph code), a result of which may produce activations (e.g., output values from layers or neurons within a neural network) stored in an activation storage 920 that are functions of input / output and / or weight parameter data stored in code and / or data storage 901 and / or code and / or data storage 905. In at least one embodiment, activations stored in activation storage 920 are generated according to linear algebraic and or matrix-based mathematics performed by ALU(s) 910 in response to performing instructions or other code, wherein weight values stored in code and / or data storage 905 and / or data storage 901 are used as operands along with other values, such as bias values, gradient information, momentum values, or other parameters or hyperparameters, any or all of which may be stored in code and / or data storage 905 or code and / or data storage 901 or another storage on or off- chip.

[0150] In at least one embodiment, ALU(s) 910 are included within one or more processors or other hardware logic devices or circuits, whereas in another embodiment, ALU(s) 910 may be external to a processor or other hardware logic device or circuit that uses them (e.g., a coprocessor). In at least one embodiment, ALUs 910 may be included within a processor’s execution units or otherwise within a bank of ALUs accessible by a processor’s execution units either within same processor or distributed between different processors of different types (e.g., central processing units, graphics processing units, fixed function units, etc.). In at least oneembodiment, code and / or data storage 901, code and / or data storage 905, and activation storage 920 may share a processor or other hardware logic device or circuit, whereas in another embodiment, they may be in different processors or other hardware logic devices or circuits, or some combination of same and different processors or other hardware logic devices or circuits. In at least one embodiment, any portion of activation storage 920 may be included with other on-chip or off-chip data storage, including a processor’s LI, L2, or L3 cache or system memory. Furthermore, inferencing and / or training code may be stored with other code accessible to a processor or other hardware logic or circuit and fetched and / or processed using a processor’s fetch, decode, scheduling, execution, retirement and / or other logical circuits.

[0151] In at least one embodiment, activation storage 920 may be cache memory, DRAM, SRAM, non-volatile memory (e.g., flash memory), or other storage. In at least one embodiment, activation storage 920 may be completely or partially within or external to one or more processors or other logical circuits. In at least one embodiment, a choice of whether activation storage 920 is internal or external to a processor, for example, or comprising DRAM, SRAM, flash memory or some other storage type may depend on available storage on-chip versus off-chip, latency requirements of training and / or inferencing functions being performed, batch size of data used in inferencing and / or training of a neural network, or some combination of these factors.

[0152] In at least one embodiment, logic 915 illustrated in FIG. 9A may be used in conjunction with an application-specific integrated circuit (“ASIC”), such as a TensorFlow® Processing Unit from Google, an inference processing unit (IPU) from Graphcore™, or a Nervana® (e.g., “Lake Crest”) processor from Intel Corp. In at least one embodiment, logic 915 illustrated in FIG. 9 A may be used in conjunction with central processing unit (“CPU”) hardware, graphics processing unit (“GPU’) hardware or other hardware, such as field programmable gate arrays (“FPGAs”).

[0153] In at least one embodiment, at least one component shown or described with respect to FIG. 9A is utilized to implement techniques and / or functions described in connection with FIGS. 1-8. In at least one embodiment, at least one component of FIG. 9A is used to cause generation of an API, parameters, libraries, runtimes, drivers, kernels, distributing kernels to one or more GPUs, and to cause execution of a kernel on one or more GPUs. In at least one embodiment, at least one component of FIG. 9A performs at least one aspect described with respect to data scaling system 100, device 102, data conversion manager 104,scaling module 106, machine learning modules 108, processors 110, communication manager 112, storage device 114, devices 116, cores 118A-118Z, storage device 120, processors 122, tensor scaling 200, input tensor 202, generate sub-tensor 204, sub-tensors 206A-206N, identify local maximum 208A-208N, scaled sub-tensor 21 OA-210N, converted sub -tensor 212A-212N, identify global maximum 214, scale with global maximum 216, data format conversion 300, values in first data format 320, scaling 304, data conversions 306, values in second data format 308, scaling operations 400, values in second data format 402, data evaluation 403, data comparison 404, global maximum determination 405, no data re-scale 406, data re-scale 408, operations of one or more scaling modules 500, method 600, method 700, processor 800, processor 820, conversion module 822, and / or scaling module 824.

[0154] FIG. 9B illustrates logic 915, according to at least one embodiment. In at least one embodiment, logic 915 is inference and / or training logic. In at least one embodiment, logic 915 may include, without limitation, hardware logic in which computational resources are dedicated or otherwise exclusively used in conjunction with weight values or other information corresponding to one or more layers of neurons within a neural network. In at least one embodiment, logic 915 illustrated in FIG. 9B may be used in conjunction with an applicationspecific integrated circuit (ASIC), such as TensorFlow® Processing Unit from Google, an inference processing unit (IPU) from Graphcore™, or a Nervana® (e.g., “Lake Crest”) processor from Intel Corp. In at least one embodiment, logic 915 illustrated in FIG. 9B may be used in conjunction with central processing unit (CPU) hardware, graphics processing unit (GPU) hardware or other hardware, such as field programmable gate arrays (FPGAs). In at least one embodiment, logic 915 includes, without limitation, code and / or data storage 901 and code and / or data storage 905, which may be used to store code (e.g., graph code), weight values and / or other information, including bias values, gradient information, momentum values, and / or other parameter or hyperparameter information. In at least one embodiment illustrated in FIG. 9B, each of code and / or data storage 901 and code and / or data storage 905 is associated with a dedicated computational resource, such as computational hardware 902 and computational hardware 906, respectively. In at least one embodiment, each of computational hardware 902 and computational hardware 906 comprises one or more ALUs that perform mathematical functions, such as linear algebraic functions, only on information stored in code and / or data storage 901 and code and / or data storage 905, respectively, result of which is stored in activation storage 920.

[0155] In at least one embodiment, each of code and / or data storage 901 and 905 and corresponding computational hardware 902 and 906, respectively, correspond to different layers of a neural network, such that resulting activation from one storage / computational pair 901 / 902 of code and / or data storage 901 and computational hardware 902 is provided as an input to a next storage / computational pair 905 / 906 of code and / or data storage 905 and computational hardware 906, in order to mirror a conceptual organization of a neural network. In at least one embodiment, each of storage / computational pairs 901 / 902 and 905 / 906 may correspond to more than one neural network layer. In at least one embodiment, additional storage / computation pairs (not shown) subsequent to or in parallel with storage / computation pairs 901 / 902 and 905 / 906 may be included in logic 915.

[0156] In at least one embodiment, at least one component shown or described with respect to FIG. 9B is utilized to implement techniques and / or functions described in connection with FIGS. 1-8. In at least one embodiment, at least one component of FIG. 9B is used to cause generation of an API, parameters, libraries, runtimes, drivers, kernels, distributing kernels to one or more GPUs, and to cause execution of a kernel on one or more GPUs. In at least one embodiment, at least one component of FIG. 9B performs at least one aspect described with respect to data scaling system 100, device 102, data conversion manager 104, scaling module 106, machine learning modules 108, processors 110, communication manager 112, storage device 114, devices 116, cores 118A-118Z, storage device 120, processors 122, tensor scaling 200, input tensor 202, generate sub-tensor 204, sub-tensors 206A-206N, identify local maximum 208A-208N, scaled sub-tensor 210A-210N, converted sub-tensor 212A-212N, identify global maximum 214, scale with global maximum 216, data format conversion 300, values in first data format 320, scaling 304, data conversions 306, values in second data format 308, scaling operations 400, values in second data format 402, data evaluation 403, data comparison 404, global maximum determination 405, no data re-scale 406, data re-scale 408, operations of one or more scaling modules 500, method 600, method 700, processor 800, processor 820, conversion module 822, and / or scaling module 824.NEURAL NETWORK TRAINING AND DEPLOYMENT

[0157] FIG. 10 illustrates training and deployment of a deep neural network, according to at least one embodiment. In at least one embodiment, untrained neural network 1006 is trained using a training dataset 1002. In at least one embodiment, training framework 1004 is a PyTorch framework, whereas in other embodiments, training framework 1004 is a TensorFlow, Boost, Caffe, Microsoft Cognitive Toolkit / CNTK, MXNet, Chainer, Keras, Deepi eaming4j, orother training framework. In at least one embodiment, training framework 1004 trains an untrained neural network 1006 and enables it to be trained using processing resources described herein to generate a trained neural network 1008. In at least one embodiment, weights may be chosen randomly or by pre-training using a deep belief network. In at least one embodiment, training may be performed in either a supervised, partially supervised, or unsupervised manner.

[0158] In at least one embodiment, untrained neural network 1006 is trained using supervised learning, wherein training dataset 1002 includes an input paired with a desired output for an input, or where training dataset 1002 includes input having a known output and an output of neural network 1006 is manually graded. In at least one embodiment, untrained neural network 1006 is trained in a supervised manner and processes inputs from training dataset 1002 and compares resulting outputs against a set of expected or desired outputs. In at least one embodiment, errors are then propagated back through untrained neural network 1006. In at least one embodiment, training framework 1004 adjusts weights that control untrained neural network 1006. In at least one embodiment, training framework 1004 includes tools to monitor how well untrained neural network 1006 is converging towards a model, such as trained neural network 1008, suitable to generating correct answers, such as in result 1014, based on input data such as a new dataset 1012. In at least one embodiment, training framework 1004 trains untrained neural network 1006 repeatedly while adjusting weights to refine an output of untrained neural network 1006 using a loss function and adjustment algorithm, such as stochastic gradient descent. In at least one embodiment, training framework 1004 trains untrained neural network 1006 until untrained neural network 1006 achieves a desired accuracy. In at least one embodiment, trained neural network 1008 can then be deployed to implement any number of machine learning operations.

[0159] In at least one embodiment, untrained neural network 1006 is trained using unsupervised learning, wherein untrained neural network 1006 attempts to train itself using unlabeled data. In at least one embodiment, unsupervised learning training dataset 1002 will include input data without any associated output data or “ground truth” data. In at least one embodiment, untrained neural network 1006 can learn groupings within training dataset 1002 and can determine how individual inputs are related to untrained dataset 1002. In at least one embodiment, unsupervised training can be used to generate a self-organizing map in trained neural network 1008 capable of performing operations useful in reducing dimensionality of new dataset 1012. In at least one embodiment, unsupervised training can also be used toperform anomaly detection, which allows identification of data points in new dataset 1012 that deviate from normal patterns of new dataset 1012.

[0160] In at least one embodiment, semi-supervised learning may be used, which is a technique in which in training dataset 1002 includes a mix of labeled and unlabeled data. In at least one embodiment, training framework 1004 may be used to perform incremental learning, such as through transferred learning techniques. In at least one embodiment, incremental learning enables trained neural network 1008 to adapt to new dataset 1012 without forgetting knowledge instilled within trained neural network 1008 during initial training.

[0161] In at least one embodiment, training framework 1004 is a framework processed in connection with a software development toolkit such as an Open VINO (Open Visual Inference and Neural network Optimization) toolkit. In at least one embodiment, an Open VINO toolkit is a toolkit such as those developed by Intel Corporation of Santa Clara, CA. In at least one embodiment, Open VINO comprises logic 915 or uses logic 915 to perform operations described herein. In at least one embodiment, an SoC, integrated circuit, or processor uses Open VINO to perform operations described herein.

[0162] In at least one embodiment, Open VINO is a toolkit for facilitating development of applications, specifically neural network applications, for various tasks and operations, such as human vision emulation, speech recognition, natural language processing, recommendation systems, and / or variations thereof. In at least one embodiment, Open VINO supports neural networks such as convolutional neural networks (CNNs), recurrent and / or attention-based neural networks, and / or various other neural network models. In at least one embodiment, Open VINO supports various software libraries such as OpenCV, OpenCL, and / or variations thereof.

[0163] In at least one embodiment, Open VINO supports neural network models for various tasks and operations, such as classification, segmentation, object detection, face recognition, speech recognition, pose estimation (e.g., humans and / or objects), monocular depth estimation, image inpainting, style transfer, action recognition, colorization, and / or variations thereof.

[0164] In at least one embodiment, Open VINO comprises one or more software tools and / or modules for model optimization, also referred to as a model optimizer. In at least one embodiment, a model optimizer is a command line tool that facilitates transitions between training and deployment of neural network models. In at least one embodiment, a model optimizer optimizes neural network models for execution on various devices and / or processingunits, such as a GPU, CPU, PPU, GPGPU, and / or variations thereof. In at least one embodiment, a model optimizer generates an internal representation of a model, and optimizes said model to generate an intermediate representation. In at least one embodiment, a model optimizer reduces a number of layers of a model. In at least one embodiment, a model optimizer removes layers of a model that are utilized for training. In at least one embodiment, a model optimizer performs various neural network operations, such as modifying inputs to a model (e.g., resizing inputs to a model), modifying a size of inputs of a model (e.g., modifying a batch size of a model), modifying a model structure (e.g., modifying layers of a model), normalization, standardization, quantization (e.g., converting weights of a model from a first representation, such as floating point, to a second representation, such as integer), and / or variations thereof.

[0165] In at least one embodiment, Open VINO comprises one or more software libraries for inferencing, also referred to as an inference engine. In at least one embodiment, an inference engine is a C++ library, or any suitable programming language library. In at least one embodiment, an inference engine is utilized to infer input data. In at least one embodiment, an inference engine implements various classes to infer input data and generate one or more results. In at least one embodiment, an inference engine implements one or more API functions to process an intermediate representation, set input and / or output formats, and / or execute a model on one or more devices.

[0166] In at least one embodiment, Open VINO provides various abilities for heterogeneous execution of one or more neural network models. In at least one embodiment, heterogeneous execution, or heterogeneous computing, refers to one or more computing processes and / or systems that utilize one or more types of processors and / or cores. In at least one embodiment, Open VINO provides various software functions to execute a program on one or more devices. In at least one embodiment, Open VINO provides various software functions to execute a program and / or portions of a program on different devices. In at least one embodiment, Open VINO provides various software functions to, for example, run a first portion of code on a CPU and a second portion of code on a GPU and / or FPGA. In at least one embodiment, Open VINO provides various software functions to execute one or more layers of a neural network on one or more devices (e.g., a first set of layers on a first device, such as a GPU, and a second set of layers on a second device, such as a CPU).

[0167] In at least one embodiment, Open VINO includes various functionality similar to functionalities associated with a CUDA programming model, such as various neural network model operations associated with frameworks such as TensorFlow, PyTorch, and / or variations thereof. In at least one embodiment, one or more CUDA programming model operations are performed using Open VINO. In at least one embodiment, various systems, methods, and / or techniques described herein are implemented using Open VINO.

[0168] In at least one embodiment, at least one component shown or described with respect to FIG. 10 is utilized to implement techniques and / or functions described in connection with FIGS. 1-8. In at least one embodiment, at least one component of FIG. 10 is used to cause generation of an API, parameters, libraries, runtimes, drivers, kernels, distributing kernels to one or more GPUs, and to cause execution of a kernel on one or more GPUs. In at least one embodiment, at least one component of FIG. 10 performs at least one aspect described with respect to data scaling system 100, device 102, data conversion manager 104, scaling module 106, machine learning modules 108, processors 110, communication manager 112, storage device 114, devices 116, cores 118A-118Z, storage device 120, processors 122, tensor scaling 200, input tensor 202, generate sub-tensor 204, sub-tensors 206A-206N, identify local maximum 208A-208N, scaled sub-tensor 210A-210N, converted sub-tensor 212A-212N, identify global maximum 214, scale with global maximum 216, data format conversion 300, values in first data format 320, scaling 304, data conversions 306, values in second data format 308, scaling operations 400, values in second data format 402, data evaluation 403, data comparison 404, global maximum determination 405, no data re-scale 406, data re-scale 408, operations of one or more scaling modules 500, method 600, method 700, processor 800, processor 820, conversion module 822, and / or scaling module 824.DATA CENTER

[0169] FIG. 11 illustrates an example data center 1100, in which at least one embodiment may be used. In at least one embodiment, data center 1100 includes a data center infrastructure layer 1110, a framework layer 1120, a software layer 1130 and an application layer 1140.

[0170] In at least one embodiment, as shown in FIG. 11 , data center infrastructure layer 1110 may include a resource orchestrator 1112, grouped computing resources 1114, and node computing resources (“node C.R.s”) 1116(1 )- 1116(N), where “N” represents a positive integer (which may be a different integer “N” than used in other figures). In at least one embodiment, node C.R.s 1116(1)-1116(N) may include, but are not limited to, any number of centralprocessing units (“CPUs”) or other processors (including accelerators, field programmable gate arrays (FPGAs), graphics processors, etc.), memory storage devices 1118(1)-1118(N) (e.g., dynamic read-only memory, solid state storage or disk drives), network input / output (“NW I / O”) devices, network switches, virtual machines (“VMs”), power modules, and cooling modules, etc. In at least one embodiment, one or more node C.R.s from among node C.R.s 1116(1)-1116(N) may be a server having one or more of above-mentioned computing resources.

[0171] In at least one embodiment, grouped computing resources 1114 may include separate groupings of node C.R.s housed within one or more racks (not shown), or many racks housed in data centers at various geographical locations (also not shown). In at least one embodiment, separate groupings of node C.R.s within grouped computing resources 1114 may include grouped compute, network, memory, or storage resources that may be configured or allocated to support one or more workloads. In at least one embodiment, several node C.R.s including CPUs or processors may be grouped within one or more racks to provide compute resources to support one or more workloads. In at least one embodiment, one or more racks may also include any number of power modules, cooling modules, and network switches, in any combination.

[0172] In at least one embodiment, resource orchestrator 1112 may configure or otherwise control one or more node C.R.s 1116(1)-1116(N) and / or grouped computing resources 1114. In at least one embodiment, resource orchestrator 1112 may include a software design infrastructure (“SDI”) management entity for data center 1100. In at least one embodiment, resource orchestrator 912 may include hardware, software or some combination thereof.

[0173] In at least one embodiment, as shown in FIG. 11, framework layer 1120 includes a job scheduler 1122, a configuration manager 1124, a resource manager 1126 and a distributed file system 1128. In at least one embodiment, framework layer 1120 may include a framework to support software 1132 of software layer 1130 and / or one or more application(s) 1142 of application layer 1140. In at least one embodiment, software 1132 or application(s) 1142 may respectively include web-based service software or applications, such as those provided by Amazon Web Services, Google Cloud and Microsoft Azure. In at least one embodiment, framework layer 1120 may be, but is not limited to, a type of free and open-source software web application framework such as Apache Spark™ (hereinafter “Spark”) that may utilize distributed file system 1128 for large-scale data processing (e.g., “big data”). In at least one embodiment, job scheduler 1122 may include a Spark driver to facilitate scheduling ofworkloads supported by various layers of data center 1100. In at least one embodiment, configuration manager 1124 may be capable of configuring different layers such as software layer 1130 and framework layer 1120 including Spark and distributed file system 1128 for supporting large-scale data processing. In at least one embodiment, resource manager 1126 may be capable of managing clustered or grouped computing resources mapped to or allocated for support of distributed file system 1128 and job scheduler 1122. In at least one embodiment, clustered or grouped computing resources may include grouped computing resources 1114 at data center infrastructure layer 1110. In at least one embodiment, resource manager 1126 may coordinate with resource orchestrator 1112 to manage these mapped or allocated computing resources.

[0174] In at least one embodiment, software 1132 included in software layer 1130 may include software used by at least portions of node C.R.s 1116(1)-1116(N), grouped computing resources 1114, and / or distributed file system 1128 of framework layer 1120. In at least one embodiment, one or more types of software may include, but are not limited to, Internet web page search software, e-mail virus scan software, database software, and streaming video content software.

[0175] In at least one embodiment, application(s) 1142 included in application layer 1140 may include one or more types of applications used by at least portions of node C.R.s 1116(1)- 1116(N), grouped computing resources 1114, and / or distributed file system 1128 of framework layer 1120. In at least one embodiment, one or more types of applications may include, but are not limited to, any number of a genomics application, a cognitive compute, application and a machine learning application, including training or inferencing software, machine learning framework software (e.g., PyTorch, TensorFlow, Caffe, etc.) or other machine learning applications used in conjunction with one or more embodiments.

[0176] In at least one embodiment, any of configuration manager 1124, resource manager 1126, and resource orchestrator 1112 may implement any number and type of self-modifying actions based on any amount and type of data acquired in any technically feasible fashion. In at least one embodiment, self-modifying actions may relieve a data center operator of data center 1100 from making possibly bad configuration decisions and possibly avoiding underutilized and / or poor performing portions of a data center.

[0177] In at least one embodiment, data center 1100 may include tools, services, software, or other resources to train one or more machine learning models or predict or infer informationusing one or more machine learning models according to one or more embodiments described herein. For example, in at least one embodiment, a machine learning model may be trained by calculating weight parameters according to a neural network architecture using software and computing resources described above with respect to data center 1100. In at least one embodiment, trained machine learning models corresponding to one or more neural networks may be used to infer or predict information using resources described above with respect to data center 1100 by using weight parameters calculated through one or more training techniques described herein.

[0178] In at least one embodiment, data center may use CPUs, application-specific integrated circuits (ASICs), GPUs, FPGAs, or other hardware to perform training and / or inferencing using above-described resources. Moreover, one or more software and / or hardware resources described above may be configured as a service to allow users to train or performing inferencing of information, such as image recognition, speech recognition, or other artificial intelligence services.

[0179] Logic 915 are used to perform inferencing and / or training operations associated with one or more embodiments. Details regarding logic 915 are provided herein in conjunction with FIGS. 9A and / or 9B. In at least one embodiment, logic 915 may be used in data center 1100 for inferencing or predicting operations based, at least in part, on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0180] In at least one embodiment, at least one component shown or described with respect to FIG. 11 is utilized to implement techniques and / or functions described in connection with FIGS. 1-8. In at least one embodiment, at least one component of FIG. 11 is used to cause generation of an API, parameters, libraries, runtimes, drivers, kernels, distributing kernels to one or more GPUs, and to cause execution of a kernel on one or more GPUs. In at least one embodiment, at least one component of FIG. 11 performs at least one aspect described with respect to data scaling system 100, device 102, data conversion manager 104, scaling module 106, machine learning modules 108, processors 110, communication manager 112, storage device 114, devices 116, cores 118A-118Z, storage device 120, processors 122, tensor scaling 200, input tensor 202, generate sub-tensor 204, sub-tensors 206A-206N, identify local maximum 208A-208N, scaled sub-tensor 210A-210N, converted sub-tensor 212A-212N, identify global maximum 214, scale with global maximum 216, data format conversion 300,values in first data format 320, scaling 304, data conversions 306, values in second data format 308, scaling operations 400, values in second data format 402, data evaluation 403, data comparison 404, global maximum determination 405, no data re-scale 406, data re-scale 408, operations of one or more scaling modules 500, method 600, method 700, processor 800, processor 820, conversion module 822, and / or scaling module 824.AUTONOMOUS VEHICLE

[0181] FIG. 12A illustrates an example of an autonomous vehicle 1200, according to at least one embodiment. In at least one embodiment, autonomous vehicle 1200 (alternatively referred to herein as “vehicle 1200”) may be, without limitation, a passenger vehicle, such as a car, a truck, a bus, and / or another type of vehicle that accommodates one or more passengers. In at least one embodiment, vehicle 1200 may be a semi-tractor-trailer truck used for hauling cargo. In at least one embodiment, vehicle 1200 may be an airplane, robotic vehicle, or other kind of vehicle.

[0182] Autonomous vehicles may be described in terms of automation levels, defined by National Highway Traffic Safety Administration (“NHTSA”), a division of US Department of Transportation, and Society of Automotive Engineers (“SAE”) “Taxonomy and Definitions for Terms Related to Driving Automation Systems for On-Road Motor Vehicles” (e.g., Standard No. J3016-201806, published on June 15, 2018, Standard No. J3016-201609, published on September 30, 2016, and previous and future versions of this standard). In at least one embodiment, vehicle 1200 may be capable of functionality in accordance with one or more of Level 1 through Level 5 of autonomous driving levels. For example, in at least one embodiment, vehicle 1200 may be capable of conditional automation (Level 3), high automation (Level 4), and / or full automation (Level 5), depending on embodiment.

[0183] In at least one embodiment, vehicle 1200 may include, without limitation, components such as a chassis, a vehicle body, wheels (e.g., 2, 4, 6, 8, 18, etc.), tires, axles, and other components of a vehicle. In at least one embodiment, vehicle 1200 may include, without limitation, a propulsion system 1250, such as an internal combustion engine, hybrid electric power plant, an all-electric engine, and / or another propulsion system type. In at least one embodiment, propulsion system 1250 may be connected to a drive train of vehicle 1200, which may include, without limitation, a transmission, to enable propulsion of vehicle 1200. In at least one embodiment, propulsion system 1250 may be controlled in response to receiving signals from a throttle / accelerator(s) 1252.

[0184] In at least one embodiment, a steering system 1254, which may include, without limitation, a steering wheel, is used to steer vehicle 1200 (e.g., along a desired path or route) when propulsion system 1250 is operating (e.g., when vehicle 1200 is in motion). In at least one embodiment, steering system 1254 may receive signals from steering actuator(s) 1256. In at least one embodiment, a steering wheel may be optional for full automation (Level 5) functionality. In at least one embodiment, a brake sensor system 1246 may be used to operate vehicle brakes in response to receiving signals from brake actuator(s) 1248 and / or brake sensors.

[0185] In at least one embodiment, controlled s) 1236, which may include, without limitation, one or more system on chips (“SoCs”) (not shown in FIG. 12A) and / or graphics processing unit(s) (“GPU(s)”), provide signals (e.g., representative of commands) to one or more components and / or systems of vehicle 1200. For instance, in at least one embodiment, controller(s) 1236 may send signals to operate vehicle brakes via brake actuator(s) 1248, to operate steering system 1254 via steering actuator(s) 1256, to operate propulsion system 1250 via throttle / accelerator(s) 1252. In at least one embodiment, controller(s) 1236 may include one or more onboard (e.g., integrated) computing devices that process sensor signals, and output operation commands (e.g., signals representing commands) to enable autonomous driving and / or to assist a human driver in driving vehicle 1200. In at least one embodiment, controller(s) 1236 may include a first controller for autonomous driving functions, a second controller for functional safety functions, a third controller for artificial intelligence functionality (e.g., computer vision), a fourth controller for infotainment functionality, a fifth controller for redundancy in emergency conditions, and / or other controllers. In at least one embodiment, a single controller may handle two or more of above functionalities, two or more controllers may handle a single functionality, and / or any combination thereof.

[0186] In at least one embodiment, controlled s) 1236 provide signals for controlling one or more components and / or systems of vehicle 1200 in response to sensor data received from one or more sensors (e.g., sensor inputs). In at least one embodiment, sensor data may be received from, for example and without limitation, global navigation satellite systems (“GNSS”) sensor(s) 1258 (e.g., Global Positioning System sensor(s)), RADAR sensor(s) 1260, ultrasonic sensor(s) 1262, LIDAR sensor(s) 1264, inertial measurement unit (“IMU”) sensor(s) 1266 (e.g., accelerometer(s), gyroscope(s), a magnetic compass or magnetic compasses, magnetometer(s), etc.), microphone(s) 1296, stereo camera(s) 1268, wide-view camera(s) 1270 (e.g., fisheye cameras), infrared camera(s) 1272, surround camera(s) 1274 (e.g., 360 degreecameras), long-range cameras (not shown in FIG. 12 A), mid-range camera(s) (not shown in FIG. 12A), speed sensor(s) 1244 (e.g., for measuring speed of vehicle 1200), vibration sensor(s) 1242, steering sensor(s) 1240, brake sensor(s) (e.g., as part of brake sensor system 1246), and / or other sensor types.

[0187] In at least one embodiment, one or more of controller(s) 1236 may receive inputs (e.g., represented by input data) from an instrument cluster 1232 of vehicle 1200 and provide outputs (e.g., represented by output data, display data, etc.) via a human-machine interface (“HMI”) display 1234, an audible annunciator, a loudspeaker, and / or via other components of vehicle 1200. In at least one embodiment, outputs may include information such as vehicle velocity, speed, time, map data (e.g., a High Definition map (not shown in FIG. 12A)), location data (e.g., vehicle’s 1200 location, such as on a map), direction, location of other vehicles (e.g., an occupancy grid), information about objects and status of objects as perceived by controller(s) 1236, etc. For example, in at least one embodiment, HMI display 1234 may display information about presence of one or more objects (e.g., a street sign, caution sign, traffic light changing, etc.), and / or information about driving maneuvers vehicle has made, is making, or will make (e.g., changing lanes now, taking exit 34B in two miles, etc.).

[0188] In at least one embodiment, vehicle 1200 further includes a network interface 1224 which may use wireless antenna(s) 1226 and / or modem(s) to communicate over one or more networks. For example, in at least one embodiment, network interface 1224 may be capable of communication over Long-Term Evolution (“LTE”), Wideband Code Division Multiple Access (“WCDMA”), Universal Mobile Telecommunications System (“UMTS”), Global System for Mobile communication (“GSM”), IMT-CDMA Multi-Carrier (“CDMA2000”) networks, etc. In at least one embodiment, wireless antenna(s) 1226 may also enable communication between objects in environment (e.g., vehicles, mobile devices, etc.), using local area network(s), such as Bluetooth, Bluetooth Low Energy (“LE”), Z-Wave, ZigBee, etc., and / or low power wide-area network(s) (“LPWANs”), such as LoRaWAN, SigFox, etc. protocols.

[0189] Logic 915 are used to perform inferencing and / or training operations associated with one or more embodiments. Details regarding logic 915 are provided herein in conjunction with FIGS. 9A and / or 9B. In at least one embodiment, logic 915 may be used in vehicle 1200 for inferencing or predicting operations based, at least in part, on weight parameters calculatedusing neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0190] In at least one embodiment, at least one component shown or described with respect to FIG. 12A is utilized to implement techniques and / or functions described in connection with FIGS. 1-8. In at least one embodiment, at least one component of FIG. 12A is used to cause generation of an API, parameters, libraries, runtimes, drivers, kernels, distributing kernels to one or more GPUs, and to cause execution of a kernel on one or more GPUs. In at least one embodiment, at least one component of FIG. 12 A performs at least one aspect described with respect to data scaling system 100, device 102, data conversion manager 104, scaling module 106, machine learning modules 108, processors 110, communication manager 112, storage device 114, devices 116, cores 118A-118Z, storage device 120, processors 122, tensor scaling 200, input tensor 202, generate sub-tensor 204, sub-tensors 206A-206N, identify local maximum 208A-208N, scaled sub-tensor 21 OA-210N, converted sub -tensor 212A-212N, identify global maximum 214, scale with global maximum 216, data format conversion 300, values in first data format 320, scaling 304, data conversions 306, values in second data format 308, scaling operations 400, values in second data format 402, data evaluation 403, data comparison 404, global maximum determination 405, no data re-scale 406, data re-scale 408, operations of one or more scaling modules 500, method 600, method 700, processor 800, processor 820, conversion module 822, and / or scaling module 824.

[0191] FIG. 12B illustrates an example of camera locations and fields of view for autonomous vehicle 1200 of FIG. 12A, according to at least one embodiment. In at least one embodiment, cameras and respective fields of view are one example embodiment and are not intended to be limiting. For instance, in at least one embodiment, additional and / or alternative cameras may be included and / or cameras may be located at different locations on vehicle 1200.

[0192] In at least one embodiment, camera types for cameras may include, but are not limited to, digital cameras that may be adapted for use with components and / or systems of vehicle 1200. In at least one embodiment, camera(s) may operate at automotive safety integrity level (“ASIL”) B and / or at another ASIL. In at least one embodiment, camera types may be capable of any image capture rate, such as 60 frames per second (fps), 1220 fps, 240 fps, etc., depending on embodiment. In at least one embodiment, cameras may be capable of using rolling shutters, global shutters, another type of shutter, or a combination thereof. In at least one embodiment, color filter array may include a red clear clear clear (“RCCC”) color filter array, a red clearclear blue (“RCCB”) color filter array, a red blue green clear (“RBGC”) color filter array, a Foveon X3 color filter array, a Bayer sensors (“RGGB”) color filter array, a monochrome sensor color filter array, and / or another type of color filter array. In at least one embodiment, clear pixel cameras, such as cameras with an RCCC, an RCCB, and / or an RBGC color filter array, may be used in an effort to increase light sensitivity.

[0193] In at least one embodiment, one or more of camera(s) may be used to perform advanced driver assistance systems (“ADAS”) functions (e.g., as part of a redundant or failsafe design). For example, in at least one embodiment, a Multi-Function Mono Camera may be installed to provide functions including lane departure warning, traffic sign assist and intelligent headlamp control. In at least one embodiment, one or more of camera(s) (e.g., all cameras) may record and provide image data (e.g., video) simultaneously.

[0194] In at least one embodiment, one or more cameras may be mounted in a mounting assembly, such as a custom designed (three-dimensional (“3D”) printed) assembly, in order to cut out stray light and reflections from within vehicle 1200 (e.g., reflections from dashboard reflected in windshield mirrors) which may interfere with camera image data capture abilities. With reference to wing-mirror mounting assemblies, in at least one embodiment, wing-mirror assemblies may be custom 3D printed so that a camera mounting plate matches a shape of a wing-mirror. In at least one embodiment, camera(s) may be integrated into wing-mirrors. In at least one embodiment, for side-view cameras, camera(s) may also be integrated within four pillars at each comer of a cabin.

[0195] In at least one embodiment, cameras with a field of view that include portions of an environment in front of vehicle 1200 (e.g., front-facing cameras) may be used for surround view, to help identify forward facing paths and obstacles, as well as aid in, with help of one or more of controlled s) 1236 and / or control SoCs, providing information critical to generating an occupancy grid and / or determining preferred vehicle paths. In at least one embodiment, frontfacing cameras may be used to perform many similar ADAS functions as LIDAR, including, without limitation, emergency braking, pedestrian detection, and collision avoidance. In at least one embodiment, front-facing cameras may also be used for ADAS functions and systems including, without limitation, Lane Departure Warnings (“LDW”), Autonomous Cruise Control (“ACC”), and / or other functions such as traffic sign recognition.

[0196] In at least one embodiment, a variety of cameras may be used in a front-facing configuration, including, for example, a monocular camera platform that includes a CMOS(“complementary metal oxide semiconductor”) color imager. In at least one embodiment, a wide-view camera 1270 may be used to perceive objects coming into view from a periphery (e.g., pedestrians, crossing traffic or bicycles). Although only one wide-view camera 1270 is illustrated in FIG. 12B, in other embodiments, there may be any number (including zero) wide- view cameras on vehicle 1200. In at least one embodiment, any number of long-range camera(s) 1298 (e.g., a long-view stereo camera pair) may be used for depth-based object detection, especially for objects for which a neural network has not yet been trained. In at least one embodiment, long-range camera(s) 1298 may also be used for object detection and classification, as well as basic object tracking.

[0197] In at least one embodiment, any number of stereo camera(s) 1268 may also be included in a front-facing configuration. In at least one embodiment, one or more of stereo camera(s) 1268 may include an integrated control unit comprising a scalable processing unit, which may provide a programmable logic (“FPGA”) and a multi -core micro-processor with an integrated Controller Area Network (“CAN”) or Ethernet interface on a single chip. In at least one embodiment, such a unit may be used to generate a 3D map of an environment of vehicle 1200, including a distance estimate for all points in an image. In at least one embodiment, one or more of stereo camera(s) 1268 may include, without limitation, compact stereo vision sensor(s) that may include, without limitation, two camera lenses (one each on left and right) and an image processing chip that may measure distance from vehicle 1200 to target object and use generated information (e.g., metadata) to activate autonomous emergency braking and lane departure warning functions. In at least one embodiment, other types of stereo camera(s) 1268 may be used in addition to, or alternatively from, those described herein.

[0198] In at least one embodiment, cameras with a field of view that include portions of environment to sides of vehicle 1200 (e.g., side-view cameras) may be used for surround view, providing information used to create and update an occupancy grid, as well as to generate side impact collision warnings. For example, in at least one embodiment, surround camera(s) 1274 (e.g., four surround cameras as illustrated in FIG. 12B) could be positioned on vehicle 1200. In at least one embodiment, surround camera(s) 1274 may include, without limitation, any number and combination of wide-view cameras, fisheye camera(s), 360 degree camera(s), and / or similar cameras. For instance, in at least one embodiment, four fisheye cameras may be positioned on a front, a rear, and sides of vehicle 1200. In at least one embodiment, vehicle 1200 may use three surround camera(s) 1274 (e.g., left, right, and rear), and may leverage one or more other camera(s) (e.g., a forward-facing camera) as a fourth surround-view camera.

[0199] In at least one embodiment, cameras with a field of view that include portions of an environment behind vehicle 1200 (e.g., rear-view cameras) may be used for parking assistance, surround view, rear collision warnings, and creating and updating an occupancy grid. In at least one embodiment, a wide variety of cameras may be used including, but not limited to, cameras that are also suitable as a front-facing camera(s) (e.g., long-range cameras 1298 and / or midrange camera(s) 1276, stereo camera(s) 1268, infrared camera(s) 1272, etc.,) as described herein.

[0200] In at least one embodiment, at least one component shown or described with respect to FIG. 12B is utilized to implement techniques and / or functions described in connection with FIGS. 1-8. In at least one embodiment, at least one component of FIG. 12B is used to cause generation of an API, parameters, libraries, runtimes, drivers, kernels, distributing kernels to one or more GPUs, and to cause execution of a kernel on one or more GPUs. In at least one embodiment, at least one component of FIG. 12B performs at least one aspect described with respect to data scaling system 100, device 102, data conversion manager 104, scaling module 106, machine learning modules 108, processors 110, communication manager 112, storage device 114, devices 116, cores 118A-118Z, storage device 120, processors 122, tensor scaling 200, input tensor 202, generate sub-tensor 204, sub-tensors 206A-206N, identify local maximum 208A-208N, scaled sub-tensor 21 OA-210N, converted sub -tensor 212A-212N, identify global maximum 214, scale with global maximum 216, data format conversion 300, values in first data format 320, scaling 304, data conversions 306, values in second data format 308, scaling operations 400, values in second data format 402, data evaluation 403, data comparison 404, global maximum determination 405, no data re-scale 406, data re-scale 408, operations of one or more scaling modules 500, method 600, method 700, processor 800, processor 820, conversion module 822, and / or scaling module 824.

[0201] FIG. 12C is a block diagram illustrating an example system architecture for autonomous vehicle 1200 of FIG. 12A, according to at least one embodiment. In at least one embodiment, each of components, features, and systems of vehicle 1200 in FIG. 12C is illustrated as being connected via a bus 1202. In at least one embodiment, bus 1202 may include, without limitation, a CAN data interface (alternatively referred to herein as a “CAN bus”). In at least one embodiment, a CAN may be a network inside vehicle 1200 used to aid in control of various features and functionality of vehicle 1200, such as actuation of brakes, acceleration, braking, steering, windshield wipers, etc. In at least one embodiment, bus 1202 may be configured to have dozens or even hundreds of nodes, each with its own uniqueidentifier (e.g., a CAN ID). In at least one embodiment, bus 1202 may be read to find steering wheel angle, ground speed, engine revolutions per minute (“RPMs”), button positions, and / or other vehicle status indicators. In at least one embodiment, bus 1202 may be a CAN bus that is ASIL B compliant.

[0202] In at least one embodiment, in addition to, or alternatively from CAN, FlexRay and / or Ethernet protocols may be used. In at least one embodiment, there may be any number of busses forming bus 1202, which may include, without limitation, zero or more CAN busses, zero or more FlexRay busses, zero or more Ethernet busses, and / or zero or more other types of busses using different protocols. In at least one embodiment, two or more busses may be used to perform different functions, and / or may be used for redundancy. For example, a first bus may be used for collision avoidance functionality and a second bus may be used for actuation control. In at least one embodiment, each bus of bus 1202 may communicate with any of components of vehicle 1200, and two or more busses of bus 1202 may communicate with corresponding components. In at least one embodiment, each of any number of system(s) on chip(s) (“SoC(s)”) 1204 (such as SoC 1204(A) and SoC 1204(B)), each of controller(s) 1236, and / or each computer within vehicle may have access to same input data (e.g., inputs from sensors of vehicle 1200), and may be connected to a common bus, such CAN bus.

[0203] In at least one embodiment, vehicle 1200 may include one or more controller(s) 1236, such as those described herein with respect to FIG. 12 A. In at least one embodiment, controller(s) 1236 may be used for a variety of functions. In at least one embodiment, controller(s) 1236 may be coupled to any of various other components and systems of vehicle 1200, and may be used for control of vehicle 1200, artificial intelligence of vehicle 1200, infotainment for vehicle 1200, and / or other functions.

[0204] In at least one embodiment, vehicle 1200 may include any number of SoCs 1204. In at least one embodiment, each of SoCs 1204 may include, without limitation, central processing units (“CPU(s)”) 1206, graphics processing units (“GPU(s)”) 1208, processor(s) 1210, cache(s) 1212, accelerator(s) 1214, data store(s) 1216, and / or other components and features not illustrated. In at least one embodiment, SoC(s) 1204 may be used to control vehicle 1200 in a variety of platforms and systems. For example, in at least one embodiment, SoC(s) 1204 may be combined in a system (e.g., system of vehicle 1200) with a High Definition (“HD”) map 1222 which may obtain map refreshes and / or updates via network interface 1224 from one or more servers (not shown in FIG. 12C).

[0205] In at least one embodiment, CPU(s) 1206 may include a CPU cluster or CPU complex (alternatively referred to herein as a “CCPLEX”). In at least one embodiment, CPU(s) 1206 may include multiple cores and / or level two (“L2”) caches. For instance, in at least one embodiment, CPU(s) 1206 may include eight cores in a coherent multi-processor configuration. In at least one embodiment, CPU(s) 1206 may include four dual-core clusters where each cluster has a dedicated L2 cache (e.g., a 2 megabyte (MB) L2 cache). In at least one embodiment, CPU(s) 1206 (e.g., CCPLEX) may be configured to support simultaneous cluster operations enabling any combination of clusters of CPU(s) 1206 to be active at any given time.

[0206] In at least one embodiment, one or more of CPU(s) 1206 may implement power management capabilities that include, without limitation, one or more of following features: individual hardware blocks may be clock-gated automatically when idle to save dynamic power; each core clock may be gated when such core is not actively executing instructions due to execution of Wait for Interrupt (“WFI”) / Wait for Event (“WFE”) instructions; each core may be independently power-gated; each core cluster may be independently clock-gated when all cores are clock-gated or power-gated; and / or each core cluster may be independently powergated when all cores are power-gated. In at least one embodiment, CPU(s) 1206 may further implement an enhanced algorithm for managing power states, where allowed power states and expected wakeup times are specified, and hardware / microcode determines which best power state to enter for core, cluster, and CCPLEX. In at least one embodiment, processing cores may support simplified power state entry sequences in software with work offloaded to microcode.

[0207] In at least one embodiment, GPU(s) 1208 may include an integrated GPU (alternatively referred to herein as an “iGPU”). In at least one embodiment, GPU(s) 1208 may be programmable and may be efficient for parallel workloads. In at least one embodiment, GPU(s) 1208 may use an enhanced tensor instruction set. In at least one embodiment, GPU(s) 1208 may include one or more streaming microprocessors, where each streaming microprocessor may include a level one (“LI”) cache (e.g., an LI cache with at least 96 KB storage capacity), and two or more streaming microprocessors may share an L2 cache (e.g., an L2 cache with a 512 KB storage capacity). In at least one embodiment, GPU(s) 1208 may include at least eight streaming microprocessors. In at least one embodiment, GPU(s) 1208 may use compute application programming interface(s) (API(s)). In at least one embodiment, GPU(s) 1208 may use one or more parallel computing platforms and / or programming models (e g., NVIDIA’s CUD A model).

[0208] In at least one embodiment, one or more of GPU(s) 1208 may be power-optimized for best performance in automotive and embedded use cases. For example, in at least one embodiment, GPU(s) 1208 could be fabricated on Fin field-effect transistor (“FinFET”) circuitry. In at least one embodiment, each streaming microprocessor may incorporate a number of mixed-precision processing cores partitioned into multiple blocks. For example, and without limitation, 64 PF32 cores and 32 FP64 cores could be partitioned into four processing blocks. In at least one embodiment, each processing block could be allocated 16 FP32 cores, 8 FP64 cores, 16 INT32 cores, two mixed-precision NVIDIA Tensor cores for deep learning matrix arithmetic, a level zero (“L0”) instruction cache, a scheduler (e.g., warp scheduler) or sequencer, a dispatch unit, and / or a 64 KB register file. In at least one embodiment, streaming microprocessors may include independent parallel integer and floating-point data paths to provide for efficient execution of workloads with a mix of computation and addressing calculations. In at least one embodiment, streaming microprocessors may include independent thread scheduling capability to enable finer-grain synchronization and cooperation between parallel threads. In at least one embodiment, streaming microprocessors may include a combined LI data cache and shared memory unit in order to improve performance while simplifying programming.

[0209] In at least one embodiment, one or more of GPU(s) 1208 may include a high bandwidth memory (“HBM”) and / or a 16 GB HBM2 memory subsystem to provide, in some examples, about 900 GB / second peak memory bandwidth. In at least one embodiment, in addition to, or alternatively from, HBM memory, a synchronous graphics random-access memory (“SGRAM”) may be used, such as a graphics double data rate type five synchronous random-access memory (“GDDR5”).

[0210] In at least one embodiment, GPU(s) 1208 may include unified memory technology. In at least one embodiment, address translation services (“ATS”) support may be used to allow GPU(s) 1208 to access CPU(s) 1206 page tables directly. In at least one embodiment, embodiment, when a GPU of GPU(s) 1208 memory management unit (“MMU”) experiences a miss, an address translation request may be transmitted to CPU(s) 1206. In response, 2 CPU of CPU(s) 1206 may look in its page tables for a virtual-to-physical mapping for an address and transmit translation back to GPU(s) 1208, in at least one embodiment. In at least one embodiment, unified memory technology may allow a single unified virtual address space for memory of both CPU(s) 1206 and GPU(s) 1208, thereby simplifying GPU(s) 1208 programming and porting of applications to GPU(s) 1208.

[0211] In at least one embodiment, GPU(s) 1208 may include any number of access counters that may keep track of frequency of access of GPU(s) 1208 to memory of other processors. In at least one embodiment, access counter(s) may help ensure that memory pages are moved to physical memory of a processor that is accessing pages most frequently, thereby improving efficiency for memory ranges shared between processors.

[0212] In at least one embodiment, one or more of SoC(s) 1204 may include any number of cache(s) 1212, including those described herein. For example, in at least one embodiment, cache(s) 1212 could include a level three (“L3”) cache that is available to both CPU(s) 1206 and GPU(s) 1208 (e.g., that is connected to CPU(s) 1206 and GPU(s) 1208). In at least one embodiment, cache(s) 1212 may include a write-back cache that may keep track of states of lines, such as by using a cache coherence protocol (e.g., MEI, MESI, MSI, etc.). In at least one embodiment, a L3 cache may include 4 MB of memory or more, depending on embodiment, although smaller cache sizes may be used.

[0213] In at least one embodiment, one or more of SoC(s) 1204 may include one or more accelerator(s) 1214 (e.g., hardware accelerators, software accelerators, or a combination thereof). In at least one embodiment, SoC(s) 1204 may include a hardware acceleration cluster that may include optimized hardware accelerators and / or large on-chip memory. In at least one embodiment, large on-chip memory (e.g., 4 MB of SRAM), may enable a hardware acceleration cluster to accelerate neural networks and other calculations. In at least one embodiment, a hardware acceleration cluster may be used to complement GPU(s) 1208 and to off-load some of tasks of GPU(s) 1208 (e.g., to free up more cycles of GPU(s) 1208 for performing other tasks). In at least one embodiment, accelerator s) 1214 could be used for targeted workloads (e.g., perception, convolutional neural networks (“CNNs”), recurrent neural networks (“RNNs”), etc.) that are stable enough to be amenable to acceleration. In at least one embodiment, a CNN may include a region-based or regional convolutional neural networks (“RCNNs”) and Fast RCNNs (e.g., as used for object detection) or other type of CNN.

[0214] In at least one embodiment, accelerator(s) 1214 (e.g., hardware acceleration cluster) may include one or more deep learning accelerator (“DLA”). In at least one embodiment, DLA(s) may include, without limitation, one or more Tensor processing units (“TPUs”) that may be configured to provide an additional ten trillion operations per second for deep learning applications and inferencing. In at least one embodiment, TPUs may be accelerators configured to, and optimized for, performing image processing functions (e.g., for CNNs, RCNNs, etc.).In at least one embodiment, DLA(s) may further be optimized for a specific set of neural network types and floating point operations, as well as inferencing. In at least one embodiment, design of DLA(s) may provide more performance per millimeter than a typical general-purpose GPU, and typically vastly exceeds performance of a CPU. In at least one embodiment, TPU(s) may perform several functions, including a single-instance convolution function, supporting, for example, INT8, INTI 6, and FP16 data types for both features and weights, as well as postprocessor functions. In at least one embodiment, DLA(s) may quickly and efficiently execute neural networks, especially CNNs, on processed or unprocessed data for any of a variety of functions, including, for example and without limitation: a CNN for object identification and detection using data from camera sensors; a CNN for distance estimation using data from camera sensors; a CNN for emergency vehicle detection and identification and detection using data from microphones; a CNN for facial recognition and vehicle owner identification using data from camera sensors; and / or a CNN for security and / or safety related events.

[0215] In at least one embodiment, DLA(s) may perform any function of GPU(s) 1208, and by using an inference accelerator, for example, a designer may target either DLA(s) or GPU(s) 1208 for any function. For example, in at least one embodiment, a designer may focus processing of CNNs and floating point operations on DLA(s) and leave other functions to GPU(s) 1208 and / or accelerator s) 1214.

[0216] In at least one embodiment, accelerator(s) 1214 may include programmable vision accelerator (“PVA”), which may alternatively be referred to herein as a computer vision accelerator. In at least one embodiment, PVA may be designed and configured to accelerate computer vision algorithms for advanced driver assistance system (“ADAS”) 1238, autonomous driving, augmented reality (“AR”) applications, and / or virtual reality (“VR”) applications. In at least one embodiment, PVA may provide a balance between performance and flexibility. For example, in at least one embodiment, each PVA may include, for example and without limitation, any number of reduced instruction set computer (“RISC”) cores, direct memory access (“DMA”), and / or any number of vector processors.

[0217] In at least one embodiment, RISC cores may interact with image sensors (e.g., image sensors of any cameras described herein), image signal processor(s), etc. In at least one embodiment, each RISC core may include any amount of memory. In at least one embodiment, RISC cores may use any of a number of protocols, depending on embodiment. In at least one embodiment, RISC cores may execute a real-time operating system (“RTOS”). In at least oneembodiment, RISC cores may be implemented using one or more integrated circuit devices, application specific integrated circuits (“ASICs”), and / or memory devices. For example, in at least one embodiment, RISC cores could include an instruction cache and / or a tightly coupled RAM.

[0218] In at least one embodiment, DMA may enable components of PVA to access system memory independently of CPU(s) 1206. In at least one embodiment, DMA may support any number of features used to provide optimization to a PVA including, but not limited to, supporting multi-dimensional addressing and / or circular addressing. In at least one embodiment, DMA may support up to six or more dimensions of addressing, which may include, without limitation, block width, block height, block depth, horizontal block stepping, vertical block stepping, and / or depth stepping.

[0219] In at least one embodiment, vector processors may be programmable processors that may be designed to efficiently and flexibly execute programming for computer vision algorithms and provide signal processing capabilities. In at least one embodiment, a PVA may include a PVA core and two vector processing subsystem partitions. In at least one embodiment, a PVA core may include a processor subsystem, DMA engine(s) (e.g., two DMA engines), and / or other peripherals. In at least one embodiment, a vector processing subsystem may operate as a primary processing engine of a PVA, and may include a vector processing unit (“VPU”), an instruction cache, and / or vector memory (e.g., “VMEM”). In at least one embodiment, VPU core may include a digital signal processor such as, for example, a single instruction, multiple data (“SIMD”), very long instruction word (“VLIW”) digital signal processor. In at least one embodiment, a combination of SIMD and VLIW may enhance throughput and speed.

[0220] In at least one embodiment, each of vector processors may include an instruction cache and may be coupled to dedicated memory. As a result, in at least one embodiment, each of vector processors may be configured to execute independently of other vector processors. In at least one embodiment, vector processors that are included in a particular PVA may be configured to employ data parallelism. For instance, in at least one embodiment, plurality of vector processors included in a single PVA may execute a common computer vision algorithm, but on different regions of an image. In at least one embodiment, vector processors included in a particular PVA may simultaneously execute different computer vision algorithms, on one image, or even execute different algorithms on sequential images or portions of an image. Inat least one embodiment, among other things, any number of PVAs may be included in hardware acceleration cluster and any number of vector processors may be included in each PVA. In at least one embodiment, PVA may include additional error correcting code (“ECC”) memory, to enhance overall system safety.

[0221] In at least one embodiment, accelerator(s) 1214 may include a computer vision network on-chip and static random-access memory (“SRAM”), for providing a high- bandwidth, low latency SRAM for accelerator(s) 1214. In at least one embodiment, on-chip memory may include at least 4 MB SRAM, comprising, for example and without limitation, eight field-configurable memory blocks, that may be accessible by both a PVA and a DLA. In at least one embodiment, each pair of memory blocks may include an advanced peripheral bus (“APB”) interface, configuration circuitry, a controller, and a multiplexer. In at least one embodiment, any type of memory may be used. In at least one embodiment, a PVA and a DLA may access memory via a backbone that provides a PVA and a DLA with high-speed access to memory. In at least one embodiment, a backbone may include a computer vision network on- chip that interconnects a PVA and a DLA to memory (e.g., using APB).

[0222] In at least one embodiment, a computer vision network on-chip may include an interface that determines, before transmission of any control signal / address / data, that both a PVA and a DLA provide ready and valid signals. In at least one embodiment, an interface may provide for separate phases and separate channels for transmitting control signals / addresses / data, as well as burst-type communications for continuous data transfer. In at least one embodiment, an interface may comply with International Organization for Standardization (“ISO”) 26262 or International Electrotechnical Commission (“IEC”) 61508 standards, although other standards and protocols may be used.

[0223] In at least one embodiment, one or more of SoC(s) 1204 may include a real-time raytracing hardware accelerator. In at least one embodiment, real-time ray-tracing hardware accelerator may be used to quickly and efficiently determine positions and extents of objects (e.g., within a world model), to generate real-time visualization simulations, for RADAR signal interpretation, for sound propagation synthesis and / or analysis, for simulation of SONAR systems, for general wave propagation simulation, for comparison to LIDAR data for purposes of localization and / or other functions, and / or for other uses.

[0224] In at least one embodiment, accelerator(s) 1214 can have a wide array of uses for autonomous driving. In at least one embodiment, a PVA may be used for key processing stagesin ADAS and autonomous vehicles. In at least one embodiment, a PVA’s capabilities are a good match for algorithmic domains needing predictable processing, at low power and low latency. In other words, a PVA performs well on semi-dense or dense regular computation, even on small data sets, which might require predictable run-times with low latency and low power. In at least one embodiment, such as in vehicle 1200, PVAs might be designed to run classic computer vision algorithms, as they can be efficient at object detection and operating on integer math.

[0225] For example, according to at least one embodiment of technology, a PVA is used to perform computer stereo vision. In at least one embodiment, a semi-global matching-based algorithm may be used in some examples, although this is not intended to be limiting. In at least one embodiment, applications for Level 3-5 autonomous driving use motion estimation / stereo matching on-the-fly (e.g., structure from motion, pedestrian recognition, lane detection, etc.). In at least one embodiment, a PVA may perform computer stereo vision functions on inputs from two monocular cameras.

[0226] In at least one embodiment, a PVA may be used to perform dense optical flow. For example, in at least one embodiment, a PVA could process raw RADAR data (e.g., using a 4D Fast Fourier Transform) to provide processed RADAR data. In at least one embodiment, a PVA is used for time of flight depth processing, by processing raw time of flight data to provide processed time of flight data, for example.

[0227] In at least one embodiment, a DLA may be used to run any type of network to enhance control and driving safety, including for example and without limitation, a neural network that outputs a measure of confidence for each object detection. In at least one embodiment, confidence may be represented or interpreted as a probability, or as providing a relative “weight” of each detection compared to other detections. In at least one embodiment, a confidence measure enables a system to make further decisions regarding which detections should be considered as true positive detections rather than false positive detections. In at least one embodiment, a system may set a threshold value for confidence and consider only detections exceeding threshold value as true positive detections. In an embodiment in which an automatic emergency braking (“AEB”) system is used, false positive detections would cause vehicle to automatically perform emergency braking, which is obviously undesirable. In at least one embodiment, highly confident detections may be considered as triggers for AEB. In at least one embodiment, a DLA may run a neural network for regressing confidence value. In at leastone embodiment, neural network may take as its input at least some subset of parameters, such as bounding box dimensions, ground plane estimate obtained (e.g., from another subsystem), output from IMU sensor(s) 1266 that correlates with vehicle 1200 orientation, distance, 3D location estimates of object obtained from neural network and / or other sensors (e.g., LIDAR sensor(s) 1264 or RADAR sensor(s) 1260), among others.

[0228] In at least one embodiment, one or more of SoC(s) 1204 may include data store(s) 1216 (e.g., memory). In at least one embodiment, data store(s) 1216 may be on-chip memory of SoC(s) 1204, which may store neural networks to be executed on GPU(s) 1208 and / or a DLA. In at least one embodiment, data store(s) 1216 may be large enough in capacity to store multiple instances of neural networks for redundancy and safety. In at least one embodiment, data store(s) 1216 may comprise L2 or L3 cache(s).

[0229] In at least one embodiment, one or more of SoC(s) 1204 may include any number of processor(s) 1210 (e.g., embedded processors). In at least one embodiment, processor(s) 1210 may include a boot and power management processor that may be a dedicated processor and subsystem to handle boot power and management functions and related security enforcement. In at least one embodiment, a boot and power management processor may be a part of a boot sequence of SoC(s) 1204 and may provide runtime power management services. In at least one embodiment, a boot power and management processor may provide clock and voltage programming, assistance in system low power state transitions, management of SoC(s) 1204 thermals and temperature sensors, and / or management of SoC(s) 1204 power states. In at least one embodiment, each temperature sensor may be implemented as a ring-oscillator whose output frequency is proportional to temperature, and SoC(s) 1204 may use ring-oscillators to detect temperatures of CPU(s) 1206, GPU(s) 1208, and / or accelerator s) 1214. In at least one embodiment, if temperatures are determined to exceed a threshold, then a boot and power management processor may enter a temperature fault routine and put SoC(s) 1204 into a lower power state and / or put vehicle 1200 into a chauffeur to safe stop mode (e.g., bring vehicle 1200 to a safe stop).

[0230] In at least one embodiment, processor(s) 1210 may further include a set of embedded processors that may serve as an audio processing engine which may be an audio subsystem that enables full hardware support for multi-channel audio over multiple interfaces, and a broad and flexible range of audio I / O interfaces. In at least one embodiment, an audio processing engine is a dedicated processor core with a digital signal processor with dedicated RAM.

[0231] In at least one embodiment, processor(s) 1210 may further include an always-on processor engine that may provide necessary hardware features to support low power sensor management and wake use cases. In at least one embodiment, an always-on processor engine may include, without limitation, a processor core, a tightly coupled RAM, supporting peripherals (e.g., timers and interrupt controllers), various I / O controller peripherals, and routing logic.

[0232] In at least one embodiment, processor(s) 1210 may further include a safety cluster engine that includes, without limitation, a dedicated processor subsystem to handle safety management for automotive applications. In at least one embodiment, a safety cluster engine may include, without limitation, two or more processor cores, a tightly coupled RAM, support peripherals (e.g., timers, an interrupt controller, etc.), and / or routing logic. In a safety mode, two or more cores may operate, in at least one embodiment, in a lockstep mode and function as a single core with comparison logic to detect any differences between their operations. In at least one embodiment, processor(s) 1210 may further include a real-time camera engine that may include, without limitation, a dedicated processor subsystem for handling real-time camera management. In at least one embodiment, processor(s) 1210 may further include a high- dynamic range signal processor that may include, without limitation, an image signal processor that is a hardware engine that is part of a camera processing pipeline.

[0233] In at least one embodiment, processor(s) 1210 may include a video image compositor that may be a processing block (e.g., implemented on a microprocessor) that implements video post-processing functions needed by a video playback application to produce a final image for a player window. In at least one embodiment, a video image compositor may perform lens distortion correction on wide-view camera(s) 1270, surround camera(s) 1274, and / or on incabin monitoring camera sensor(s). In at least one embodiment, in-cabin monitoring camera sensor(s) are preferably monitored by a neural network running on another instance of SoC 1204, configured to identify in cabin events and respond accordingly. In at least one embodiment, an in-cabin system may perform, without limitation, lip reading to activate cellular service and place a phone call, dictate emails, change a vehicle’s destination, activate or change a vehicle’ s infotainment system and settings, or provide voice-activated web surfing. In at least one embodiment, certain functions are available to a driver when a vehicle is operating in an autonomous mode and are disabled otherwise.

[0234] In at least one embodiment, a video image compositor may include enhanced temporal noise reduction for both spatial and temporal noise reduction. For example, in at least one embodiment, where motion occurs in a video, noise reduction weights spatial information appropriately, decreasing weights of information provided by adjacent frames. In at least one embodiment, where an image or portion of an image does not include motion, temporal noise reduction performed by video image compositor may use information from a previous image to reduce noise in a current image.

[0235] In at least one embodiment, a video image compositor may also be configured to perform stereo rectification on input stereo lens frames. In at least one embodiment, a video image compositor may further be used for user interface composition when an operating system desktop is in use, and GPU(s) 1208 are not required to continuously render new surfaces. In at least one embodiment, when GPU(s) 1208 are powered on and active doing 3D rendering, a video image compositor may be used to offload GPU(s) 1208 to improve performance and responsiveness.

[0236] In at least one embodiment, one or more SoC of SoC(s) 1204 may further include a mobile industry processor interface (“MIPr’) camera serial interface for receiving video and input from cameras, a high-speed interface, and / or a video input block that may be used for a camera and related pixel input functions. In at least one embodiment, one or more of SoC(s) 1204 may further include an input / output controlled s) that may be controlled by software and may be used for receiving I / O signals that are uncommitted to a specific role.

[0237] In at least one embodiment, one or more SoC of SoC(s) 1204 may further include a broad range of peripheral interfaces to enable communication with peripherals, audio encoders / decoders (“codecs”), power management, and / or other devices. In at least one embodiment, SoC(s) 1204 may be used to process data from cameras (e.g., connected over Gigabit Multimedia Serial Link and Ethernet channels), sensors (e.g., LIDAR sensor(s) 1264, RADAR sensor(s) 1260, etc. that may be connected over Ethernet channels), data from bus 1202 (e.g., speed of vehicle 1200, steering wheel position, etc.), data from GNSS sensor(s) 1258 (e.g., connected over a Ethernet bus or a CAN bus), etc. In at least one embodiment, one or more SoC of SoC(s) 1204 may further include dedicated high-performance mass storage controllers that may include their own DMA engines, and that may be used to free CPU(s) 1206 from routine data management tasks.

[0238] In at least one embodiment, SoC(s) 1204 may be an end-to-end platform with a flexible architecture that spans automation Levels 3-5, thereby providing a comprehensive functional safety architecture that leverages and makes efficient use of computer vision and ADAS techniques for diversity and redundancy, and provides a platform for a flexible, reliable driving software stack, along with deep learning tools. In at least one embodiment, SoC(s) 1204 may be faster, more reliable, and even more energy-efficient and space-efficient than conventional systems. For example, in at least one embodiment, accelerator(s) 1214, when combined with CPU(s) 1206, GPU(s) 1208, and data store(s) 1216, may provide for a fast, efficient platform for Level 3-5 autonomous vehicles.

[0239] In at least one embodiment, computer vision algorithms may be executed on CPUs, which may be configured using a high-level programming language, such as C, to execute a wide variety of processing algorithms across a wide variety of visual data. However, in at least one embodiment, CPUs are oftentimes unable to meet performance requirements of many computer vision applications, such as those related to execution time and power consumption, for example. In at least one embodiment, many CPUs are unable to execute complex object detection algorithms in real-time, which is used in in-vehicle ADAS applications and in practical Level 3-5 autonomous vehicles.

[0240] Embodiments described herein allow for multiple neural networks to be performed simultaneously and / or sequentially, and for results to be combined together to enable Level 3- 5 autonomous driving functionality. For example, in at least one embodiment, a CNN executing on a DLA or a discrete GPU (e.g., GPU(s) 1220) may include text and word recognition, allowing reading and understanding of traffic signs, including signs for which a neural network has not been specifically trained. In at least one embodiment, a DLA may further include a neural network that is able to identify, interpret, and provide semantic understanding of a sign, and to pass that semantic understanding to path planning modules running on a CPU Complex.

[0241] In at least one embodiment, multiple neural networks may be run simultaneously, as for Level 3, 4, or 5 driving. For example, in at least one embodiment, a warning sign stating “Caution: flashing lights indicate icy conditions,” along with an electric light, may be independently or collectively interpreted by several neural networks. In at least one embodiment, such warning sign itself may be identified as a traffic sign by a first deployed neural network (e.g., a neural network that has been trained), text “flashing lights indicate icy conditions” may be interpreted by a second deployed neural network, which informs a vehicle’spath planning software (preferably executing on a CPU Complex) that when flashing lights are detected, icy conditions exist. In at least one embodiment, a flashing light may be identified by operating a third deployed neural network over multiple frames, informing a vehicle’s pathplanning software of a presence (or an absence) of flashing lights. In at least one embodiment, all three neural networks may run simultaneously, such as within a DLA and / or on GPU(s) 1208.

[0242] In at least one embodiment, a CNN for facial recognition and vehicle owner identification may use data from camera sensors to identify presence of an authorized driver and / or owner of vehicle 1200. In at least one embodiment, an always-on sensor processing engine may be used to unlock a vehicle when an owner approaches a driver door and turns on lights, and, in a security mode, to disable such vehicle when an owner leaves such vehicle. In this way, SoC(s) 1204 provide for security against theft and / or carjacking.

[0243] In at least one embodiment, a CNN for emergency vehicle detection and identification may use data from microphones 1296 to detect and identify emergency vehicle sirens. In at least one embodiment, SoC(s) 1204 use a CNN for classifying environmental and urban sounds, as well as classifying visual data. In at least one embodiment, a CNN running on a DLA is trained to identify a relative closing speed of an emergency vehicle (e.g., by using a Doppler effect). In at least one embodiment, a CNN may also be trained to identify emergency vehicles specific to a local area in which a vehicle is operating, as identified by GNSS sensor(s) 1258. In at least one embodiment, when operating in Europe, a CNN will seek to detect European sirens, and when in North America, a CNN will seek to identify only North American sirens. In at least one embodiment, once an emergency vehicle is detected, a control program may be used to execute an emergency vehicle safety routine, slowing a vehicle, pulling over to a side of a road, parking a vehicle, and / or idling a vehicle, with assistance of ultrasonic sensor(s) 1262, until emergency vehicles pass.

[0244] In at least one embodiment, vehicle 1200 may include CPU(s) 1218 (e.g., discrete CPU(s), or dCPU(s)), that may be coupled to SoC(s) 1204 via a high-speed interconnect (e.g., PCIe). In at least one embodiment, CPU(s) 1218 may include an X86 processor, for example. CPU(s) 1218 may be used to perform any of a variety of functions, including arbitrating potentially inconsistent results between ADAS sensors and SoC(s) 1204, and / or monitoring status and health of controller(s) 1236 and / or an infotainment system on a chip (“infotainment SoC”) 1230, for example. In at least one embodiment, SoC(s) 1204 includes one or moreinterconnects, and an interconnect can include a peripheral component interconnect express (PCIe).

[0245] In at least one embodiment, vehicle 1200 may include GPU(s) 1220 (e.g., discrete GPU(s), or dGPU(s)), that may be coupled to SoC(s) 1204 via a high-speed interconnect (e.g., NVIDIA’s NVLINK channel). In at least one embodiment, GPU(s) 1220 may provide additional artificial intelligence functionality, such as by executing redundant and / or different neural networks, and may be used to train and / or update neural networks based at least in part on input (e.g., sensor data) from sensors of a vehicle 1200.

[0246] In at least one embodiment, vehicle 1200 may further include network interface 1224 which may include, without limitation, wireless antenna(s) 1226 (e.g., one or more wireless antennas for different communication protocols, such as a cellular antenna, a Bluetooth antenna, etc.). In at least one embodiment, network interface 1224 may be used to enable wireless connectivity to Internet cloud services (e.g., with server(s) and / or other network devices), with other vehicles, and / or with computing devices (e.g., client devices of passengers). In at least one embodiment, to communicate with other vehicles, a direct link may be established between vehicle 1200 and another vehicle and / or an indirect link may be established (e.g., across networks and over the Internet). In at least one embodiment, direct links may be provided using a vehi cl e-to- vehicle communication link. In at least one embodiment, a vehi cl e-to- vehicle communication link may provide vehicle 1200 information about vehicles in proximity to vehicle 1200 (e.g., vehicles in front of, on a side of, and / or behind vehicle 1200). In at least one embodiment, such aforementioned functionality may be part of a cooperative adaptive cruise control functionality of vehicle 1200.

[0247] In at least one embodiment, network interface 1224 may include an SoC that provides modulation and demodulation functionality and enables controller(s) 1236 to communicate over wireless networks. In at least one embodiment, network interface 1224 may include a radio frequency front-end for up-conversion from baseband to radio frequency, and down conversion from radio frequency to baseband. In at least one embodiment, frequency conversions may be performed in any technically feasible fashion. For example, frequency conversions could be performed through well-known processes, and / or using super-heterodyne processes. In at least one embodiment, radio frequency front end functionality may be provided by a separate chip. In at least one embodiment, network interfaces may include wirelessfunctionality for communicating over LTE, WCDMA, UMTS, GSM, CDMA2000, Bluetooth, Bluetooth LE, Wi-Fi, Z-Wave, ZigBee, LoRaWAN, and / or other wireless protocols.

[0248] In at least one embodiment, vehicle 1200 may further include data store(s) 1228 which may include, without limitation, off-chip (e.g., off SoC(s) 1204) storage. In at least one embodiment, data store(s) 1228 may include, without limitation, one or more storage elements including RAM, SRAM, dynamic random-access memory (“DRAM”), video random-access memory (“VRAM”), flash memory, hard disks, and / or other components and / or devices that may store at least one bit of data.

[0249] In at least one embodiment, vehicle 1200 may further include GNSS sensor(s) 1258 (e.g., GPS and / or assisted GPS sensors), to assist in mapping, perception, occupancy grid generation, and / or path planning functions. In at least one embodiment, any number of GNSS sensor(s) 1258 may be used, including, for example and without limitation, a GPS using a USB connector with an Ethemet-to-Serial (e.g., RS-232) bridge.

[0250] In at least one embodiment, vehicle 1200 may further include RADAR sensor(s) 1260. In at least one embodiment, RADAR sensor(s) 1260 may be used by vehicle 1200 for long-range vehicle detection, even in darkness and / or severe weather conditions. In at least one embodiment, RADAR functional safety levels may be ASIL B. In at least one embodiment, RADAR sensor(s) 1260 may use a CAN bus and / or bus 1202 (e.g., to transmit data generated by RADAR sensor(s) 1260) for control and to access object tracking data, with access to Ethernet channels to access raw data in some examples. In at least one embodiment, a wide variety of RADAR sensor types may be used. For example, and without limitation, RADAR sensor(s) 1260 may be suitable for front, rear, and side RADAR use. In at least one embodiment, one or more sensor of RADAR sensors(s) 1260 is a Pulse Doppler RADAR sensor.

[0251] In at least one embodiment, RADAR sensor(s) 1260 may include different configurations, such as long-range with narrow field of view, short-range with wide field of view, short-range side coverage, etc. In at least one embodiment, long-range RADAR may be used for adaptive cruise control functionality. In at least one embodiment, long-range RADAR systems may provide a broad field of view realized by two or more independent scans, such as within a 250 m (meter) range. In at least one embodiment, RADAR sensor(s) 1260 may help in distinguishing between static and moving objects, and may be used by ADAS system 1238 for emergency brake assist and forward collision warning. In at least one embodiment, sensors1260(s) included in a long-range RADAR system may include, without limitation, monostatic multimodal RADAR with multiple (e.g., six or more) fixed RADAR antennae and a high-speed CAN and FlexRay interface. In at least one embodiment, with six antennae, a central four antennae may create a focused beam pattern, designed to record vehicle’s 1200 surroundings at higher speeds with minimal interference from traffic in adjacent lanes. In at least one embodiment, another two antennae may expand field of view, making it possible to quickly detect vehicles entering or leaving a lane of vehicle 1200.

[0252] In at least one embodiment, mid-range RADAR systems may include, as an example, a range of up to 160 m (front) or 80 m (rear), and a field of view of up to 42 degrees (front) or 150 degrees (rear). In at least one embodiment, short-range RADAR systems may include, without limitation, any number of RADAR sensor(s) 1260 designed to be installed at both ends of a rear bumper. When installed at both ends of a rear bumper, in at least one embodiment, a RADAR sensor system may create two beams that constantly monitor blind spots in a rear direction and next to a vehicle. In at least one embodiment, short-range RADAR systems may be used in ADAS system 1238 for blind spot detection and / or lane change assist.

[0253] In at least one embodiment, vehicle 1200 may further include ultrasonic sensor(s) 1262. In at least one embodiment, ultrasonic sensor(s) 1262, which may be positioned at a front, a back, and / or side location of vehicle 1200, may be used for parking assist and / or to create and update an occupancy grid. In at least one embodiment, a wide variety of ultrasonic sensor(s) 1262 may be used, and different ultrasonic sensor(s) 1262 may be used for different ranges of detection (e.g., 2.5 m, 4 m). In at least one embodiment, ultrasonic sensor(s) 1262 may operate at functional safety levels of ASIL B.

[0254] In at least one embodiment, vehicle 1200 may include LIDAR sensor(s) 1264. In at least one embodiment, LIDAR sensor(s) 1264 may be used for object and pedestrian detection, emergency braking, collision avoidance, and / or other functions. In at least one embodiment, LIDAR sensor(s) 1264 may operate at functional safety level ASIL B. In at least one embodiment, vehicle 1200 may include multiple LIDAR sensors 1264 (e.g., two, four, six, etc.) that may use an Ethernet channel (e.g., to provide data to a Gigabit Ethernet switch).

[0255] In at least one embodiment, LIDAR sensor(s) 1264 may be capable of providing a list of objects and their distances for a 360-degree field of view. In at least one embodiment, commercially available LIDAR sensor(s) 1264 may have an advertised range of approximately 100 m, with an accuracy of 2 cm to 3 cm, and with support for a 100 Mbps Ethernet connection,for example. In at least one embodiment, one or more non-protruding LIDAR sensors may be used. In such an embodiment, LIDAR sensor(s) 1264 may include a small device that may be embedded into a front, a rear, a side, and / or a corner location of vehicle 1200. In at least one embodiment, LIDAR sensor(s) 1264, in such an embodiment, may provide up to a 120-degree horizontal and 35-degree vertical field-of-view, with a 200 m range even for low-reflectivity objects. In at least one embodiment, front-mounted LIDAR sensor(s) 1264 may be configured for a horizontal field of view between 45 degrees and 135 degrees.

[0256] In at least one embodiment, LIDAR technologies, such as 3D flash LIDAR, may also be used. In at least one embodiment, 3D flash LIDAR uses a flash of a laser as a transmission source, to illuminate surroundings of vehicle 1200 up to approximately 200 m. In at least one embodiment, a flash LIDAR unit includes, without limitation, a receptor, which records laser pulse transit time and reflected light on each pixel, which in turn corresponds to a range from vehicle 1200 to objects. In at least one embodiment, flash LIDAR may allow for highly accurate and distortion-free images of surroundings to be generated with every laser flash. In at least one embodiment, four flash LIDAR sensors may be deployed, one at each side of vehicle 1200. In at least one embodiment, 3D flash LIDAR systems include, without limitation, a solid-state 3D staring array LIDAR camera with no moving parts other than a fan (e.g., a nonscanning LIDAR device). In at least one embodiment, flash LIDAR device may use a 5 nanosecond class I (eye-safe) laser pulse per frame and may capture reflected laser light as a 3D range point cloud and co-registered intensity data.

[0257] In at least one embodiment, vehicle 1200 may further include IMU sensor(s) 1266. In at least one embodiment, IMU sensor(s) 1266 may be located at a center of a rear axle of vehicle 1200. In at least one embodiment, IMU sensor(s) 1266 may include, for example and without limitation, accelerometer(s), magnetometer(s), gyroscope(s), a magnetic compass, magnetic compasses, and / or other sensor types. In at least one embodiment, such as in six-axis applications, IMU sensor(s) 1266 may include, without limitation, accelerometers and gyroscopes. In at least one embodiment, such as in nine-axis applications, IMU sensor(s) 1266 may include, without limitation, accelerometers, gyroscopes, and magnetometers.

[0258] In at least one embodiment, IMU sensor(s) 1266 may be implemented as a miniature, high performance GPS-Aided Inertial Navigation System (“GPS / INS”) that combines micro- electro-mechanical systems (“MEMS”) inertial sensors, a high-sensitivity GPS receiver, and advanced Kalman filtering algorithms to provide estimates of position, velocity, and attitude.In at least one embodiment, IMU sensor(s) 1266 may enable vehicle 1200 to estimate its heading without requiring input from a magnetic sensor by directly observing and correlating changes in velocity from a GPS to IMU sensor(s) 1266. In at least one embodiment, IMU sensor(s) 1266 and GNSS sensor(s) 1258 may be combined in a single integrated unit.

[0259] In at least one embodiment, vehicle 1200 may include microphone(s) 1296 placed in and / or around vehicle 1200. In at least one embodiment, microphone(s) 1296 may be used for emergency vehicle detection and identification, among other things.

[0260] In at least one embodiment, vehicle 1200 may further include any number of camera types, including stereo camera(s) 1268, wide-view camera(s) 1270, infrared camera(s) 1272, surround camera(s) 1274, long-range camera(s) 1298, mid-range camera(s) 1276, and / or other camera types. In at least one embodiment, cameras may be used to capture image data around an entire periphery of vehicle 1200. In at least one embodiment, which types of cameras used depends on vehicle 1200. In at least one embodiment, any combination of camera types may be used to provide necessary coverage around vehicle 1200. In at least one embodiment, a number of cameras deployed may differ depending on embodiment. For example, in at least one embodiment, vehicle 1200 could include six cameras, seven cameras, ten cameras, twelve cameras, or another number of cameras. In at least one embodiment, cameras may support, as an example and without limitation, Gigabit Multimedia Serial Link (“GMSL”) and / or Gigabit Ethernet communications. In at least one embodiment, each camera might be as described with more detail previously herein with respect to FIG. 12A and FIG. 12B.

[0261] In at least one embodiment, vehicle 1200 may further include vibration sensor(s) 1242. In at least one embodiment, vibration sensor(s) 1242 may measure vibrations of components of vehicle 1200, such as axle(s). For example, in at least one embodiment, changes in vibrations may indicate a change in road surfaces. In at least one embodiment, when two or more vibration sensors 1242 are used, differences between vibrations may be used to determine friction or slippage of road surface (e.g., when a difference in vibration is between a power- driven axle and a freely rotating axle).

[0262] In at least one embodiment, vehicle 1200 may include ADAS system 1238. In at least one embodiment, ADAS system 1238 may include, without limitation, an SoC, in some examples. In at least one embodiment, ADAS system 1238 may include, without limitation, any number and combination of an autonomous / adaptive / automatic cruise control (“ACC”) system, a cooperative adaptive cruise control (“CACC”) system, a forward crash warning(“FCW”) system, an automatic emergency braking (“AEB”) system, a lane departure warning (“LDW”) system, a lane keep assist (“LKA”) system, a blind spot warning (“BSW”) system, a rear cross-traffic warning (“RCTW”) system, a collision warning (“CW”) system, a lane centering (“LC”) system, and / or other systems, features, and / or functionality.

[0263] In at least one embodiment, ACC system may use RADAR sensor(s) 1260, LIDAR sensor(s) 1264, and / or any number of camera(s). In at least one embodiment, ACC system may include a longitudinal ACC system and / or a lateral ACC system. In at least one embodiment, a longitudinal ACC system monitors and controls distance to another vehicle immediately ahead of vehicle 1200 and automatically adjusts speed of vehicle 1200 to maintain a safe distance from vehicles ahead. In at least one embodiment, a lateral ACC system performs distance keeping, and advises vehicle 1200 to change lanes when necessary. In at least one embodiment, a lateral ACC is related to other ADAS applications, such as LC and CW.

[0264] In at least one embodiment, a CACC system uses information from other vehicles that may be received via network interface 1224 and / or wireless antenna(s) 1226 from other vehicles via a wireless link, or indirectly, over a network connection (e.g., over the Internet). In at least one embodiment, direct links may be provided by a vehicle-to-vehicle (“V2V”) communication link, while indirect links may be provided by an infrastructure-to-vehicle (“I2V”) communication link. In general, V2V communication provides information about immediately preceding vehicles (e.g., vehicles immediately ahead of and in same lane as vehicle 1200), while 12 V communication provides information about traffic further ahead. In at least one embodiment, a CACC system may include either or both I2V and V2V information sources. In at least one embodiment, given information of vehicles ahead of vehicle 1200, a CACC system may be more reliable and it has potential to improve traffic flow smoothness and reduce congestion on road.

[0265] In at least one embodiment, an FCW system is designed to alert a driver to a hazard, so that such driver may take corrective action. In at least one embodiment, an FCW system uses a front-facing camera and / or RADAR sensor(s) 1260, coupled to a dedicated processor, DSP, FPGA, and / or ASIC, that is electrically coupled to provide driver feedback, such as a display, speaker, and / or vibrating component. In at least one embodiment, an FCW system may provide a warning, such as in form of a sound, visual warning, vibration and / or a quick brake pulse.

[0266] In at least one embodiment, an AEB system detects an impending forward collision with another vehicle or other object, and may automatically apply brakes if a driver does not take corrective action within a specified time or distance parameter. In at least one embodiment, AEB system may use front-facing camera(s) and / or RADAR sensor(s) 1260, coupled to a dedicated processor, DSP, FPGA, and / or ASIC. In at least one embodiment, when an AEB system detects a hazard, it will typically first alert a driver to take corrective action to avoid collision and, if that driver does not take corrective action, that AEB system may automatically apply brakes in an effort to prevent, or at least mitigate, an impact of a predicted collision. In at least one embodiment, an AEB system may include techniques such as dynamic brake support and / or crash imminent braking.

[0267] In at least one embodiment, an LDW system provides visual, audible, and / or tactile warnings, such as steering wheel or seat vibrations, to alert driver when vehicle 1200 crosses lane markings. In at least one embodiment, an LDW system does not activate when a driver indicates an intentional lane departure, such as by activating a turn signal. In at least one embodiment, an LDW system may use front-side facing cameras, coupled to a dedicated processor, DSP, FPGA, and / or ASIC, that is electrically coupled to provide driver feedback, such as a display, speaker, and / or vibrating component. In at least one embodiment, an LKA system is a variation of an LDW system. In at least one embodiment, an LKA system provides steering input or braking to correct vehicle 1200 if vehicle 1200 starts to exit its lane.

[0268] In at least one embodiment, a BSW system detects and warns a driver of vehicles in an automobile’s blind spot. In at least one embodiment, a BSW system may provide a visual, audible, and / or tactile alert to indicate that merging or changing lanes is unsafe. In at least one embodiment, a BSW system may provide an additional warning when a driver uses a turn signal. In at least one embodiment, a BSW system may use rear-side facing camera(s) and / or RADAR sensor(s) 1260, coupled to a dedicated processor, DSP, FPGA, and / or ASIC, that is electrically coupled to driver feedback, such as a display, speaker, and / or vibrating component.

[0269] In at least one embodiment, an RCTW system may provide visual, audible, and / or tactile notification when an object is detected outside a rear-camera range when vehicle 1200 is backing up. In at least one embodiment, an RCTW system includes an AEB system to ensure that vehicle brakes are applied to avoid a crash. In at least one embodiment, an RCTW system may use one or more rear-facing RADAR sensor(s) 1260, coupled to a dedicated processor,DSP, FPGA, and / or ASIC, that is electrically coupled to provide driver feedback, such as a display, speaker, and / or vibrating component.

[0270] In at least one embodiment, conventional ADAS systems may be prone to false positive results which may be annoying and distracting to a driver, but typically are not catastrophic, because conventional ADAS systems alert a driver and allow that driver to decide whether a safety condition truly exists and act accordingly. In at least one embodiment, vehicle 1200 itself decides, in case of conflicting results, whether to heed result from a primary computer or a secondary computer (e.g., a first controller or a second controller of controllers 1236). For example, in at least one embodiment, ADAS system 1238 may be a backup and / or secondary computer for providing perception information to a backup computer rationality module. In at least one embodiment, a backup computer rationality monitor may run redundant diverse software on hardware components to detect faults in perception and dynamic driving tasks. In at least one embodiment, outputs from ADAS system 1238 may be provided to a supervisory MCU. In at least one embodiment, if outputs from a primary computer and outputs from a secondary computer conflict, a supervisory MCU determines how to reconcile conflict to ensure safe operation.

[0271] In at least one embodiment, a primary computer may be configured to provide a supervisory MCU with a confidence score, indicating that primary computer’s confidence in a chosen result. In at least one embodiment, if that confidence score exceeds a threshold, that supervisory MCU may follow that primary computer’s direction, regardless of whether that secondary computer provides a conflicting or inconsistent result. In at least one embodiment, where a confidence score does not meet a threshold, and where primary and secondary computers indicate different results (e.g., a conflict), a supervisory MCU may arbitrate between computers to determine an appropriate outcome.

[0272] In at least one embodiment, a supervisory MCU may be configured to run a neural network(s) that is trained and configured to determine, based at least in part on outputs from a primary computer and outputs from a secondary computer, conditions under which that secondary computer provides false alarms. In at least one embodiment, neural network(s) in a supervisory MCU may learn when a secondary computer’s output may be trusted, and when it cannot. For example, in at least one embodiment, when that secondary computer is a RADAR- based FCW system, a neural network(s) in that supervisory MCU may learn when an FCW system is identifying metallic objects that are not, in fact, hazards, such as a drainage grate ormanhole cover that triggers an alarm. In at least one embodiment, when a secondary computer is a camera-based LDW system, a neural network in a supervisory MCU may learn to override LDW when bicyclists or pedestrians are present and a lane departure is, in fact, a safest maneuver. In at least one embodiment, a supervisory MCU may include at least one of a DLA or a GPU suitable for running neural network(s) with associated memory. In at least one embodiment, a supervisory MCU may comprise and / or be included as a component of SoC(s) 1204.

[0273] In at least one embodiment, ADAS system 1238 may include a secondary computer that performs ADAS functionality using traditional rules of computer vision. In at least one embodiment, that secondary computer may use classic computer vision rules (if-then), and presence of a neural network(s) in a supervisory MCU may improve reliability, safety and performance. For example, in at least one embodiment, diverse implementation and intentional non-identity makes an overall system more fault-tolerant, especially to faults caused by software (or software-hardware interface) functionality. For example, in at least one embodiment, if there is a software bug or error in software running on a primary computer, and non-identical software code running on a secondary computer provides a consistent overall result, then a supervisory MCU may have greater confidence that an overall result is correct, and a bug in software or hardware on that primary computer is not causing a material error.

[0274] In at least one embodiment, an output of ADAS system 1238 may be fed into a primary computer’s perception block and / or a primary computer’s dynamic driving task block. For example, in at least one embodiment, if ADAS system 1238 indicates a forward crash warning due to an object immediately ahead, a perception block may use this information when identifying objects. In at least one embodiment, a secondary computer may have its own neural network that is trained and thus reduces a risk of false positives, as described herein.

[0275] In at least one embodiment, vehicle 1200 may further include infotainment SoC 1230 (e.g., an in-vehicle infotainment system (IVI)). Although illustrated and described as an SoC, infotainment system SoC 1230, in at least one embodiment, may not be an SoC, and may include, without limitation, two or more discrete components. In at least one embodiment, infotainment SoC 1230 may include, without limitation, a combination of hardware and software that may be used to provide audio (e.g., music, a personal digital assistant, navigational instructions, news, radio, etc.), video (e.g., TV, movies, streaming, etc.), phone (e.g., hands-free calling), network connectivity (e.g., LTE, WiFi, etc.), and / or informationservices (e.g., navigation systems, rear-parking assistance, a radio data system, vehicle related information such as fuel level, total distance covered, brake fuel level, oil level, door open / close, air filter information, etc.) to vehicle 1200. For example, infotainment SoC 1230 could include radios, disk players, navigation systems, video players, USB and Bluetooth connectivity, carputers, in-car entertainment, WiFi, steering wheel audio controls, hands free voice control, a heads-up display (“HUD”), HMI display 1234, a telematics device, a control panel (e.g., for controlling and / or interacting with various components, features, and / or systems), and / or other components. In at least one embodiment, infotainment SoC 1230 may further be used to provide information (e.g., visual and / or audible) to user(s) of vehicle 1200, such as information from ADAS system 1238, autonomous driving information such as planned vehicle maneuvers, trajectories, surrounding environment information (e.g., intersection information, vehicle information, road information, etc.), and / or other information.

[0276] In at least one embodiment, infotainment SoC 1230 may include any amount and type of GPU functionality. In at least one embodiment, infotainment SoC 1230 may communicate over bus 1202 with other devices, systems, and / or components of vehicle 1200. In at least one embodiment, infotainment SoC 1230 may be coupled to a supervisory MCU such that a GPU of an infotainment system may perform some self-driving functions in event that primary controller(s) 1236 (e.g., primary and / or backup computers of vehicle 1200) fail. In at least one embodiment, infotainment SoC 1230 may put vehicle 1200 into a chauffeur to safe stop mode, as described herein.

[0277] In at least one embodiment, vehicle 1200 may further include instrument cluster 1232 (e.g., a digital dash, an electronic instrument cluster, a digital instrument panel, etc.). In at least one embodiment, instrument cluster 1232 may include, without limitation, a controller and / or supercomputer (e.g., a discrete controller or supercomputer). In at least one embodiment, instrument cluster 1232 may include, without limitation, any number and combination of a set of instrumentation such as a speedometer, fuel level, oil pressure, tachometer, odometer, turn indicators, gearshift position indicator, seat belt warning light(s), parking-brake warning light(s), engine-malfunction light(s), supplemental restraint system (e.g., airbag) information, lighting controls, safety system controls, navigation information, etc. In some examples, information may be displayed and / or shared among infotainment SoC 1230 and instrument cluster 1232. In at least one embodiment, instrument cluster 1232 may be included as part of infotainment SoC 1230, or vice versa.

[0278] In at least one embodiment, at least one component shown or described with respect to FIG. 12C is utilized to implement techniques and / or functions described in connection with FIGS. 1-8. In at least one embodiment, at least one component of FIG. 12C is used to cause generation of an API, parameters, libraries, runtimes, drivers, kernels, distributing kernels to one or more GPUs, and to cause execution of a kernel on one or more GPUs. In at least one embodiment, at least one component of FIG. 12C performs at least one aspect described with respect to data scaling system 100, device 102, data conversion manager 104, scaling module 106, machine learning modules 108, processors 110, communication manager 112, storage device 114, devices 116, cores 118A-118Z, storage device 120, processors 122, tensor scaling 200, input tensor 202, generate sub-tensor 204, sub-tensors 206A-206N, identify local maximum 208A-208N, scaled sub-tensor 21 OA-210N, converted sub -tensor 212A-212N, identify global maximum 214, scale with global maximum 216, data format conversion 300, values in first data format 320, scaling 304, data conversions 306, values in second data format 308, scaling operations 400, values in second data format 402, data evaluation 403, data comparison 404, global maximum determination 405, no data re-scale 406, data re-scale 408, operations of one or more scaling modules 500, method 600, method 700, processor 800, processor 820, conversion module 822, and / or scaling module 824.

[0279] FIG. 12D is a diagram of a system for communication between cloud-based server(s) and autonomous vehicle 1200 of FIG. 12A, according to at least one embodiment. In at least one embodiment, system may include, without limitation, server(s) 1278, network(s) 1290, and any number and type of vehicles, including vehicle 1200. In at least one embodiment, server(s) 1278 may include, without limitation, a plurality of GPUs 1284(A)- 1284(H) (collectively referred to herein as GPUs 1284), PCIe switches 1282(A)- 1282(D) (collectively referred to herein as PCIe switches 1282), and / or CPUs 1280(A)-1280(B) (collectively referred to herein as CPUs 1280). In at least one embodiment, GPUs 1284, CPUs 1280, and PCIe switches 1282 may be interconnected with high-speed interconnects such as, for example and without limitation, NVLink interfaces 1288 developed by NVIDIA and / or PCIe connections 1286. In at least one embodiment, GPUs 1284 are connected via an NVLink and / or NVSwitch SoC and GPUs 1284 and PCIe switches 1282 are connected via PCIe interconnects. Although eight GPUs 1284, two CPUs 1280, and four PCIe switches 1282 are illustrated, this is not intended to be limiting. In at least one embodiment, each of server(s) 1278 may include, without limitation, any number of GPUs 1284, CPUs 1280, and / or PCIe switches 1282, in anycombination. For example, in at least one embodiment, server(s) 1278 could each include eight, sixteen, thirty -two, and / or more GPUs 1284.

[0280] In at least one embodiment, server(s) 1278 may receive, over network(s) 1290 and from vehicles, image data representative of images showing unexpected or changed road conditions, such as recently commenced road-work. In at least one embodiment, server(s) 1278 may transmit, over network(s) 1290 and to vehicles, neural networks 1292, updated or otherwise, and / or map information 1294, including, without limitation, information regarding traffic and road conditions. In at least one embodiment, updates to map information 1294 may include, without limitation, updates for HD map 1222, such as information regarding construction sites, potholes, detours, flooding, and / or other obstructions. In at least one embodiment, neural networks 1292, and / or map information 1294 may have resulted from new training and / or experiences represented in data received from any number of vehicles in an environment, and / or based at least in part on training performed at a data center (e.g., using server(s) 1278 and / or other servers).

[0281] In at least one embodiment, server(s) 1278 may be used to train machine learning models (e.g., neural networks) based at least in part on training data. In at least one embodiment, training data may be generated by vehicles, and / or may be generated in a simulation (e.g., using a game engine). In at least one embodiment, any amount of training data is tagged (e.g., where associated neural network benefits from supervised learning) and / or undergoes other pre-processing. In at least one embodiment, any amount of training data is not tagged and / or pre-processed (e.g., where associated neural network does not require supervised learning). In at least one embodiment, once machine learning models are trained, machine learning models may be used by vehicles (e.g., transmitted to vehicles over network(s) 1290), and / or machine learning models may be used by server(s) 1278 to remotely monitor vehicles.

[0282] In at least one embodiment, server(s) 1278 may receive data from vehicles and apply data to up-to-date real-time neural networks for real-time intelligent inferencing. In at least one embodiment, server(s) 1278 may include deep-learning supercomputers and / or dedicated Al computers powered by GPU(s) 1284, such as a DGX and DGX Station machines developed by NVIDIA. However, in at least one embodiment, server(s) 1278 may include deep learning infrastructure that uses CPU-powered data centers.

[0283] In at least one embodiment, deep-learning infrastructure of server(s) 1278 may be capable of fast, real-time inferencing, and may use that capability to evaluate and verify healthof processors, software, and / or associated hardware in vehicle 1200. For example, in at least one embodiment, deep-learning infrastructure may receive periodic updates from vehicle 1200, such as a sequence of images and / or objects that vehicle 1200 has located in that sequence of images (e.g., via computer vision and / or other machine learning object classification techniques). In at least one embodiment, deep-learning infrastructure may run its own neural network to identify objects and compare them with objects identified by vehicle 1200 and, if results do not match and deep-learning infrastructure concludes that Al in vehicle 1200 is malfunctioning, then server(s) 1278 may transmit a signal to vehicle 1200 instructing a failsafe computer of vehicle 1200 to assume control, notify passengers, and complete a safe parking maneuver.

[0284] In at least one embodiment, server(s) 1278 may include GPU(s) 1284 and one or more programmable inference accelerators (e.g., NVIDIA’ s TensorRT 3 devices). In at least one embodiment, a combination of GPU-powered servers and inference acceleration may make real-time responsiveness possible. In at least one embodiment, such as where performance is less critical, servers powered by CPUs, FPGAs, and other processors may be used for inferencing. In at least one embodiment, hardware structure(s) 915 are used to perform one or more embodiments. Details regarding hardware structure(s) 915 are provided herein in conjunction with FIGS. 9A and / or 9B.

[0285] In at least one embodiment, at least one component shown or described with respect to FIG. 12D is utilized to implement techniques and / or functions described in connection with FIGS. 1-8. In at least one embodiment, at least one component of FIG. 12D is used to cause generation of an API, parameters, libraries, runtimes, drivers, kernels, distributing kernels to one or more GPUs, and to cause execution of a kernel on one or more GPUs. In at least one embodiment, at least one component of FIG. 12D performs at least one aspect described with respect to data scaling system 100, device 102, data conversion manager 104, scaling module 106, machine learning modules 108, processors 110, communication manager 112, storage device 114, devices 116, cores 118A-118Z, storage device 120, processors 122, tensor scaling 200, input tensor 202, generate sub-tensor 204, sub-tensors 206A-206N, identify local maximum 208A-208N, scaled sub-tensor 21 OA-210N, converted sub -tensor 212A-212N, identify global maximum 214, scale with global maximum 216, data format conversion 300, values in first data format 320, scaling 304, data conversions 306, values in second data format 308, scaling operations 400, values in second data format 402, data evaluation 403, data comparison 404, global maximum determination 405, no data re-scale 406, data re-scale 408,operations of one or more scaling modules 500, method 600, method 700, processor 800, processor 820, conversion module 822, and / or scaling module 824.COMPUTER SYSTEMS

[0286] FIG. 13 is a block diagram illustrating an exemplary computer system, which may be a system with interconnected devices and components, a system-on-a-chip (SOC) or some combination thereof formed with a processor that may include execution units to execute an instruction, according to at least one embodiment. In at least one embodiment, a computer system 1300 may include, without limitation, a component, such as a processor 1302 to employ execution units including logic to perform algorithms for process data, in accordance with present disclosure, such as in embodiment described herein. In at least one embodiment, computer system 1300 may include processors, such as PENTIUM® Processor family, Xeon™, Itanium®, XScale™ and / or StrongARM™, Intel® Core™, or Intel® Nervana™ microprocessors available from Intel Corporation of Santa Clara, California, although other systems (including PCs having other microprocessors, engineering workstations, set-top boxes and like) may also be used. In at least one embodiment, computer system 1300 may execute a version of WINDOWS operating system available from Microsoft Corporation of Redmond, Wash., although other operating systems (UNIX and Linux, for example), embedded software, and / or graphical user interfaces, may also be used.

[0287] Embodiments may be used in other devices such as handheld devices and embedded applications. Some examples of handheld devices include cellular phones, Internet Protocol devices, digital cameras, personal digital assistants (“PDAs”), and handheld PCs. In at least one embodiment, embedded applications may include a microcontroller, a digital signal processor (“DSP”), system on a chip, network computers (“NetPCs”), set-top boxes, network hubs, wide area network (“WAN”) switches, or any other system that may perform one or more instructions in accordance with at least one embodiment.

[0288] In at least one embodiment, computer system 1300 may include, without limitation, processor 1302 that may include, without limitation, one or more execution units 1308 to perform machine learning model training and / or inferencing according to techniques described herein. In at least one embodiment, computer system 1300 is a single processor desktop or server system, but in another embodiment, computer system 1300 may be a multiprocessor system. In at least one embodiment, processor 1302 may include, without limitation, a complex instruction set computer (“CISC”) microprocessor, a reduced instruction set computing(“RISC”) microprocessor, a very long instruction word (“VLIW”) microprocessor, a processor implementing a combination of instruction sets, or any other processor device, such as a digital signal processor, for example. In at least one embodiment, processor 1302 may be coupled to a processor bus 1310 that may transmit data signals between processor 1302 and other components in computer system 1300.

[0289] In at least one embodiment, processor 1302 may include, without limitation, a Level 1 (“LI”) internal cache memory (“cache”) 1304. In at least one embodiment, processor 1302 may have a single internal cache or multiple levels of internal cache. In at least one embodiment, cache memory may reside external to processor 1302. Other embodiments may also include a combination of both internal and external caches depending on particular implementation and needs. In at least one embodiment, a register file 1306 may store different types of data in various registers including, without limitation, integer registers, floating point registers, status registers, and an instruction pointer register.

[0290] In at least one embodiment, execution unit 1308, including, without limitation, logic to perform integer and floating point operations, also resides in processor 1302. In at least one embodiment, processor 1302 may also include a microcode (“ucode”) read only memory (“ROM”) that stores microcode for certain macro instructions. In at least one embodiment, execution unit 1308 may include logic to handle a packed instruction set 1309. In at least one embodiment, by including packed instruction set 1309 in an instruction set of a general-purpose processor, along with associated circuitry to execute instructions, operations used by many multimedia applications may be performed using packed data in processor 1302. In at least one embodiment, many multimedia applications may be accelerated and executed more efficiently by using a full width of a processor’s data bus for performing operations on packed data, which may eliminate a need to transfer smaller units of data across that processor’ s data bus to perform one or more operations one data element at a time.

[0291] In at least one embodiment, execution unit 1308 may also be used in microcontrollers, embedded processors, graphics devices, DSPs, and other types of logic circuits. In at least one embodiment, computer system 1300 may include, without limitation, a memory 1320. In at least one embodiment, memory 1320 may be a Dynamic Random Access Memory (“DRAM”) device, a Static Random Access Memory (“SRAM”) device, a flash memory device, or another memory device. In at least one embodiment, memory 1320 may store instruct! on(s) 1319 and / or data 1321 represented by data signals that may be executed by processor 1302.

[0292] In at least one embodiment, a system logic chip may be coupled to processor bus 1310 and memory 1320. In at least one embodiment, a system logic chip may include, without limitation, a memory controller hub (“MCH”) 1316, and processor 1302 may communicate with MCH 1316 via processor bus 1310. In at least one embodiment, MCH 1316 may provide a high bandwidth memory path 1318 to memory 1320 for instruction and data storage and for storage of graphics commands, data and textures. In at least one embodiment, MCH 1316 may direct data signals between processor 1302, memory 1320, and other components in computer system 1300 and to bridge data signals between processor bus 1310, memory 1320, and a system I / O interface 1322. In at least one embodiment, a system logic chip may provide a graphics port for coupling to a graphics controller. In at least one embodiment, MCH 1316 may be coupled to memory 1320 through high bandwidth memory path 1318 and a graphics / video card 1312 may be coupled to MCH 1316 through an Accelerated Graphics Port (“AGP”) interconnect 1314.

[0293] In at least one embodiment, computer system 1300 may use system I / O interface 1322 as a proprietary hub interface bus to couple MCH 1316 to an I / O controller hub (“ICH”) 1330. In at least one embodiment, ICH 1330 may provide direct connections to some I / O devices via a local I / O bus. In at least one embodiment, a local I / O bus may include, without limitation, a high-speed I / O bus for connecting peripherals to memory 1320, a chipset, and processor 1302. Examples may include, without limitation, an audio controller 1329, a firmware hub (“flash BIOS”) 1328, a wireless transceiver 1326, a data storage 1324, a legacy I / O controller 1323 containing user input and keyboard interfaces 1325, a serial expansion port 1327, such as a Universal Serial Bus (“USB”) port, and a network controller 1334. In at least one embodiment, data storage 1324 may comprise a hard disk drive, a floppy disk drive, a CD-ROM device, a flash memory device, or other mass storage device.

[0294] In at least one embodiment, FIG. 13 illustrates a system, which includes interconnected hardware devices or “chips”, whereas in other embodiments, FIG. 13 may illustrate an exemplary SoC. In at least one embodiment, devices illustrated in FIG. 13 may be interconnected with proprietary interconnects, standardized interconnects (e.g., PCIe) or some combination thereof. In at least one embodiment, one or more components of computer system 1300 are interconnected using compute express link (CXL) interconnects.

[0295] Logic 915 are used to perform inferencing and / or training operations associated with one or more embodiments. Details regarding logic 915 are provided herein in conjunction withFIGS. 9A and / or 9B. In at least one embodiment, logic 915 may be used in computer system 1300 for inferencing or predicting operations based, at least in part, on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0296] In at least one embodiment, at least one component shown or described with respect to FIG. 13 is utilized to implement techniques and / or functions described in connection with FIGS. 1-8. In at least one embodiment, at least one component of FIG. 13 is used to cause generation of an API, parameters, libraries, runtimes, drivers, kernels, distributing kernels to one or more GPUs, and to cause execution of a kernel on one or more GPUs. In at least one embodiment, at least one component of FIG. 13 performs at least one aspect described with respect to data scaling system 100, device 102, data conversion manager 104, scaling module 106, machine learning modules 108, processors 110, communication manager 112, storage device 114, devices 116, cores 118A-118Z, storage device 120, processors 122, tensor scaling 200, input tensor 202, generate sub-tensor 204, sub-tensors 206A-206N, identify local maximum 208A-208N, scaled sub-tensor 210A-210N, converted sub-tensor 212A-212N, identify global maximum 214, scale with global maximum 216, data format conversion 300, values in first data format 320, scaling 304, data conversions 306, values in second data format 308, scaling operations 400, values in second data format 402, data evaluation 403, data comparison 404, global maximum determination 405, no data re-scale 406, data re-scale 408, operations of one or more scaling modules 500, method 600, method 700, processor 800, processor 820, conversion module 822, and / or scaling module 824.

[0297] FIG. 14 is a block diagram illustrating an electronic device 1400 for utilizing a processor 1410, according to at least one embodiment. In at least one embodiment, electronic device 1400 may be, for example and without limitation, a notebook, a tower server, a rack server, a blade server, a laptop, a desktop, a tablet, a mobile device, a phone, an embedded computer, or any other suitable electronic device.

[0298] In at least one embodiment, electronic device 1400 may include, without limitation, processor 1410 communicatively coupled to any suitable number or kind of components, peripherals, modules, or devices. In at least one embodiment, processor 1410 is coupled using a bus or interface, such as a I2C bus, a System Management Bus (“SMBus”), a Low Pin Count (LPC) bus, a Serial Peripheral Interface (“SPI”), a High Definition Audio (“HDA”) bus, a Serial Advance Technology Attachment (“SATA”) bus, a Universal Serial Bus (“USB”)(versions 1, 2, 3, etc.), or a Universal Asynchronous Receiver / Transmitter (“UART”) bus. In at least one embodiment, FIG. 14 illustrates a system, which includes interconnected hardware devices or “chips”, whereas in other embodiments, FIG. 14 may illustrate an exemplary SoC. In at least one embodiment, devices illustrated in FIG. 14 may be interconnected with proprietary interconnects, standardized interconnects (e.g., PCIe) or some combination thereof. In at least one embodiment, one or more components of FIG. 14 are interconnected using compute express link (CXL) interconnects.

[0299] In at least one embodiment, FIG. 14 may include a display 1424, a touch screen 1425, a touch pad 1430, a Near Field Communications unit (“NFC”) 1445, a sensor hub 1440, a thermal sensor 1446, an Express Chipset (“EC”) 1435, a Trusted Platform Module (“TPM”) 1438, BlOS / firmware / flash memory (“BIOS, FW Flash”) 1422, a DSP 1460, a drive 1420 such as a Solid State Disk (“SSD”) or a Hard Disk Drive (“HDD”), a wireless local area network unit (“WLAN”) 1450, a Bluetooth unit 1452, a Wireless Wide Area Network unit (“WWAN”) 1456, a Global Positioning System (GPS) unit 1455, a camera (“USB 3.0 camera”) 1454 such as a USB 3.0 camera, and / or a Low Power Double Data Rate (“LPDDR”) memory unit (“LPDDR3”) 1415 implemented in, for example, an LPDDR3 standard. These components may each be implemented in any suitable manner.

[0300] In at least one embodiment, other components may be communicatively coupled to processor 1410 through components described herein. In at least one embodiment, an accelerometer 1441, an ambient light sensor (“ALS”) 1442, a compass 1443, and a gyroscope 1444 may be communicatively coupled to sensor hub 1440. In at least one embodiment, a thermal sensor 1439, a fan 1437, a keyboard 1436, and touch pad 1430 may be communicatively coupled to EC 1435. In at least one embodiment, speakers 1463, headphones 1464, and a microphone (“mic”) 1465 may be communicatively coupled to an audio unit (“audio codec and class D amp”) 1462, which may in turn be communicatively coupled to DSP 1460. In at least one embodiment, audio unit 1462 may include, for example and without limitation, an audio coder / decoder (“codec”) and a class D amplifier. In at least one embodiment, a SIM card (“SIM”) 1457 may be communicatively coupled to WWAN unit 1456. In at least one embodiment, components such as WLAN unit 1450 and Bluetooth unit 1452, as well as WWAN unit 1456 may be implemented in a Next Generation Form Factor (“NGFF”).

[0301] Logic 915 are used to perform inferencing and / or training operations associated with one or more embodiments. Details regarding logic 915 are provided herein in conjunction with FIGS. 9A and / or 9B. In at least one embodiment, logic 915 may be used in electronic device 1400 for inferencing or predicting operations based, at least in part, on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0302] In at least one embodiment, at least one component shown or described with respect to FIG. 14 is utilized to implement techniques and / or functions described in connection with FIGS. 1-8. In at least one embodiment, at least one component of FIG. 14 is used to cause generation of an API, parameters, libraries, runtimes, drivers, kernels, distributing kernels to one or more GPUs, and to cause execution of a kernel on one or more GPUs. In at least one embodiment, at least one component of FIG. 14 performs at least one aspect described with respect to data scaling system 100, device 102, data conversion manager 104, scaling module 106, machine learning modules 108, processors 110, communication manager 112, storage device 114, devices 116, cores 118A-118Z, storage device 120, processors 122, tensor scaling 200, input tensor 202, generate sub-tensor 204, sub-tensors 206A-206N, identify local maximum 208A-208N, scaled sub-tensor 210A-210N, converted sub-tensor 212A-212N, identify global maximum 214, scale with global maximum 216, data format conversion 300, values in first data format 320, scaling 304, data conversions 306, values in second data format 308, scaling operations 400, values in second data format 402, data evaluation 403, data comparison 404, global maximum determination 405, no data re-scale 406, data re-scale 408, operations of one or more scaling modules 500, method 600, method 700, processor 800, processor 820, conversion module 822, and / or scaling module 824.

[0303] FIG. 15 illustrates a computer system 1500, according to at least one embodiment. In at least one embodiment, computer system 1500 is configured to implement various processes and methods described throughout this disclosure.

[0304] In at least one embodiment, computer system 1500 comprises, without limitation, at least one central processing unit (“CPU”) 1502 that is connected to a communication bus 1510 implemented using any suitable protocol, such as PCI (“Peripheral Component Interconnect”), peripheral component interconnect express (“PCI-Express”), AGP (“Accelerated Graphics Port”), HyperTransport, or any other bus or point-to-point communication protocol(s). In at least one embodiment, computer system 1500 includes, without limitation, a main memory1504 and control logic (e.g., implemented as hardware, software, or a combination thereof) and data are stored in main memory 1504, which may take form of random access memory (“RAM”). In at least one embodiment, a network interface subsystem (“network interface”) 1522 provides an interface to other computing devices and networks for receiving data from and transmitting data to other systems with computer system 1500.

[0305] In at least one embodiment, computer system 1500, in at least one embodiment, includes, without limitation, input devices 1508, a parallel processing system 1512, and display devices 1506 that can be implemented using a conventional cathode ray tube (“CRT”), a liquid crystal display (“LCD”), a light emitting diode (“LED”) display, a plasma display, or other suitable display technologies. In at least one embodiment, user input is received from input devices 1508 such as keyboard, mouse, touchpad, microphone, etc. In at least one embodiment, each module described herein can be situated on a single semiconductor platform to form a processing system.

[0306] Logic 915 are used to perform inferencing and / or training operations associated with one or more embodiments. Details regarding inference and / or training logic 915 are provided herein in conjunction with FIGS. 9A and / or 9B. In at least one embodiment, logic 915 may be used in computer system 1500 for inferencing or predicting operations based, at least in part, on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0307] In at least one embodiment, at least one component shown or described with respect to FIG. 15 is utilized to implement techniques and / or functions described in connection with FIGS. 1-8. In at least one embodiment, at least one component of FIG. 15 is used to cause generation of an API, parameters, libraries, runtimes, drivers, kernels, distributing kernels to one or more GPUs, and to cause execution of a kernel on one or more GPUs. In at least one embodiment, at least one component of FIG. 15 performs at least one aspect described with respect to data scaling system 100, device 102, data conversion manager 104, scaling module 106, machine learning modules 108, processors 110, communication manager 112, storage device 114, devices 116, cores 118A-118Z, storage device 120, processors 122, tensor scaling 200, input tensor 202, generate sub-tensor 204, sub-tensors 206A-206N, identify local maximum 208A-208N, scaled sub-tensor 210A-210N, converted sub-tensor 212A-212N, identify global maximum 214, scale with global maximum 216, data format conversion 300, values in first data format 320, scaling 304, data conversions 306, values in second data format308, scaling operations 400, values in second data format 402, data evaluation 403, data comparison 404, global maximum determination 405, no data re-scale 406, data re-scale 408, operations of one or more scaling modules 500, method 600, method 700, processor 800, processor 820, conversion module 822, and / or scaling module 824.

[0308] FIG. 16 illustrates a computer system 1600, according to at least one embodiment. In at least one embodiment, computer system 1600 includes, without limitation, a computer 1610 and a USB stick 1620. In at least one embodiment, computer 1610 may include, without limitation, any number and type of processor(s) (not shown) and a memory (not shown). In at least one embodiment, computer 1610 includes, without limitation, a server, a cloud instance, a laptop, and a desktop computer.

[0309] In at least one embodiment, USB stick 1620 includes, without limitation, a processing unit 1630, a USB interface 1640, and USB interface logic 1650. In at least one embodiment, processing unit 1630 may be any instruction execution system, apparatus, or device capable of executing instructions. In at least one embodiment, processing unit 1630 may include, without limitation, any number and type of processing cores (not shown). In at least one embodiment, processing unit 1630 comprises an application specific integrated circuit (“ASIC”) that is optimized to perform any amount and type of operations associated with machine learning. For instance, in at least one embodiment, processing unit 1630 is a tensor processing unit (“TPC”) that is optimized to perform machine learning inference operations. In at least one embodiment, processing unit 1630 is a vision processing unit (“VPU”) that is optimized to perform machine vision and machine learning inference operations.

[0310] In at least one embodiment, USB interface 1640 may be any type of USB connector or USB socket. For instance, in at least one embodiment, USB interface 1640 is a USB 3.0 Type-C socket for data and power. In at least one embodiment, USB interface 1640 is a USB 3.0 Type-A connector. In at least one embodiment, USB interface logic 1650 may include any amount and type of logic that enables processing unit 1630 to interface with devices (e.g., computer 1610) via USB connector 1640.

[0311] Logic 915 are used to perform inferencing and / or training operations associated with one or more embodiments. Details regarding logic 915 are provided herein in conjunction with FIGS. 9A and / or 9B. In at least one embodiment, logic 915 may be used in computer system 1600 for inferencing or predicting operations based, at least in part, on weight parameterscalculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0312] In at least one embodiment, at least one component shown or described with respect to FIG. 16 is utilized to implement techniques and / or functions described in connection with FIGS. 1-8. In at least one embodiment, at least one component of FIG. 16 is used to cause generation of an API, parameters, libraries, runtimes, drivers, kernels, distributing kernels to one or more GPUs, and to cause execution of a kernel on one or more GPUs. In at least one embodiment, at least one component of FIG. 16 performs at least one aspect described with respect to data scaling system 100, device 102, data conversion manager 104, scaling module 106, machine learning modules 108, processors 110, communication manager 112, storage device 114, devices 116, cores 118A-118Z, storage device 120, processors 122, tensor scaling 200, input tensor 202, generate sub-tensor 204, sub-tensors 206A-206N, identify local maximum 208A-208N, scaled sub-tensor 210A-210N, converted sub-tensor 212A-212N, identify global maximum 214, scale with global maximum 216, data format conversion 300, values in first data format 320, scaling 304, data conversions 306, values in second data format 308, scaling operations 400, values in second data format 402, data evaluation 403, data comparison 404, global maximum determination 405, no data re-scale 406, data re-scale 408, operations of one or more scaling modules 500, method 600, method 700, processor 800, processor 820, conversion module 822, and / or scaling module 824.

[0313] FIG. 17A illustrates an exemplary architecture in which a plurality of GPUs 1710(1)- 1710(N) is communicatively coupled to a plurality of multi-core processors 1705(l)-1705(M) over high-speed links 1740(l)-1740(N) (e.g., buses, point-to-point interconnects, etc.). In at least one embodiment, high-speed links 1740(l)-1740(N) support a communication throughput of 4 GB / s, 30 GB / s, 80 GB / s or higher. In at least one embodiment, various interconnect protocols may be used including, but not limited to, PCIe 4.0 or 5.0 and NVLink 2.0. In various figures, “N” and “M” represent positive integers, values of which may be different from figure to figure. In at least one embodiment, one or more GPUs in a plurality of GPUs 1710(1)- 1710(N) includes one or more graphics cores (also referred to simply as “cores”) 2000 as disclosed in Figures 20 A and 20B. In at least one embodiment, one or more graphics cores 2000 may be referred to as streaming multiprocessors (“SMs”), stream processors (“SPs”), stream processing units (“SPUs”), compute units (“CUs”), execution units (“EUs”), and / or slices, where a slice in this context can refer to a portion of processing resources in a processing unit (e.g., 16 cores, a ray tracing unit, a thread director or scheduler).

[0314] In addition, and in at least one embodiment, two or more of GPUs 1710 are interconnected over high-speed links 1729(1)- 1729(2), which may be implemented using similar or different protocol s / links than those used for high-speed links 1740(l)-1740(N). Similarly, two or more of multi-core processors 1705 may be connected over a high-speed link 1728 which may be symmetric multi-processor (SMP) buses operating at 20 GB / s, 30 GB / s, 120 GB / s or higher. Alternatively, all communication between various system components shown in FIG. 17A may be accomplished using similar protocol s / links (e.g., over a common interconnection fabric).

[0315] In at least one embodiment, each multi-core processor 1705 is communicatively coupled to a processor memory 1701(l)-1701(M), via memory interconnects 1726(1)- 1726(M), respectively, and each GPU 1710(l)-1710(N) is communicatively coupled to GPU memory 1720(l)-1720(N) over GPU memory interconnects 1750(l)-1750(N), respectively. In at least one embodiment, memory interconnects 1726 and 1750 may utilize similar or different memory access technologies. By way of example, and not limitation, processor memories 1701(l)-1701(M) and GPU memories 1720 may be volatile memories such as dynamic random access memories (DRAMs) (including stacked DRAMs), Graphics DDR SDRAM (GDDR) (e.g., GDDR5, GDDR6), or High Bandwidth Memory (HBM) and / or may be non-volatile memories such as 3D XPoint or Nano-Ram. In at least one embodiment, some portion of processor memories 1701 may be volatile memory and another portion may be non-volatile memory (e.g., using a two-level memory (2LM) hierarchy).

[0316] As described herein, although various multi-core processors 1705 and GPUs 1710 may be physically coupled to a particular memory 1701, 1720, respectively, and / or a unified memory architecture may be implemented in which a virtual system address space (also referred to as “effective address” space) is distributed among various physical memories. For example, processor memories 1701(l)-1701(M) may each comprise 64 GB of system memory address space and GPU memories 1720(l)-1720(N) may each comprise 32 GB of system memory address space resulting in a total of 256 GB addressable memory when M=2 and N=4. Other values for N and M are possible.

[0317] In at least one embodiment, at least one component shown or described with respect to FIG. 17A is utilized to implement techniques and / or functions described in connection with FIGS. 1-8. In at least one embodiment, at least one component of FIG. 17A is used to cause generation of an API, parameters, libraries, runtimes, drivers, kernels, distributingkernels to one or more GPUs, and to cause execution of a kernel on one or more GPUs. In at least one embodiment, at least one component of FIG. 17A performs at least one aspect described with respect to data scaling system 100, device 102, data conversion manager 104, scaling module 106, machine learning modules 108, processors 110, communication manager 112, storage device 114, devices 116, cores 118A-118Z, storage device 120, processors 122, tensor scaling 200, input tensor 202, generate sub-tensor 204, sub-tensors 206A-206N, identify local maximum 208A-208N, scaled sub-tensor 21 OA-210N, converted sub -tensor 212A-212N, identify global maximum 214, scale with global maximum 216, data format conversion 300, values in first data format 320, scaling 304, data conversions 306, values in second data format 308, scaling operations 400, values in second data format 402, data evaluation 403, data comparison 404, global maximum determination 405, no data re-scale 406, data re-scale 408, operations of one or more scaling modules 500, method 600, method 700, processor 800, processor 820, conversion module 822, and / or scaling module 824.

[0318] FIG. 17B illustrates additional details for an interconnection between a multi-core processor 1707 and a graphics acceleration module 1746 in accordance with one exemplary embodiment. In at least one embodiment, graphics acceleration module 1746 may include one or more GPU chips integrated on a line card which is coupled to processor 1707 via high-speed link 1740 (e.g., a PCIe bus, NVLink, etc.). In at least one embodiment, graphics acceleration module 1746 may alternatively be integrated on a package or chip with processor 1707.

[0319] In at least one embodiment, processor 1707 includes a plurality of cores 1760A- 1760D (which may be referred to as “execution units”), each with a translation lookaside buffer (“TLB”) 1761A-1761D and one or more caches 1762A-1762D. In at least one embodiment, cores 1760A-1760D may include various other components for executing instructions and processing data that are not illustrated. In at least one embodiment, caches 1762A-1762D may comprise Level 1 (LI) and Level 2 (L2) caches. In addition, one or more shared caches 1756 may be included in caches 1762A-1762D and shared by sets of cores 1760A-1760D. For example, one embodiment of processor 1707 includes 24 cores, each with its own LI cache, twelve shared L2 caches, and twelve shared L3 caches. In this embodiment, one or more L2 and L3 caches are shared by two adjacent cores. In at least one embodiment, processor 1707 and graphics acceleration module 1746 connect with system memory 1714, which may include processor memories 1701(l)-1701(M) of FIG. 17A.

[0320] In at least one embodiment, coherency is maintained for data and instructions stored in various caches 1762A-1762D, 1756 and system memory 1714 via inter-core communication over a coherence bus 1764. In at least one embodiment, for example, each cache may have cache coherency logic / circuitry associated therewith to communicate to over coherence bus 1764 in response to detected reads or writes to particular cache lines. In at least one embodiment, a cache snooping protocol is implemented over coherence bus 1764 to snoop cache accesses.

[0321] In at least one embodiment, a proxy circuit 1725 communicatively couples graphics acceleration module 1746 to coherence bus 1764, allowing graphics acceleration module 1746 to participate in a cache coherence protocol as a peer of cores 1760A-1760D. In particular, in at least one embodiment, an interface 1735 provides connectivity to proxy circuit 1725 over high-speed link 1740 and an interface 1737 connects graphics acceleration module 1746 to high-speed link 1740.

[0322] In at least one embodiment, an accelerator integration circuit 1736 provides cache management, memory access, context management, and interrupt management services on behalf of a plurality of graphics processing engines 1731(1)-1731(N) of graphics acceleration module 1746. In at least one embodiment, graphics processing engines 1731 (1)-1731 (N) may each comprise a separate graphics processing unit (GPU). In at least one embodiment, plurality of graphics processing engines 1731(1)-1731(N) of graphics acceleration module 1746 include one or more graphics cores 2000 as discussed in connection with Figures 20A and 20B. In at least one embodiment, graphics processing engines 1731(1)-1731(N) alternatively may comprise different types of graphics processing engines within a GPU, such as graphics execution units, media processing engines (e.g., video encoders / decoders), samplers, and blit engines. In at least one embodiment, graphics acceleration module 1746 may be a GPU with a plurality of graphics processing engines 1731(1)-1731(N) or graphics processing engines 1731 (1)- 1731(N) may be individual GPUs integrated on a common package, line card, or chip.

[0323] In at least one embodiment, accelerator integration circuit 1736 includes a memory management unit (MMU) 1739 for performing various memory management functions such as virtual-to-physical memory translations (also referred to as effective-to-real memory translations) and memory access protocols for accessing system memory 1714. In at least one embodiment, MMU 1739 may also include a translation lookaside buffer (TLB) (not shown) for caching virtual / effective to physical / real address translations. In at least one embodiment,a cache 1738 can store commands and data for efficient access by graphics processing engines 1731(1)-1731 (N). In at least one embodiment, data stored in cache 1738 and graphics memories 1733(1)-1733(M) is kept coherent with core caches 1762A-1762D, 1756 and system memory 1714, possibly using a fetch unit 1744. As mentioned, this may be accomplished via proxy circuit 1725 on behalf of cache 1738 and memories 1733(1)-1733(M) (e.g., sending updates to cache 1738 related to modifications / accesses of cache lines on processor caches 1762A-1762D, 1756 and receiving updates from cache 1738).

[0324] In at least one embodiment, a set of registers 1745 store context data for threads executed by graphics processing engines 1731(1)-1731(N) and a context management circuit 1748 manages thread contexts. For example, context management circuit 1748 may perform save and restore operations to save and restore contexts of various threads during contexts switches (e.g., where a first thread is saved and a second thread is stored so that a second thread can be execute by a graphics processing engine). For example, on a context switch, context management circuit 1748 may store current register values to a designated region in memory (e.g., identified by a context pointer). It may then restore register values when returning to a context. In at least one embodiment, an interrupt management circuit 1747 receives and processes interrupts received from system devices.

[0325] In at least one embodiment, virtual / effective addresses from a graphics processing engine 1731 are translated to real / physical addresses in system memory 1714 by MMU 1739. In at least one embodiment, accelerator integration circuit 1736 supports multiple (e.g., 4, 8, 16) graphics accelerator modules 1746 and / or other accelerator devices. In at least one embodiment, graphics accelerator module 1746 may be dedicated to a single application executed on processor 1707 or may be shared between multiple applications. In at least one embodiment, a virtualized graphics execution environment is presented in which resources of graphics processing engines 1731 (1)-1731(N) are shared with multiple applications or virtual machines (VMs). In at least one embodiment, resources may be subdivided into “slices” which are allocated to different VMs and / or applications based on processing requirements and priorities associated with VMs and / or applications.

[0326] In at least one embodiment, accelerator integration circuit 1736 performs as a bridge to a system for graphics acceleration module 1746 and provides address translation and system memory cache services. In addition, in at least one embodiment, accelerator integration circuit1736 may provide virtualization facilities for a host processor to manage virtualization of graphics processing engines 1731 (1)-1731 (N), interrupts, and memory management.

[0327] In at least one embodiment, because hardware resources of graphics processing engines 1731 (1)-1731(N) are mapped explicitly to a real address space seen by host processor 1707, any host processor can address these resources directly using an effective address value. In at least one embodiment, one function of accelerator integration circuit 1736 is physical separation of graphics processing engines 1731 (1)- 1731 (N) so that they appear to a system as independent units.

[0328] In at least one embodiment, one or more graphics memories 1733(1)-1733(M) are coupled to each of graphics processing engines 1731(1)-1731(N), respectively and N=M. In at least one embodiment, graphics memories 1733(1)- 1733(M) store instructions and data being processed by each of graphics processing engines 1731(1)-1731(N). In at least one embodiment, graphics memories 1733(1)-1733(M) may be volatile memories such as DRAMs (including stacked DRAMs), GDDR memory (e.g., GDDR5, GDDR6), or HBM, and / or may be non-volatile memories such as 3D XPoint or Nano-Ram.

[0329] In at least one embodiment, to reduce data traffic over high-speed link 1740, biasing techniques can be used to ensure that data stored in graphics memories 1733(1)-1733(M) is data that will be used most frequently by graphics processing engines 1731(1)-1731(N) and preferably not used by cores 1760A-1760D (at least not frequently). Similarly, in at least one embodiment, a biasing mechanism attempts to keep data needed by cores (and preferably not graphics processing engines 1731 (1)-1731(N)) within caches 1762A-1762D, 1756 and system memory 1714.

[0330] In at least one embodiment, at least one component shown or described with respect to FIG. 17B is utilized to implement techniques and / or functions described in connection with FIGS. 1-8. In at least one embodiment, at least one component of FIG. 17B is used to cause generation of an API, parameters, libraries, runtimes, drivers, kernels, distributing kernels to one or more GPUs, and to cause execution of a kernel on one or more GPUs. In at least one embodiment, at least one component of FIG. 17B performs at least one aspect described with respect to data scaling system 100, device 102, data conversion manager 104, scaling module 106, machine learning modules 108, processors 110, communication manager 112, storage device 114, devices 116, cores 118A-118Z, storage device 120, processors 122, tensor scaling 200, input tensor 202, generate sub-tensor 204, sub-tensors 206A-206N, identifylocal maximum 208A-208N, scaled sub-tensor 21 OA-2 ION, converted sub -tensor 212A-212N, identify global maximum 214, scale with global maximum 216, data format conversion 300, values in first data format 320, scaling 304, data conversions 306, values in second data format 308, scaling operations 400, values in second data format 402, data evaluation 403, data comparison 404, global maximum determination 405, no data re-scale 406, data re-scale 408, operations of one or more scaling modules 500, method 600, method 700, processor 800, processor 820, conversion module 822, and / or scaling module 824.

[0331] FIG. 17C illustrates another exemplary embodiment in which accelerator integration circuit 1736 is integrated within processor 1707. In this embodiment, graphics processing engines 1731(1)-1731(N) communicate directly over high-speed link 1740 to accelerator integration circuit 1736 via interface 1737 and interface 1735 (which, again, may be any form of bus or interface protocol). In at least one embodiment, accelerator integration circuit 1736 may perform similar operations as those described with respect to FIG. 17B, but potentially at a higher throughput given its close proximity to coherence bus 1764 and caches 1762A-1762D, 1756. In at least one embodiment, an accelerator integration circuit supports different programming models including a dedicated-process programming model (no graphics acceleration module virtualization) and shared programming models (with virtualization), which may include programming models which are controlled by accelerator integration circuit 1736 and programming models which are controlled by graphics acceleration module 1746.

[0332] In at least one embodiment, graphics processing engines 1731(1)-1731(N) are dedicated to a single application or process under a single operating system. In at least one embodiment, a single application can funnel other application requests to graphics processing engines 1731 (1)-1731 (N), providing virtualization within a VM / partition.

[0333] In at least one embodiment, graphics processing engines 1731 (1)- 1731 (N), may be shared by multiple VM / application partitions. In at least one embodiment, shared models may use a system hypervisor to virtualize graphics processing engines 1731(1)-1731(N) to allow access by each operating system. In at least one embodiment, for single-partition systems without a hypervisor, graphics processing engines 1731 (1 )- 1731(N) are owned by an operating system. In at least one embodiment, an operating system can virtualize graphics processing engines 1731 (1)-1731 (N) to provide access to each process or application.

[0334] In at least one embodiment, graphics acceleration module 1746 or an individual graphics processing engine 1731 (1 )- 1731(N) selects a process element using a process handle.In at least one embodiment, process elements are stored in system memory 1714 and are addressable using an effective address to real address translation technique described herein. In at least one embodiment, a process handle may be an implementation-specific value provided to a host process when registering its context with graphics processing engine 1731(1)-1731 (N) (that is, calling system software to add a process element to a process element linked list). In at least one embodiment, a lower 16-bits of a process handle may be an offset of a process element within a process element linked list.

[0335] In at least one embodiment, at least one component shown or described with respect to FIG. 17C is utilized to implement techniques and / or functions described in connection with FIGS. 1-8. In at least one embodiment, at least one component of FIG. 17C is used to cause generation of an API, parameters, libraries, runtimes, drivers, kernels, distributing kernels to one or more GPUs, and to cause execution of a kernel on one or more GPUs. In at least one embodiment, at least one component of FIG. 17C performs at least one aspect described with respect to data scaling system 100, device 102, data conversion manager 104, scaling module 106, machine learning modules 108, processors 110, communication manager 112, storage device 114, devices 116, cores 118A-118Z, storage device 120, processors 122, tensor scaling 200, input tensor 202, generate sub-tensor 204, sub-tensors 206A-206N, identify local maximum 208A-208N, scaled sub-tensor 21 OA-210N, converted sub -tensor 212A-212N, identify global maximum 214, scale with global maximum 216, data format conversion 300, values in first data format 320, scaling 304, data conversions 306, values in second data format 308, scaling operations 400, values in second data format 402, data evaluation 403, data comparison 404, global maximum determination 405, no data re-scale 406, data re-scale 408, operations of one or more scaling modules 500, method 600, method 700, processor 800, processor 820, conversion module 822, and / or scaling module 824.

[0336] FIG. 17D illustrates an exemplary accelerator integration slice 1790. In at least one embodiment, a “slice” comprises a specified portion of processing resources of accelerator integration circuit 1736. In at least one embodiment, an application is effective address space 1782 within system memory 1714 stores process elements 1783. In at least one embodiment, process elements 1783 are stored in response to GPU invocations 1781 from applications 1780 executed on processor 1707. In at least one embodiment, a process element 1783 contains process state for corresponding application 1780. In at least one embodiment, a work descriptor (WD) 1784 contained in process element 1783 can be a single job requested by anapplication or may contain a pointer to a queue of jobs. In at least one embodiment, WD 1784 is a pointer to a job request queue in an application’s effective address space 1782.

[0337] In at least one embodiment, graphics acceleration module 1746 and / or individual graphics processing engines 1731(1)-1731(N) can be shared by all or a subset of processes in a system. In at least one embodiment, an infrastructure for setting up process states and sending a WD 1784 to a graphics acceleration module 1746 to start a job in a virtualized environment may be included.

[0338] In at least one embodiment, a dedicated-process programming model is implementation-specific. In at least one embodiment, in this model, a single process owns graphics acceleration module 1746 or an individual graphics processing engine 1731. In at least one embodiment, when graphics acceleration module 1746 is owned by a single process, a hypervisor initializes accelerator integration circuit 1736 for an owning partition and an operating system initializes accelerator integration circuit 1736 for an owning process when graphics acceleration module 1746 is assigned.

[0339] In at least one embodiment, in operation, a WD fetch unit 1791 in accelerator integration slice 1790 fetches next WD 1784, which includes an indication of work to be done by one or more graphics processing engines of graphics acceleration module 1746. In at least one embodiment, data from WD 1784 may be stored in registers 1745 and used by MMU 1739, interrupt management circuit 1747 and / or context management circuit 1748 as illustrated. For example, one embodiment of MMU 1739 includes segment / page walk circuitry for accessing segment / page tables 1786 within an OS virtual address space 1785. In at least one embodiment, interrupt management circuit 1747 may process interrupt events 1792 received from graphics acceleration module 1746. In at least one embodiment, when performing graphics operations, an effective address 1793 generated by a graphics processing engine 1731(1)-1731(N) is translated to a real address by MMU 1739.

[0340] In at least one embodiment, registers 1745 are duplicated for each graphics processing engine 1731(1)-1731(N) and / or graphics acceleration module 1746 and may be initialized by a hypervisor or an operating system. In at least one embodiment, each of these duplicated registers may be included in an accelerator integration slice 1790. Exemplary registers that may be initialized by a hypervisor are shown in Table 1.Table 1 - Hypervisor Initialized RegistersRegister # Description1 Slice Control Register2 Real Address (RA) Scheduled Processes Area Pointer3 Authority Mask Override Register4 Interrupt Vector Table Entry Offset5 Interrupt Vector Table Entry Limit6 State Register7 Logical Partition ID8 Real address (RA) Hypervisor Accelerator Utilization Record Pointer9 Storage Description Register

[0031] Exemplary registers that may be initialized by an operating system are shown in Table 2.Table 2 - Operating System Initialized RegistersRegister # Description1 Process and Thread Identification2 Effective Address (EA) Context Save / Restore Pointer3 Virtual Address (VA) Accelerator Utilization Record Pointer4 Virtual Address (VA) Storage Segment Table Pointer5 Authority Mask6 Work descriptor

[0342] In at least one embodiment, each WD 1784 is specific to a particular graphics acceleration module 1746 and / or graphics processing engines 1731 ( 1 )- 1731(N). In at least one embodiment, it contains all information required by a graphics processing engine 1731(1)- 1731(N) to do work, or it can be a pointer to a memory location where an application has set up a command queue of work to be completed.

[0343] In at least one embodiment, at least one component shown or described with respect to FIG. 17D is utilized to implement techniques and / or functions described in connection with FIGS. 1-8. In at least one embodiment, at least one component of FIG. 17D is used to cause generation of an API, parameters, libraries, runtimes, drivers, kernels, distributing kernels to one or more GPUs, and to cause execution of a kernel on one or more GPUs. In at least one embodiment, at least one component of FIG. 17D performs at least one aspectdescribed with respect to data scaling system 100, device 102, data conversion manager 104, scaling module 106, machine learning modules 108, processors 110, communication manager 112, storage device 114, devices 116, cores 118A-118Z, storage device 120, processors 122, tensor scaling 200, input tensor 202, generate sub-tensor 204, sub-tensors 206A-206N, identify local maximum 208A-208N, scaled sub-tensor 21 OA-210N, converted sub -tensor 212A-212N, identify global maximum 214, scale with global maximum 216, data format conversion 300, values in first data format 320, scaling 304, data conversions 306, values in second data format 308, scaling operations 400, values in second data format 402, data evaluation 403, data comparison 404, global maximum determination 405, no data re-scale 406, data re-scale 408, operations of one or more scaling modules 500, method 600, method 700, processor 800, processor 820, conversion module 822, and / or scaling module 824.

[0344] FIG. 17E illustrates additional details for one exemplary embodiment of a shared model. This embodiment includes a hypervisor real address space 1798 in which a process element list 1799 is stored. In at least one embodiment, hypervisor real address space 1798 is accessible via a hypervisor 1796 which virtualizes graphics acceleration module engines for operating system 1795.

[0345] In at least one embodiment, shared programming models allow for all or a subset of processes from all or a subset of partitions in a system to use a graphics acceleration module 1746. In at least one embodiment, there are two programming models where graphics acceleration module 1746 is shared by multiple processes and partitions, namely time-sliced shared and graphics directed shared.

[0346] In at least one embodiment, in this model, system hypervisor 1796 owns graphics acceleration module 1746 and makes its function available to all operating systems 1795. In at least one embodiment, for a graphics acceleration module 1746 to support virtualization by system hypervisor 1796, graphics acceleration module 1746 may adhere to certain requirements, such as (1) an application’s job request must be autonomous (that is, state does not need to be maintained between jobs), or graphics acceleration module 1746 must provide a context save and restore mechanism, (2) an application’s job request is guaranteed by graphics acceleration module 1746 to complete in a specified amount of time, including any translation faults, or graphics acceleration module 1746 provides an ability to preempt processing of a job, and (3) graphics acceleration module 1746 must be guaranteed fairness between processes when operating in a directed shared programming model.

[0347] In at least one embodiment, application 1780 is required to make an operating system 1795 system call with a graphics acceleration module type, a work descriptor (WD), an authority mask register (AMR) value, and a context save / restore area pointer (CSRP). In at least one embodiment, graphics acceleration module type describes a targeted acceleration function for a system call. In at least one embodiment, graphics acceleration module type may be a system-specific value. In at least one embodiment, WD is formatted specifically for graphics acceleration module 1746 and can be in a form of a graphics acceleration module 1746 command, an effective address pointer to a user-defined structure, an effective address pointer to a queue of commands, or any other data structure to describe work to be done by graphics acceleration module 1746.

[0348] In at least one embodiment, an AMR value is an AMR state to use for a current process. In at least one embodiment, a value passed to an operating system is similar to an application setting an AMR. In at least one embodiment, if accelerator integration circuit 1736 (not shown) and graphics acceleration module 1746 implementations do not support a User Authority Mask Override Register (UAMOR), an operating system may apply a current UAMOR value to an AMR value before passing an AMR in a hypervisor call. In at least one embodiment, hypervisor 1796 may optionally apply a current Authority Mask Override Register (AMOR) value before placing an AMR into process element 1783. In at least one embodiment, CSRP is one of registers 1745 containing an effective address of an area in an application’s effective address space 1782 for graphics acceleration module 1746 to save and restore context state. In at least one embodiment, this pointer is optional if no state is required to be saved between jobs or when a job is preempted. In at least one embodiment, context save / restore area may be pinned system memory.

[0349] Upon receiving a system call, operating system 1795 may verify that application 1780 has registered and been given authority to use graphics acceleration module 1746. In at least one embodiment, operating system 1795 then calls hypervisor 1796 with information shown in Table 3.Table 3 - OS to Hypervisor Call ParametersParameter # Description1 A work descriptor (WD)2 An Authority Mask Register (AMR) value (potentially masked)3 An effective address (EA) Context Save / Restore Area Pointer (CSRP)4 A process ID (PID) and optional thread ID (TID)5 A virtual address (VA) accelerator utilization record pointer (AURP)6 Virtual address of storage segment table pointer (SSTP)7 A logical interrupt service number (LISN)

[0350] In at least one embodiment, upon receiving a hypervisor call, hypervisor 1796 verifies that operating system 1795 has registered and been given authority to use graphics acceleration module 1746. In at least one embodiment, hypervisor 1796 then puts process element 1783 into a process element linked list for a corresponding graphics acceleration module 1746 type. In at least one embodiment, a process element may include information shown in Table 4.Table 4 -Process Element InformationElement # Description1 A work descriptor (WD)2 An Authority Mask Register (AMR) value (potentially masked).3 An effective address (EA) Context Save / Restore Area Pointer (CSRP)4 A process ID (PID) and optional thread ID (TID)5 A virtual address (VA) accelerator utilization record pointer (AURP)6 Virtual address of storage segment table pointer (SSTP)7 A logical interrupt service number (LISN)8 Interrupt vector table, derived from hypervisor call parameters9 A state register (SR) value10 A logical partition ID (LPID)11 A real address (RA) hypervisor accelerator utilization record pointer12 Storage Descriptor Register (SDR)

[0351] In at least one embodiment, hypervisor initializes a plurality of accelerator integration slice 1790 registers 1745.

[0352] In at least one embodiment, at least one component shown or described with respect to FIG. 17E is utilized to implement techniques and / or functions described in connection with FIGS. 1-8. In at least one embodiment, at least one component of FIG. 17E is used to cause generation of an API, parameters, libraries, runtimes, drivers, kernels, distributing kernels to one or more GPUs, and to cause execution of a kernel on one or more GPUs. In at least one embodiment, at least one component of FIG. 17E performs at least one aspectdescribed with respect to data scaling system 100, device 102, data conversion manager 104, scaling module 106, machine learning modules 108, processors 110, communication manager 112, storage device 114, devices 116, cores 118A-118Z, storage device 120, processors 122, tensor scaling 200, input tensor 202, generate sub-tensor 204, sub-tensors 206A-206N, identify local maximum 208A-208N, scaled sub-tensor 21 OA-210N, converted sub -tensor 212A-212N, identify global maximum 214, scale with global maximum 216, data format conversion 300, values in first data format 320, scaling 304, data conversions 306, values in second data format 308, scaling operations 400, values in second data format 402, data evaluation 403, data comparison 404, global maximum determination 405, no data re-scale 406, data re-scale 408, operations of one or more scaling modules 500, method 600, method 700, processor 800, processor 820, conversion module 822, and / or scaling module 824.

[0353] As illustrated in FIG. 17F, in at least one embodiment, a unified memory is used, addressable via a common virtual memory address space used to access physical processor memories 1701(l)-1701(N) and GPU memories 1720(l)-1720(N). In this implementation, operations executed on GPUs 1710(l)-1710(N) utilize a same virtual / effective memory address space to access processor memories 1701(l)-1701(M) and vice versa, thereby simplifying programmability. In at least one embodiment, a first portion of a virtual / effective address space is allocated to processor memory 1701(1), a second portion to second processor memory 1701(N), a third portion to GPU memory 1720(1), and so on. In at least one embodiment, an entire virtual / effective memory space (sometimes referred to as an effective address space) is thereby distributed across each of processor memories 1701 and GPU memories 1720, allowing any processor or GPU to access any physical memory with a virtual address mapped to that memory.

[0354] In at least one embodiment, bias / coherence management circuitry 1794A-1794E within one or more of MMUs 1739A-1739E ensures cache coherence between caches of one or more host processors (e.g., 1705) and GPUs 1710 and implements biasing techniques indicating physical memories in which certain types of data should be stored. In at least one embodiment, while multiple instances of bias / coherence management circuitry 1794A-1794E are illustrated in FIG. 17F, bias / coherence circuitry may be implemented within an MMU of one or more host processors 1705 and / or within accelerator integration circuit 1736.

[0355] One embodiment allows GPU memories 1720 to be mapped as part of system memory, and accessed using shared virtual memory (SVM) technology, but without sufferingperformance drawbacks associated with full system cache coherence. In at least one embodiment, an ability for GPU memories 1720 to be accessed as system memory without onerous cache coherence overhead provides a beneficial operating environment for GPU offload. In at least one embodiment, this arrangement allows software of host processor 1705 to setup operands and access computation results, without overhead of tradition I / O DMA data copies. In at least one embodiment, such traditional copies involve driver calls, interrupts and memory mapped I / O (MMIO) accesses that are all inefficient relative to simple memory accesses. In at least one embodiment, an ability to access GPU memories 1720 without cache coherence overheads can be critical to execution time of an offloaded computation. In at least one embodiment, in cases with substantial streaming write memory traffic, for example, cache coherence overhead can significantly reduce an effective write bandwidth seen by a GPU 1710. In at least one embodiment, efficiency of operand setup, efficiency of results access, and efficiency of GPU computation may play a role in determining effectiveness of a GPU offload.

[0356] In at least one embodiment, selection of GPU bias and host processor bias is driven by a bias tracker data structure. In at least one embodiment, a bias table may be used, for example, which may be a page-granular structure (e.g., controlled at a granularity of a memory page) that includes 1 or 2 bits per GPU-attached memory page. In at least one embodiment, a bias table may be implemented in a stolen memory range of one or more GPU memories 1720, with or without a bias cache in a GPU 1710 (e.g., to cache frequently / recently used entries of a bias table). Alternatively, in at least one embodiment, an entire bias table may be maintained within a GPU.

[0357] In at least one embodiment, a bias table entry associated with each access to a GPU attached memory 1720 is accessed prior to actual access to a GPU memory, causing following operations. In at least one embodiment, local requests from a GPU 1710 that find their page in GPU bias are forwarded directly to a corresponding GPU memory 1720. In at least one embodiment, local requests from a GPU that find their page in host bias are forwarded to processor 1705 (e.g., over a high-speed link as described herein). In at least one embodiment, requests from processor 1705 that find a requested page in host processor bias complete a request like a normal memory read. Alternatively, requests directed to a GPU-biased page may be forwarded to a GPU 1710. In at least one embodiment, a GPU may then transition a page to a host processor bias if it is not currently using a page. In at least one embodiment, a bias state of a page can be changed either by a software-based mechanism, a hardware-assisted softwarebased mechanism, or, for a limited set of cases, a purely hardware-based mechanism.

[0358] In at least one embodiment, one mechanism for changing bias state employs an API call (e.g., OpenCL), which, in turn, calls a GPU’s device driver which, in turn, sends a message (or enqueues a command descriptor) to a GPU directing it to change a bias state and, for some transitions, perform a cache flushing operation in a host. In at least one embodiment, a cache flushing operation is used for a transition from host processor 1705 bias to GPU bias, but is not for an opposite transition.

[0359] In at least one embodiment, cache coherency is maintained by temporarily rendering GPU-biased pages uncacheable by host processor 1705. In at least one embodiment, to access these pages, processor 1705 may request access from GPU 1710, which may or may not grant access right away. In at least one embodiment, thus, to reduce communication between processor 1705 and GPU 1710 it is beneficial to ensure that GPU-biased pages are those which are required by a GPU but not host processor 1705 and vice versa.

[0360] Hardware structure(s) 915 are used to perform one or more embodiments. Details regarding a hardware structure(s) 915 may be provided herein in conjunction with FIGS. 9A and / or 9B.

[0361] In at least one embodiment, at least one component shown or described with respect to FIG. 17F is utilized to implement techniques and / or functions described in connection with FIGS. 1-8. In at least one embodiment, at least one component of FIG. 17F is used to cause generation of an API, parameters, libraries, runtimes, drivers, kernels, distributing kernels to one or more GPUs, and to cause execution of a kernel on one or more GPUs. In at least one embodiment, at least one component of FIG. 17F performs at least one aspect described with respect to data scaling system 100, device 102, data conversion manager 104, scaling module 106, machine learning modules 108, processors 110, communication manager 112, storage device 114, devices 116, cores 118A-118Z, storage device 120, processors 122, tensor scaling 200, input tensor 202, generate sub-tensor 204, sub-tensors 206A-206N, identify local maximum 208A-208N, scaled sub-tensor 21 OA-210N, converted sub -tensor 212A-212N, identify global maximum 214, scale with global maximum 216, data format conversion 300, values in first data format 320, scaling 304, data conversions 306, values in second data format 308, scaling operations 400, values in second data format 402, data evaluation 403, data comparison 404, global maximum determination 405, no data re-scale 406, data re-scale 408, operations of one or more scaling modules 500, method 600, method 700, processor 800, processor 820, conversion module 822, and / or scaling module 824.

[0362] FIG. 18 illustrates exemplary integrated circuits and associated graphics processors that may be fabricated using one or more IP cores, according to various embodiments described herein. In addition to what is illustrated, other logic and circuits may be included in at least one embodiment, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores.

[0363] FIG. 18 is a block diagram illustrating an exemplary system on a chip integrated circuit 1800 that may be fabricated using one or more IP cores, according to at least one embodiment. In at least one embodiment, integrated circuit 1800 includes one or more application processor(s) 1805 (e.g., CPUs), at least one graphics processor 1810, and may additionally include an image processor 1815 and / or a video processor 1820, any of which may be a modular IP core. In at least one embodiment, integrated circuit 1800 includes peripheral or bus logic including a USB controller 1825, a UART controller 1830, an SPI / SDIO controller 1835, and an I22S / I22C controller 1840. In at least one embodiment, integrated circuit 1800 can include a display device 1845 coupled to one or more of a high-definition multimedia interface (HDMI) controller 1850 and a mobile industry processor interface (MIPI) display interface 1855. In at least one embodiment, storage may be provided by a flash memory subsystem 1860 including flash memory and a flash memory controller. In at least one embodiment, a memory interface may be provided via a memory controller 1865 for access to SDRAM or SRAM memory devices. In at least one embodiment, some integrated circuits additionally include an embedded security engine 1870.

[0364] Logic 915 are used to perform inferencing and / or training operations associated with one or more embodiments. Details regarding logic 915 are provided herein in conjunction with FIGS. 9A and / or 9B. In at least one embodiment, logic 915 may be used in integrated circuit 1800 for inferencing or predicting operations based, at least in part, on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0365] In at least one embodiment, at least one component shown or described with respect to FIG. 18 is utilized to implement techniques and / or functions described in connection with FIGS. 1-8. In at least one embodiment, at least one component of FIG. 18 is used to cause generation of an API, parameters, libraries, runtimes, drivers, kernels, distributing kernels to one or more GPUs, and to cause execution of a kernel on one or more GPUs. In at least one embodiment, at least one component of FIG. 18 performs at least one aspect describedwith respect to data scaling system 100, device 102, data conversion manager 104, scaling module 106, machine learning modules 108, processors 110, communication manager 112, storage device 114, devices 116, cores 118A-118Z, storage device 120, processors 122, tensor scaling 200, input tensor 202, generate sub-tensor 204, sub-tensors 206A-206N, identify local maximum 208A-208N, scaled sub-tensor 210A-210N, converted sub-tensor 212A-212N, identify global maximum 214, scale with global maximum 216, data format conversion 300, values in first data format 320, scaling 304, data conversions 306, values in second data format 308, scaling operations 400, values in second data format 402, data evaluation 403, data comparison 404, global maximum determination 405, no data re-scale 406, data re-scale 408, operations of one or more scaling modules 500, method 600, method 700, processor 800, processor 820, conversion module 822, and / or scaling module 824.

[0366] FIGS. 19A-19B illustrate exemplary integrated circuits and associated graphics processors that may be fabricated using one or more IP cores, according to various embodiments described herein. In addition to what is illustrated, other logic and circuits may be included in at least one embodiment, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores.

[0367] FIGS. 19A-19B are block diagrams illustrating exemplary graphics processors for use within an SoC, according to embodiments described herein. FIG. 19A illustrates an exemplary graphics processor 1910 of a system on a chip integrated circuit that may be fabricated using one or more IP cores, according to at least one embodiment. FIG. 19B illustrates an additional exemplary graphics processor 1940 of a system on a chip integrated circuit that may be fabricated using one or more IP cores, according to at least one embodiment. In at least one embodiment, graphics processor 1910 of FIG. 19A is a low power graphics processor core. In at least one embodiment, graphics processor 1940 of FIG. 19B is a higher performance graphics processor core. In at least one embodiment, each of graphics processors 1910, 1940 can be variants of graphics processor 1810 of FIG. 18.

[0368] In at least one embodiment, graphics processor 1910 includes a vertex processor 1905 and one or more fragment processor(s) 1915A-1915N (e.g., 1915A, 1915B, 1915C, 1915D, through 1915N-1, and 1915N). In at least one embodiment, graphics processor 1910 can execute different shader programs via separate logic, such that vertex processor 1905 is optimized to execute operations for vertex shader programs, while one or more fragment processor(s) 1915A-1915N execute fragment (e.g., pixel) shading operations for fragment orpixel shader programs. In at least one embodiment, vertex processor 1905 performs a vertex processing stage of a 3D graphics pipeline and generates primitives and vertex data. In at least one embodiment, fragment processor(s) 1915A-1915N use primitive and vertex data generated by vertex processor 1905 to produce a framebuffer that is displayed on a display device. In at least one embodiment, fragment processor(s) 1915 A- 1915N are optimized to execute fragment shader programs as provided for in an OpenGL API, which may be used to perform similar operations as a pixel shader program as provided for in a Direct 3D API.

[0369] In at least one embodiment, graphics processor 1910 additionally includes one or more memory management units (MMUs) 1920A-1920B, cache(s) 1925A-1925B, and circuit interconnect(s) 1930A-1930B. In at least one embodiment, one or more MMU(s) 1920A- 1920B provide for virtual to physical address mapping for graphics processor 1910, including for vertex processor 1905 and / or fragment processor(s) 1915A-1915N, which may reference vertex or image / texture data stored in memory, in addition to vertex or image / texture data stored in one or more cache(s) 1925A-1925B. In at least one embodiment, one or more MMU(s) 1920A-1920B may be synchronized with other MMUs within a system, including one or more MMUs associated with one or more application processor(s) 1805, image processors 1815, and / or video processors 1820 of FIG. 18, such that each processor 1805-1820 can participate in a shared or unified virtual memory system. In at least one embodiment, one or more circuit interconnect s) 1930A-1930B enable graphics processor 1910 to interface with other IP cores within SoC, either via an internal bus of SoC or via a direct connection.

[0370] In at least one embodiment, graphics processor 1940 includes one or more shader core(s) 1955A-1955N (e.g., 1955A, 1955B, 1955C, 1955D, 1955E, 1955F, through 1955N-1, and 1955N) as shown in FIG. 19B, which provides for a unified shader core architecture in which a single core or type or core can execute all types of programmable shader code, including shader program code to implement vertex shaders, fragment shaders, and / or compute shaders. In at least one embodiment, a number of shader cores can vary. In at least one embodiment, graphics processor 1940 includes an inter-core task manager 1945, which acts as a thread dispatcher to dispatch execution threads to one or more shader cores 1955A-1955N and a tiling unit 1958 to accelerate tiling operations for tile-based rendering, in which rendering operations for a scene are subdivided in image space, for example to exploit local spatial coherence within a scene or to optimize use of internal caches.

[0371] Logic 915 are used to perform inferencing and / or training operations associated with one or more embodiments. Details regarding logic 915 are provided herein in conjunction with FIGS. 9A and / or 9B. In at least one embodiment, logic 915 may be used in graphics processor 1910 and / or 1940 for inferencing or predicting operations based, at least in part, on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0372] In at least one embodiment, at least one component shown or described with respect to FIG. 19A-19B is utilized to implement techniques and / or functions described in connection with FIGS. 1-8. In at least one embodiment, at least one component of FIG. 19A-19B is used to cause generation of an API, parameters, libraries, runtimes, drivers, kernels, distributing kernels to one or more GPUs, and to cause execution of a kernel on one or more GPUs. In at least one embodiment, at least one component of FIG. 19A-19B performs at least one aspect described with respect to data scaling system 100, device 102, data conversion manager 104, scaling module 106, machine learning modules 108, processors 110, communication manager 112, storage device 114, devices 116, cores 118A-118Z, storage device 120, processors 122, tensor scaling 200, input tensor 202, generate sub-tensor 204, sub-tensors 206A-206N, identify local maximum 208A-208N, scaled sub-tensor 21 OA-210N, converted sub -tensor 212A-212N, identify global maximum 214, scale with global maximum 216, data format conversion 300, values in first data format 320, scaling 304, data conversions 306, values in second data format 308, scaling operations 400, values in second data format 402, data evaluation 403, data comparison 404, global maximum determination 405, no data re-scale 406, data re-scale 408, operations of one or more scaling modules 500, method 600, method 700, processor 800, processor 820, conversion module 822, and / or scaling module 824.

[0373] FIGS. 20A-20B illustrate additional exemplary graphics processor logic according to embodiments described herein. In at least one embodiment, components illustrated in and described in connection with FIGS. 20A-20B are integrated into a single system, such as a graphics processing unit (GPU), SoC, or another type of processor. FIG. 20A illustrates a graphics core 2000 that may be included within graphics processor 1810 of FIG. 18, in at least one embodiment, and may be a unified shader core 1955A-1955N as in FIG. 19B in at least one embodiment. FIG. 20B illustrates a highly-parallel general-purpose graphics processing unit (“GPGPU”, which can also be referred to as a “graphics processing unit”) 2030 suitable for deployment on a multi-chip module in at least one embodiment. In at least one embodiment, graphics processing unit 2030 is a GPGPU that comprises a graphics processor. In at least oneembodiment, integrated circuit 1800 comprises graphics core 2000, e.g., to form an integrated circuit and / or to form an SoC, where such an integrated circuit and / or such an SoC perform operations described herein.

[0374] In at least one embodiment, graphics core 2000 includes a shared instruction cache 2002, a texture unit 2018, and a cache / shared memory 2020 (e.g., including LI, L2, L3, last level cache, or other caches) that are common to execution resources within graphics core 2000. In at least one embodiment, graphics core 2000 can include multiple slices 2001 A-2001N or a partition for each core, and a graphics processor can include multiple instances of graphics core 2000. In at least one embodiment, each slice 2001A-2001N refers to graphics core 2000. In at least one embodiment, slices 2001A-2001N have sub-slices, which are part of a slice 2001A- 200 IN. In at least one embodiment, slices 2001A-2001N are independent of other slices or dependent on other slices. In at least one embodiment, slices 2001A-2001N can include support logic including a local instruction cache 2004A-2004N, a thread scheduler (sequencer) 2006A- 2006N, a thread dispatcher 2008A-2008N, and a set of registers 2010A-2010N. In at least one embodiment, slices 2001 A-2001N can include a set of additional function units (AFUs 2012A- 2012N), floating-point units (FPUs 2014A-2014N), integer arithmetic logic units (ALUs 2016A-2016N), address computational units (ACUs 2013A-2013N), double-precision floating-point units (DPFPUs 2015A-2015N), and matrix processing units (MPUs 2017A- 2017N). In at least one embodiment, MPUs 2017A-2017N are referred to as matrix engines.

[0375] In at least one embodiment, each slice 2001A-2001N includes one or more engines for floating point and integer vector operations and one or more engines to accelerate convolution and matrix operations in Al, machine learning, or large dataset workloads. In at least one embodiment, one or more slices 2001 A-2001N include one or more vector engines to compute a vector (e.g., compute mathematical operations for vectors). In at least one embodiment, a vector engine can compute a vector operation in 16-bit floating point (also referred to as “FP16”), 32-bit floating point (also referred to as “FP32”), or 64-bit floating point (also referred to as “FP64”). In at least one embodiment, one or more slices 2001A-2001N includes 16 vector engines that are paired with 16 matrix math units to compute matrix / tensor operations, where vector engines and math units are exposed via matrix extensions. In at least one embodiment, a slice a specified portion of processing resources of a processing unit, e.g., 16 cores and a ray tracing unit or 8 cores, a thread scheduler, a thread dispatcher, and additional functional units for a processor. In at least one embodiment, graphics core 2000 includes one or more matrix engines to compute matrix operations, e.g., when computing tensor operations.

[0376] In at least one embodiment, one or more slices 2001 A-2001N includes one or more ray tracing units to compute ray tracing operations (e.g., 16 ray tracing units per slice slices 2001 A-2001N). In at least one embodiment, a ray tracing unit computes ray traversal, triangle intersection, bounding box intersect, or other ray tracing operations.

[0377] In at least one embodiment, one or more slices 2001A-2001N includes a media slice that encodes, decodes, and / or transcodes data; scales and / or format converts data; and / or performs video quality operations on video data.

[0378] In at least one embodiment, one or more slices 2001 A-2001N are linked to L2 cache and memory fabric, link connectors, high-bandwidth memory (HBM) (e.g., HBM2e, HDM3) stacks, and a media engine. In at least one embodiment, one or more slices 2001A-2001N include multiple cores (e.g., 16 cores) and multiple ray tracing units (e.g., 16) paired to each core. In at least one embodiment, one or more slices 2001 A-2001N has one or more LI caches. In at least one embodiment, one or more slices 2001A-2001N include one or more vector engines; one or more instruction caches to store instructions; one or more LI caches to cache data; one or more shared local memories (SLMs) to store data, e.g., corresponding to instructions; one or more samplers to sample data; one or more ray tracing units to perform ray tracing operations; one or more geometries to perform operations in geometry pipelines and / or apply geometric transformations to vertices or polygons; one or more rasterizers to describe an image in vector graphics format (e.g., shape) and convert it into a raster image (e.g., a series of pixels, dots, or lines, which when displayed together, create an image that is represented by shapes) ; one or more a Hierarchical Depth Buffer (Hiz) to buffer data; and / or one or more pixel backends. In at least one embodiment, a slice 2001A-2001N includes a memory fabric, e.g., an L2 cache.

[0379] In at least one embodiment, FPUs 2014A-2014N can perform single-precision (32- bit) and half-precision (16-bit) floating point operations, while DPFPUs 2015A-2015N perform double precision (64-bit) floating point operations. In at least one embodiment, ALUs 2016A-2016N can perform variable precision integer operations at 8-bit, 16-bit, and 32-bit precision, and can be configured for mixed precision operations. In at least one embodiment, MPUs 2017A-2017N can also be configured for mixed precision matrix operations, including half-precision floating point and 8-bit integer operations. In at least one embodiment, MPUs 2017-2017N can perform a variety of matrix operations to accelerate machine learning application frameworks, including enabling support for accelerated general matrix to matrixmultiplication (GEMM). In at least one embodiment, AFUs 2012A-2012N can perform additional logic operations not supported by floating-point or integer units, including trigonometric operations (e.g., sine, cosine, etc.).

[0380] Logic 915 are used to perform inferencing and / or training operations associated with one or more embodiments. Details regarding logic 915 are provided herein in conjunction with FIGS. 9A and / or 9B. In at least one embodiment, logic 915 may be used in graphics core 2000 for inferencing or predicting operations based, at least in part, on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0381] In at least one embodiment, graphics core 2000 includes an interconnect and a link fabric sublayer that is attached to a switch and a GPU-GPU bridge that enables multiple graphics processors 2000 (e.g., 8) to be interlinked without glue to each other with load / store units (LSUs), data transfer units, and sync semantics across multiple graphics processors 2000. In at least one embodiment, interconnects include standardized interconnects (e.g., PCIe) or some combination thereof.

[0382] In at least one embodiment, graphics core 2000 includes multiple tiles. In at least one embodiment, a tile is an individual die or one or more dies, where individual dies can be connected with an interconnect (e.g., embedded multi-die interconnect bridge (EMIB)). In at least one embodiment, graphics core 2000 includes a compute tile, a memory tile (e.g., where a memory tile can be exclusively accessed by different tiles or different chipsets such as a Rambo tile), substrate tile, a base tile, a HMB tile, a link tile, and EMIB tile, where all tiles are packaged together in graphics core 2000 as part of a GPU. In at least one embodiment, graphics core 2000 can include multiple tiles in a single package (also referred to as a “multi tile package”). In at least one embodiment, a compute tile can have 8 graphics cores 2000, an LI cache; and a base tile can have a host interface with PCIe 5.0, HBM2e, MDFI, and EMIB, a link tile with 8 links, 8 ports with an embedded switch. In at least one embodiment, tiles are connected with face-to-face (F2F) chip-on-chip bonding through fine-pitched, 36-micron, microbumps (e.g., copper pillars). In at least one embodiment, graphics core 2000 includes memory fabric, which includes memory, and is tile that is accessible by multiple tiles. In at least one embodiment, graphics core 2000 stores, accesses, or loads its own hardware contexts in memory, where a hardware context is a set of data loaded from registers before a process resumes, and where a hardware context can indicate a state of hardware (e.g., state of a GPU).

[0383] In at least one embodiment, graphics core 2000 includes serializer / deserializer (SERDES) circuitry that converts a serial data stream to a parallel data stream, or converts a parallel data stream to a serial data stream.

[0384] In at least one embodiment, graphics core 2000 includes a high speed coherent unified fabric (GPU to GPU), load / store units, bulk data transfer and sync semantics, and connected GPUs through an embedded switch, where a GPU-GPU bridge is controlled by a controller.

[0385] In at least one embodiment, graphics core 2000 performs an API, where said API abstracts hardware of graphics core 2000 and access libraries with instructions to perform math operations (e.g., math kernel library), deep neural network operations (e.g., deep neural network library), vector operations, collective communications, thread building blocks, video processing, data analytics library, and / or ray tracing operations.

[0386] In at least one embodiment, at least one component shown or described with respect to FIG. 20A-20B is utilized to implement techniques and / or functions described in connection with FIGS. 1-8. In at least one embodiment, at least one component of FIG. 20A-20B is used to cause generation of an API, parameters, libraries, runtimes, drivers, kernels, distributing kernels to one or more GPUs, and to cause execution of a kernel on one or more GPUs. In at least one embodiment, at least one component of FIG. 20A-20B performs at least one aspect described with respect to data scaling system 100, device 102, data conversion manager 104, scaling module 106, machine learning modules 108, processors 110, communication manager 112, storage device 114, devices 116, cores 118A-118Z, storage device 120, processors 122, tensor scaling 200, input tensor 202, generate sub-tensor 204, sub-tensors 206A-206N, identify local maximum 208A-208N, scaled sub-tensor 21 OA-210N, converted sub -tensor 212A-212N, identify global maximum 214, scale with global maximum 216, data format conversion 300, values in first data format 320, scaling 304, data conversions 306, values in second data format 308, scaling operations 400, values in second data format 402, data evaluation 403, data comparison 404, global maximum determination 405, no data re-scale 406, data re-scale 408, operations of one or more scaling modules 500, method 600, method 700, processor 800, processor 820, conversion module 822, and / or scaling module 824.

[0387] FIG. 20B illustrates GPGPU 2030 that can be configured to enable highly-parallel compute operations to be performed by an array of graphics processing units, in at least one embodiment. In at least one embodiment, GPGPU 2030 can be linked directly to other instances of GPGPU 2030 to create a multi-GPU cluster to improve training speed for deepneural networks. In at least one embodiment, GPGPU 2030 includes a host interface 2032 to enable a connection with a host processor. In at least one embodiment, host interface 2032 is a PCI Express interface. In at least one embodiment, host interface 2032 can be a vendor-specific communications interface or communications fabric. In at least one embodiment, GPGPU 2030 receives commands from a host processor and uses a global scheduler 2034 (which may be referred to as a thread sequencer and / or asynchronous compute engine) to distribute execution threads associated with those commands to a set of compute clusters 2036A-2036H. In at least one embodiment, compute clusters 2036A-2036H share a cache memory 2038. In at least one embodiment, cache memory 2038 can serve as a higher-level cache for cache memories within compute clusters 2036A-2036H. In at least one embodiment, compute clusters 2036A-2036H comprise a slice or are referred to as “slices.” In at least one embodiment, GPGPU 2030 is part of an SoC such as part of integrated circuit 1800 (FIG. 18).

[0388] In at least one embodiment, GPGPU 2030 includes memory 2044A-2044B coupled with compute clusters 2036A-2036H via a set of memory controllers 2042A-2042B (e.g., one or more controllers for HBM2e). In at least one embodiment, memory 2044A-2044B can include various types of memory devices including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory.

[0389] In at least one embodiment, compute clusters 2036A-2036H each include a set of graphics cores, such as graphics core 2000 of FIG. 20A, which can include multiple types of integer and floating point logic units that can perform computational operations at a range of precisions including suited for machine learning computations. For example, in at least one embodiment, at least a subset of floating point units in each of compute clusters 2036A-2036H can be configured to perform 16-bit or 32-bit floating point operations, while a different subset of floating point units can be configured to perform 64-bit floating point operations.

[0390] In at least one embodiment, multiple instances of GPGPU 2030 can be configured to operate as a compute cluster. In at least one embodiment, communication used by compute clusters 2036A-2036H for synchronization and data exchange varies across embodiments. In at least one embodiment, multiple instances of GPGPU 2030 communicate over host interface 2032. In at least one embodiment, GPGPU 2030 includes an VO hub 2039 that couples GPGPU 2030 with a GPU link 2040 that enables a direct connection to other instances of GPGPU 2030. In at least one embodiment, GPU link 2040 is coupled to a dedicated GPU-to-GPU bridge thatenables communication and synchronization between multiple instances of GPGPU 2030. In at least one embodiment, GPU link 2040 couples with a high-speed interconnect to transmit and receive data to other GPGPUs or parallel processors. In at least one embodiment, multiple instances of GPGPU 2030 are located in separate data processing systems and communicate via a network device that is accessible via host interface 2032. In at least one embodiment GPU link 2040 can be configured to enable a connection to a host processor in addition to or as an alternative to host interface 2032.

[0391] In at least one embodiment, GPGPU 2030 can be configured to train neural networks. In at least one embodiment, GPGPU 2030 can be used within an inferencing platform. In at least one embodiment, in which GPGPU 2030 is used for inferencing, GPGPU 2030 may include fewer compute clusters 2036A-2036H relative to when GPGPU 2030 is used for training a neural network. In at least one embodiment, memory technology associated with memory 2044A-2044B may differ between inferencing and training configurations, with higher bandwidth memory technologies devoted to training configurations. In at least one embodiment, an inferencing configuration of GPGPU 2030 can support inferencing specific instructions. For example, in at least one embodiment, an inferencing configuration can provide support for one or more 8-bit integer dot product instructions, which may be used during inferencing operations for deployed neural networks.

[0392] Logic 915 are used to perform inferencing and / or training operations associated with one or more embodiments. Details regarding logic 915 are provided herein in conjunction with FIGS. 9A and / or 9B. In at least one embodiment, logic 915 may be used in GPGPU 2030 for inferencing or predicting operations based, at least in part, on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0393] In at least one embodiment, at least one component shown or described with respect to FIG. 20B is utilized to implement techniques and / or functions described in connection with FIGS. 1-8. In at least one embodiment, at least one component of FIG. 20B is used to cause generation of an API, parameters, libraries, runtimes, drivers, kernels, distributing kernels to one or more GPUs, and to cause execution of a kernel on one or more GPUs. In at least one embodiment, at least one component of FIG. 20B performs at least one aspect described with respect to data scaling system 100, device 102, data conversion manager 104, scaling module 106, machine learning modules 108, processors 110, communication manager112, storage device 114, devices 116, cores 118A-118Z, storage device 120, processors 122, tensor scaling 200, input tensor 202, generate sub-tensor 204, sub-tensors 206A-206N, identify local maximum 208A-208N, scaled sub-tensor 21 OA-210N, converted sub-tensor 212A-212N, identify global maximum 214, scale with global maximum 216, data format conversion 300, values in first data format 320, scaling 304, data conversions 306, values in second data format 308, scaling operations 400, values in second data format 402, data evaluation 403, data comparison 404, global maximum determination 405, no data re-scale 406, data re-scale 408, operations of one or more scaling modules 500, method 600, method 700, processor 800, processor 820, conversion module 822, and / or scaling module 824.

[0394] FIG. 21 is a block diagram illustrating a computing system 2100 according to at least one embodiment. In at least one embodiment, computing system 2100 includes a processing subsystem 2101 having one or more processor(s) 2102 and a system memory 2104 communicating via an interconnection path that may include a memory hub 2105. In at least one embodiment, memory hub 2105 may be a separate component within a chipset component or may be integrated within one or more processor(s) 2102. In at least one embodiment, memory hub 2105 couples with an I / O subsystem 2111 via a communication link 2106. In at least one embodiment, I / O subsystem 2111 includes an I / O hub 2107 that can enable computing system 2100 to receive input from one or more input device(s) 2108. In at least one embodiment, I / O hub 2107 can enable a display controller, which may be included in one or more processor(s) 2102, to provide outputs to one or more display device(s) 2110A. In at least one embodiment, one or more display device(s) 2110A coupled with I / O hub 2107 can include a local, internal, or embedded display device.

[0395] In at least one embodiment, processing subsystem 2101 includes one or more parallel processor(s) 2112 coupled to memory hub 2105 via a bus or other communication link 2113. In at least one embodiment, communication link 2113 may use one of any number of standards based communication link technologies or protocols, such as, but not limited to PCI Express, or may be a vendor-specific communications interface or communications fabric. In at least one embodiment, one or more parallel processor(s) 2112 form a computationally focused parallel or vector processing system that can include a large number of processing cores and / or processing clusters, such as a many-integrated core (MIC) processor. In at least one embodiment, some or all of parallel processor(s) 2112 form a graphics processing subsystem that can output pixels to one of one or more display device(s) 2110A coupled via VO Hub 2107. In at least one embodiment, parallel processor(s) 2112 can also include a display controller anddisplay interface (not shown) to enable a direct connection to one or more display device(s) 2110B. In at least one embodiment, parallel processor(s) 2112 include one or more cores, such as graphics cores 2000 discussed herein.

[0396] In at least one embodiment, a system storage unit 2114 can connect to I / O hub 2107 to provide a storage mechanism for computing system 2100. In at least one embodiment, an I / O switch 2116 can be used to provide an interface mechanism to enable connections between I / O hub 2107 and other components, such as a network adapter 2118 and / or a wireless network adapter 2119 that may be integrated into platform, and various other devices that can be added via one or more add-in device(s) 2120. In at least one embodiment, network adapter 2118 can be an Ethernet adapter or another wired network adapter. In at least one embodiment, wireless network adapter 2119 can include one or more of a Wi-Fi, Bluetooth, near field communication (NFC), or other network device that includes one or more wireless radios.

[0397] In at least one embodiment, computing system 2100 can include other components not explicitly shown, including USB or other port connections, optical storage drives, video capture devices, and like, may also be connected to VO hub 2107. In at least one embodiment, communication paths interconnecting various components in FIG. 21 may be implemented using any suitable protocols, such as PCI (Peripheral Component Interconnect) based protocols (e.g., PCI-Express), or other bus or point-to-point communication interfaces and / or protocol(s), such as NV-Link high-speed interconnect, or interconnect protocols.

[0398] In at least one embodiment, parallel processor(s) 2112 incorporate circuitry optimized for graphics and video processing, including, for example, video output circuitry, and constitutes a graphics processing unit (GPU), e.g., parallel processor(s) 2112 includes graphics core 2000. In at least one embodiment, parallel processor(s) 2112 incorporate circuitry optimized for general purpose processing. In at least one embodiment, components of computing system 2100 may be integrated with one or more other system elements on a single integrated circuit. For example, in at least one embodiment, parallel processor(s) 2112, memory hub 2105, processor(s) 2102, and VO hub 2107 can be integrated into a system on chip (SoC) integrated circuit. In at least one embodiment, components of computing system 2100 can be integrated into a single package to form a system in package (SIP) configuration. In at least one embodiment, at least a portion of components of computing system 2100 can be integrated into a multi-chip module (MCM), which can be interconnected with other multi-chip modules into a modular computing system.

[0399] Logic 915 are used to perform inferencing and / or training operations associated with one or more embodiments. Details regarding logic 915 are provided herein in conjunction with FIGS. 9A and / or 9B. In at least one embodiment, logic 915 may be used in computing system 2100 for inferencing or predicting operations based, at least in part, on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0400] In at least one embodiment, at least one component shown or described with respect to FIG. 21 is utilized to implement techniques and / or functions described in connection with FIGS. 1-8. In at least one embodiment, at least one component of FIG. 21 is used to cause generation of an API, parameters, libraries, runtimes, drivers, kernels, distributing kernels to one or more GPUs, and to cause execution of a kernel on one or more GPUs. In at least one embodiment, at least one component of FIG. 21 performs at least one aspect described with respect to data scaling system 100, device 102, data conversion manager 104, scaling module 106, machine learning modules 108, processors 110, communication manager 112, storage device 114, devices 116, cores 118A-118Z, storage device 120, processors 122, tensor scaling 200, input tensor 202, generate sub-tensor 204, sub-tensors 206A-206N, identify local maximum 208A-208N, scaled sub-tensor 210A-210N, converted sub-tensor 212A-212N, identify global maximum 214, scale with global maximum 216, data format conversion 300, values in first data format 320, scaling 304, data conversions 306, values in second data format 308, scaling operations 400, values in second data format 402, data evaluation 403, data comparison 404, global maximum determination 405, no data re-scale 406, data re-scale 408, operations of one or more scaling modules 500, method 600, method 700, processor 800, processor 820, conversion module 822, and / or scaling module 824.PROCESSORS

[0401] FIG. 22 A illustrates a parallel processor 2200 according to at least one embodiment. In at least one embodiment, various components of parallel processor 2200 may be implemented using one or more integrated circuit devices, such as programmable processors, application specific integrated circuits (ASICs), or field programmable gate arrays (FPGA). In at least one embodiment, illustrated parallel processor 2200 is a variant of one or more parallel processor(s) 2112 shown in FIG. 21 according to an exemplary embodiment. In at least one embodiment, a parallel processor 2200 includes one or more graphics cores 2000.I l l

[0402] In at least one embodiment, parallel processor 2200 includes a parallel processing unit 2202. In at least one embodiment, parallel processing unit 2202 includes an I / O unit 2204 that enables communication with other devices, including other instances of parallel processing unit 2202. In at least one embodiment, I / O unit 2204 may be directly connected to other devices. In at least one embodiment, I / O unit 2204 connects with other devices via use of a hub or switch interface, such as a memory hub 2205. In at least one embodiment, connections between memory hub 2205 and I / O unit 2204 form a communication link 2213. In at least one embodiment, I / O unit 2204 connects with a host interface 2206 and a memory crossbar 2216, where host interface 2206 receives commands directed to performing processing operations and memory crossbar 2216 receives commands directed to performing memory operations.

[0403] In at least one embodiment, when host interface 2206 receives a command buffer via I / O unit 2204, host interface 2206 can direct work operations to perform those commands to a front end 2208. In at least one embodiment, front end 2208 couples with a scheduler 2210 (which may be referred to as a sequencer), which is configured to distribute commands or other work items to a processing cluster array 2212. In at least one embodiment, scheduler 2210 ensures that processing cluster array 2212 is properly configured and in a valid state before tasks are distributed to a cluster of processing cluster array 2212. In at least one embodiment, scheduler 2210 is implemented via firmware logic executing on a microcontroller. In at least one embodiment, microcontroller implemented scheduler 2210 is configurable to perform complex scheduling and work distribution operations at coarse and fine granularity, enabling rapid preemption and context switching of threads executing on processing array 2212. In at least one embodiment, host software can prove workloads for scheduling on processing cluster array 2212 via one of multiple graphics processing pa...

Claims

CLAIMSWHAT IS CLAIMED IS:

1. A processor comprising: one or more circuits to cause a largest value of each portion of two or more portions of an array to be identified and to use the largest value of each portion to scale one or more values within each portion sequentially.

2. The processor of claim 1, wherein the one or more circuits are to compare the largest values of each portion to a largest identified value of the array and use the greater of the largest values of each portion and the largest identified value of the array to scale the one or more values within each portion sequentially.

3. The processor of claim 1, wherein the one or more circuits are to cause one or more values of one or more portions of the two or more portions of the array to be scaled using a largest values of another portion of the two or more portions of the array.

4. The processor of claim 1, wherein the one or more values within each portion are to be scaled to be represented using a lower number of bits.

5. The processor of claim 1, wherein the one or more values within each portion of the two or more portions of the array are to be scaled subsequent to one or more tensor operations associated with the one or more values within each portion of the two or more portions of the array.

6. The processor of claim 1, wherein the one or more circuits are to identify one or more scaling factors based, at least in part, on the largest value of each portion.

7. The processor of claim 1, wherein the one or more values within each portion are scaled in a lower precision representation.

8. A system comprising: one or more processors to cause a largest value of each portion of two or more portions of an array to be identified and to use the largest value of each portion to scale one or more values within each portion sequentially.

9. The system of claim 8, wherein the one or more processors are to compare the largest values of each portion to a largest identified value of the array and use the greater ofthe largest values of each portion and the largest identified value of the array to scale the one or more values within each portion sequentially.

10. The processor of claim 8, wherein the one or more processors are to cause one or more values of one or more portions of the two or more portions of the array to be scaled using a largest values of another portion of the two or more portions of the array.

11. The processor of claim 8, wherein the one or more values within each portion are to be scaled to be represented using a lower number of bits.

12. The processor of claim 8, wherein the one or more values within each portion of the two or more portions of the array are to be scaled subsequent to one or more tensor operations associated with the one or more values within each portion of the two or more portions of the array.

13. The processor of claim 8, wherein the one or more processors are to identify one or more scaling factors based, at least in part, on the largest value of each portion.

14. The processor of claim 8, wherein the one or more values within each portion are scaled in a lower precision representation.

15. A method comprising causing a largest value of each portion of two or more portions of an array to be identified and to use the largest value of each portion to scale one or more values within each portion sequentially.

16. The method of claim 15 further comprising, comparing the largest values of each portion to a largest identified value of the array and use the greater of the largest values of each portion and the largest identified value of the array to scale the one or more values within each portion sequentially.

17. The method of claim 15 further comprising, causing one or more values of one or more portions of the two or more portions of the array to be scaled using a largest values of another portion of the two or more portions of the array.

18. The method of claim 15, wherein the one or more values within each portion are to be scaled to be represented using a lower number of bits.

19. The method of claim 15, wherein the one or more values within each portion of the two or more portions of the array are to be scaled subsequent to one or more tensor operations associated with the one or more values within each portion of the two or more portions of the array.

20. The method of claim 15 further comprising, identifying one or more scaling factors based, at least in part, on the largest value of each portion.

Images