Comparator circuit

Abstract

A comparator circuit, comprising: a first pre-amplification stage, amplifying an input signal when in a comparison state, so as to generate a first output signal; a second pre-amplification stage, switching between a reset state and the comparison state on the basis of the first output signal, amplifying the first output signal when in the comparison state, so as to generate a second output signal, and providing positive feedback for the second output signal by means of a first positive feedback structure; and a latch stage, wherein in the reset state, an output end of the latch stage is reset to a second preset level on the basis of a clock signal, and in the comparison state, a second positive feedback structure and a third positive feedback structure are controlled to be on by means of the second output signal and the clock signal, so as to provide positive feedback to the output end. The comparator circuit reduces the number of transistors connected to the clock signal, thereby suppressing jittering of the clock signal, and effectively improving comparator precision.

Description

A comparator circuit Technical Field

[0001] This invention relates to the field of analog-to-digital conversion, and more particularly to a comparator circuit. Background Technology

[0002] In recent years, with the continuous development of integrated circuit manufacturing technology, the feature size of CMOS devices has been continuously reduced, and the operating voltage of integrated circuits has also been continuously lowered. Under deep submicron processes, the operating speed of analog-to-digital converters (ADCs) has been greatly improved, while power consumption has been further reduced. However, as the core component of ADCs, the performance of comparators has become a bottleneck in high-speed, low-power design. Traditional comparator structures struggle to simultaneously meet the requirements of speed, power consumption, and low supply voltage.

[0003] In traditional comparator structures, the clock signal always appears in every stage of the comparator, which introduces large clock jitter into each stage, resulting in high noise. Furthermore, the clock routing in the layout is relatively complex, which greatly limits the accuracy of the comparator.

[0004] Summary of the Invention

[0005] In view of the problems existing in the prior art, the present invention proposes a comparator circuit, which mainly solves the problem that traditional comparators introduce a lot of clock jitter, thus affecting the accuracy of the comparator.

[0006] To achieve the above and other objectives, the technical solution adopted by the present invention is as follows.

[0007] This application provides a comparator circuit, comprising: a first preamplifier stage, which switches between a reset state and a comparison state via a clock signal; in the reset state, the input signal is cut off and the output of the first preamplifier stage is reset to a first preset level; in the comparison state, the input signal is amplified to generate a first output signal; a second preamplifier stage, which includes a first positive feedback structure; the second preamplifier stage switches between a reset state and a comparison state according to the first output signal; in the comparison state, the first output signal is amplified to generate a second output signal, and positive feedback is provided to the second output signal through the first positive feedback structure; and a latch stage, which is connected to the second output signal and the clock signal; the latch stage includes a second positive feedback structure and a third positive feedback structure; in the reset state, the output of the latch stage is reset to a second preset level according to the clock signal; in the comparison state, the second positive feedback structure and the third positive feedback structure are turned on by the second output signal and the clock signal to provide positive feedback to the output.

[0008] In one embodiment of this application, the first pre-amplification stage includes: a zeroth transistor, a first transistor, a second transistor, a third transistor, and a fourth transistor. The gate of the zeroth transistor is connected to the clock signal, and the source of the zeroth transistor is grounded. The sources of the first transistor and the second transistor are respectively connected to the drain of the zeroth transistor. The gates of the first transistor and the second transistor are respectively connected to the positive and negative phases of the input signal. The drain of the first transistor is connected to the drain of the third transistor as the positive output terminal of the first pre-amplification stage, and the drain of the second transistor is connected to the drain of the fourth transistor as the secondary output terminal of the first pre-amplification stage. The sources of the third transistor and the fourth transistor are connected to the power supply voltage, and the gates of the third transistor and the fourth transistor are connected to the clock signal.

[0009] In one embodiment of this application, the second pre-amplification stage includes: a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor; the sources of the fifth transistor and the sixth transistor are grounded, the gates of the fifth transistor and the sixth transistor are respectively connected to the positive and negative phases of the first output signal, the drain of the fifth transistor is connected to the drain of the seventh transistor as the positive phase of the second output signal, the drain of the sixth transistor is connected to the drain of the eighth transistor as the negative phase of the second output signal, the gates of the seventh transistor and the eighth transistor are respectively connected to the negative and positive phases of the first output signal, and the sources of the seventh transistor and the eighth transistor are connected to the power supply voltage; wherein the fifth transistor to the eighth transistor constitute the first positive feedback structure.

[0010] In one embodiment of this application, the latch stage includes a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, a sixteenth transistor, a seventeenth transistor, and an eighteenth transistor; the sources of the ninth and tenth transistors are grounded, and their gates are respectively connected to the inverting and non-inverting phases of the second output signal; the drains of the ninth and tenth transistors are respectively connected to the sources of the twelfth and thirteenth transistors; the gates of the twelfth and sixteenth transistors are connected to the drains of the thirteenth and seventeenth transistors as the inverting output terminals of the latch stage; the drains of the twelfth and sixteenth transistors are connected to the gates of the thirteenth and seventeenth transistors as the non-inverting output terminals of the latch stage; the sources of the sixteenth and seventeenth transistors are connected to the power supply voltage; and the fifteenth transistor... The gate of the transistor is connected to the clock signal; the source of the fifteenth transistor is connected to the power supply voltage; and the drain of the fifteenth transistor is connected to the drain of the sixteenth transistor. The gate of the eighteenth transistor is connected to the clock signal; the source of the eighteenth transistor is connected to the power supply voltage; and the drain of the eighteenth transistor is connected to the drain of the seventeenth transistor. The source of the eleventh transistor is connected to the power supply voltage; the drain of the eleventh transistor serves as the positive output terminal of the latch stage; and the gate of the eleventh transistor is connected to the inverted output of the second output signal. The source of the fourteenth transistor is connected to the power supply voltage; and the gate of the fourteenth transistor is connected to the positive output of the second output signal. The drain of the fourteenth transistor serves as the inverted output terminal of the latch stage. The eleventh and fourteenth transistors form the second positive feedback structure. The twelfth, thirteenth, sixteenth, and seventeenth transistors form the third positive feedback structure.

[0011] In one embodiment of this application, the number of NMOS transistors in the power supply voltage path to ground in the latch stage is greater than the number of PMOS transistors.

[0012] In one embodiment of this application, the zeroth transistor, the first transistor, the second transistor, the fifth transistor, the sixth transistor, the ninth transistor, the tenth transistor, the twelfth transistor, and the thirteenth transistor are all NMOS transistors; the third transistor, the fourth transistor, the seventh transistor, the eighth transistor, the eleventh transistor, the fourteenth transistor, the fifteenth transistor, the sixteenth transistor, the seventeenth transistor, and the eighteenth transistor are all PMOS transistors.

[0013] As described above, the comparator circuit proposed in this application has the following beneficial effects.

[0014] The second preamplifier stage of this application is completely controlled by the output signal of the first preamplifier stage, which reduces the number of transistors connected to the clock signal and thus suppresses clock signal jitter, effectively improving the accuracy of the comparator. In addition, this application has positive feedback structures in both the second preamplifier stage and the latch stage, increasing the number of positive feedback loops and effectively improving the comparison speed of the comparator. Attached Figure Description

[0015] Figure 1 is a schematic diagram of a traditional comparator structure.

[0016] Figure 2 is a schematic diagram of the existing improved comparator structure.

[0017] Figure 3 is a schematic diagram of the module structure of the comparator circuit in one embodiment of this application.

[0018] Figure 4 is a schematic diagram of a comparator circuit in one embodiment of this application.

[0019] Figure 5 shows a comparison of the comparison delay simulations of the three comparator circuits in Figures 1, 2, and 4 as the input signal amplitude changes.

[0020] Figure 6 is a simulation comparison of the reset delay of the three comparator circuits in Figures 1, 2 and 4 as the power supply voltage changes.

[0021] Figure 7 shows a noise simulation comparison of the three comparator circuits in Figures 1, 2, and 4 as the input common-mode voltage changes. Detailed Implementation

[0022] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that, unless otherwise specified, the following embodiments and features described therein can be combined with each other.

[0023] It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0024] The inventors discovered through research that traditional comparator structures have the following problems:

[0025] In applications with lower precision requirements, a single-stage latch structure can be used as the comparator structure. The advantages of this structure are high speed and low power consumption. However, its disadvantages include higher noise and offset. In applications with higher precision requirements, to suppress the high noise and high offset of the single-stage latch structure, the comparator is usually composed of multiple cascaded preamplifier stages connected to the latch stage. A traditional comparator structure is shown in Figure 1. The preamplifier stage consists of NMOS transistors M0, M1, and M2, and PMOS transistors M3 and M4. The latch stage consists of NMOS transistors M5, M6, M7, M8, M9, and M12, and PMOS transistors M10, M11, M13, and M14. When the clock signal CLK is low, the comparator is in a reset state. M0 in the preamplifier stage is disconnected, while M3 and M4 are turned on, and the output signals VP and VN of the preamplifier stage are reset to high. In the latch stage, M5, M8, M9, and M12 are turned on, while M13 and M14 are turned off. Therefore, the latch output signals VOP and VON are reset to low level. When the clock signal CLK goes high, the comparator is in comparison mode. M0 turns on, and the preamplifier stage amplifies the input signals VIP and VIN. M5, M8, M9, and M12 in the latch stage are turned off, while M13 and M14 are turned on. The positive feedback loop formed by latches M6, M7, M10, and M11 is activated, latching the preamplifier stage output signals VP and VN, generating high and low level signals VOP and VON, completing the comparison process. The problem with this structure is that the latch stage has three MOSFETs from power supply to ground, resulting in a relatively high impedance. Furthermore, two of these MOSFETs are PMOS transistors, further increasing the latch delay. Based on these issues, an improved comparator structure has been proposed, as shown in Figure 2. The structure consists of two preamplifier stages and one latch stage. The first preamplifier stage is composed of NMOS transistors M0, M1, and M2, and PMOS transistors M3 and M4. The second preamplifier stage is composed of NMOS transistors M5 and M6, and PMOS transistors M7 and M8. The latch stage is composed of NMOS transistors M9, M10, M12, and M13, and PMOS transistors M11, M14, M15, M16, M17, and M18. The signal CLKN is the inverted signal of CLK; when the clock signal CLK is low, CLKN is high. With the comparator in reset state, the output signals VOP1 and VON1 of the first preamplifier stage are high. In the second preamplifier stage, M5 and M6 are turned on, while M7 and M8 are turned off. Therefore, VOP2 and VON2 are low. In the latch stage, M9 and M10 are turned off, while M11, M14, M15, and M18 are turned on. Thus, the latch output signals VOP and VON are reset to high. When the clock signal CLK goes high, CLKN goes low.When the comparator is in comparison mode, M0 is turned on. The first pre-amplifier stage amplifies the input signals VIP and VIN, and VOP1 and VON1 gradually decrease from high level. In the second pre-amplifier stage, M5 and M6 are turned off. The second pre-amplifier stage amplifies the output signals VOP1 and VON1 of the first pre-amplifier stage, and VOP2 and VON2 gradually increase from low level. The pre-amplified results VOP2 and VON2 of the second stage are output to the latch stage. In the latch stage, M9 and M10 are turned on, M11, M14, M15, and M18 are turned off, and the positive feedback loop formed by M12, M13, M16, and M17 is activated, generating high and low level signals VOP and VON to complete the comparison process. The structure shown in Figure 2 uses a two-stage pre-amplifier structure, which increases the accuracy of the comparator. In the latch stage, there are two NMOS transistors and one PMOS transistor between the power supply and ground. Compared with the structure shown in Figure 1, the speed of the comparator is improved. However, the problem with the structure shown in Figure 2 is that both the preamplifier stage and the latch stage require clock signals for control, which increases the routing complexity and affects the accuracy of the comparator. At the same time, there is still only one positive feedback structure, and the speed of the comparator still has room for improvement.

[0026] In view of the problems existing in the prior art, this application proposes a comparator circuit. The comparator circuit of this application will be described in detail below with reference to specific embodiments.

[0027] Please refer to Figure 3, which is a schematic diagram of the module structure of a comparator circuit in one embodiment of this application. The comparator circuit of this application embodiment includes: a first pre-amplifier stage 01, which switches between a reset state and a comparison state via a clock signal. In the reset state, the input signal is cut off, and the output of the first pre-amplifier stage 01 is reset to a first preset level. In the comparison state, the input signal is amplified to generate a first output signal. A second pre-amplifier stage 02 includes a first positive feedback structure 021. The second pre-amplifier stage 02 switches between a reset state and a comparison state according to the first output signal. In the comparison state, the first output signal is amplified to generate a second output signal, and positive feedback is provided to the second output signal through the first positive feedback structure 021. A latch stage 03 is connected to the second output signal and the clock signal. The latch stage includes a second positive feedback structure 031 and a third positive feedback structure 032. In the reset state, the output of the latch stage 03 is reset to a second preset level according to the clock signal. In the comparison state, the second positive feedback structure 031 and the third positive feedback structure 032 are turned on by the second output signal and the clock signal to provide positive feedback to the output. Specifically, in the comparison state, the first pre-amplifier stage 01 amplifies the input signal under the control of a clock signal, generating a first output signal which is output to the second pre-amplifier stage 02. The second pre-amplifier stage 02 may include two sets of input terminals, both of which are connected to the first output signal. Under the control of the first output signal, the second pre-amplifier stage 02 generates a second output signal which is sent to the latch stage 03. Since the second pre-amplifier stage 02 is directly controlled by the output of the first pre-amplifier stage 01, and no additional clock signal is required, the jitter introduced by the clock signal can be reduced, and the noise can be lowered.

[0028] Please refer to Figure 4, which is a circuit schematic of a comparator circuit in one embodiment of this application. In one embodiment, the first pre-amplification stage includes: a zeroth transistor M0, a first transistor M1, a second transistor M2, a third transistor M3, and a fourth transistor M4. The gate of the zeroth transistor M0 is connected to the clock signal, and the source of the zeroth transistor M0 is grounded. The sources of the first transistor M1 and the second transistor M2 are respectively connected to the drains of the zeroth transistor M0. The gates of the first transistor M1 and the second transistor M2 are respectively connected to the positive phase VIP and the negative phase VIN of the input signal. The drain of the first transistor M1 is connected to the drain of the third transistor M3 as the positive phase output terminal VOP1 of the first pre-amplification stage. The drain of the second transistor M2 is connected to the drain of the fourth transistor M4 as the secondary output terminal VON1 of the first pre-amplification stage. The sources of the third transistor M3 and the fourth transistor M4 are connected to the power supply voltage VDD, and the gates of the third transistor M3 and the fourth transistor M4 are connected to the clock signal CLK. Specifically, the first pre-amplification stage is composed of NMOS transistors M0, M1, and M2, and PMOS transistors M3 and M4. The sources of M1 and M2 are grounded, and their gates are connected to the input signals VIP and VIN, respectively. The drains of M1 and M2 are connected to the drains of M3 and M4, respectively. The gates of M3 and M4 are connected to the clock signal CLK, and the sources of M3 and M4 are connected to the power supply VDD. VOP1 and VON1 are the output signals of the first pre-amplification stage.

[0029] In one embodiment, the second pre-amplification stage includes: a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, and an eighth transistor M8; the sources of the fifth transistor M5 and the sixth transistor M6 are grounded, the gates of the fifth transistor M5 and the sixth transistor M6 are respectively connected to the positive phase VOP1 and the negative phase VON1 of the first output signal, the drain of the fifth transistor M5 is connected to the drain of the seventh transistor M7 as the positive phase VOP2 of the second output signal, the drain of the sixth transistor M6 is connected to the drain of the eighth transistor M8 as the negative phase VON2 of the second output signal, the gates of the seventh transistor M7 and the eighth transistor M8 are respectively connected to the negative phase VON1 and the positive phase VOP1 of the first output signal, and the sources of the seventh transistor M7 and the eighth transistor M8 are connected to the power supply voltage VDD; wherein the fifth transistor M5 to the eighth transistor M8 constitute the first positive feedback structure. Specifically, the second pre-amplification stage is composed of NMOS transistors M5 and M6, and PMOS transistors M7 and M8. The sources of M5 and M6 are grounded, and their gates are connected to the output signals VOP1 and VON1 of the first pre-amplification stage, respectively. The drains of M5 and M6 are connected to the drains of M7 and M8, respectively. The gates of M7 and M8 are connected to the output signals VON1 and VOP1 of the first pre-amplification stage, respectively. The sources of M7 and M8 are connected to the power supply VDD. VOP2 and VON2 are the output signals of the second pre-amplification stage.

[0030] In one embodiment, the latch stage includes a ninth transistor M9, a tenth transistor M10, an eleventh transistor M11, a twelfth transistor M12, a thirteenth transistor M13, a fourteenth transistor M14, a fifteenth transistor M15, a sixteenth transistor M16, a seventeenth transistor M17, and an eighteenth transistor M18; the sources of the ninth transistor M9 and the tenth transistor M10 are grounded, and the gates of the ninth transistor M9 and the tenth transistor M10 are respectively connected to the inverted VON2 and the non-inverted VOP2 of the second output signal; the ninth transistor M9 and the tenth transistor M10... The drain of transistor M10 is connected to the source of transistor M12 and transistor M13, respectively; the gates of transistor M12 and transistor M16 are connected to the drains of transistor M13 and transistor M17 as the inverting output VON of the latch stage; the drains of transistor M12 and transistor M16 are connected to the gates of transistor M13 and transistor M17 as the non-inverting output VOP of the latch stage, and the source of transistor M16 and transistor M17 is... The gate of the fifteenth transistor M15 is connected to the clock signal CLK, the source of the fifteenth transistor M15 is connected to the power supply voltage VDD, and the drain of the fifteenth transistor M15 is connected to the drain of the sixteenth transistor M16; the gate of the eighteenth transistor M18 is connected to the clock signal CLK, the source of the eighteenth transistor M18 is connected to the power supply voltage VDD, and the drain of the eighteenth transistor M18 is connected to the drain of the seventeenth transistor M17; the source of the eleventh transistor M11 is connected to the power supply voltage VDD, and the eleventh transistor... The drain of transistor M11 serves as the positive output terminal VOP of the latch stage; the gate of the eleventh transistor M11 is connected to the inverted VON2 of the second output signal; the source of the fourteenth transistor M14 is connected to the power supply voltage VDD; the gate of the fourteenth transistor M14 is connected to the positive VOP2 of the second output signal; the drain of the fourteenth transistor M14 serves as the inverted output terminal VON of the latch stage; wherein, the eleventh transistor M11 and the fourteenth transistor M14 form the second positive feedback structure; the twelfth transistor M12, the thirteenth transistor M13, the sixteenth transistor M16, and the seventeenth transistor M17 form the third positive feedback structure. Specifically, the latch stage consists of M9-M18, where the sources of NMOS transistors M9 and M10 are grounded, and their gates are connected to the output signals VON2 and VOP2 of the second pre-amplification stage, respectively. The drains of M9 and M10 are connected to the sources of NMOS transistors M12 and M13, respectively. NMOS transistors M12 and M13 and PMOS transistors M16 and M17 form two back-to-back inverter structures connected end to end. VOP and VON are the output signals of the latch stage.The drains of PMOS transistors M15 and M18 are connected to the drains of M16 and M17, respectively. The sources of M15 and M18 are connected to the power supply VDD, and the gates of M15 and M18 are connected to the clock signal CLK. The sources of PMOS transistors M11 and M14 are connected to the power supply VDD, and their gates are connected to the output signals VON2 and VOP2 of the second-stage latch, respectively. Their drains are connected to the output signals VOP and VON of the latch, respectively.

[0031] The comparator circuit of this embodiment operates as follows: When the clock signal CLK is low, the comparator is in a reset state. In the first preamplifier stage, M3 and M4 are turned on, and VOP1 and VON1 are reset to high. Therefore, in the second preamplifier stage, NMOS transistors M5 and M6 are turned on, and PMOS transistors M7 and M8 are turned off. The output signals VOP2 and VON2 of the second preamplifier stage are reset to low. Since the input transistors of the latch stage are NMOS transistors M9 and M10, M9 and M10 are turned off in the reset state. Because the gates of PMOS transistors M15 and M18 are connected to the clock signal CLK, M15 and M18 are turned on. At the same time, since the gates of PMOS transistors M11 and M14 are connected to VOP2 and VON2 respectively, both M11 and M14 are turned on. Therefore, the output signals VOP and VON are reset to high. When the clock signal CLK becomes high, the comparator enters the comparison state. In the first pre-amplifier stage, M3 and M4 are currently disconnected. The input signals VIP and VIN are amplified by the first pre-amplifier stage, generating the output signals VOP1 and VON1. Simultaneously, VOP1 and VON1 gradually decrease from the power supply voltage VDD. As VOP1 and VON1 gradually decrease from the power supply voltage VDD, the NMOS transistors M5 and M6 in the second pre-amplifier stage gradually disconnect, while the PMOS transistors M7 and M8 gradually turn on, generating the output signals VOP2 and VON2 of the second pre-amplifier stage. Simultaneously, VOP2 and VON2 gradually increase from 0. It should be noted that since the gates of NMOS transistors M5 and M8 are connected to VOP1, and the gates of NMOS transistors M6 and M7 are connected to VON1, the second pre-amplifier stage, composed of the M5-M8 structure, forms the first positive feedback structure. Compared with the traditional structure shown in Figure 2, this first positive feedback structure significantly improves the comparison speed of the second pre-amplifier stage. At the same time, since all the input signals of the second pre-amplifier stage are the output signals of the first pre-amplifier stage, and no clock is input to the second pre-amplifier stage, the noise caused by clock jitter is not introduced into the second pre-amplifier stage, thus improving the accuracy of the comparator. As VOP2 and VON2 gradually increase from 0 to VDD during the comparison state, M9 and M10 in the latch stage gradually turn on. The clock signal CLK of the gates of PMOS transistors M15 and M18 is high during the comparison state, so M15 and M18 are both turned off during the comparison state. The third positive feedback structure composed of NMOS transistors M12 and M13 and PMOS transistors M16 and M17 latches the input signal of the latch. At the same time, another positive feedback structure (i.e., the second positive feedback structure) is formed by PMOS transistors M11 and M14. Compared with the structure shown in Figure 2, since there is a positive feedback loop in the second preamplifier stage, the latch has two positive feedback loops, which further improves the speed of the comparator.In addition, in the latch stage, the clock signal CLK is only connected to the gates of M15 and M18, while in the structure shown in Figure 2, the clock signal CLK is connected to the gates of PMOS transistors M11, M14, M15 and M18. Compared with the structure shown in Figure 2, the load capacitance that the clock signal needs to drive in this embodiment is reduced by half, which improves the speed of the latch.

[0032] The following verification examines the three comparator structures shown in Figures 1-3. To effectively verify the effectiveness of the embodiments of this application, the transistors in all three structures are fabricated using a 65nm CMOS process, and the three comparator structures use the same input / output transistor dimensions, the same latch stage dimensions, and a load capacitor of 15fF. The clock frequency is 2GHz, the power supply voltage is 1.2V, and the common-mode voltage is 0.6V. During latching, the comparator is considered to have completed latching when |VOP-VON|=0.6V. The comparison curves of the latch delay of the three comparators as a function of the input differential signal ΔVin are shown in Figure 5. As can be seen from Figure 5, the latch delay of the comparator shown in this invention is reduced by at least 22%. The clock frequency is 2GHz, the input differential signal ΔVin is set to 50mV, and the comparator is considered to have completed reset when both VOP and VON are greater than 0.5VDD. Figure 6 shows a comparison of the reset delay of the three comparators as a function of the power supply voltage. As can be seen from Figure 6, the latching delay of the comparator shown in this invention is reduced by at least 38%. Figure 7 shows a comparison of the equivalent noise of the three comparators as a function of the input common-mode voltage (Vcm). As can be seen from Figure 7, the equivalent noise of the comparator shown in this invention is reduced by at least 41%.

[0033] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A comparator circuit, characterized in that, include: The first pre-amplifier stage switches between a reset state and a comparison state via a clock signal. In the reset state, the input signal is cut off and the output of the first pre-amplifier stage is reset to a first preset level. In the comparison state, the input signal is amplified to generate a first output signal. The second pre-amplification stage includes a first positive feedback structure. The second pre-amplification stage switches between a reset state and a comparison state based on the first output signal. In the comparison state, it amplifies the first output signal to generate a second output signal, and provides positive feedback to the second output signal through the first positive feedback structure. A latch stage is connected to the second output signal and the clock signal. The latch stage includes a second positive feedback structure and a third positive feedback structure. In the reset state, the output terminal of the latch stage is reset to a second preset level according to the clock signal. In the comparison state, the second positive feedback structure and the third positive feedback structure are turned on by the second output signal and the clock signal to provide positive feedback to the output terminal.

2. The comparator circuit according to claim 1, characterized in that, The first pre-amplification stage includes: a zeroth transistor, a first transistor, a second transistor, a third transistor, and a fourth transistor. The gate of the zeroth transistor is connected to the clock signal, and the source of the zeroth transistor is grounded. The sources of the first transistor and the second transistor are respectively connected to the drains of the zeroth transistor. The gates of the first transistor and the second transistor are respectively connected to the positive and negative phases of the input signal. The drain of the first transistor is connected to the drain of the third transistor as the positive output terminal of the first pre-amplification stage, and the drain of the second transistor is connected to the drain of the fourth transistor as the secondary output terminal of the first pre-amplification stage. The sources of the third transistor and the fourth transistor are connected to the power supply voltage, and the gates of the third transistor and the fourth transistor are connected to the clock signal.

3. The comparator circuit according to claim 2, characterized in that, The second pre-amplification stage includes a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor; the sources of the fifth transistor and the sixth transistor are grounded, the gates of the fifth transistor and the sixth transistor are respectively connected to the positive and negative phases of the first output signal, the drain of the fifth transistor is connected to the drain of the seventh transistor as the positive phase of the second output signal, the drain of the sixth transistor is connected to the drain of the eighth transistor as the negative phase of the second output signal, the gates of the seventh transistor and the eighth transistor are respectively connected to the negative and positive phases of the first output signal, and the sources of the seventh transistor and the eighth transistor are connected to the power supply voltage; wherein the fifth transistor to the eighth transistor constitute the first positive feedback structure.

4. The comparator circuit according to claim 3, characterized in that, The latch stage includes a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, a sixteenth transistor, a seventeenth transistor, and an eighteenth transistor; The sources of the ninth and tenth transistors are grounded, and their gates are connected to the inverted and positive phases of the second output signal, respectively. The drains of the ninth and tenth transistors are connected to the sources of the twelfth and thirteenth transistors, respectively. The gates of the twelfth and sixteenth transistors are connected to the drains of the thirteenth and seventeenth transistors as the inverted output terminals of the latch stage. The drains of the twelfth and sixteenth transistors are connected to the gates of the thirteenth and seventeenth transistors as the positive output terminals of the latch stage. The sources of the sixteenth and seventeenth transistors are connected to the power supply voltage. The gate of the fifteenth transistor... With the clock signal connected, the source of the fifteenth transistor is connected to the power supply voltage, and the drain of the fifteenth transistor is connected to the drain of the sixteenth transistor; the gate of the eighteenth transistor is connected to the clock signal, the source of the eighteenth transistor is connected to the power supply voltage, and the drain of the eighteenth transistor is connected to the drain of the seventeenth transistor; the source of the eleventh transistor is connected to the power supply voltage, the drain of the eleventh transistor serves as the positive output terminal of the latch stage, and the gate of the eleventh transistor is connected to the inverted output of the second output signal; the source of the fourteenth transistor is connected to the power supply voltage, the gate of the fourteenth transistor is connected to the positive output of the second output signal, and the drain of the fourteenth transistor serves as the inverted output terminal of the latch stage; Wherein, the eleventh transistor and the fourteenth transistor form the second positive feedback structure; the twelfth transistor, the thirteenth transistor, the sixteenth transistor, and the seventeenth transistor form the... Three positive feedback structures.

5. The comparator circuit according to claim 4, characterized in that, In the latch stage, the number of NMOS transistors in the path from the power supply voltage to ground is greater than the number of PMOS transistors.

6. The comparator circuit according to claim 5, characterized in that, The zeroth transistor, the first transistor, the second transistor, the fifth transistor, the sixth transistor, the ninth transistor, the tenth transistor, the twelfth transistor, and the thirteenth transistor are all NMOS transistors; The third, fourth, seventh, eighth, eleventh, fourteenth, fifteenth, sixteenth, seventeenth, and eighteenth transistors are all PMOS transistors.

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