Semiconductor structure, manufacturing method therefor, and electronic device

Abstract

The present disclosure relates to the field of semiconductors, and relates to a semiconductor structure, a manufacturing method therefor, and an electronic device, for use in increasing storage density. The semiconductor structure comprises a common bit line (300), a read source line (400), and a storage unit. The common bit line (300) and the read source line (400) are arranged in a first direction, and both extend in a second direction. The storage unit is located between the common bit line (300) and the read source line (400) in the first direction. The storage unit comprises a write transistor (500) and a read transistor (200). A write channel layer (530) of the write transistor (500) surrounds a write gate dielectric layer (520), and is connected to the common bit line (300) in the first direction. A read gate (210) of the read transistor (200) comprises a storage gate (211) and a control gate (212). The storage gate (211) is located on the side of the write transistor (500) distant from the common bit line (300) in the first direction, and is connected to the write channel layer (530) in the first direction. The control gate (212) is located between the storage gate (211) and the read source line (400) in the first direction, and is insulated from and spaced apart from the storage gate (211) and the read source line (400). The two sides of a read channel layer (230) in the first direction are respectively connected to the common bit line (300) and the read source line (400).

Description

Semiconductor structure and its fabrication method, electronic devices

[0001] Cross-reference to related applications

[0002] This disclosure claims priority to Chinese Patent Application No. 2024106753041, filed on May 29, 2024, entitled "Semiconductor Structure and Preparation Method Thereof, Electronic Device", the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to the field of integrated circuit technology, and in particular to a semiconductor structure and its fabrication method, and an electronic device. Background Technology

[0004] With the development of integrated circuit technology, the critical dimensions of devices are shrinking, and the types and number of devices contained in a single chip are increasing, making it possible for even the slightest differences in the manufacturing process to affect device performance.

[0005] To minimize product costs, the goal is to fabricate as many device units as possible on a limited substrate. Since the advent of Moore's Law, the industry has proposed various semiconductor structure designs and process optimizations to meet current product demands.

[0006] Summary of the Invention

[0007] According to various embodiments of this disclosure, a semiconductor structure, a method for fabricating the same, and an electronic device are provided.

[0008] According to various embodiments of the present disclosure, a semiconductor structure is provided, the semiconductor structure comprising:

[0009] A common bit line and a read source line, wherein the common bit line and the read source line are arranged along a first direction and both extend along a second direction, the second direction intersecting the first direction;

[0010] A storage unit, located between the common bit line and the read source line in the first direction, the storage unit includes:

[0011] A write transistor includes a write gate, a write gate dielectric layer, and a write channel layer, wherein the write gate dielectric layer surrounds the write gate, the write channel layer surrounds the write gate dielectric layer, and is connected to the common bit line in the first direction;

[0012] A read transistor includes a read gate, a read gate dielectric layer, and a read channel layer. The read gate includes a memory gate and a control gate. The memory gate is located on the side of the write transistor away from the common bit line in a first direction and is connected to the write channel layer in the first direction. The control gate is located between the memory gate and the read source line in the first direction and is insulated from and spaced apart from both the memory gate and the read source line. The read gate dielectric layer is located between the common bit line and the read source line in the first direction and connects the control gate and the memory gate in a second direction. The read channel layer is located on the side of the read gate dielectric layer away from the read gate in the second direction, and the common bit line and the read source line are respectively connected to both sides of the read channel layer in the first direction.

[0013] In some embodiments, the read transistor includes a junctionless N-type transistor.

[0014] In some embodiments, the memory gate is U-shaped and surrounds the write channel layer.

[0015] In some embodiments, the read gate has a read gate dielectric layer and a read channel layer connected to both sides on both sides in the second direction.

[0016] In some embodiments, the read channel layer is U-shaped and includes a first doped region, a second doped region, and a channel region located between the two. The first doped region is connected to the common bit line, the second doped region is connected to the read source line, and the channel region is located on the surface of the read gate dielectric layer away from the memory gate.

[0017] In some embodiments, the same read source line is symmetrically provided with the storage cells connected thereto on opposite sides of the first direction.

[0018] In some embodiments, the semiconductor structure further includes:

[0019] A substrate on which multiple layers of the memory cells are stacked and arranged in an array along the first direction and the second direction;

[0020] A write word line extends from above the top layer of the memory cell to the substrate and includes the write gates of a plurality of write transistors arranged perpendicular to the substrate;

[0021] A read word line extends from above the top-level memory cell to the substrate and includes the control gate of a plurality of read transistors arranged perpendicular to the substrate;

[0022] The read source line extends from above the top layer of the memory cell to the substrate and along the second direction, connecting the read channel layer of the plurality of read transistors arranged perpendicular to the substrate and along the second direction.

[0023] In some embodiments, the semiconductor structure further includes:

[0024] Multiple isolation layers are stacked at intervals, and the memory cell and the common bit line are located between two adjacent isolation layers;

[0025] A first filling medium layer is located in the first direction between the control gate and the memory gate and between the read word line and the read source line, and extends from above the top memory cell to the substrate;

[0026] The second filling medium layer is located on the side of the read channel layer away from the read gate medium layer in the second direction, and extends from above the top memory cell to the substrate;

[0027] The third filling medium layer is located between the two adjacent isolation layers and is located between the common bit line and the memory gate in the first direction;

[0028] A fourth filling medium layer is located on the side of the common bit line away from the memory cell in the first direction, and extends from above the top memory cell to the substrate;

[0029] The fifth filling medium layer is located between the write channel layer and the isolation layer.

[0030] According to various embodiments of this disclosure, a method for fabricating a semiconductor structure is also provided, the method comprising:

[0031] Provide a base;

[0032] A read transistor is formed on the substrate. The read transistor includes a read gate, a read gate dielectric layer, and a read channel layer. The read gate includes a memory gate and a control gate arranged in a first direction and separated by an insulating distance. The read gate dielectric layer connects the control gate and the memory gate in a second direction. The read channel layer is located on the side of the read gate dielectric layer away from the read gate in the second direction.

[0033] A common bit line is formed on the side of the storage gate away from the control gate in the first direction, and a read source line is formed on the side of the control gate away from the storage gate in the first direction, and both the common bit line and the read source line extend along the second direction, and the common bit line and the read source line are respectively connected to the two sides of the read channel layer in the first direction.

[0034] A write transistor is formed between the common bit line and the memory gate. The write transistor includes a write gate, a write gate dielectric layer, and a write channel layer. The write gate dielectric layer surrounds the write gate, and the write channel layer surrounds the write gate dielectric layer. The common bit line and the memory gate are respectively connected on both sides in the first direction.

[0035] In some embodiments, prior to forming the read transistor on the substrate, the process includes:

[0036] A stacked layer is formed on the substrate, the stacked layer comprising alternately stacked isolation layers and a first sacrificial layer;

[0037] A pseudo-source line and a pseudo-transistor layer are formed through the stacked layers along a first direction. The pseudo-source line extends along a second direction. The pseudo-transistor layer is located on at least one side of the pseudo-source line in the first direction and protrudes towards the first sacrificial layer between adjacent isolation layers. The pseudo-transistor layer includes a read pseudo-transistor portion and a write pseudo-transistor portion that are spaced apart. The read pseudo-transistor portion is located on at least one side of the write pseudo-transistor portion in the second direction. The protruding portion of the read pseudo-transistor portion connects to the pseudo-source line in the first direction. The write pseudo-transistor portion is spaced apart from the pseudo-source line.

[0038] In some embodiments, forming a read transistor on the substrate includes:

[0039] A second read via and a second read lateral via are formed between the write pseudo tube portion and the pseudo source line. The second read via penetrates the stacked layer and exposes the pseudo source line and the protruding portion of the read pseudo tube portion on its sidewall. The second read lateral via is formed by lateral etching of the first sacrificial layer located between the second read via and the write pseudo tube portion in the first direction, and the second read lateral via is U-shaped and surrounds the read pseudo tube portion.

[0040] A storage gate is formed in the second read side hole, and a read word line and a first filling dielectric layer are formed in the second read through hole. The read word line includes the control gate of a plurality of read transistors arranged perpendicular to the substrate. The first filling dielectric layer is located on both sides of the read word line in the first direction.

[0041] Remove the read pseudo tube portion to form a first read through hole and a first read side hole. A read gate medium initial layer and a read channel layer are formed in the first read side hole, and a second filling medium layer is formed in the first read through hole. The read gate medium initial layer is formed at least on the hole wall surface of the first read side hole opposite to the first read through hole, and the read channel layer is formed on the surface of the read gate medium initial layer.

[0042] The portion of the initial layer of the read gate medium located on the side of the read channel layer away from the second fill medium layer in the first direction is removed to form the read gate medium layer.

[0043] In some embodiments, a dummy source line and a dummy transistor layer arranged along a first direction are formed through the stacked layers, including:

[0044] The stacked layer is etched toward the substrate to form a source trench extending along the second direction;

[0045] A pseudo-source line is formed within the source line trench;

[0046] The stacked layer is etched toward the substrate to form a first read via and a write via;

[0047] The first sacrificial layer is etched from the first read via and the write via to form the first read side via and the write side via;

[0048] A pseudo transistor layer is formed within the first read side hole, the first read through hole, the write side hole, and the write through hole.

[0049] In some embodiments, before etching the stacked layer toward the substrate to form the first read via and write via, the method further includes:

[0050] The stacked layer is etched toward the substrate to form a second read via that exposes the dummy source line;

[0051] A second sacrificial layer is formed within the second read hole;

[0052] Furthermore, when the first sacrificial layer is etched from the first read via to form the first read side via, the first read side via exposes the second sacrificial layer;

[0053] The method of forming a second read through hole and a second read side hole between the write pseudo tube and the pseudo source line includes:

[0054] Remove the second sacrificial layer;

[0055] The first sacrificial layer is etched laterally from the second read via to form the second read lateral via.

[0056] In some embodiments, before removing the read pseudo-tube portion and forming the first read through hole and the first read lateral hole, the process includes:

[0057] A bit line slot is formed on the side of the write pseudo-tube portion away from the memory gate in the first direction. The bit line slot includes a bit line trench and a bit line lateral slot. The bit line trench penetrates the stacked layer, and the bit line lateral slot is formed by lateral etching of the first sacrificial layer and exposes the write pseudo-tube portion, the read pseudo-tube portion and the memory gate.

[0058] A third filling medium layer is formed in the slot on the side of the bit line, and the third filling medium layer covers the memory gate;

[0059] A pseudo bit line layer is formed in the remaining space of the bit line slot, and the pseudo bit line layer connects the write pseudo tube section, the read pseudo tube section and the second filling medium layer in the second direction.

[0060] In some embodiments, removing a portion of the initial layer of the read gate medium located on the side of the read channel layer away from the second filling medium layer in the first direction to form a read gate medium layer includes:

[0061] Remove the pseudo bit line layer to form a bit line slot, and remove the pseudo source line to form a source line trench;

[0062] The read gate dielectric initial layer is etched from the bit line slots and source line trenches to form the read gate dielectric layer.

[0063] In some embodiments, forming a common bit line spaced apart from the control gate on the side of the memory gate away from the control gate in the first direction, and forming a read source line spaced apart from the control gate on the side of the control gate away from the memory gate in the first direction, includes:

[0064] A common bit line is formed in the bit line side groove, a fourth filling medium layer is formed in the bit line trench, and a read source line is formed in the source line trench.

[0065] In some embodiments, forming a storage gate within the second read-side via and forming a read word line and a first filling medium layer within the second read-through via includes:

[0066] A storage gate is formed within the second read side aperture;

[0067] A first initial filling layer is formed within the second read hole;

[0068] The first initial filling layer is etched to form a first filling medium layer and a readout line hole, wherein the first filling medium layer is located on both sides of the readout line hole in the first direction;

[0069] A reading line is formed within the reading line hole.

[0070] In some embodiments, forming a write transistor between the common bit line and the memory gate includes:

[0071] Remove the pseudo-write tube portion to form a write through hole and a write side hole;

[0072] A write channel layer and a write gate dielectric layer are formed in the write side hole. The write channel layer is formed on the hole wall surface opposite to the write through hole in the write side hole, and the write gate dielectric layer is formed on the surface of the write channel layer.

[0073] A fifth filling dielectric layer is formed between the write channel layer and the isolation layer;

[0074] A write word line is formed within the write via, the write word line including the write gates of a plurality of write transistors arranged perpendicular to the substrate.

[0075] According to various embodiments of this disclosure, an electronic device is also provided, the electronic device comprising the semiconductor structure provided in the above embodiments, or a semiconductor structure fabricated according to the preparation method of the semiconductor structure provided in the above embodiments.

[0076] Details of one or more embodiments of this disclosure are set forth in the following drawings and description. Other features, objects, and advantages of this disclosure will become apparent from the specification, drawings, and claims. Attached Figure Description

[0077] To more clearly illustrate the technical solutions in the embodiments or conventional technologies of this disclosure, the accompanying drawings used in the description of the embodiments or conventional technologies will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0078] Figure 1 is a flowchart of a method for fabricating a semiconductor structure provided in one embodiment;

[0079] Figures 2 to 17 are perspective views and cross-sectional views of the semiconductor structure obtained during the fabrication process of one embodiment;

[0080] Figure 18 is a perspective view of a semiconductor structure provided in one embodiment.

[0081] It is understandable that in Figures 2 to 18, when different film layers use the same material, some of the attached figures connect different film layers of the same material to make the attached figures closer to the actual structural morphology.

[0082] To better describe and illustrate embodiments and / or examples of the inventions disclosed herein, reference may be made to one or more accompanying drawings. Additional details or examples used to describe the drawings should not be considered as limiting the scope of any of the disclosed inventions, the currently described embodiments and / or examples, or the best mode of these inventions as currently understood. Detailed Implementation

[0083] To facilitate understanding of this disclosure, a more complete description will now be given with reference to the accompanying drawings, in which preferred embodiments of the present disclosure are shown. However, this disclosure may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

[0084] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of this disclosure.

[0085] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, parts, regions, layers, doping types, and / or portions, these elements, parts, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, part, region, layer, doping type, or portion from another element, part, region, layer, doping type, or portion. Therefore, without departing from the teachings of this disclosure, the first element, part, region, layer, doping type, or portion discussed below may be referred to as a second element, part, region, layer, or portion.

[0086] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as “below,” “under,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.

[0087] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that when the terms “comprise” and / or “comprising” are used in this specification, the presence of the stated feature, integer, step, operation, element, and / or part is established, but the presence or addition of one or more other features, integers, steps, operations, elements, parts, and / or groups is not excluded. Meanwhile, when used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0088] In one embodiment, referring to Figure 1, a method for fabricating a semiconductor structure is provided, comprising the following steps:

[0089] Step S1, see Figure 2, provide substrate 100.

[0090] The substrate 100 may include a semiconductor substrate 110. The semiconductor substrate 110 may, but is not limited to, include a silicon substrate. In addition, the substrate 100 may also include an insulating isolation layer 120 for insulating the memory cells from the semiconductor substrate 110, thereby preventing leakage current between the memory cells and the semiconductor substrate 110.

[0091] Step S3, referring to FIG15, a read transistor 200 is formed on the substrate 100. The read transistor 200 includes a read gate 210, a read gate dielectric layer 220, and a read channel layer 230. The read gate 210 includes a storage gate 211 and a control gate 212 arranged along a first direction and separated by an insulating distance. The read gate dielectric layer 220 connects the control gate 212 and the storage gate 211 in a second direction. The read channel layer 230 is located on the side of the read gate dielectric layer 220 away from the read gate 210 in the second direction.

[0092] The read transistor 200 can be a junctionless transistor, and its read channel layer 230 can be a doped semiconductor layer. The material of the read channel layer 230 can be, but is not limited to, polysilicon. For example, the material of the read channel layer 230 can also be a metal oxide material, such as IGZO.

[0093] As an example, the read transistor 200 may include an N-type transistor (such as an NMOS transistor). N-type semiconductor materials (such as silicon) have high mobility, which is beneficial for improving read speed. Of course, the read transistor 200 may also include a P-type transistor; there is no limitation on the conductivity type of the read transistor 200.

[0094] Meanwhile, the read gate 210 of the read transistor 200 includes a storage gate 211 and a control gate 212. The storage gate 211 and the control gate 212 are disposed side by side on one side of the read gate dielectric layer 220, and both play a controlling role in the formation of the conductive channel in the read channel layer 230. Among them, the storage gate 211 is in contact with the write channel layer 530 of the write transistor 500 and can serve as a storage node.

[0095] The materials of the storage gate 211 and the control gate 212 can be different or the same. For example, the material of the storage gate 211 can be, but is not limited to, the conductive material TiN. The material of the control gate 212 can be, but is not limited to, the conductive material W.

[0096] The material of the read gate dielectric layer 220 may include, but is not limited to, a high dielectric constant material. For example, the material of the read gate dielectric layer 220 may include, but is not limited to, HfOx, HfSiOx, HfOx / SiO2 stacked materials, or materials such as Al2O3 and STO.

[0097] In step S4, referring to FIG15, a common bit line 300 is formed on the side of the storage gate 211 away from the control gate 212 in the first direction, and a read source line 400 is formed on the side of the control gate 212 away from the storage gate 211 in the first direction, and both the common bit line 300 and the read source line 400 extend along the second direction, and the common bit line 300 and the read source line 400 are respectively connected to both sides of the read channel layer 230 in the first direction.

[0098] The common bit line 300 and the read source line 400 can be made of conductive materials, including but not limited to TiN. They can be made of the same or different materials.

[0099] The common bit line 300 and the read source line 400 are respectively connected to the two sides of the read channel layer 230 in the first direction, so that the source region and the drain region of the read transistor can be connected respectively.

[0100] Both the common bit line 300 and the read source line 400 extend along the second direction, thereby providing read bit line signals and source signals (such as ground signals) to multiple read transistors arranged in the second direction.

[0101] In step S5, referring to FIG17, a write transistor 500 is formed between the common bit line 300 and the memory gate 211. The write transistor 500 includes a write gate 510, a write gate dielectric layer 520 and a write channel layer 530. The write gate dielectric layer 520 surrounds the write gate 510, and the write channel layer 530 surrounds the write gate dielectric layer 520. The common bit line 300 and the memory gate 211 are respectively connected on both sides in the first direction.

[0102] The material written to the channel layer 530 can be IGZO, thereby giving the write transistor 500 a lower off-state current. Of course, the material written to the channel layer 530 is not limited to this; for example, it can also be other metal oxide materials.

[0103] The material written to the gate 510 may include, but is not limited to, the conductive material ITO. The material written to the gate dielectric layer 520 may include, but is not limited to, a high dielectric constant material.

[0104] The write channel layer 530 is connected to the common bit line 300 and the memory gate 211 on both sides in the first direction, so that the common bit line 300 and the memory gate 211 can be connected to the source region and drain region of the write transistor 500, respectively. At this time, the write transistor 500 can obtain the write bit line signal from the common bit line 300, and at the same time, when the write gate 510 controls the write transistor 500 to be turned on, it stores the data to the memory gate 211.

[0105] The write transistor 500 and the read transistor 200 can form a memory cell with a 2TOC architecture. As an example, multiple layers of memory cells arranged in an array along a first direction and a second direction can be stacked on the substrate 100, and multiple write word lines 510a and multiple read word lines 212a can be formed. The write word line 510a extends from above the top layer memory cell to the substrate 100 and includes the write gate 510 of multiple write transistors 500 arranged vertically to the substrate.

[0106] The read word line 212a extends from above the top-level memory cell to the substrate 100 and includes a control gate 212 of a plurality of read transistors arranged along the vertical substrate.

[0107] When the read transistor is an N-type transistor, during the reading and writing of the memory cell, voltages can be applied to the write word line 510a, read word line 212a, common bit line 300, and read source line 400 as shown in the table below.

[0108] Specifically, when writing data, a 0 / -V signal can be applied to the read word line 212a. WL The voltage, thereby making the voltage on the control gate 212 0V or -V. WL This shuts down the read transistor 200. At this time, the common bit line 300 can be used to provide the write bit line signal. When writing data "1", a voltage Vw is applied to the common bit line 300, allowing a positive voltage to be stored on the memory gate 211, which serves as the memory node. When writing data "0", a voltage of 0V is applied to the common bit line 300, allowing zero voltage to be stored on the memory gate 211, which serves as the memory node.

[0109] During data reading, the common bit line 300 can be used to provide the read bit line signal, to which a voltage V can be applied. R At the same time, a V-shaped force can be applied to the read word line 212a. WL The voltage, thus making the voltage on the control gate 212 V. WL At this time, the switching state of the read transistor 200 is affected by the voltage on the memory gate 211. Different voltages applied to the memory gate 211 result in different switching states of the read transistor 200. Therefore, applying V to the read word line 212a... WL Subsequently, the voltage change and current value on the common bit line 300 differ. Therefore, the voltage change on the common bit line 300 can be read in voltage mode, or the current on the common bit line 300 can be read in current mode, thus allowing the data "1" and "0" to be read. When a positive voltage is stored on the memory gate 211, the voltage change on the common bit line 300 is large, and the current value is large, thus allowing the data "1" to be read. When zero voltage is stored on the memory gate 211, the voltage change on the common bit line 300 is small, and the current value is small, thus allowing the data "0" to be read.

[0110] In this embodiment, by setting the read gate 210 to include a storage gate 211 and a control gate 212, the switch of the read transistor 200 can be directly controlled through the control gate 212, thereby facilitating read and write control. Simultaneously, by forming the storage gate 211 and the control gate 212 arranged along a first direction and spaced apart insulated from each other, a common bit line 300 is formed on the side of the storage gate 211 away from the control gate 212 in the first direction, and a read source line 400 is formed on the side of the control gate 212 away from the storage gate 211 in the first direction, spaced apart from it. This allows the common bit line 300, storage gate 211, control gate 212, and read source line 400 to be sequentially arranged along the first direction. Simultaneously, a read gate dielectric layer 220 is formed to connect the control gate 212 and the memory gate 211 in the second direction, and a read channel layer 230 is formed on the side of the read gate dielectric layer 220 away from the read gate 210 in the second direction, so that the read channel layer 230 and the read gate 210 (including the memory gate 211 and the control gate 212) can be arranged along the second direction. Therefore, the common bit line 300 and the read source line 400 on both sides of the formed read channel layer 230 and the read gate 210 can be connected. At the same time, a write transistor 500 is formed between the common bit line 300 and the memory gate 211, so that the common bit line 300 and the memory gate 211 can be connected on both sides of the write channel layer in the first direction, respectively. Therefore, in this embodiment, the write transistor 500 and the read transistor 200 can share the common bit line 300, thereby effectively reducing the number of bit lines, and thus reducing the subsequent step-by-step process for connecting the bit lines by half. Furthermore, the write transistor 500 and the read transistor 200 share a common bit line 300, which can effectively increase the density of memory cells per unit area.

[0111] In one embodiment, before forming the read transistor 200 on the substrate 100 in step S3, the method further includes:

[0112] Step S21, please refer to FIG2, a stacked layer 600 is formed on the substrate 100. The stacked layer 600 includes an alternately stacked isolation layer 610 and a first sacrificial layer 620.

[0113] An isolation layer 610 and a first sacrificial layer 620 can be alternately stacked on a substrate 100 using a deposition process. The deposition process may include, but is not limited to, chemical vapor deposition or sol-gel methods.

[0114] The isolation layer 610 is used to provide insulation isolation between adjacent memory cells after the semiconductor structure is fabricated. The isolation layer 610 is made of an insulating material. The first sacrificial layer 620 is a film layer formed during the semiconductor structure fabrication process; its material can be an insulating material or other materials.

[0115] As an example, the material of the isolation layer 610 can be silicon oxide, and the material of the first sacrificial layer 620 can be silicon nitride. The isolation layer 610 can be prepared, for example, by a process such as the TEOS sol-gel method, and the first sacrificial layer 620 can be prepared, for example, by a process such as plasma-enhanced chemical vapor deposition (PECVD).

[0116] Step S22, referring to FIG6, a pseudo source line 710 and a pseudo transistor layer 720 are formed through the stacked layer 600 along a first direction. The pseudo source line 710 extends along a second direction. The pseudo transistor layer 720 is located on at least one side of the pseudo source line 710 in the first direction and protrudes towards the first sacrificial layer 620 between adjacent isolation layers 610. The pseudo transistor layer 720 includes a read pseudo transistor portion 721 and a write pseudo transistor portion 722 disposed at intervals. The read pseudo transistor portion 721 is located on at least one side of the write pseudo transistor portion 722 in the second direction, and the protruding portion of the read pseudo transistor portion 721 is connected to the pseudo source line 710 in the first direction. The write pseudo transistor portion 722 is disposed at intervals with the pseudo source line 710.

[0117] The pseudo-source line 710 is a pseudo-film layer that presets the position of the read source line 400 of the read transistor. The pseudo-transistor layer 720 is a pseudo-film layer that presets the position of the transistor in the memory cell. Specifically, the pseudo-transistor layer 720 includes a read pseudo-transistor section 721 and a write pseudo-transistor section 722. The read pseudo-transistor section 721 is used to locate the position of the read transistor 200, specifically defining the channel position of the read transistor 200. The write pseudo-transistor section 722 is used to locate the position of the write transistor 500.

[0118] As an example, step S22 may include:

[0119] Step S221, please refer to Figure 3, etch the stacked layer 600 toward the substrate 100 to form a source trench 10 extending along the second direction.

[0120] Source trenches 10 can be formed through processes such as photolithography and etching (e.g., dry etching).

[0121] Step S222, please refer to Figure 3, a pseudo source line 710 is formed in the source line trench 10.

[0122] The dummy source line 710 can be formed, for example, by a spin-coating dielectric layer (SOD) process. The material of the dummy source line 710 can be, but is not limited to, silicon oxide.

[0123] In step S224, please refer to Figure 4, etch the stacked layer 600 toward the substrate 100 to form the first read via 21 and write via 31.

[0124] The first read hole 21 and write hole 31 can be formed by photolithography, etching (such as dry etching) and other processes.

[0125] As an example, a first read via 21 can be formed on both sides of the pseudo-source line 710 in the first direction, and a write via 31 can be formed on both sides of the pseudo-source line 710. In this case, two memory cells symmetrically arranged in the first direction can be formed on both sides of the pseudo-source line 710.

[0126] Of course, the first read hole 21 and write hole 31 can also be formed only on one side of the first direction, and there is no restriction on this.

[0127] In step S225, please refer to Figure 5, the first sacrificial layer 620 is etched from the first read via 21 and the write via 31 to form the first read side via 22 and the write side via 32.

[0128] At this point, a lateral wet etching process can be used to form a first read side hole 22 around the first read via 21 and a write side hole 32 around the write via 31. The etching depth of the first read side hole 22 and the write side hole 32 can be, for example, 25nm-35nm (e.g., 30nm).

[0129] In step S226, please refer to Figure 6, a pseudo transistor layer 720 is formed in the first read side hole 22, the first read through hole 21, the write side hole 32, and the write through hole 31.

[0130] The portion of the pseudo transistor layer 720 located within the write side hole 32 and the write through hole 31 constitutes a protrusion facing the first sacrificial layer 620.

[0131] A pseudo transistor layer 720 can be formed by simultaneously depositing a pseudo transistor material (such as amorphous silicon) in the first read side hole 22, the first read through hole 21, the write side hole 32, and the write through hole 31 through a deposition process.

[0132] At this time, the dummy transistor material formed in the first read side hole 22 and the first read through hole 21 can form a read dummy transistor section 721. The dummy transistor material formed in the write side hole 32 and the write through hole 31 can form a write dummy transistor section 722.

[0133] Of course, in other examples, the formation of the dummy source line 710 and the dummy transistor layer 720 can also be different. For example, the first read via 21 and write via 31 of different sizes can be etched separately to form the read dummy transistor portion 721 and the write dummy transistor portion 722 sequentially. Alternatively, if the process precision is feasible, the source trench 10, the first read via 21, and the write via 31 can be formed simultaneously. Then, the dummy source line 710 is filled. Afterward, the dummy source line 710 within the first read via 21 and write via 31 is removed, and the first read side via 22 and write side via 32 are further etched to form them. Then, the dummy transistor layer 720 is filled.

[0134] In one embodiment, based on steps S21 and S22 preceding step S3, step S3, forming a read transistor 200 on the substrate 100, includes:

[0135] In step S31, referring to Figures 5 and 6, a second read via 41 and a second read lateral via 42 are formed between the write pseudo tube portion 722 and the pseudo source line 710. The second read via 41 penetrates the stacked layer 600 and exposes the protruding portion of the pseudo source line 710 and the read pseudo tube portion 721 on its sidewall. The second read lateral via 42 is formed by laterally etching a first sacrificial layer 620 located between the second read via 41 and the write pseudo tube portion 722 in the first direction, and the second read lateral via 42 surrounds the write pseudo tube portion 722 in a U-shape.

[0136] As an example, in order to perform step S31, while step S22 includes steps S221 to S226, please refer to Figure 3, before step S224, the following steps are included:

[0137] In step S2231, the stacked layer 600 is etched toward the substrate 100 to form a second read hole 41 that exposes the dummy source line 710.

[0138] The second read hole 41 can be formed through processes such as photolithography and etching (e.g., dry etching).

[0139] The second read hole 41 is formed on both sides of the pseudo source line 710 in the first direction, or it can be formed only on one side of the pseudo source line 710 in the first direction.

[0140] Step S2232: A second sacrificial layer 730 is formed in the second read hole 41.

[0141] The second sacrificial layer 730 can be formed, for example, by a process such as spin coating dielectric layer (SOD). The material of the second sacrificial layer 730 may include, but is not limited to, silicon oxide.

[0142] Meanwhile, in step S225, when the first sacrificial layer 620 is etched from the first read via 21 to form the first read side via 22, the first read side via 22 exposes the second sacrificial layer 730.

[0143] At this point, referring to Figure 6, step S31 may include:

[0144] Step S311: Remove the second sacrificial layer 730.

[0145] After the second sacrificial layer 730 is removed, the second read hole 41 formed previously is re-formed.

[0146] Step S312: The first sacrificial layer 620 is etched laterally from the second read via 41 to form the second read lateral via 42.

[0147] Since the dummy source line 710 and the protruding portion of the read dummy tube 721 are exposed on the sidewall of the second read via 41, when the second read lateral via 42 is formed by lateral etching, the first sacrificial layer 620 facing the write dummy tube 722 is etched unidirectionally in the first direction.

[0148] Of course, in other examples, step S31 can also be performed by directly etching the stacked layer 600 to form the second read via 41. Then, the first sacrificial layer 620 is etched laterally from the second read via 41 to form the second read lateral via 42.

[0149] In step S32, referring to FIG10, a storage gate 211 is formed in the second read side hole 42, and a read word line 212a and a first filling dielectric layer 810 are formed in the second read through hole 41. The read word line 212a includes control gates 212 of a plurality of read transistors arranged along the vertical substrate, and the first filling dielectric layer 810 is located on both sides of the read word line 212a in a first direction.

[0150] As an example, step S32 may include:

[0151] In step S321, please refer to Figure 7, a storage gate 211 is formed in the second read side hole 42.

[0152] A first conductive material layer can be deposited on the structural surface after the formation of the second read side aperture 42. This first conductive material layer can fill the second read side aperture 42. The first conductive material layer outside the second read side aperture 42 is then removed, thereby forming the memory gate 211. As an example, the memory gate 211 can fill a portion of the second read side aperture 42. Of course, the memory gate 211 can also fill the entire second read side aperture 42.

[0153] The memory gate 211 is formed within the second read-side via 42, which is U-shaped and surrounds the write dummy transistor 722. Therefore, the memory gate 211 is U-shaped and surrounds the write dummy transistor 722. Thus, after the semiconductor structure is fabricated, the memory gate 211 is U-shaped and surrounds the write transistor 500. This increases the contact area between the memory gate 211 and the write channel layer 530 of the write transistor 500, thereby reducing the contact resistance between them. Simultaneously, the memory gate 211 and the write transistor 500 can partially overlap, effectively reducing the size of the memory cell in the first direction, thereby reducing the memory cell area and increasing the storage density.

[0154] Step S322, please refer to Figure 8, a first filling initial layer 810a is formed in the second read hole 41.

[0155] The first initial filling layer 810a can be formed, for example, by a process such as spin coating dielectric layer (SOD). The material of the first initial filling layer 810a may include, but is not limited to, silicon oxide.

[0156] Step S323, please refer to FIG9, etch the first filling initial layer 810a to form the first filling dielectric layer 810 and the read line hole, the first filling dielectric layer 810 being located on both sides of the read line hole in the first direction.

[0157] The first initial filling layer 810a can be etched using processes such as photolithography and etching (e.g., dry etching) to form the reading line holes.

[0158] The protruding portion of the read pseudo tube 721 is exposed on the sidewall of the second read through hole 41. Therefore, after the first filling initial layer 810a is formed in the second read through hole 41 by etching, the read word line hole can expose the protruding portion of the read pseudo tube in the second direction.

[0159] Step S324, please refer to Figure 10, form a reading line 212a in the reading line hole.

[0160] A read word line 212a is formed in a read word line hole, thereby penetrating the stacked layer 600 and including a control gate 212 of a plurality of read transistors arranged along a vertical substrate.

[0161] The material of the read word line 212a may include, but is not limited to, metal W.

[0162] In step S34, please refer to FIG14, remove the read pseudo tube portion 721 to form a first read through hole 21 and a first read side hole 22. A read gate medium initial layer 2201 and a read channel layer 230 are formed in the first read side hole 22, and a second filling medium layer 820 is formed in the first read through hole 21. The read gate medium initial layer 2201 is formed at least on the hole wall surface of the first read side hole 22 opposite to the first read through hole 21, and the read channel layer 230 is formed on the surface of the read gate medium initial layer 2201.

[0163] Referring to Figure 13, a patterned mask layer can be formed first to expose the read pseudo-channel section 721 while covering the write pseudo-channel section 722. Then, the read pseudo-channel section 721 can be removed using a wet etching process. After that, the patterned mask layer is removed.

[0164] Then, a read gate dielectric material layer and a read channel material layer can be sequentially formed on the structural surface of the removed read pseudo-tube portion 721 using deposition processes such as atomic layer deposition (ALD) or chemical vapor deposition (CVD). Next, the read channel material layer and the read gate dielectric material layer located outside the first read side aperture 22 are removed, thereby forming the read channel layer 230 and the initial read gate dielectric layer 2201. In some examples, the read gate dielectric material layer outside the first read side aperture 22 may not be removed.

[0165] Simultaneously, as an example, after forming the read channel material layer, a protective dielectric material layer can also be formed on the surface of the read channel material layer. Then, the protective dielectric material layer other than the first read side hole 22 is removed, thereby forming a protective dielectric layer 910. Afterwards, the read gate dielectric material layer and the read channel material layer other than the first read side hole 22 can be etched as a protection against the protective dielectric layer 910, thereby forming a read gate dielectric initial layer 2201 and a read channel layer 230. At this time, the read gate dielectric material layer and the read channel material layer on the hole wall surface of the first read side hole 22 opposite to the first read via 21 can be effectively retained, so that the formed read channel layer 230 can be effectively opposite to the read gate 210 (including the memory gate 211 and the control gate 212) in the second direction.

[0166] Then, referring to Figure 14, a second filling dielectric layer 820 can be formed to fill the first read via 21. It can be understood that when the read gate dielectric initial layer 2201, the read channel layer 230, and the protective dielectric layer 910 do not completely fill the first read side via 22, the second filling dielectric layer 820 can also extend from the first read via 21 into the first read side via 22.

[0167] Step S35, please refer to FIG15, remove part of the initial read gate dielectric layer 2201 located on the side of the read channel layer 230 away from the second fill dielectric layer 820 in the first direction to form the read gate dielectric layer 220.

[0168] At this point, the two ends of the read channel layer 230 can be exposed in the first direction so that the read channel layer 230 can be effectively connected to the subsequently formed common bit line 300 and read source line 400.

[0169] In this embodiment, the formation of the storage gate 211, control gate 212, and channel of the read transistor 200 can all be completed through a hole etching process, which gives it significant advantages in terms of size and process flow.

[0170] In one embodiment, when the process of forming the read transistor 200 in step S3 includes steps S31 to S35, please refer to FIG11. Before removing the dummy read transistor 721 in step S34, the process includes:

[0171] In step S331, a bit line slot 50 is formed on the side of the write pseudo-channel 722 away from the memory gate 211 in the first direction. The bit line slot 50 includes a bit line trench 51 and a bit line lateral slot 52. The bit line trench 51 penetrates the stacked layer 600, and the bit line lateral slot 52 is formed by lateral etching of the first sacrificial layer 620, and exposes the write pseudo-channel 722, the read pseudo-channel 721 and the memory gate 211.

[0172] First, the stacked layer 600 can be etched toward the substrate 100 to form a bit line slot 50. Then, the write pseudo-channel 722, the read pseudo-channel 721, and the memory gate 211 can be used as etch stop layers, and the first sacrificial layer 620 can be etched laterally from the bit line slot 50 to form a bit line lateral slot 52.

[0173] In step S332, a third filling dielectric layer 830 is formed in the bit line side slot 52, and the third filling dielectric layer 830 covers the memory gate 211.

[0174] First, a third filling material layer can be formed on the structural surface after the bit line lateral groove 52 is formed using deposition processes such as ALD. Then, the third filling material layer is etched back until the write pseudo tube 722 and the read pseudo tube 721 are exposed, thereby forming the third filling dielectric layer 830.

[0175] The third filler dielectric layer 830 covers the memory gate 211, thereby effectively isolating the memory gate 211 from the subsequently formed common bit line 300. The material of the third filler dielectric layer 830 may include, but is not limited to, SiO2. For example, the material of the third filler dielectric layer 830 may also include HfOx, Al2O3, etc.

[0176] In step S333, please refer to FIG12, a pseudo bit line layer 740 is formed in the remaining space of the bit line slot 50. The pseudo bit line layer 740 is connected to the write pseudo tube section 722, the read pseudo tube section 721 and the second filling medium layer 820 in the second direction.

[0177] The pseudo-position line layer 740 is a pseudo-film layer positioned at the predetermined location of the common position line 300. The pseudo-position line layer 740 can be formed using processes such as low-pressure chemical vapor deposition (LPCVD). The material of the pseudo-position line layer 740 can be, but is not limited to, Si3N4.

[0178] Based on this, as an example, referring to Figures 14 and 15, the process of forming the read gate dielectric layer 220 in step S35 may include:

[0179] Step S351: Remove the pseudo bit line layer 740 to form a bit line slot 50, and remove the pseudo source line 710 to form a source line trench 10.

[0180] The pseudo bit line layer 740 and pseudo source line 710 can be removed by wet selective etching.

[0181] In the previous step, the pseudo bit line layer 740 is formed after the bit line slot 50 is formed, and the pseudo source line 710 can be formed after the source line trench 10 is formed. Therefore, after removing the pseudo bit line layer 740, the bit line slot 50 can be re-formed, and after removing the pseudo source line 710, the source line trench 10 can be re-formed.

[0182] In step S352, the self-alignment trench 50 and the source trench 10 are etched to form the read gate dielectric initial layer 2201, thereby forming the read gate dielectric layer 220.

[0183] The read gate dielectric initial layer 2201 exposed by the bit line slot 50 and the source line trench 10 can be removed by wet selective etching, thereby forming the read gate dielectric layer 220.

[0184] After the read gate dielectric layer 220 is formed, the read channel layer 230 is exposed by the bit line slot 50 and the source line trench 10. As an example, the read channel layer 230 can also be doped with source and drain through the bit line slot 50 and the source line trench 10 to form a first doped region and a second doped region, respectively, thereby reducing the contact resistance between the read channel layer 230 and the subsequently formed common bit line 300 and read source line 400. The read channel layer 230 between the first doped region and the second doped region can serve as the channel region.

[0185] Furthermore, the formation process of the common bit line 300 and the read source line 400 in step S4 may include:

[0186] In step S41, please refer to Figure 15, a common bit line 300 is formed in the bit line side groove 52, a fourth filling medium layer 840 is formed in the bit line trench 51, and a read source line 400 is formed in the source line trench 10.

[0187] First, a second conductive material layer can be formed to fill the bit line slot 50 and the source line trench 10. Then, the second conductive material layer is planarized. Afterward, the second conductive material layer outside the bit line side slot 52 is removed. The second conductive material layer remaining in the bit line side slot 52 forms a common bit line 300. The second conductive material layer remaining in the source line trench 10 forms a read source line 400. Subsequently, a fourth filling dielectric layer 840 can be formed within the bit line trench 51.

[0188] In other examples, the pseudo bitline layer 740 can be removed first to form the bitline slot 50, and then the read gate dielectric initial layer 2201 can be etched from the bitline slot 50. A common bitline 300 is then formed within the bitline lateral slot 52, and a fourth filler dielectric layer 840 is formed within the bitline trench 51. Then, the pseudo source line 710 is removed to form the source line trench 10, and the read gate dielectric initial layer 2201 is etched from the source line trench 10 to form the read gate dielectric layer 220. Finally, the read source line 400 is formed within the source line trench 10. Alternatively, similarly, the source line trench 10 can be removed first, followed by the removal of the pseudo bitline layer 740.

[0189] After the read gate dielectric layer 220 is formed, the read channel layer 230 is exposed by the bit line side slot 52 and the source line slot 10. Therefore, the two ends of the read channel layer 230 in the first direction can be effectively connected to the common bit line 300 and the read source line 400, respectively.

[0190] In one embodiment, based on steps S21 and S22 preceding step S3, the process of forming the write transistor 500 in step S5 may include:

[0191] Step S51, please refer to Figure 15, remove the pseudo tube section 722 to form the write through hole 31 and the write side hole 32.

[0192] The pseudo-writing section 722 can be removed by wet selective etching.

[0193] In the previous step, the write pseudo-pipe 722 is formed after the write via 31 and the write side via 32 are formed. Therefore, after removing the pseudo bit line layer 740, the write via 31 and the write side via 32 can be re-formed.

[0194] In step S52, please refer to FIG16, a write channel layer 530 and a write gate dielectric layer 520 are formed in the write side hole 32. The write channel layer 530 is formed on the hole wall surface of the write side hole 32 opposite to the write through hole 31, and the write gate dielectric layer 520 is formed on the surface of the write channel layer 530.

[0195] First, a write channel material layer, a write gate dielectric material layer, and a conductive protection material layer can be sequentially formed on the structural surface after removing the write pseudo-tube section 722. As an example, the material of the write channel material layer can be set to IGZO, the material of the write gate dielectric material layer to HfOx, and the material of the conductive protection material layer to ITO.

[0196] Then, the conductive protective material layer located outside the write side hole 32 is removed to form the conductive protective layer 920.

[0197] Subsequently, with the conductive protective layer 920 as a protection, the write gate dielectric material layer and write channel material layer located outside the write side hole 32 are etched away, thereby forming the write channel layer 530 and the write gate dielectric layer 520.

[0198] In step S53, please refer to Figure 17, a fifth filling dielectric layer 850 is formed between the write channel layer 530 and the isolation layer 610.

[0199] Referring to Figure 16, after etching away the write gate dielectric material layer and write channel material layer located outside the write side via 32, protected by the conductive protective layer 920, a gap will be formed between the write channel layer 530 and the write gate dielectric layer 520 and the isolation layer 610. Referring to Figure 17, a fifth filler dielectric layer 850 can be filled into this gap. The material of the fifth filler dielectric layer 850 may include, but is not limited to, silicon oxide.

[0200] In step S54, a write word line 510a is formed in the write via 31. The write word line 510a includes the write gates 510 of a plurality of write transistors 500 arranged along the vertical substrate.

[0201] The material of the write word line 510a can be the same as that of the conductive protective layer 920, for example, both can be ITO. Of course, the materials of the two can also be different, depending on the actual requirements.

[0202] In this embodiment, the write transistor 500 can be formed through a hole etching process, which gives it significant advantages in terms of size and process flow.

[0203] It should be understood that although the steps in the flowchart of Figure 1 are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some of the steps in Figure 1 may include multiple steps or multiple stages, which are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages in other steps.

[0204] In one embodiment, referring to Figure 17 or Figure 18, a semiconductor structure is provided, the semiconductor structure including: a common bit line 300, a read source line 400, and a memory cell.

[0205] The common bit line 300 and the read source line 400 are arranged along a first direction. Both the common bit line 300 and the read source line 400 extend along a second direction, which intersects with the first direction. The memory cell is located between the common bit line 300 and the read source line 400 in the first direction.

[0206] Meanwhile, the storage unit includes a write transistor 500 and a read transistor 200.

[0207] The write transistor 500 includes a write gate 510, a write gate dielectric layer 520, and a write channel layer 530. The circumferential direction of the write gate 510 may intersect with a first direction and a second direction. The write gate dielectric layer 520 surrounds the write gate 510. The write channel layer 530 surrounds the write gate dielectric layer 520 and is connected to a common bit line 300 in the first direction.

[0208] The read transistor 200 includes a read gate 210, a read gate dielectric layer 220, and a read channel layer 230.

[0209] The read gate 210 includes a memory gate 211 and a control gate 212. The memory gate 211 and the control gate 212 are arranged along a first direction.

[0210] The memory gate 211 is located on the side of the write transistor 500 away from the common bit line 300 in the first direction, and is connected to the write channel layer 530 in the first direction. Therefore, the two sides of the write channel layer 530 in the first direction are respectively connected to the memory gate 211 and the common bit line 300, so that the common bit line 300 and the memory gate 211 can be connected to the source region and drain region of the write transistor 500, respectively. At this time, the write transistor 500 can obtain the write bit line signal from the common bit line 300, and simultaneously, when the write gate 510 controls the write transistor 500 to be turned on, it stores data in the memory gate 211.

[0211] The control gate 212 is located between the storage gate 211 and the read source line 400 in the first direction, and is insulated from both the storage gate 211 and the read source line 400.

[0212] The read gate dielectric layer 220 is located between the common bit line 300 and the read source line 400 in a first direction, and connects the control gate 212 and the memory gate 211 in a second direction. The read channel layer 230 is located on the side of the read gate dielectric layer 220 away from the read gate 210 in the second direction. Therefore, the read channel layer 230 and the read gate 210 (including the memory gate 211 and the control gate 212) can be arranged along the second direction.

[0213] The read channel layer 230 can be a doped semiconductor layer, and the two sides of the read channel layer 230 in the first direction are respectively connected to the common bit line 300 and the read source line 400, so that the common bit line 300 and the read source line 400 can be respectively connected to the source region and the drain region of the read transistor 200. At this time, the read transistor 200 can obtain the read bit line signal from the common bit line 300 and the source signal from the read source line 400.

[0214] The materials of the common bit line 300, read source line 400, control gate 212, and storage gate 211 can be selected from conductive materials such as W, Cu, Al, Ti, Mo, Nb, V, Hf, Ta, Cr, Zr, Fe, Ru, Os, Co, Rh, Ir, Ni, Pa, Pt, Ag, Au, as well as Co-based alloys, Fe-based alloys, Ni-based alloys, FeNi-based alloys, CoNi-based alloys, FeCo-based alloys, Al-based alloys, Cu-based alloys, Mg-based alloys, Ti-based alloys, low-carbon steel, stainless steel, or conductive metal nitrides such as titanium nitride (TiN), conductive metal silicides, conductive metal carbides, conductive doped semiconductors such as doped polysilicon, and conductive metal oxide semiconductors such as indium tin oxide.

[0215] The materials used for reading the gate dielectric layer 220 and writing the gate dielectric layer 520 may include, but are not limited to, High K materials. High K materials may include, but are not limited to, HfOx, and may also be HfSiOx, HfOx / SiO2 stacked materials, or other oxide materials (e.g., Al2O3, STO, etc.).

[0216] The material written to the channel layer 530 may include, but is not limited to, IGZO. The material read from the channel layer 230 may include, but is not limited to, amorphous silicon.

[0217] The process of reading and writing the storage unit can be referred to above, and will not be repeated here.

[0218] In this embodiment, by configuring the read gate 210 to include a storage gate 211 and a control gate 212, the control gate 212 can directly control the switching of the read transistor 200, thereby facilitating read and write control. Simultaneously, the common bit line 300 is connected to both the write channel layer 530 and the read channel layer 230, allowing the write transistor 500 and the read transistor 200 to share the common bit line 300. This effectively reduces the number of bit lines, thereby halving the subsequent step-by-step process for connecting the bit lines. Furthermore, the shared common bit line 300 between the write transistor 500 and the read transistor 200 allows for a significantly higher storage cell density per unit area.

[0219] In one embodiment, the read transistor 200 includes a junctionless N-type transistor. N-type semiconductor materials (such as silicon) have high mobility, which is beneficial for improving read speed. Of course, the read transistor 200 may also include a P-type transistor; there is no limitation on the conductivity type of the read transistor 200.

[0220] In one embodiment, the memory gate 211 is U-shaped and surrounds the write channel layer 530. For example, the memory gate 211 may partially surround the write channel layer 530. In this case, the contact area between the memory gate 211 and the write channel layer 530 can be increased, thereby reducing the contact resistance between them. At the same time, the memory gate 211 and the write transistor 500 may partially overlap, thereby effectively reducing the size of the memory cell in the first direction, thereby reducing the memory cell area and increasing the storage density.

[0221] In one embodiment, the read gate 210 has a read gate dielectric layer 220 and a read channel layer 230 connected to both sides in the second direction. In this case, the gate control capability of the read transistor 200 can be effectively increased.

[0222] In other embodiments, a read gate dielectric layer 220 and a read channel layer 230 connected thereto may also be provided on one side of the read gate 210, and this is not a limitation.

[0223] In one embodiment, the read channel layer 230 is U-shaped and includes a first doped region, a second doped region, and a channel region located between the two. The first doped region is connected to a common bit line 300, the second doped region is connected to a read source line 400, and the channel region is located on the surface of the read gate dielectric layer 220 away from the memory gate 211.

[0224] The first doped region can reduce the contact resistance between the read channel layer 230 and the common bit line 300. The second doped region can reduce the contact resistance between the read channel layer 230 and the read source line 400.

[0225] In one embodiment, the same read source line 400 has symmetrically arranged storage cells connected to it on opposite sides in a first direction. In this case, the read source line 400 can be shared by the storage cells on both sides, thereby reducing the number of read source lines 400 and increasing storage density.

[0226] In other embodiments, a storage unit connected to the same read source line 400 may be provided only on one side of the read source line 400, and this is not a limitation.

[0227] In one embodiment, the semiconductor structure further includes a substrate 100, a write word line 510a, and a read word line 212a.

[0228] Multiple layers of memory cells are stacked on the substrate 100 and arranged in an array along the first and second directions.

[0229] The write word line 510a extends from above the top layer memory cell to the substrate 100 and includes write gates 510 of a plurality of write transistors 500 arranged along the vertical substrate.

[0230] The read word line 212a extends from above the top-level memory cell to the substrate 100 and includes a control gate 212 of a plurality of read transistors arranged along the vertical substrate.

[0231] Meanwhile, the read source line 400 extends from above the top layer memory cell to the substrate 100 and along the second direction, connecting the read channel layer 230 of a plurality of read transistors arranged vertically to the substrate and along the second direction.

[0232] In one embodiment, the semiconductor structure further includes multiple layers of spaced-apart isolation layers 610. The memory cells and common bit lines 300 are located between adjacent isolation layers 610. The isolation layers 610 isolate adjacent memory cells.

[0233] Meanwhile, the semiconductor structure also includes a first filling dielectric layer 810, a second filling dielectric layer 820, a third filling dielectric layer 830, a fourth filling dielectric layer 840, and a fifth filling dielectric layer 850, which serve as insulation and isolation.

[0234] The first filler medium layer 810 is located in a first direction between the control gate 212 and the memory gate 211, and between the read word line 212a and the read source line 400. Furthermore, the first filler medium layer 810 extends from above the top memory cell to the substrate 100. The first filler medium layer 810 can insulate and isolate the control gate 212 from the memory gates 211 on both sides and the read source line 400.

[0235] The second filler medium layer 820 is located on the side of the read channel layer 230 away from the read gate medium layer 220 in the second direction. Furthermore, the second filler medium layer 820 extends from above the top memory cell to the substrate 100. The second filler medium layer 820 can isolate the read channel layer 230 from the outside.

[0236] The third filling dielectric layer 830 is located between the adjacent isolation layers 610 and between the common bit line 300 and the memory gate 211 in the first direction, thereby insulating and isolating the common bit line 300 from the memory gate 211.

[0237] The fourth filler dielectric layer 840 is located on the side of the common bit line 300 away from the memory cell in the first direction. Furthermore, the fourth filler dielectric layer 840 extends from above the top memory cell to the substrate 100. The fourth filler dielectric layer 840 can insulate and isolate the common bit line 300.

[0238] The fifth filling dielectric layer 850 is located between the write channel layer 530 and the isolation layer 610, thereby isolating the two.

[0239] The materials of the isolation layer 610, the first filling dielectric layer 810, the second filling dielectric layer 820, the third filling dielectric layer 830, the fourth filling dielectric layer 840, and the fifth filling dielectric layer 850 can be selected from SiO2, other low K materials, HfOx, or other oxides or nitrides.

[0240] In one embodiment, an electronic device is also provided, comprising the semiconductor structure described in any of the foregoing embodiments, or a semiconductor structure formed according to the semiconductor device fabrication method described in any of the foregoing embodiments. The electronic device may be a storage device, smartphone, computer, tablet computer, artificial intelligence device, wearable device, or power bank, etc. The storage device may include memory in a computer, etc., and is not limited thereto.

[0241] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0242] The embodiments described above are merely illustrative of several implementations of this disclosure, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this disclosure, and these all fall within the scope of protection of this disclosure. Therefore, the scope of protection of this patent should be determined by the appended claims.

Claims

A semiconductor structure, comprising: A common bit line and a read source line, wherein the common bit line and the read source line are arranged along a first direction and both extend along a second direction, the second direction intersecting the first direction; A storage unit, located between the common bit line and the read source line in the first direction, the storage unit includes: A write transistor includes a write gate, a write gate dielectric layer, and a write channel layer, wherein the write gate dielectric layer surrounds the write gate, the write channel layer surrounds the write gate dielectric layer, and is connected to the common bit line in the first direction; A read transistor includes a read gate, a read gate dielectric layer, and a read channel layer. The read gate includes a memory gate and a control gate. The memory gate is located on the side of the write transistor away from the common bit line in a first direction and is connected to the write channel layer in the first direction. The control gate is located between the memory gate and the read source line in the first direction and is insulated from and spaced apart from both the memory gate and the read source line. The read gate dielectric layer is located between the common bit line and the read source line in the first direction and connects the control gate and the memory gate in a second direction. The read channel layer is located on the side of the read gate dielectric layer away from the read gate in the second direction, and the common bit line and the read source line are respectively connected to both sides of the read channel layer in the first direction. The semiconductor structure according to claim 1, wherein, The read transistor includes a junctionless N-type transistor. The semiconductor structure according to claim 1, wherein, The storage gate is U-shaped and surrounds the write channel layer. The semiconductor structure according to claim 1, wherein, The read gate has a read gate dielectric layer and a read channel layer connected to both sides in the second direction. The semiconductor structure according to claim 1, wherein, The read channel layer is U-shaped and includes a first doped region, a second doped region, and a channel region located between the two. The first doped region is connected to the common bit line, the second doped region is connected to the read source line, and the channel region is located on the surface of the read gate dielectric layer away from the memory gate. The semiconductor structure according to claim 1, wherein, The same read source line has symmetrically arranged storage cells connected to it on opposite sides in the first direction. The semiconductor structure according to claim 1, wherein, The semiconductor structure also includes: A substrate on which multiple layers of the memory cells are stacked and arranged in an array along the first direction and the second direction; A write word line extends from above the top layer of the memory cell to the substrate and includes the write gates of a plurality of write transistors arranged perpendicular to the substrate; A read word line extends from above the top-level memory cell to the substrate and includes the control gate of a plurality of read transistors arranged perpendicular to the substrate; The read source line extends from above the top layer of the memory cell to the substrate and along the second direction, connecting the read channel layer of the plurality of read transistors arranged perpendicular to the substrate and along the second direction. The semiconductor structure according to claim 7, wherein, The semiconductor structure also includes: Multiple isolation layers are stacked at intervals, and the memory cell and the common bit line are located between two adjacent isolation layers; A first filling medium layer is located in the first direction between the control gate and the memory gate and between the read word line and the read source line, and extends from above the top memory cell to the substrate; The second filling medium layer is located on the side of the read channel layer away from the read gate medium layer in the second direction, and extends from above the top memory cell to the substrate; The third filling medium layer is located between the two adjacent isolation layers and is located between the common bit line and the memory gate in the first direction; A fourth filling medium layer is located on the side of the common bit line away from the memory cell in the first direction, and extends from above the top memory cell to the substrate; The fifth filling medium layer is located between the write channel layer and the isolation layer. A method for fabricating a semiconductor structure, comprising: Provide a base; A read transistor is formed on the substrate. The read transistor includes a read gate, a read gate dielectric layer, and a read channel layer. The read gate includes a memory gate and a control gate arranged in a first direction and separated by an insulating distance. The read gate dielectric layer connects the control gate and the memory gate in a second direction. The read channel layer is located on the side of the read gate dielectric layer away from the read gate in the second direction. A common bit line is formed on the side of the storage gate away from the control gate in the first direction, and a read source line is formed on the side of the control gate away from the storage gate in the first direction, and both the common bit line and the read source line extend along the second direction, and the common bit line and the read source line are respectively connected to the two sides of the read channel layer in the first direction. A write transistor is formed between the common bit line and the memory gate. The write transistor includes a write gate, a write gate dielectric layer, and a write channel layer. The write gate dielectric layer surrounds the write gate, and the write channel layer surrounds the write gate dielectric layer. The common bit line and the memory gate are respectively connected on both sides in the first direction. The method for preparing a semiconductor structure according to claim 9, wherein, Before forming the read transistor on the substrate, the process includes: A stacked layer is formed on the substrate, the stacked layer comprising alternately stacked isolation layers and a first sacrificial layer; A pseudo-source line and a pseudo-transistor layer are formed through the stacked layers along a first direction. The pseudo-source line extends along a second direction. The pseudo-transistor layer is located on at least one side of the pseudo-source line in the first direction and protrudes towards the first sacrificial layer between adjacent isolation layers. The pseudo-transistor layer includes a read pseudo-transistor portion and a write pseudo-transistor portion that are spaced apart. The read pseudo-transistor portion is located on at least one side of the write pseudo-transistor portion in the second direction. The protruding portion of the read pseudo-transistor portion connects to the pseudo-source line in the first direction. The write pseudo-transistor portion is spaced apart from the pseudo-source line. The method for preparing a semiconductor structure according to claim 10, wherein, The formation of a read transistor on the substrate includes: A second read via and a second read lateral via are formed between the write pseudo tube portion and the pseudo source line. The second read via penetrates the stacked layer and exposes the pseudo source line and the protruding portion of the read pseudo tube portion on its sidewall. The second read lateral via is formed by lateral etching of the first sacrificial layer located between the second read via and the write pseudo tube portion in the first direction, and the second read lateral via is U-shaped and surrounds the read pseudo tube portion. A storage gate is formed in the second read side hole, and a read word line and a first filling dielectric layer are formed in the second read through hole. The read word line includes the control gate of a plurality of read transistors arranged perpendicular to the substrate. The first filling dielectric layer is located on both sides of the read word line in the first direction. Remove the read pseudo tube portion to form a first read through hole and a first read side hole. A read gate medium initial layer and a read channel layer are formed in the first read side hole, and a second filling medium layer is formed in the first read through hole. The read gate medium initial layer is formed at least on the hole wall surface of the first read side hole opposite to the first read through hole, and the read channel layer is formed on the surface of the read gate medium initial layer. The portion of the initial layer of the read gate medium located on the side of the read channel layer away from the second fill medium layer in the first direction is removed to form the read gate medium layer. The method for preparing a semiconductor structure according to claim 11, wherein, A dummy source line and a dummy transistor layer arranged along a first direction are formed through the stacked layers, including: The stacked layer is etched toward the substrate to form a source trench extending along the second direction; A pseudo-source line is formed within the source line trench; The stacked layer is etched toward the substrate to form a first read via and a write via; The first sacrificial layer is etched from the first read via and the write via to form the first read side via and the write side via; A pseudo transistor layer is formed within the first read side hole, the first read through hole, the write side hole, and the write through hole. The method for preparing a semiconductor structure according to claim 12, wherein, Before etching the stacked layer toward the substrate to form the first read via and write via, the method further includes: The stacked layer is etched toward the substrate to form a second read via that exposes the dummy source line; A second sacrificial layer is formed within the second read hole; Furthermore, when the first sacrificial layer is etched from the first read via to form the first read side via, the first read side via exposes the second sacrificial layer; The method of forming a second read through hole and a second read side hole between the write pseudo tube and the pseudo source line includes: Remove the second sacrificial layer; The first sacrificial layer is etched laterally from the second read via to form the second read lateral via. The method for preparing a semiconductor structure according to claim 11, wherein, Before removing the false reading tube portion and forming the first read through hole and the first read side hole, the process includes: A bit line slot is formed on the side of the write pseudo-tube portion away from the memory gate in the first direction. The bit line slot includes a bit line trench and a bit line lateral slot. The bit line trench penetrates the stacked layer, and the bit line lateral slot is formed by lateral etching of the first sacrificial layer and exposes the write pseudo-tube portion, the read pseudo-tube portion and the memory gate. A third filling medium layer is formed in the slot on the side of the bit line, and the third filling medium layer covers the memory gate; A pseudo bit line layer is formed in the remaining space of the bit line slot, and the pseudo bit line layer connects the write pseudo tube section, the read pseudo tube section and the second filling medium layer in the second direction. The method for preparing a semiconductor structure according to claim 14, wherein, The step of removing a portion of the initial read gate dielectric layer located on the side of the read channel layer away from the second fill dielectric layer in the first direction to form a read gate dielectric layer includes: Remove the pseudo bit line layer to form a bit line slot, and remove the pseudo source line to form a source line trench; The read gate dielectric initial layer is etched from the bit line slots and source line trenches to form the read gate dielectric layer. The method for preparing a semiconductor structure according to claim 15, wherein, The step of forming a common bit line spaced apart from the control gate on the side of the storage gate away from the control gate in the first direction, and forming a read source line spaced apart from the control gate on the side of the control gate away from the storage gate in the first direction, includes: A common bit line is formed in the bit line side groove, a fourth filling medium layer is formed in the bit line trench, and a read source line is formed in the source line trench. The method for preparing a semiconductor structure according to claim 11, wherein, The formation of a storage gate within the second read side aperture, and the formation of a read word line and a first filling medium layer within the second read through aperture, includes: A storage gate is formed within the second read side aperture; A first initial filling layer is formed within the second read hole; The first initial filling layer is etched to form a first filling medium layer and a readout line hole, wherein the first filling medium layer is located on both sides of the readout line hole in the first direction; A reading line is formed within the reading line hole. The method for preparing a semiconductor structure according to claim 10, wherein, The formation of a write transistor between the common bit line and the memory gate includes: Remove the pseudo-write tube portion to form a write through hole and a write side hole; A write channel layer and a write gate dielectric layer are formed in the write side hole. The write channel layer is formed on the hole wall surface opposite to the write through hole in the write side hole, and the write gate dielectric layer is formed on the surface of the write channel layer. A fifth filling dielectric layer is formed between the write channel layer and the isolation layer; A write word line is formed within the write via, the write word line including the write gates of a plurality of write transistors arranged along a vertical substrate. An electronic device comprising a semiconductor structure as described in any one of claims 1-8, or a semiconductor structure fabricated according to the method for fabricating a semiconductor structure as described in any one of claims 9-18.

Images