Chip, voltage drop detection method, and electronic device

Abstract

A chip, a voltage drop detection method, and an electronic device, applied to the technical field of chips, and configured to improve the calibration efficiency of a voltage drop detection circuit in a chip and improve voltage drop detection efficiency. A voltage drop detection circuit (410) in the chip comprises: a state machine (411), a signal generation circuit (412), a critical path replication circuit (413), an adjustable delay chain circuit (414), and a timing alarm circuit (415). The critical path replication circuit (413) is used for replicating a critical path in an actual circuit. An output terminal of the signal generation circuit (412) is coupled to an input terminal of the critical path replication circuit (413). An output terminal of the critical path replication circuit (413) is coupled to an input terminal of the adjustable delay chain circuit (414). An output terminal of the adjustable delay chain circuit (414) is coupled to an input terminal of the timing alarm circuit (415). An output terminal of the timing alarm circuit (415) is coupled to an input terminal of the state machine (411). An output terminal of the state machine (411) is coupled to a control terminal of the adjustable delay chain circuit (414).

Description

A chip, a voltage drop detection method, and an electronic device.

[0001] This application claims priority to Chinese Patent Application No. 202410696403.8, filed on May 30, 2024, entitled "A Chip, Voltage Drop Detection Method and Electronic Device", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of chip technology, and in particular to a chip, a voltage drop detection method, and an electronic device. Background Technology

[0003] With the continuous increase in the operating speed of multi-core processors and chips, the transient current inside the chip is relatively large, causing significant voltage fluctuations on the power supply network. To ensure the correctness of chip function, the maximum voltage drop in the operating scenario needs to be considered, resulting in a large timing margin and wasted power. To reduce the timing margin, chips typically incorporate an adaptive frequency adjustment system, including voltage drop detection and frequency adjustment. When the internal voltage drop of the chip reaches a threshold, the operating frequency is reduced. However, existing voltage drop detection circuits are relatively complex and have low calibration efficiency during voltage drop detection, thus affecting detection efficiency. Summary of the Invention

[0004] This application provides a chip, a voltage drop detection method, and an electronic device to improve the calibration efficiency of the voltage drop detection circuit in the chip, thereby improving the efficiency of voltage drop detection.

[0005] To achieve the above objectives, the embodiments of this application adopt the following technical solutions:

[0006] In a first aspect, embodiments of this application provide a chip. The chip includes: a state machine, a signal generation circuit, a critical path replication circuit, an adjustable delay chain circuit, and a timing alarm circuit. The critical path replication circuit is a timing replication circuit for the critical path in the actual circuit within the chip. The output terminal of the signal generation circuit is coupled to the input terminal of the critical path replication circuit. The output terminal of the critical path replication circuit is coupled to the input terminal of the adjustable delay chain circuit. The output terminal of the adjustable delay chain circuit is coupled to the input terminal of the timing alarm circuit. The output terminal of the timing alarm circuit is coupled to the input terminal of the state machine. The output terminal of the state machine is coupled to the control terminal of the adjustable delay chain circuit.

[0007] When performing voltage drop detection on a chip, the voltage drop detection circuit within the chip needs to be calibrated first. Traditional calibration methods require manual calibration by operators, resulting in low detection efficiency throughout the entire voltage drop detection process. The state machine, signal generation circuit, critical path replication circuit, adjustable delay chain circuit, and timing alarm circuit in the chip provided in this application form a closed-loop voltage drop detection circuit. During voltage drop detection, this voltage drop detection circuit needs to be calibrated first. Through the aforementioned voltage drop detection circuit, the state machine can first output a configuration signal to the adjustable delay chain circuit to adjust the initial length of the delay chain in the adjustable delay chain circuit, thereby adjusting the initial delay of the circuit through the adjustable delay chain circuit. The signal output from the signal generation circuit, after being transmitted through the critical path replication circuit and the adjustable delay chain circuit, can be processed by the timing alarm circuit and output a timing alarm signal. The state machine can further adjust the configuration signal output to the control terminal of the adjustable delay chain circuit according to the timing alarm signal to increase or decrease the length of the delay chain in the adjustable delay chain circuit, achieving closed-loop calibration of the voltage drop detection circuit. During normal chip operation, the configuration signal output to the control terminal of the adjustable delay chain circuit can be adjusted via the state machine, thereby increasing or decreasing the length of the delay chain in the adjustable delay chain circuit to achieve voltage drop detection within a certain range. Based on this, manual calibration of the voltage drop detection circuit is unnecessary, improving the efficiency of voltage drop detection.

[0008] In one possible implementation, the critical path replication circuit includes multiple cascaded digital standard units. Each of these digital standard units has a different voltage threshold. The digital standard units include at least one of NAND gates, NOR gates, NOT gates, or transmission gates. By using digital standard units with different voltage thresholds to form the critical path replication circuit, the influence of different processes, voltages, and temperatures (PVT) on the timing of the digital standard units can be avoided, achieving more accurate voltage drop detection.

[0009] In one possible implementation, the chip further includes a register; the output of the state machine is also coupled to the register. The register stores the configuration signals output by the state machine to the control terminal of the adjustable delay chain circuit. This method facilitates obtaining the configuration signals input to the control terminal of the adjustable delay chain circuit, enabling the querying of the delay chain length.

[0010] In one possible implementation, the chip further includes an accumulator. The input of the accumulator is coupled to the output of the timing alarm circuit, and the output of the accumulator is coupled to a register. The register is also used to store the accumulated value of the timing alarm signal output by the timing alarm circuit. In this way, the accumulator can calculate the number of timing alarm signals over a period of time to obtain the operating status of the voltage drop detection circuit.

[0011] In one possible implementation, the timing alarm circuit includes a flip-flop, a latch, and an XOR circuit. The inputs of both the flip-flop and the latch are coupled to the output of the adjustable delay chain circuit. The first input of the XOR circuit is coupled to the output of the flip-flop, the second input to the latch, and the output of the XOR circuit to the input of the state machine. In this manner, the output signal of the adjustable delay chain circuit can generate a timing alarm signal via the XOR circuit after passing through the flip-flop and latch. When a timing violation occurs, the timing alarm signal is high, indicating a low voltage and poor timing. At this point, the current voltage drop value can be obtained based on the mapping relationship between voltage drop and timing.

[0012] In one possible implementation, the adjustable delay chain circuit includes a multiplexer and multiple cascaded delay circuits. The input of the first-stage delay circuit is coupled to the output of the critical path replication circuit, and the outputs of the multiple delay circuits are correspondingly coupled to multiple selection terminals of the multiplexer. The control terminal of the multiplexer is coupled to the output of the state machine. The output of the multiplexer is coupled to the input of the timing alarm circuit. In this way, the delay of the signals transmitted in the circuit can be controlled by multiple cascaded delay circuits.

[0013] In one possible implementation, the chip further includes a frequency adjustment circuit. This frequency adjustment circuit is coupled to the state machine and is used to adjust the chip's operating frequency. In this way, when the voltage drop of the critical path replication circuit reaches a threshold, the operating frequency of the actual circuit corresponding to the critical path replication circuit can be reduced.

[0014] Secondly, a voltage drop detection method is provided, which is applied to a chip. The chip includes a state machine, a signal generation circuit, a critical path replication circuit, an adjustable delay chain circuit, and a timing alarm circuit. The critical path replication circuit is a timing replication circuit of the critical path in the actual circuit within the chip. The output terminal of the signal generation circuit is coupled to the input terminal of the critical path replication circuit. The output terminal of the critical path replication circuit is coupled to the input terminal of the adjustable delay chain circuit. The output terminal of the adjustable delay chain circuit is coupled to the input terminal of the timing alarm circuit. The output terminal of the timing alarm circuit is coupled to the input terminal of the state machine. The output terminal of the state machine is coupled to the control terminal of the adjustable delay chain circuit. During voltage drop detection, the method includes: the signal generation circuit receiving an input clock signal and outputting a signal to the critical path replication circuit; the timing alarm circuit receiving a delayed signal from the signal output by the signal generation circuit after transmission through the critical path replication circuit and the adjustable delay chain circuit, and outputting a timing alarm signal; and the state machine adjusting the delay chain length of the adjustable delay chain circuit according to the timing alarm signal.

[0015] In one possible implementation, when the critical path replication circuit is operating at the lowest operating voltage, the method further includes: in response to the timing alarm signal output by the timing alarm circuit being low, the state machine increases the delay chain length of the adjustable delay chain circuit, and when the timing alarm signal output by the timing alarm circuit is high, the configuration signal of the previous adjustable delay chain circuit is saved.

[0016] In one possible implementation, when the critical path replication circuit is operating at the lowest operating voltage, the method further includes: in response to the timing alarm signal output by the timing alarm circuit being high, the state machine reduces the delay chain length of the adjustable delay chain circuit, and saves the configuration signal of the current adjustable delay chain circuit when the timing alarm signal output by the timing alarm circuit is low.

[0017] Thirdly, an electronic device is provided. This electronic device includes a circuit board and a chip as described in any of the possible implementations of the first aspect above. The chip is disposed on the circuit board.

[0018] The technical principles and beneficial effects of the second and third aspects mentioned above can be referred to the relevant description of the first aspect mentioned above, and will not be repeated here. Attached Figure Description

[0019] Figure 1 is a schematic diagram of the structure of a chip provided in an embodiment of this application;

[0020] Figure 2 is a schematic diagram of a voltage drop detection circuit provided in an embodiment of this application;

[0021] Figure 3 is a schematic diagram of another voltage drop detection circuit provided in an embodiment of this application;

[0022] Figure 4 is a schematic diagram of the structure of a chip provided in an embodiment of this application;

[0023] Figure 5 is a schematic diagram of a calibration method for a voltage drop detection circuit provided in an embodiment of this application;

[0024] Figure 6 is a schematic diagram of a critical path replication circuit provided in an embodiment of this application;

[0025] Figure 7 is a schematic diagram of another critical path replication circuit provided in an embodiment of this application;

[0026] Figure 8 is a schematic diagram of a timing alarm circuit provided in an embodiment of this application;

[0027] Figure 9 is a schematic diagram of an adjustable delay chain circuit provided in an embodiment of this application;

[0028] Figure 10 is a schematic diagram of another adjustable delay chain circuit provided in an embodiment of this application;

[0029] Figure 11 is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0030] The technical solutions in the embodiments of this application will now be described with reference to the accompanying drawings.

[0031] To facilitate a clear description of the technical solutions in the embodiments of this application, the terms "first" and "second" are used to distinguish identical or similar items with substantially the same function and effect. Those skilled in the art will understand that the terms "first" and "second" do not limit the quantity or execution order, nor do they necessarily imply differences. Furthermore, in the embodiments of this application, the terms "exemplary" or "for example" are used to indicate examples, illustrations, or explanations. Any embodiment or design scheme described as "exemplary" or "for example" in the embodiments of this application should not be construed as superior or more advantageous than other embodiments or design schemes. Specifically, the use of terms such as "exemplary" or "for example" is intended to present related concepts in a concrete manner for ease of understanding. In the description of the embodiments of this application, unless otherwise stated, "multiple" means two or more. For example, multiple processors means two or more processors.

[0032] In describing some embodiments, the terms "coupled" and "connected," and their derivative expressions, may be used. For example, the term "connected" may be used in describing some embodiments to indicate that two or more components have direct physical contact or point contact with each other. Similarly, the term "coupled" may be used in describing some embodiments to indicate that two or more components have direct physical contact or electrical contact, or it may refer to two or more components that do not have direct contact with each other but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content of this document.

[0033] In addition, for ease of understanding, the technical terms involved in the embodiments of this application will be introduced below.

[0034] Critical path: The critical path refers to the circuit that is frequently called and has a large delay or a high probability of unexpected events.

[0035] Digital standard unit: A digital standard unit is a set of pre-designed digital chip circuits. They are usually composed of some basic gate circuits, such as AND gate, OR gate, NOT gate, NAND gate, NOR gate, transmission gate, and other logic gates.

[0036] Critical path replication circuit: The critical path replication circuit is a timing replication circuit of the critical path in the actual circuit within the chip.

[0037] The present application will now be described in detail with reference to the accompanying drawings and embodiments:

[0038] All devices in a chip receive their required supply voltage through a power grid. During current transmission, due to the resistance of the power grid material, current flows through the power grid, causing energy consumption and resulting in voltage drops for each device, known as IRdrop. This IRdrop reduces the voltage received by each device. IRdrop in each device reduces its switching speed and noise margin, and can even lead to logic errors.

[0039] As the integration density and operating frequency of VLSI chips continue to increase, voltage drop has a growing impact on chip operation. To ensure the correctness of chip functionality, the maximum voltage drop in the operating scenario needs to be considered, resulting in a large margin that needs to be reserved, leading to wasted power consumption. As shown in Figure 1, to reduce the reserved timing margin, a voltage drop detection circuit 110 and a frequency adjustment circuit 120 are typically added to chip 100. The frequency adjustment circuit 120 is coupled to the voltage drop detection circuit 110. The voltage drop detection circuit 110 is used to detect the voltage drop of the critical path in the chip. The frequency adjustment circuit 120 is used to adjust the chip's operating frequency. For example, when the voltage drop detection circuit 110 detects that the voltage drop of the critical path in the chip reaches a threshold, the frequency adjustment circuit 120 can reduce the chip's operating frequency.

[0040] Currently, various methods can be used to detect voltage drop in critical paths within a chip. Figure 2 shows a schematic diagram of a voltage drop detection circuit. As shown in Figure 2, the voltage drop detection circuit 200 can include a time-to-digital converter module 210, a bubble suppression and decoding module 220, an adjustable delay module 230, and an H-type clock tree module 240. The time-to-digital converter module 210, the bubble suppression and decoding module 220, the adjustable delay module 230, and the H-type clock tree module 240 can all be constructed using standard digital cells. Their working principle is as follows: the adjustable delay module 230 adjusts the phase of the input clock signal to form the input measurement signal for the time-to-digital converter module 210. The H-type clock tree module 240 reduces the clock offset of the input clock signal to form the input clock signal for the time-to-digital converter module 210. The time-to-digital converter module 210 encodes the chip's power supply voltage to form a digital code value. Bubble suppression and decoding module 220 is used to eliminate bubble problems caused by metastable sampling of the trigger, forming a decoded value that represents the voltage drop of the circuit. However, the above scheme uses an open-loop method to adjust the delay chain length of the adjustable delay module 230, which requires manual calibration during testing, resulting in low detection efficiency. In addition, the above scheme does not take into account that the delay of digital standard units with different voltage thresholds will vary under different processes, voltages, and temperatures (PVT), thereby reducing the accuracy of detection.

[0041] Figure 3 shows a schematic diagram of another voltage drop detection circuit. As shown in Figure 3, the voltage drop detection circuit 300 includes multiple delay chain circuits 310, a floating-point arithmetic unit 320, and an adder 330. The input signal can be delayed by the multiple delay chain circuits 310 and then output to the floating-point arithmetic unit 320. The floating-point arithmetic unit 320 can sample the floating-point values ​​of each delay chain circuit 310 to determine the logic function of each delay chain circuit 310 completed within one clock cycle. The adder 330 sums the number of delay chain circuits 310 that have passed through each clock cycle, and the resulting output signal can be decoded to represent the circuit voltage drop value. However, the above scheme requires a large number of delay chain circuits 310 and floating-point arithmetic units 320, resulting in a large area and high cost. Furthermore, the voltage drop detection circuit 300 requires the floating-point arithmetic unit 320 to calculate the outputs of multiple delay chain circuits 310, reducing detection efficiency. In addition, the voltage drop detection circuit 300 described above does not take into account that the delay of the digital standard unit with different voltage thresholds (VT) will be different under different PVT, thereby reducing the accuracy of detection.

[0042] To address the aforementioned problems, as shown in Figure 4, this application provides a chip 400, which includes a voltage drop detection circuit 410 and a frequency adjustment circuit 420. The voltage drop detection circuit 410 includes a state machine 411, a signal generation circuit 412, a critical path replication circuit 413, an adjustable delay chain circuit 414, and a timing alarm circuit 415. The critical path replication circuit 413 is a timing replication circuit for the critical path in the actual circuit within the chip. The output of the signal generation circuit 412 is coupled to the input of the critical path replication circuit 413. The output of the critical path replication circuit 413 is coupled to the input of the adjustable delay chain circuit 414, and the output of the adjustable delay chain circuit 414 is coupled to the input of the timing alarm circuit 415. The output of the timing alarm circuit 415 is coupled to the input of the state machine 411, and the output of the state machine 411 is coupled to the control terminal of the adjustable delay chain circuit 414. The frequency adjustment circuit 420 is coupled to the state machine 411 in the voltage drop detection circuit 410.

[0043] In practical designs, the delay of the voltage drop detection circuit 410 described above will differ from the delay of the critical path in the actual circuit. Therefore, the voltage drop detection circuit 410 needs to be calibrated before voltage drop detection. Current calibration methods typically require manual calibration by operators at minimum working voltage, resulting in low calibration efficiency and thus reducing the efficiency of voltage drop detection.

[0044] In one possible implementation, as shown in Figure 4, the chip 400 further includes a register 416. The output of the state machine 411 is also coupled to the register 416, which stores the configuration signal output by the state machine 411 to the control terminal of the adjustable delay chain circuit 414. The current timing of the voltage drop detection circuit 410 can be obtained by reading the signal value in the register 416.

[0045] In one possible implementation, as shown in Figure 4, the chip 400 further includes an accumulator 417, the input of which is coupled to the output of the timing alarm circuit 415, and the output of which is coupled to a register 416. The register 416 is also used to store the accumulated value of the timing alarm signal output by the timing alarm circuit 415.

[0046] In the above manner, state machine 411 can process timing alarm signals and output configuration signals to adjustable delay chain circuit 414, thereby achieving closed-loop control of voltage drop detection circuit 410. Accumulator 417 is responsible for accumulating and calculating the number of timing alarm signals over a period of time. Register 416 stores the configuration signals of adjustable delay chain circuit 414 issued by state machine 411, the accumulated values ​​of timing alarm signals output by accumulator 417, etc. Based on this, the configuration signals of adjustable delay chain circuit 414 and the accumulated values ​​of timing alarm signals can be read from register 416 through software addressing, so as to monitor the operating status of voltage drop detection circuit 410 through the configuration signals of adjustable delay chain circuit 414 and the accumulated values ​​of timing alarm signals. In the above implementation process, register 416 and accumulator 417 can be selectively set, and this embodiment does not impose specific limitations on this.

[0047] It is understood that the above-mentioned register 416 and accumulator 417 can also be selectively set, and this application embodiment does not impose specific restrictions on this.

[0048] Figure 5 is a schematic diagram of a calibration method for a voltage drop detection circuit provided in an embodiment of this application. Through the voltage drop detection circuit 410 provided in this embodiment, the state machine 411, signal generation circuit 412, critical path replication circuit 413, adjustable delay chain circuit 414, and timing alarm circuit 415 can form a closed loop. Referring to Figure 4, as shown in Figure 5, when calibration of the voltage drop detection circuit 410 is required, it can be calibrated at the lowest operating voltage. After the voltage drop detection circuit 410 is powered on, the state machine 411 can set the delay chain length of the adjustable delay chain circuit 414 according to the initial configuration signal. After the signal generation circuit 412 is enabled by the input enable signal, it can periodically output a test signal according to the input clock signal. This test signal, after being transmitted through the critical path replication circuit 413 and the adjustable delay chain circuit 414, can be input to the timing alarm circuit 415. If the timing alarm signal output by the timing alarm circuit 415 is high at the lowest operating voltage, it indicates that the delay of the critical path replication circuit 413 and the adjustable delay chain circuit 414 is greater than the delay of the critical path in the actual circuit. In this case, the configuration signal of the adjustable delay chain circuit 414 can be adjusted via the state machine 411 to reduce the length of the delay chain in the adjustable delay chain circuit until the timing alarm signal output by the timing alarm circuit 415 is low, at which point the current configuration signal of the adjustable delay chain circuit 414 is saved. Conversely, if the timing alarm signal output by the timing alarm circuit 415 is low at the lowest operating voltage, it indicates that the delay of the critical path replication circuit 413 and the adjustable delay chain circuit 414 is less than the delay of the critical path in the actual circuit. In this case, the configuration signal of the adjustable delay chain circuit 414 can be adjusted via the state machine 411 to increase the length of the delay chain in the adjustable delay chain circuit until the timing alarm signal output by the timing alarm circuit 415 is high, at which point the previous configuration signal of the adjustable delay chain circuit 414 is saved. The above method enables the calibration of the closed-loop controlled voltage drop detection circuit 410, improving calibration efficiency and thus increasing the efficiency of the entire voltage drop detection process.

[0049] Furthermore, when the voltage drop detection circuit 410 completes calibration and enters the normal operating state, the signal generation circuit 412 can generate periodic signals as input signals to the critical path replication circuit 413. At this time, based on the calibrated voltage drop detection circuit 410, the state machine 411 can increase or decrease the delay chain length of the adjustable delay chain circuit 414, thereby achieving voltage drop detection within a certain range.

[0050] In the above implementation process, the critical path replication circuit 413 is the core module of the entire voltage drop detection circuit 410. Its function is to simulate the timing of the critical path in the actual circuit of the chip. The critical path needs to be determined based on the structure of the actual circuit. For example, when determining the critical path in the actual circuit, a suitable path can be selected as a reference, using the worst-case PVT condition as a benchmark, and considering the characteristics of the path's constituent elements, to select a representative critical path. The selected critical path is then simulated to obtain its delay, which serves as a reference for designing the critical path replication circuit 413. Based on this, the critical path replication circuit 413 can be composed of the main digital standard units in the critical path.

[0051] In practical circuits, PVT deviations can cause timing fluctuations between different wafers and at different times within the same wafer, leading to circuit malfunctions. To ensure that the chip operates correctly under all PVT conditions, traditional designs typically reserve sufficient timing margins for the worst-case PVT scenario. However, this approach results in wasted power consumption.

[0052] To address the aforementioned issues, in one possible implementation, the critical path replication circuit 413 provided in this application embodiment may include multiple cascaded digital standard units with different voltage thresholds. The proportion of different VT digital standard units in the critical path replication circuit 413 can be adjusted according to the types of digital standard units in the actual circuit's critical path, ensuring that the critical path replication circuit 413 can effectively characterize the delay of the actual critical path under various PVT conditions. The aforementioned digital standard units include NAND gates, NOR gates, NOT gates, and transmission gates.

[0053] Figure 6 is a schematic diagram of a critical path replication circuit provided in an embodiment of this application. In one example, as shown in Figure 6, the critical path replication circuit 413 provided in this embodiment may include a cascaded first sub-circuit 4131, a second sub-circuit 4132, a third sub-circuit 4133, and a fourth sub-circuit 4134. The first sub-circuit 4131 includes three cascaded NAND gates, which can be divided into a NAND gate A1 with a high voltage threshold (HVT), a NAND gate A2 with a standard voltage threshold (SVT), and a NAND gate A3 with a low voltage threshold (LVT). The second sub-circuit 4132 includes three cascaded NOR gates, which can be divided into a NOR gate B1 with a high voltage threshold (HVT), a NOR gate B2 with a standard voltage threshold (SVT), and a NOR gate B3 with a low voltage threshold (LVT). The third sub-circuit 4133 includes three cascaded NOT gates, which can be classified as NOT gate C1 with a high voltage threshold (HVT), NOT gate C2 with a standard voltage threshold (SVT), and NOT gate C3 with a low voltage threshold (LVT). The fourth sub-circuit 4134 includes three cascaded transmission gates, which can be classified as transmission gate D1 with a high voltage threshold (HVT), transmission gate D2 with a standard voltage threshold (SVT), and transmission gate D3 with a low voltage threshold (LVT).

[0054] In the above implementation process, the specific values ​​of HVT, SVT and LVT can be set according to the actual use environment of the chip, and this application embodiment does not impose specific restrictions on this.

[0055] Figure 7 is a schematic diagram of another critical path replication circuit provided in an embodiment of this application. In one example, as shown in Figure 7, the critical path replication circuit 413 provided in this embodiment may also include a cascaded first sub-circuit 4131, a second sub-circuit 4132, a third sub-circuit 4133, a fourth sub-circuit 4134, and a fifth sub-circuit 4135. The first sub-circuit 4131 includes three cascaded NAND gates, with the two input terminals of each NAND gate coupled to each other to input the same signal. The three NAND gates can be divided into a high voltage threshold (HVT) NAND gate A1, a standard voltage threshold (SVT) NAND gate A2, and a low voltage threshold (LVT) NAND gate A3. The second sub-circuit 4132 includes three cascaded NOR gates, with the two input terminals of each NOR gate coupled to each other to input the same signal. The three NOR gates mentioned above can be categorized as follows: NOR gate B1 with a high voltage threshold (HVT), NOR gate B2 with a standard voltage threshold (SVT), and NOR gate B3 with a low voltage threshold (LVT). The third sub-circuit 4133 includes three cascaded NOT gates, which can be categorized as follows: NOT gate C1 with a high voltage threshold (HVT), NOT gate C2 with a standard voltage threshold (SVT), and NOT gate C3 with a low voltage threshold (LVT). The fourth sub-circuit 4134 includes three cascaded transmission gates, which can be categorized as follows: transmission gate D1 with a high voltage threshold (HVT), transmission gate D2 with a standard voltage threshold (SVT), and transmission gate D3 with a low voltage threshold (LVT). The fifth sub-circuit 4135 includes multiple cascaded OR gates (E1, E2, and E3 in Figure 7), with the two input terminals of each OR gate coupled to receive the same signal. These three OR gates can also be categorized as OR gates with three voltage thresholds: HVT, SVT, and LVT.

[0056] It is understood that the two critical path replication circuits 413 described above are merely exemplary implementations under one scenario provided in this application embodiment. In specific implementations, the types and quantities of digital standard units included in each of the above sub-circuits may also be different. In addition, because the composition of critical paths varies in different chips, the types and quantities of digital standard units in the critical path replication circuit 413 can be set according to the actual composition of the chip, and this application embodiment does not impose specific limitations on this.

[0057] Figure 8 is a schematic diagram of a timing alarm circuit provided in an embodiment of this application. In one possible implementation, referring to Figure 4, as shown in Figure 8, the timing alarm circuit 415 provided in this embodiment includes a flip-flop 4151, a latch 4152, and an XOR circuit 4153. The input terminals of the flip-flop 4151 and the latch 4152 are both coupled to the output terminal of the adjustable delay chain circuit 414. The first input terminal of the XOR circuit 4153 is coupled to the output terminal of the flip-flop 4151, the second input terminal of the XOR circuit 4153 is coupled to the output terminal of the latch 4152, and the output terminal of the XOR circuit 4153 is coupled to the input terminal of the state machine 411. The output signal of the adjustable delay chain circuit 414 can generate a timing alarm signal through the XOR circuit 4153 after passing through the flip-flop 4151 and the latch 4152. In the actual circuit of the chip, there is a definite mapping relationship between the voltage drop of the circuit and the timing. Specifically, the larger the voltage drop of the circuit, the worse the timing of the signal. When a timing violation occurs in the voltage drop detection circuit 410, the timing alarm signal goes high, indicating that the voltage is low, the voltage drop in the circuit is large, and the timing is poor. The current voltage drop value can be determined based on the mapping relationship between voltage drop and timing.

[0058] In the above implementation process, flip-flop 4151 can be either a D flip-flop or a D latch. When calibrating the voltage drop detection circuit 410, the delay signal output by the adjustable delay chain circuit 414 can be output to the D flip-flop and the D latch respectively. If the signal values ​​of the delay signal are the same after passing through the D flip-flop and the D latch, the signal value output by the XOR circuit 4153 is 0. At this time, the timing alarm signal output by the timing alarm circuit 415 is 0. The state machine 411 can modify the configuration signal sent to the control terminal of the multiplexer in the adjustable delay chain circuit 414 to increase the delay chain length of the adjustable delay chain circuit 414. This process is repeated until the timing alarm signal output by the timing alarm circuit is 1. Then, the configuration signal output by the state machine is saved, completing the calibration of the voltage drop detection circuit.

[0059] It is understood that the above-described timing alarm circuit is merely an exemplary implementation provided in this application. In specific implementations, other types of logic circuits capable of achieving the same or similar functions may also be used for the above-described timing alarm circuit, and this application does not impose specific limitations on this.

[0060] Figure 9 is a schematic diagram of an adjustable delay chain circuit provided in an embodiment of this application. In one possible implementation, referring to Figure 4 and as shown in Figure 9, the adjustable delay chain circuit 414 provided in this embodiment includes a multiplexer 4141 and multiple cascaded delay circuits 4142. The output terminal of each delay circuit 4142 is coupled to a corresponding selection terminal of the multiplexer 4141. The control terminal of the multiplexer 4141 is coupled to the output terminal of the state machine 411, and the output terminal of the multiplexer 4141 is coupled to the input terminal of the timing alarm circuit 415.

[0061] In one example, each of the aforementioned delay circuits 4142 may include multiple cascaded inverters. The number of inverters in each delay circuit 4142 is even. Because the number of inverters in each delay circuit 4142 is even, the delay circuit 4142 only increases the transmission delay, and the signal value transmitted by the adjustable delay chain circuit 414 remains unchanged. Based on this, the transmitted signal can be delayed using the delay circuit 4142 composed of inverters, and this circuit structure is simple, reducing the area and cost of the voltage drop detection circuit 410.

[0062] Figure 10 is a schematic diagram of another adjustable delay chain circuit provided in an embodiment of this application. In another example, each of the above-mentioned delay circuits 4142 may also include multiple cascaded logic gates. For example, as shown in Figure 10, each delay circuit 4142 may include multiple cascaded AND gates. The two input terminals of the AND gates are coupled to input the same signal. Based on this, the adjustable delay chain circuit 414 only increases the transmission delay, and the signal value transmitted in the adjustable delay chain circuit 414 does not change. In the above implementation process, the delay chain length of the adjustable delay chain circuit 414 can be set to an intermediate state to leave a certain timing margin for subsequent voltage drop detection.

[0063] It is understood that the delay circuit 4142 in the aforementioned adjustable delay chain circuit 414 can also be implemented using other cascaded logic gates, and this application embodiment does not impose specific limitations on this. Furthermore, the two types of adjustable delay chain circuits 414 described above are merely exemplary implementations provided in this application embodiment. Other types of adjustable delay chain circuits can also be used for the aforementioned adjustable delay chain circuit 414, and this application embodiment does not impose specific limitations on this.

[0064] In one possible implementation, referring to FIG4 and as shown in FIG11, this application embodiment also provides an electronic device 1100, which includes a circuit board 1110 and a chip 400 disposed on the circuit board 1110 as described in any of the possible implementations above. The circuit board 1110 can be any of a printed circuit board (PCB), a flexible printed circuit board (FPC), and a rigid-flex PCB; this application embodiment does not impose specific limitations on this.

[0065] In summary, this application provides a chip, a voltage drop detection method, and an electronic device. The chip forms a closed-loop voltage drop detection circuit through a state machine, a signal generation circuit, a critical path replication circuit, an adjustable delay chain circuit, and a timing alarm circuit. During voltage drop detection, the state machine can output a configuration signal to the adjustable delay chain circuit to adjust the initial length of the delay chain, thereby adjusting the initial delay of the circuit. The test signal output by the signal generation circuit, after being transmitted through the critical path replication circuit and the adjustable delay chain circuit, can be processed by the timing alarm circuit and output a timing alarm signal. The state machine can further adjust the configuration signal output to the control terminal of the adjustable delay chain circuit based on the timing alarm signal to increase or decrease the length of the delay chain, achieving closed-loop calibration of the voltage drop detection circuit. During normal chip operation, the state machine can adjust the configuration signal output to the control terminal of the adjustable delay chain circuit to increase or decrease the length of the delay chain, achieving voltage drop detection within a certain range. Therefore, no manual calibration of the voltage drop detection circuit is required from the operator, which improves the efficiency of voltage drop detection.

[0066] It should be understood that in the various embodiments of this application, the order of the above-mentioned processes does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0067] Those skilled in the art will recognize that the modules and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0068] In the several embodiments provided in this application, it should be understood that the disclosed chips, devices, and components can be implemented in other ways. For example, the device embodiments described above are merely illustrative; for instance, the division of modules is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple modules or components may be combined or integrated into another device, or some features may be ignored or not executed. Furthermore, the displayed or discussed mutual couplings, direct couplings, or communication connections may be through some interfaces; indirect couplings or communication connections between devices or modules may be electrical, mechanical, or other forms.

[0069] The modules described as separate components may or may not be physically separate. The components shown as modules may or may not be physical modules; that is, they may be located on one device or distributed across multiple devices. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0070] In addition, the functional modules in the various embodiments of this application can be integrated into one device, or each module can exist physically separately, or two or more modules can be integrated into one device.

[0071] In the above embodiments, implementation can be achieved, in whole or in part, through software, hardware, firmware, or any combination thereof. When implemented using software programs, implementation can be, in whole or in part, in the form of a computer program product. This computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of this application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium accessible to a computer or a data storage device containing one or more servers, data centers, etc., that can be integrated with the medium. The available media can be magnetic media (e.g., floppy disks, hard disks, magnetic tapes), optical media (e.g., DVDs), or semiconductor media (e.g., solid-state disks, SSDs), etc.

[0072] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A chip, characterized by The chip comprises a state machine, a signal generating circuit, a critical path replication circuit, an adjustable delay chain circuit and a timing alarm circuit; wherein the critical path replication circuit is a timing replication circuit of a critical path in an actual circuit in the chip; an output end of the signal generating circuit is coupled with an input end of the critical path replication circuit; an output end of the critical path replication circuit is coupled with an input end of the adjustable delay chain circuit; an output end of the adjustable delay chain circuit is coupled with an input end of the timing alarm circuit; an output end of the timing alarm circuit is coupled with an input end of the state machine; an output end of the state machine is coupled with a control end of the adjustable delay chain circuit.

2. The chip according to claim 1, characterized in that, The critical path replication circuit comprises a plurality of digital standard units connected in cascade; voltage thresholds of each digital standard unit in the plurality of digital standard units are different; the digital standard unit comprises at least one of an NAND gate, an NOR gate, a NOT gate or a transmission gate.

3. The chip according to claim 1 or 2, characterized in that Further comprising: a register; an output end of the state machine is further coupled with the register; the register is used for storing a signal value output by the state machine to the control end of the adjustable delay chain circuit.

4. The chip according to claim 3, characterized in that Further comprising: an accumulator; an input end of the accumulator is coupled with an output end of the timing alarm circuit; an output end of the accumulator is coupled with the register; the register is further used for storing a timing alarm signal accumulated value output by the timing alarm circuit.

5. The chip according to any one of claims 1 to 4, characterized in that The timing alarm circuit comprises a flip-flop, a latch and an XOR circuit; an input end of the flip-flop and an input end of the latch are both coupled with an output end of the adjustable delay chain circuit; a first input end of the XOR circuit is coupled with an output end of the flip-flop; a second input end of the XOR circuit is coupled with an output end of the latch; an output end of the XOR circuit is coupled with an input end of the state machine.

6. The chip according to any one of claims 1 to 5, characterized in that The adjustable delay chain circuit comprises a multiplexer and a plurality of delay circuits connected in cascade; an input end of a first delay circuit is coupled with an output end of the critical path replication circuit; output ends of the plurality of delay circuits are further coupled with a plurality of selection ends of the multiplexer correspondingly; a control end of the multiplexer is coupled with an output end of the state machine; an output end of the multiplexer is coupled with an input end of the timing alarm circuit.

7. The chip according to any one of claims 1 to 6, characterized in that The chip further comprises a frequency adjusting circuit; the frequency adjusting circuit is coupled with the state machine; the frequency adjusting circuit is used for adjusting a working frequency of the chip.

8. A pressure drop detection method, characterized by, The chip comprises a state machine, a signal generating circuit, a critical path replication circuit, an adjustable delay chain circuit and a timing alarm circuit; the critical path replication circuit is a timing replication circuit of a critical path in an actual circuit in the chip; an output end of the signal generating circuit is coupled with an input end of the critical path replication circuit; an output end of the critical path replication circuit is coupled with an input end of the adjustable delay chain circuit; an output end of the adjustable delay chain circuit is coupled with an input end of the timing alarm circuit; an output end of the timing alarm circuit is coupled with an input end of the state machine; an output end of the state machine is coupled with a control end of the adjustable delay chain circuit; When performing voltage drop detection, the method includes: The signal generation circuit receives the input clock signal and outputs a signal to the critical path replication circuit; The timing alarm circuit receives the delayed signal after the signal output by the signal generation circuit is transmitted through the critical path replication circuit and the adjustable delay chain circuit, and outputs a timing alarm signal. The state machine adjusts the delay chain length of the adjustable delay chain circuit according to the timing alarm signal.

9. The method of claim 8, wherein, When the critical path replication circuit operates at its lowest operating voltage, the method further includes: In response to the timing alarm signal output by the timing alarm circuit being low, the state machine increases the delay chain length of the adjustable delay chain circuit, and saves the configuration signal of the adjustable delay chain circuit from the previous time when the timing alarm signal output by the timing alarm circuit is high.

10. The method according to claim 8 or 9, characterized in that, When the first voltage signal is the minimum operating voltage of the critical path replication circuit, the method further includes: In response to the timing alarm signal output by the timing alarm circuit being high, the state machine reduces the delay chain length of the adjustable delay chain circuit, and saves the current configuration signal of the adjustable delay chain circuit when the timing alarm signal output by the timing alarm circuit is low.

11. An electronic device, comprising: It includes a circuit board and a chip as described in any one of claims 1-7, the chip being disposed on the circuit board.

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