Server clock architecture and configuration method therefor, device, product, and medium

Abstract

The present application relates to the field of servers, and discloses a server clock architecture and a configuration method therefor, a device, a product, and a medium, used for solving the problem that a clock transmission link of a server clock architecture cannot satisfy the clock constraint of a common clock architecture. The server clock architecture comprises a main control assembly, a chipset, a crystal oscillator circuit, and a first-stage clock buffer that are arranged on a server main board, and further comprises a second-stage clock buffer arranged on an external card. The main control assembly is used for adjusting the working mode of the first-stage clock buffer and / or the working mode of the second-stage clock buffer when the current transmission delay time of a clock transmission link does not satisfy a clock constraint corresponding to the server clock architecture, so that the current transmission delay time of the clock transmission link satisfies the clock constraint. The present application enables the clock transmission link of the server clock architecture to satisfy the clock constraint, and allows for peripheral compatibility due to an adaptable peripheral slot.

Description

A server clock architecture, a configuration method, device, product and medium thereof

[0001] Cross-reference to related applications

[0002] The present application claims priority to the Chinese patent application No. 202410683490.3, filed on May 29, 2024, and entitled "A server clock architecture, a configuration method, device, product and medium thereof", the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0003] The present application relates to the field of servers, and in particular to a server clock architecture, a configuration method, device, product and medium thereof. BACKGROUND

[0004] PCIe (Peripheral Component Interconnect express) is the most common peripheral expansion bus standard in computer systems, and the logical unit needs to be driven by a clock for work and data transmission. The physical layer of PCIe and the external reference clock include three clock architectures, namely, a server clock architecture, a source-synchronous clock architecture and an independent clock architecture. Among them, the server clock architecture is the most commonly used clock architecture in PCIe, and it is also a clock architecture supported in the technical iteration of the PCIe bus specification and maintains backward compatibility.

[0005] The inventors realized that, as the functions of the external devices of PCIe become more complex, a computer system using the server clock architecture needs at least two levels of clock buffers to fan out the clock signal to each external device. However, the clock buffer introduces delay and jitter in the clock transmission link, which degrades the quality of the clock signal under the server clock architecture, and the PCIe clock transmission link of the computer system cannot meet the clock constraints of the server clock architecture.

[0006] Therefore, how to provide a solution to the above technical problems is a problem that those skilled in the art need to solve at present. SUMMARY

[0007] The present application provides a server clock architecture, which comprises a main control component, a chip set, a crystal oscillator circuit and a first level clock buffer arranged on a server mainboard, and further comprises a second level clock buffer arranged on an external card, and the server mainboard further comprises a peripheral slot for connecting the external card, wherein:

[0008] The chip set is connected with the first-stage clock buffer through a first transmission line, the first-stage clock buffer is connected with the peripheral slot through a second transmission line, the second-stage clock buffer is connected with the peripheral slot through a third transmission line, the second-stage clock buffer is connected with each end device of the external card, and the crystal oscillator circuit is connected with the first-stage clock buffer or the chip set.

[0009] The master component is configured to adjust the working mode of the first-stage clock buffer and / or the working mode of the second-stage clock buffer when the current transmission delay time of the clock transmission link of the server clock architecture does not satisfy the clock constraint corresponding to the server clock architecture, so that the current transmission delay time of the clock transmission link satisfies the clock constraint.

[0010] The server clock architecture further includes a slave component arranged on the external card.

[0011] The master component is specifically configured to generate a configuration instruction corresponding to a target working mode of the second-stage clock buffer when the current transmission delay time of the clock transmission link of the server clock architecture does not satisfy the clock constraint corresponding to the server clock architecture, so that the current transmission delay time of the clock transmission link satisfies the clock constraint.

[0012] The slave component is configured to adjust the current working mode of the second-stage clock buffer to the target working mode according to the configuration instruction after receiving the configuration instruction.

[0013] The current transmission delay time of the clock transmission link is determined based on a first delay parameter from the input end to the output end of the second-stage clock buffer, and the first delay parameter of the second-stage clock buffer is different in different working modes.

[0014] The chip set is connected with the crystal oscillator circuit.

[0015] The chip set is configured to output a first clock signal according to a signal output by the crystal oscillator circuit.

[0016] The first-stage clock buffer is configured to fan out multiple second clock signals according to the first clock signal.

[0017] The second-stage clock buffer is configured to fan out multiple third clock signals to multiple end devices on the external card according to the second clock signal, so that the multiple end devices all work under the third clock signal.

[0018] The first-stage clock buffer is connected with the crystal oscillator circuit.

[0019] The first-stage clock buffer is configured to fan out multiple fourth clock signals according to a signal output by the crystal oscillator circuit.

[0020] The chip set is configured to work under the fourth clock signal.

[0021] a second level clock buffer for fanning out a plurality of fifth clock signals from the fourth clock signal to the end devices on the add-in card, so that the plurality of end devices all work under the fifth clock signals.

[0022] To solve the above technical problems, the application further provides a configuration method of a server clock architecture, the server clock architecture being the server clock architecture of any one of the above, and the configuration method comprising:

[0023] determining a clock output mode of the server clock architecture; the clock output mode being a first output mode corresponding to a chip set outputting a clock signal in the server clock architecture or a second output mode corresponding to a first level clock buffer outputting a clock signal in the server clock architecture;

[0024] calculating a current transmission delay time of a clock transmission link under the clock output mode; the current transmission delay time being determined based on a first delay parameter from an input end to an output end of a second level clock buffer in the server clock architecture;

[0025] judging whether the current transmission delay time meets a clock constraint of the server clock architecture;

[0026] if not, adjusting a working mode of the first level clock buffer and / or a working mode of the second level clock buffer, so that the current transmission delay time of the clock transmission link under the clock output mode meets the clock constraint; the first delay parameter of the second level clock buffer being different in length corresponding to different working modes.

[0027] The process of calculating the current transmission delay time of the clock transmission link under the clock output mode comprises:

[0028] determining a current delay parameter group corresponding to the clock transmission link under the clock output mode; when the clock output mode is the first output mode, the current delay parameter group is a first delay parameter group, and the first delay parameter group comprises a second delay parameter from an input end to an output end of the first level clock buffer and the first delay parameter from the input end to the output end of the second level clock buffer; when the clock output mode is the second output mode, the current delay parameter group is a second delay parameter group, and the second delay parameter group comprises an output clock skew parameter and the first delay parameter from the input end to the output end of the second level clock buffer;

[0029] calculating the current delay time by using all parameters in the current delay parameter group.

[0030] The server clock architecture comprises a server mainboard, and the server mainboard is provided with a peripheral slot, and the process of determining the current delay parameter group corresponding to the clock transmission link under the clock output mode comprises:

[0031] When the clock output mode is the first output mode, a second delay parameter of an input end to an output end of the first stage clock buffer, a first delay parameter of an input end to an output end of the second stage clock buffer, a third delay parameter of a phase-locked loop in the chipset to an output pin of the chipset, a fourth delay parameter corresponding to a first transmission line between the chipset and the first stage clock buffer, a fifth delay parameter corresponding to a second transmission line between the first stage clock buffer and the peripheral slot, a sixth delay parameter corresponding to a third transmission line between the second stage clock buffer and the peripheral device on the external card, and a seventh delay parameter corresponding to the bus data link are acquired;

[0032] A first delay parameter group is constructed based on the first delay parameter, the second delay parameter, the third delay parameter, the fourth delay parameter, the fifth delay parameter, the sixth delay parameter, and the seventh delay parameter.

[0033] The first delay parameter group is taken as a current delay parameter group corresponding to the clock transmission link in the first output mode.

[0034] The process of calculating the current delay time by using all parameters in the current delay parameter group comprises:

[0035] A first calculation relationship is established based on all parameters in the current delay parameter group.

[0036] The current delay time is calculated by using the first calculation relationship.

[0037] The first calculation relationship is: T1=t delay1 +t clkpcb1 +tclkbuffer1+t clkpcb2 +tclkbuffer2+t clkpcb3 +t data .

[0038] Wherein, T1 is the current delay time, tclkbuffer1 is the first delay parameter, tclkbuffer2 is the second delay parameter, t delay1 is the third delay parameter, t clkpcb1 is the fourth delay parameter, t clkpcb2 is the fifth delay parameter, t clkpcb3 is the sixth delay parameter, and t data is the seventh delay parameter.

[0039] Wherein, the server clock architecture comprises a server mainboard, and the server mainboard is provided with a peripheral slot. The process of determining the current delay parameter group corresponding to the clock transmission link in the clock output mode comprises:

[0040] When the clock output mode is the second output mode, the output clock skew parameter, the second delay parameter between the input end and the output end of the second stage clock buffer, the first line delay parameter corresponding to the second transmission line between the first stage clock buffer and the peripheral slot, the second line delay parameter corresponding to the third transmission line between the first stage clock buffer and the chipset, the third line delay parameter corresponding to the third transmission line between the second stage clock buffer and the external card, the seventh delay parameter corresponding to the bus data link, and the eighth delay parameter corresponding to the clock delay in the chipset are acquired;

[0041] The second delay parameter group is constructed based on the output clock skew parameter, the second delay parameter, the seventh delay parameter, the eighth delay parameter, the first line delay parameter, the second line delay parameter, and the third line delay parameter;

[0042] The second delay parameter group is taken as the current delay parameter group corresponding to the clock transmission link of the second output mode.

[0043] The process of calculating the current delay time by using all the parameters in the current delay parameter group comprises:

[0044] The second calculation relationship corresponding to the chipset as a sending end and the third calculation relationship corresponding to the external card as a sending end are established based on all the parameters in the current delay parameter group;

[0045] The first delay time is calculated by using the second calculation relationship;

[0046] The second delay time is calculated by using the third calculation relationship;

[0047] The maximum value between the first delay time and the second delay time is taken as the current delay time.

[0048] The second calculation relationship is: T a = | (t delay2 + t clkpcb4 + t data ) - (t clkpcb5 + tclkbuffer2 + t clkpcb6 ) | + t clkskew ;

[0049] The first delay time is T a , the eighth delay parameter is t delay2 , the seventh delay parameter is t data , the output clock skew parameter is t clkskew , the second delay parameter is tclkbuffer2, the first line delay parameter is t clkpcb4 , the second line delay parameter is t clkpcb5 , and the third line delay parameter is t clkpcb6 .

[0050] wherein the third calculation relationship is: T b = |(t delay2 + t clkpcb4 ) - (t clkpcb5 + tclkbuffer2 + t clkpcb6 + t data )| + t clkskew ;

[0051] wherein T b is a second delay time, t delay2 is an eighth delay parameter, t data is a seventh delay parameter, t clkskew is an output clock skew parameter, tclkbuffer2 is a second delay parameter, t clkpcb4 is a first line delay parameter, t clkpcb5 is a second line delay parameter, and t clkpcb6 is a third line delay parameter.

[0052] wherein the server clock architecture comprises a server motherboard, after judging whether the current transmission delay time satisfies the clock constraint of the server clock architecture, the configuration method further comprises:

[0053] calculating a time difference value between the current transmission delay time and a constraint time corresponding to the clock constraint of the server clock architecture;

[0054] judging whether the time difference value is less than or equal to a preset difference value;

[0055] if yes, adjusting the position of the first-stage clock buffer on the server motherboard, so that the time difference value is greater than the preset difference value.

[0056] wherein the process of calculating the current transmission delay time of the clock transmission link in the clock output mode comprises:

[0057] calculating the current transmission delay time of the clock transmission link in the clock output mode and when the working mode of the first-stage clock buffer and the working mode of the second-stage clock buffer are both bypass modes.

[0058] wherein the process of adjusting the working mode of the first-stage clock buffer and / or the working mode of the second-stage clock buffer, so that the current transmission delay time of the clock transmission link in the clock output mode satisfies the clock constraint, comprises:

[0059] determining any one of the first-stage clock buffer and the second-stage clock buffer as a first adjustment buffer, and the other as a second adjustment buffer;

[0060] switching the working mode of the first adjustment buffer from the bypass mode to the phase-locked loop mode.

[0061] calculating the current transmission delay time of the clock transmission link when the clock output mode and the working mode of the first adjustment buffer and the working mode of the second adjustment buffer are the phase-locked loop mode;

[0062] judging whether the current transmission delay time meets the clock constraint of the server clock architecture;

[0063] if yes, determining that the server clock architecture configuration is completed;

[0064] if no, switching the working mode of the second adjustment buffer from the bypass mode to the phase-locked loop mode;

[0065] calculating the current transmission delay time of the clock transmission link when the clock output mode and the working mode of the first adjustment buffer and the working mode of the second adjustment buffer are the phase-locked loop mode;

[0066] judging whether the current transmission delay time meets the clock constraint of the server clock architecture;

[0067] if yes, determining that the server clock architecture configuration is completed;

[0068] if no, prompting configuration error information.

[0069] wherein the process of determining any one of the first-stage clock buffer and the second-stage clock buffer as the first adjustment buffer and the other as the second adjustment buffer comprises:

[0070] determining the second-stage clock buffer as the first adjustment buffer and the first-stage clock buffer as the second adjustment buffer.

[0071] To solve the above technical problems, the present application further provides a computer readable instruction product comprising computer readable instructions, which, when executed by a processor, implement the steps of the configuration method of the server clock architecture according to any one of the above.

[0072] To solve the above technical problems, the present application further provides an electronic device comprising:

[0073] a memory for storing computer readable instructions;

[0074] a processor for implementing the steps of the configuration method of the server clock architecture according to any one of the above when executing the computer readable instructions.

[0075] To solve the above technical problems, the present application further provides a computer readable storage medium, which stores computer readable instructions, and the computer readable instructions, when executed by a processor, implement the steps of the configuration method of the server clock architecture according to any one of the above. Attached Figure Description

[0076] To more clearly illustrate the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0077] Figure 1 is a schematic diagram of the structure of a first server clock architecture provided by one or more embodiments of this application;

[0078] Figure 2 is a schematic diagram of the second server clock architecture provided by one or more embodiments of this application;

[0079] Figure 3 is a schematic diagram of a third server clock architecture provided by one or more embodiments of this application;

[0080] Figure 4 is a flowchart of the steps of a server clock architecture configuration method provided by one or more embodiments of this application;

[0081] Figure 5 is a schematic diagram of a clock transmission link under a clock output mode provided by one or more embodiments of this application;

[0082] Figure 6 is a schematic diagram of a clock transmission link under another clock output mode provided by one or more embodiments of this application;

[0083] Figure 7 is a schematic diagram of the configuration system of a server clock architecture provided by one or more embodiments of this application;

[0084] Figure 8 is a schematic diagram of the structure of an electronic device provided by one or more embodiments of this application;

[0085] Figure 9 is a schematic diagram of the structure of a computer-readable storage medium provided in one or more embodiments of this application. Detailed Implementation

[0086] The core of this application is to provide a server clock architecture and its configuration method, device, product and medium, which enables the clock transmission link of the server clock architecture to meet clock constraints, while also having peripheral compatibility that adapts to peripheral slots.

[0087] In order to make the purposes, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the scope of protection of the present application.

[0088] In a first aspect, referring to FIG. 1, FIG. 1 is a structural schematic diagram of a first server clock architecture provided by the present application, and the server clock architecture comprises:

[0089] The main control component 01, the chip set 02, the crystal oscillator circuit 03 and the first-level clock buffer 04 are arranged on a server mainboard, and further comprising a second-level clock buffer 05 arranged on an external card, and the server mainboard further comprises a peripheral slot for connecting the external card, wherein:

[0090] The chip set 02 and the first-level clock buffer 04 are connected through a first transmission line, the first-level clock buffer and the peripheral slot are connected through a second transmission line, the second-level clock buffer 05 and the peripheral slot are connected through a third transmission line, the second-level clock buffer 05 is connected with each end device of the external card, and the crystal oscillator circuit 03 is connected with the first-level clock buffer 04 or the chip set 02;

[0091] The main control component 01 is configured to adjust the working mode of the first-level clock buffer 04 and / or the working mode of the second-level clock buffer 05 when the current transmission delay time of the clock transmission link does not meet the clock constraint corresponding to the server clock architecture, so that the current transmission delay time of the clock transmission link meets the clock constraint.

[0092] The server clock architecture provided by the application comprises a master component, a chipset, a crystal oscillator circuit and a first-stage clock buffer on a server mainboard, and further comprises a second-stage clock buffer arranged on an external card, so that each terminal device on the external card can work under the same clock signal through the two-stage clock buffers, and if the current transmission delay time of the clock transmission link does not meet the clock constraint of the server clock architecture, considering that the internal clock delays of the first-stage clock buffer and the second-stage clock buffer are different in different working modes, the application adjusts the working mode of the clock buffer to shorten the internal clock delay time of the first-stage clock buffer and / or the second-stage clock buffer, so as to shorten the current transmission delay time, so that the clock transmission link of the server clock architecture can meet the clock constraint, and meanwhile, the peripheral device compatibility of the peripheral device slot can be matched. The application further provides a configuration method of a server clock architecture, an electronic device, a computer storage medium and a computer program product, which have the same beneficial effects as the configuration method of the server clock architecture.

[0093] In some embodiments, the server clock architecture comprises a master component 01, a chipset 02, a first-stage clock buffer 04 and a crystal oscillator circuit 03 connected with the first-stage clock buffer 04 or the master component 01 arranged on a server mainboard, the master component 01 mainly comprises a BMC (Baseboard Management Controller), and the chipset 02 specifically comprises a phase-locked loop, a south bridge or a PCH (Platform Controller Hub), the south bridge is mainly responsible for tasks such as I / O control, storage control and network control. The PCH is a combination of the south bridge and the north bridge, and its main task is to connect the CPU (Central Processing Unit), the memory, the south bridge and the external device, and it comprises interfaces such as the USB (Universal Serial Bus), the SATA (Serial Advanced Technology Attachment) and the PCIe, so as to realize the data transmission and control among the CPU, the memory, the south bridge and the external device, and the PCH further integrates functions such as the sound card, the network card and the wireless network card, so as to help the computer to realize functions such as multimedia and network.

[0094] The server clock architecture further comprises a second-level clock buffer 05 arranged on the add-on card, and a peripheral slot (not shown in FIG. 1) for connecting the add-on card is further arranged on the server mainboard. The add-on card can be fixed in the peripheral slot or connected to an expansion interface slot (PCIe slot) connected to the peripheral slot. The add-on card further comprises a plurality of end devices. The chip set 02 is connected to the plurality of end devices on the add-on card in one-to-one correspondence through a plurality of data buses. The add-on card can be a PCIe expansion card, such as a memory expansion card, a network card, etc.

[0095] The crystal oscillator circuit 03 is an electronic circuit for generating a stable frequency, which mainly provides an accurate and stable clock signal. The crystal oscillator circuit 03 can be connected to the chip set 02 or the first-level clock buffer 04. In FIG. 1, the crystal oscillator circuit 03 can be connected to the chip set 02 or the first-level clock buffer 04, which is shown by a dashed line. When the crystal oscillator circuit 03 is connected to the chip set 02, the chip set 02 outputs a clock signal for the end devices on the add-on card. When the crystal oscillator circuit 03 is connected to the first-level clock buffer 04, the first-level clock buffer 04 outputs a clock signal for the end devices on the add-on card.

[0096] Referring to FIG. 2, when the phase-locked loop in the chip set 02 is connected to the crystal oscillator circuit 03, the chip set 02 is configured to output a first clock signal, the first-level clock buffer 04 is configured to fan out a plurality of second clock signals according to the first clock signal, and the second-level clock buffer 05 is configured to fan out a plurality of third clock signals to the plurality of end devices on the add-on card according to the second clock signals, so that the plurality of end devices work under the third clock signals.

[0097] Referring to FIG. 3, when the first-level clock buffer 04 is connected to the crystal oscillator circuit 03, the first-level clock buffer 04 is configured to fan out a plurality of fourth clock signals according to the signal output by the crystal oscillator circuit 03, the chip set 02 works under the fourth clock signals, and the second-level clock buffer 05 is configured to fan out a plurality of fifth clock signals to the end devices on the add-on card according to the fourth clock signals, so that the plurality of end devices work under the fifth clock signals.

[0098] In some embodiments, considering that the internal clock transmission delay times of the first-level clock buffer 04 and the second-level clock buffer 05 are different in different working modes, when the current transmission delay time of the clock transmission link of the master component 01 does not meet the corresponding clock constraint of the server clock architecture, the working mode of the first-level clock buffer 04 and / or the second-level clock buffer 05 is adjusted to shorten the internal clock delay time of the first-level clock buffer 04 and / or the second-level clock buffer 05, so as to shorten the current transmission delay time, so that the clock transmission link of the server clock architecture can meet the clock constraint, while the peripheral compatibility of the peripheral slot can be maintained.

[0099] On the basis of the above embodiments:

[0100] In some embodiments, the server clock architecture further comprises a slave component on the add-on card;

[0101] The master component 01 is specifically configured to generate a configuration instruction corresponding to the target working mode of the second-stage clock buffer 05 when the current transmission delay time of the clock transmission link does not meet the clock constraint corresponding to the server clock architecture, so that the current transmission delay time of the clock transmission link meets the clock constraint;

[0102] The slave component is configured to adjust the current working mode of the second-stage clock buffer 05 to the target working mode according to the configuration instruction after receiving the configuration instruction.

[0103] The current transmission delay time is determined based on a first delay parameter from the input end to the output end of the second-stage clock buffer 05, and the first delay parameter of the second-stage clock buffer 05 is different in different working modes.

[0104] It can be understood that the master component 01 can directly adjust the working mode of the second-stage clock buffer 05 on the add-on card, or indirectly adjust the working mode of the second-stage clock buffer 05 on the add-on card, that is, the master component 01 sends a corresponding configuration instruction to the slave component on the add-on card, and the slave component adjusts the working mode of the second-stage clock buffer 05 according to the configuration instruction, thereby improving the adjustment efficiency. The slave component includes but is not limited to a single-chip microcomputer, an MCU (Microcontroller Unit), a BMC, etc. on the add-on card.

[0105] The working modes of the clock buffer of the PCIe bus include a bypass mode and a phase-locked loop (PLL) mode. The delay of the output relative to the input clock generated by the bypass mode is larger than that of the PLL mode, generally two to three orders of magnitude. With the upgrade of the PCIe bus rate, the performance indicators of the PCIe clock device are also constantly improved, and the delay of the clock buffer in the bypass mode is about several nanoseconds (ns). The delay of the PLL mode is about several hundred femtoseconds (fs), or negative delay (i.e., the output phase is ahead). The clock jitter introduced by the bypass mode is relatively small compared with the PLL mode, generally one to two orders of magnitude. The clock jitter (cycle to cycle) generated by the bypass mode is about several hundred femtoseconds (fs) to several tens of picoseconds (ps), and the clock jitter generated by the PLL mode is about several tens to several hundred picoseconds (ps). On this basis, in some embodiments, the configuration instructions include a first configuration instruction configured to the bypass mode and a second configuration instruction configured to the PLL mode. After receiving the first configuration instruction, the slave component first determines whether the current working mode of the second-level clock buffer 05 is the bypass mode. If yes, no adjustment is made, and the bypass mode is maintained. If not, the current working mode of the second-level clock buffer 05 is adjusted to the bypass mode. Correspondingly, after receiving the second configuration instruction, the slave component first determines whether the current working mode of the second-level clock buffer 05 is the PLL mode. If yes, no adjustment is made, and the PLL mode is maintained. If not, the current working mode of the second-level clock buffer 05 is adjusted to the PLL mode.

[0106] In a second aspect, the application further provides a configuration method of a server clock architecture. The server clock architecture is as described in any one of the above embodiments. Please refer to FIG. 4, which is a step flowchart of the configuration method of the server clock architecture provided by the application. The configuration method includes:

[0107] S101: determining a clock output mode of the server clock architecture; the clock output mode is a first output mode corresponding to the clock signal output by the chipset in the server clock architecture or a second output mode corresponding to the clock signal output by the first-level clock buffer in the server clock architecture;

[0108] It can be understood that the server clock architecture includes at least two clock output modes. The clock output mode in which the clock signal is output by the chipset is the first output mode, and the clock output mode in which the clock signal is output by the first-level clock buffer is the second output mode. When the clock signal is output by the chipset, the crystal oscillator circuit is connected with the phase-locked loop in the chipset, as shown in FIG. 5. When the clock signal is output by the first-level clock buffer, the crystal oscillator circuit is connected with the first-level clock buffer, as shown in FIG. 6.

[0109] Referring to the first output mode shown in FIG. 5, the chip set outputs the clock signal, which is transmitted to the first-stage clock buffer, then is fanned out from the first-stage clock buffer to each second-stage clock buffer, and finally is fanned out from the second-stage clock buffer to each end device. The transmission path of the clock signal is from the chip set to the first-stage clock buffer to the second-stage clock buffer to the end device.

[0110] Referring to the second output mode shown in FIG. 6, the first-stage clock buffer outputs the clock signal to the second-stage clock buffer and the chip set, which is then fanned out from the second-stage clock buffer to each end device. The transmission path of the clock signal is from the first-stage clock buffer to the second-stage clock buffer to the end device.

[0111] In different clock output modes, the transmission path of the clock signal is different, and the delay parameters and calculation methods for calculating the delay time are also different, so that the delay time of the clock transmission link is different. Therefore, the embodiment first determines the clock transmission mode of the server clock architecture, so as to subsequently determine the delay parameters and calculation methods for calculating the current transmission delay time based on the clock transmission mode.

[0112] S102: Calculate the current transmission delay time of the clock transmission link in the clock output mode; the current transmission delay time is determined based on the first delay parameter of the input end to the output end of the second-stage clock buffer in the server clock architecture;

[0113] In some embodiments, first, all parameters that can cause the transmission delay of the clock signal on the clock transmission link in the clock output mode are determined, including but not limited to the delay parameter corresponding to the transmission line, the delay parameter of the input end to the output end of the clock buffer, etc. The delay parameter of the input end to the output end of the clock buffer is determined based on the working mode of the clock buffer, and the time length corresponding to the delay parameter of the input end to the output end of the clock buffer is different in different working modes.

[0114] S103: Determine whether the current transmission delay time meets the clock constraint of the server clock architecture. If the current transmission delay time does not meet the clock constraint of the server clock architecture, perform S104; if the current transmission delay time meets the clock constraint of the server clock architecture, perform S105;

[0115] S104: Adjust the working mode of the first-stage clock buffer and / or the working mode of the second-stage clock buffer; the first delay parameter of the second-stage clock buffer corresponds to different time lengths in different working modes, and then repeat S102;

[0116] S105: Determine that the configuration of the server clock architecture is completed.

[0117] In some embodiments, it is firstly judged whether the current delay time is less than a preset constraint time, the preset constraint time being determined based on the bus type, assuming that the bus type is a PCIe bus, the preset constraint time being 12 ns, if the current delay time is less than 12 ns, it is determined that the current transmission delay time satisfies the clock constraint of the server clock architecture, at this time, the server clock architecture configuration is completed, and the clock buffers at all levels work in the current working mode, if the current delay time is not less than the preset constraint time, it is determined that the current transmission delay time does not satisfy the clock constraint of the server clock architecture, at this time, the server clock architecture needs to be adjusted. The embodiment considers that the delay parameters corresponding to the time length of the input end to the output end of the clock buffer are different in different working modes, and the current transmission delay time includes the delay time of the input end to the output end of the clock buffer, therefore, the working mode of the clock buffer is adjusted in the embodiment to shorten the delay time of the input end to the output end of the clock buffer, so as to reduce the current transmission delay time, so that the current transmission delay time can satisfy the clock constraint of the server clock architecture.

[0118] It can be understood that, in the first transmission mode, since the clock signal is output by the chipset, the input-to-output delay time of the first-level clock buffer needs to be considered when calculating the current delay time, and in the second transmission mode, since the clock signal is output by the first-level clock buffer, the input-to-output delay time of the first-level clock buffer does not need to be considered when calculating the current delay time, that is, the working mode of the second-level clock buffer can be adjusted in the second transmission mode, based on which, in some embodiments, the adjustable clock buffer among the first-level clock buffer and the second-level clock buffer can be determined based on the clock transmission mode, the adjustable clock buffer can be one or two, and the working mode of the adjustable clock buffer is adjusted, so that the current transmission delay time can satisfy the clock constraint of the server clock architecture as soon as possible, improving the configuration efficiency.

[0119] It can be seen that in some embodiments, firstly, the clock output mode currently adopted by the server clock architecture is determined, and it is determined whether the clock signal is output by the chipset or output by the first-stage clock buffer. In different output modes, because the transmission paths of the clock signal are different, the current transmission delay time of the clock transmission link is different. The current transmission delay time of the clock transmission link in the clock output mode is calculated, and it is judged whether the current transmission delay time meets the clock constraint of the server clock architecture. If the clock constraint is not met, considering that the internal clock delays of the first-stage clock buffer and the second-stage clock buffer are different in different working modes, the application adjusts the working mode of the clock buffer to shorten the internal clock delay time of the first-stage clock buffer and / or the second-stage clock buffer, thereby shortening the current transmission delay time, so that the PCIe clock transmission link of the computer system can meet the clock constraint of the server clock architecture, and at the same time can have peripheral compatibility of adapting peripheral slots.

[0120] On the basis of the above-mentioned embodiments:

[0121] In some embodiments, the process of calculating the current transmission delay time of the clock transmission link in the clock output mode comprises:

[0122] The current delay parameter group corresponding to the clock transmission link in the clock output mode is determined. When the clock output mode is the first output mode, the current delay parameter group is the first delay parameter group, and the first delay parameter group includes the second delay parameter from the input end to the output end of the first-stage clock buffer and the first delay parameter from the input end to the output end of the second-stage clock buffer. When the clock output mode is the second output mode, the current delay parameter group is the second delay parameter group, and the second delay parameter group includes the output clock skew parameter and the first delay parameter from the input end to the output end of the second-stage clock buffer.

[0123] The current delay time is calculated by using all the parameters in the current delay parameter group.

[0124] In some embodiments, in each clock output mode, a delay parameter group is established based on all possible delay parameters on the clock transmission link. The clock output mode and the delay parameter group are one-to-one corresponding. Each delay parameter in the delay parameter group corresponding to the clock output mode is used to calculate the current delay time, thereby improving the accuracy of the calculation result of the current delay time.

[0125] It can be understood that, in the first output mode, since the transmission path of the clock signal includes the chipset to the first-stage clock buffer to the second-stage clock buffer, in order to improve the accuracy of the calculation result of the current delay time in the first transmission mode, the corresponding first delay parameter group needs to include the second delay parameter of the input end to the output end of the first-stage clock buffer and the first delay parameter of the input end to the output end of the second-stage clock buffer. In the second output mode, since the transmission path of the clock signal does not include the path from the chipset to the first-stage clock buffer, the second delay parameter of the input end to the output end of the first-stage clock buffer does not need to be included as one of the delay parameters in the second delay parameter group. It can be understood that, in the second output mode, the first-stage clock buffer respectively fans out the clock signal to the chipset and the PCIe peripheral slot, and therefore, the phase difference between the output clock signals needs to be considered, that is, the output clock skew.

[0126] In some embodiments, the process of determining the current delay parameter group corresponding to the clock transmission link in the clock output mode includes:

[0127] When the clock output mode is the first output mode, the second delay parameter of the input end to the output end of the first-stage clock buffer, the first delay parameter of the input end to the output end of the second-stage clock buffer, the third delay parameter of the phase-locked loop in the chipset to the output pin of the chipset, the fourth delay parameter corresponding to the first transmission line between the chipset and the first-stage clock buffer, the fifth delay parameter corresponding to the second transmission line between the first-stage clock buffer and the peripheral slot, the sixth delay parameter corresponding to the third transmission line between the second-stage clock buffer and the end device on the external card, and the seventh delay parameter corresponding to the bus data link are obtained.

[0128] The first delay parameter group is constructed based on the first delay parameter, the second delay parameter, the third delay parameter, the fourth delay parameter, the fifth delay parameter, the sixth delay parameter, and the seventh delay parameter.

[0129] The first delay parameter group is taken as the current delay parameter group corresponding to the clock transmission link in the first output mode.

[0130] Referring to FIG. 5, the clock signal is multiplied by the phase-locked loop inside the chipset and output to the PCIe physical layer (PHY), and the output clock is used by the external device of the PCIe. The delay parameters involved in the clock transmission link include but are not limited to:

[0131] The clock delay time t of the phase-locked loop in the chipset to the output pin delay1 , that is, the third delay parameter, which is denoted by t d1 in FIG. 5.

[0132] The PCB line delay time t of the chipset output clock signal to the first-stage clock bufferclkpcb1 , i.e. the fourth delay parameter, represented by t p1 in Fig. 5.

[0133] The delay time t b1 of the input end to the output end of the first-stage clock buffer, i.e. the second delay parameter, represented by t clkpcb2 in Fig. 5, which has a difference in orders of magnitude between the bypass mode and the phase-locked loop mode;

[0134] The delay time t p2 of the PCB line of the first-stage clock buffer to the peripheral slot of PCIe, i.e. the fifth delay parameter, represented by t b2 in Fig. 5.

[0135] The delay time t clkpcb3 of the input end to the output end of the second-stage clock buffer on the peripheral card, i.e. the first delay parameter, represented by t p3 in Fig. 5, which has a difference in orders of magnitude between the bypass mode and the phase-locked loop mode, and the second-stage clock buffer is absent if the peripheral card is a single PCIe-end device.

[0136] The delay time t data of the PCB line of the second-stage clock buffer on the peripheral card to the end device on the peripheral card, i.e. the sixth delay parameter, represented by t d in Fig. 5, which can be understood as being small in comparison with the delay of the line on the peripheral card and the delay caused by the clock buffer itself.

[0137] The delay time t delay1 of the bus data link, i.e. the seventh delay parameter, represented by t clkpcb1 in Fig. 5.

[0138] All the above delay parameters form a first delay parameter group.

[0139] It can be understood that the PCIe data transmission relationship between the chipset and the peripheral device is mutual, i.e. the chipset is the transmitting end while the PCIe card peripheral is the receiving end, and vice versa. The most serious and deteriorated case of the clock transmission link delay in this clock output mode is that the peripheral card is the transmitting end while the chipset is the receiving end. In this case, the process of calculating the current delay time by using all the parameters in the current delay parameter group includes:

[0140] Establishing a first calculation relationship based on all the parameters in the current delay parameter group;

[0141] Calculating the current delay time by using the first calculation relationship;

[0142] The first calculation relationship is T1 = t delay1 + t clkpcb1+ tclkbuffer1 + t clkpcb2 + tclkbuffer2 + t clkpcb3 + t data ;

[0143] Wherein, T1 is the current delay time, tclkbuffer1 is the first delay parameter, tclkbuffer2 is the second delay parameter, t delay1 is the third delay parameter, t clkpcb1 is the fourth delay parameter, t clkpcb2 is the fifth delay parameter, t clkpcb3 is the sixth delay parameter, t data is the seventh delay parameter. Wherein, T1 needs to be less than 12ns. T1 = t delay1 + t clkpcb1 + tclkbuffer1 + t clkpcb2 + tclkbuffer2 + t clkpcb3 + t data ;

[0144] Correspondingly, the clock delay from the chip set phase-locked loop to the chip set PCIe physical layer (PHY) is:

[0145] T2 = t' delay1 .

[0146] Further description of PCIe clock quality constraints:

[0147] The PCIe bus specification clock parameters have strict specifications. The specification gives a clock jitter calculation model under the common clock topology. The jitter relationship of the clock signal on two transmission links is: X cc1 (s) = X(s) × [H1(s) × e -sT -H2(s)] × H3(s); X cc2 (s) = X(s) × [H2(s) × e -sT -H1(s)] × H3(s);

[0148] X cc1 (s) is the jitter of the clock signal on the first transmission link, X cc2 (s) is the jitter of the clock signal on the second transmission link, wherein X(s) is the jitter of the reference clock signal, H1(s) is the phase-locked loop transfer function of the sending end, H2(s) is the phase-locked loop transfer function of the receiving end, H3(s) is the transfer function of the receiving end CDR (Clock Data Recovery, clock recovery module), T is the absolute value of the delay time difference of the two links (take positive number), that is: T = |T1-T2|;

[0149] From the above, the jitter of the reference clock at the receiving end is Xcc1 (s) and X cc2( s) Relative maximum value MAX[X cc1 (s), X cc2( s)).

[0150] Based on the jitter relationship of the clock signal on the two transmission links, considering that the physical layer phase-locked loop parameters H1(s) and H2(s) of different PCIe devices are constrained within a very small range according to the PCIe bus specification, the parameters are close. Therefore, it can be obtained that when the parameter T (T=|T1-T2|) is close to 0, the delay element e -sT Approaching 1, clock jitter X cc1 (s) and X cc2 (s) reaches its minimum value.

[0151] Generally, the internal t of the chip delay1 and t' delay1 Approximating, we obtain: T = t clkpcb1 +tclkbuffer1+t clkpcb2 +tclkbuffer2+t clkpcb3 +t data .

[0152] In some embodiments, the process of determining the current delay parameter set corresponding to the clock transmission link in clock output mode includes:

[0153] When the clock output mode is the second output mode, the following parameters are obtained: output clock skew parameter, second delay parameter between the input and output of the second-level clock buffer, first line delay parameter corresponding to the second transmission line between the first-level clock buffer and the peripheral slot, second line delay parameter corresponding to the third transmission line between the first-level clock buffer and the chipset, third line delay parameter corresponding to the third transmission line between the second-level clock buffer and the external card, seventh delay parameter corresponding to the bus data link, and eighth delay parameter corresponding to the clock delay within the chipset.

[0154] The second delay parameter group is constructed based on the output clock skew parameter, the second delay parameter, the seventh delay parameter, the eighth delay parameter, the first line delay parameter, the second line delay parameter, and the third line delay parameter;

[0155] The second delay parameter group is used as the current delay parameter group corresponding to the clock transmission link of the second output mode.

[0156] In some embodiments, as shown in FIG6, the first-stage clock buffer fans out clock signals to the chipset and peripheral slots respectively. In this case, the input-output delay time of the first-stage clock buffer is no longer the focus, but the parameter t needs to be considered. clkskew In Figure 6, ts This parameter indicates that it represents the phase difference between the output clocks, i.e., the output clock skew.

[0157] In addition to output clock skew, the delay parameters involved in its clock transmission link include, but are not limited to:

[0158] Clock delay time t within the chipset delay2 That is, the eighth delay parameter, denoted as t in Figure 6. d2 This indicates that the main focus at this point is on the chipset's IBIS (Input / Output Buffer Information Specification) parameters. Clock routing to the chipset requires fan-out to multiple PCIe physical layers, thus including the latency of the chipset's internal buffers.

[0159] The delay time t from the first-level clock buffer to the chipset's PCB trace is... clkpcb4 That is, the second line delay parameter, denoted as t in Figure 6. p4 express;

[0160] The delay time t between the first-stage clock buffer and the PCB trace in the peripheral slot. clkpcb5 That is, the first line delay parameter, denoted as t in Figure 6. p5 express.

[0161] The input-to-output delay time tclkbuffer2 of the second-level clock buffer on the external card, i.e. the second delay parameter, has an order of magnitude difference between bypass mode and phase-locked loop mode. If the peripheral card is a single PCIe device, it does not have this clock buffer.

[0162] The delay time t between the second-level clock buffer on the external card and the PCB trace of the end device on the external card. clkpcb6 That is, the third line delay parameter, denoted as t in Figure 6. p6 This means that the lines on a typical external card are shorter, and the delay caused by the lines and clock buffer on the computer motherboard is relatively small;

[0163] Bus data link delay time t data That is, the seventh delay parameter, denoted as t in Figure 6. d express.

[0164] The second delay parameter group is formed based on the above parameters.

[0165] In summary, in this clock output mode, one of the clock transmission links of the first-level clock buffer is directly connected to the chipset, and its latency can be evaluated by the chip's IBIS model and PCB traces. The other link is connected to the PCIe peripheral slot, or the latency is degraded through the second-level clock buffer. The latency of a single link needs to be less than 12ns.

[0166] When the chipset is the transmitter: T a =|(t) delay2 +t clkpcb4 +t data )-(t clkpcb5 +tclkbuffer2+t clkpcb6 )|+t clkskew ;

[0167] When the external card is the transmitter: T b =|(t) delay2 +t clkpcb4 )-(t clkpcb5 +tclkbuffer2+t clkpcb6 +t data )|+t clkskew ;

[0168] Among them, clock skew t clkskew A positive value represents the parameters of latency degradation and clock jitter. The worst-case latency for the entire clock transmission link is obtained as: T max =MAX[T a T b ].

[0169] In some embodiments, the current latency is calculated under the worst-case latency condition. In some embodiments, after determining whether the current transmission latency meets the clock constraints of the server clock architecture, the configuration method further includes:

[0170] Calculate the time difference between the current transmission delay and the constraint time corresponding to the clock constraint of the server clock architecture;

[0171] Determine whether the time difference is less than or equal to a preset difference;

[0172] If so, adjust the position of the first-level clock buffer on the server motherboard so that the time difference is greater than the preset difference.

[0173] In some embodiments, to further reduce the latency of the always-transmitting link, the position of the first-level clock buffer is also adjusted. Specifically, under the condition that the current transmission time delay meets the always-container constraint, the time difference between the current transmission delay and the constraint time corresponding to the clock constraint of the server clock architecture is determined. If the time difference is small, the position of the first-level clock buffer can be adjusted to further reduce the current transmission delay. For example, assuming the preset difference is 1ns, if the current transmission delay is 11ns and the preset constraint time is 12ns, the time difference between the two is less than or equal to 1ns, and the position of the first-level clock buffer is adjusted.

[0174] In the first output mode, the first-stage clock buffer is between the chipset and the peripheral slot, and it is necessary to reduce t clkpcb1 +t clkpcb2 to reduce the delay and improve the clock jitter. For the motherboard design, the first-stage clock buffer is relatively close to the chipset and far away from the PCIe card slot, and vice versa. Both of them need to be considered to achieve the shortest delay.

[0175] In the second output mode, assuming that the positions of the chipset and the peripheral slot on the server motherboard are determined, and the PCIe data link length is determined, the position of the first-stage clock buffer can be adjusted to optimize the PCIe clock jitter, that is, t clkpcb4 and t clkpcb 5 are two variable parameters, so that the value of T max is minimized.

[0176] In some embodiments, the clock buffer outputs a plurality of clock skew t clkskew , t clkskew is a parameter of deteriorating delay and clock jitter. When selecting a device, the smaller the parameter is, the better it is.

[0177] In some embodiments, the process of calculating the current transmission delay time of the clock transmission link in the clock output mode includes:

[0178] calculating the current transmission delay time of the clock transmission link in the clock output mode and when the working mode of the first-stage clock buffer and the working mode of the second-stage clock buffer are both bypass modes.

[0179] It can be understood that the clock buffer of the PCIe bus includes two configurations: a bypass mode and a phase-locked loop (PLL) mode. The output delay of the bypass mode relative to the input clock is larger than that of the PLL mode, generally two to three orders of magnitude. With the upgrade of the PCIe bus rate, the performance indicators of the PCIe clock device are also constantly improved, and the clock buffer in the bypass mode has a delay of about several nanoseconds (ns). The delay of the PLL mode is about several hundred femtoseconds (fs), or negative delay (i.e., output phase advance). The clock jitter introduced by the bypass mode is relatively small compared to the PLL mode, generally one to two orders of magnitude. The clock jitter (cycle to cycle) generated by the bypass mode is about several hundred femtoseconds (fs) to several tens of picoseconds (ps), and the clock jitter generated by the PLL mode is about several tens to several hundred picoseconds (ps). Since the clock jitter introduced by the bypass mode is relatively small compared to the PLL mode, the working mode of the two-stage clock buffer is first configured to the bypass mode in the embodiment, and the current transmission delay time is calculated in the bypass mode. If the current transmission delay time meets the clock constraint, the clock jitter of the clock transmission link in the clock output mode will be relatively small, thereby improving the reliability of clock transmission.

[0180] In some embodiments, the process of adjusting the working mode of the first-stage clock buffer and / or the working mode of the second-stage clock buffer to make the current transmission delay time of the clock transmission link in the clock output mode meet the clock constraint includes:

[0181] determining either of the first-stage clock buffer and the second-stage clock buffer as a first adjustment buffer and the other as a second adjustment buffer;

[0182] switching the working mode of the first adjustment buffer from the bypass mode to the PLL mode;

[0183] calculating the current transmission delay time of the clock transmission link in the clock output mode, with the working mode of the first adjustment buffer being the PLL mode and the working mode of the second adjustment buffer being the bypass mode;

[0184] judging whether the current transmission delay time meets the clock constraint of the server clock architecture;

[0185] if the current transmission delay time meets the clock constraint of the server clock architecture, determining that the server clock architecture configuration is completed;

[0186] if the current transmission delay time does not meet the clock constraint of the server clock architecture, switching the working mode of the second adjustment buffer from the bypass mode to the PLL mode;

[0187] calculating a current transmission delay time of the clock transmission link when the clock output mode and the working mode of the first adjustment buffer and the working mode of the second adjustment buffer are all in the phase-locked loop mode;

[0188] judging whether the current transmission delay time meets the clock constraint of the server clock architecture;

[0189] if the current transmission delay time meets the clock constraint of the server clock architecture, determining that the server clock architecture configuration is completed;

[0190] if the current transmission delay time does not meet the clock constraint of the server clock architecture, prompting a configuration error information.

[0191] In some embodiments, the adjustment is performed when both the two-stage clock buffers are in the bypass mode, and first, any one of the two-stage clock buffers is determined as the first adjustment buffer and the other is determined as the second adjustment buffer. For example, if the first-stage clock buffer is the first adjustment buffer, the second-stage clock buffer is the second adjustment buffer, and if the first-stage clock buffer is the second adjustment buffer, the second-stage clock buffer is the first adjustment buffer. The working mode of the first adjustment buffer is first adjusted to the phase-locked loop mode. After the adjustment to the phase-locked loop mode, the delay time from the input to the output of the first adjustment buffer is reduced. At this time, the current transmission delay time of the clock transmission link is recalculated. If the current transmission delay time meets the clock constraint, it is determined that the server clock architecture configuration is completed. Since the second adjustment buffer is still in the bypass mode at this time, only one stage of the clock buffer is adjusted to the phase-locked loop mode, which has lower clock jitter compared to both stages being in the phase-locked loop mode. If the one-stage phase-locked loop mode cannot make the current transmission delay meet the clock constraint, the working mode of the second adjustment buffer is also adjusted to the phase-locked loop mode to reduce the delay time from the input to the output of the second adjustment buffer. If the two-stage phase-locked loop mode still cannot make the current transmission delay time meet the clock constraint, a configuration error information is prompted for targeted processing by engineers.

[0192] In some embodiments, the process of determining any one of the first-stage clock buffer and the second-stage clock buffer as the first adjustment buffer and the other as the second adjustment buffer includes:

[0193] determining the second-stage clock buffer as the first adjustment buffer and the first-stage clock buffer as the second adjustment buffer.

[0194] In view of the greater adjustment flexibility of the second-stage clock buffer on the external card, the second-stage clock buffer is determined as the first adjustment buffer in this embodiment, and the working mode of the second-stage clock buffer is adjusted preferentially, thereby improving the adjustment efficiency.

[0195] In a third aspect, referring to FIG. 7, which is a structural schematic diagram of a configuration system of a server clock architecture, the server clock architecture is the server clock architecture described in any one of the above embodiments, and the configuration system comprises:

[0196] a determination module 11 configured to determine a clock output mode of the server clock architecture, the clock output mode being a first output mode corresponding to a clock signal output by a chipset in the server clock architecture or a second output mode corresponding to a clock signal output by a first-stage clock buffer in the server clock architecture;

[0197] a first calculation module 12 configured to calculate a current transmission delay time of a clock transmission link in the clock output mode, the current transmission delay time being determined based on a first delay parameter of an input end to an output end of a second-stage clock buffer in the server clock architecture;

[0198] a first judgment module 13 configured to judge whether the current transmission delay time meets a clock constraint of the server clock architecture, and generate a first trigger instruction if the current transmission delay time does not meet the clock constraint;

[0199] a first adjustment module 14 configured to, after receiving the first trigger instruction, adjust a working mode of the first-stage clock buffer and / or a working mode of the second-stage clock buffer, so that the current transmission delay time of the clock transmission link in the clock output mode meets the clock constraint, and the first delay parameter of the second-stage clock buffer corresponding to different working modes has different time lengths.

[0200] In some embodiments, the process of calculating the current transmission delay time of the clock transmission link in the clock output mode comprises:

[0201] determining a current delay parameter group corresponding to the clock transmission link in the clock output mode; when the clock output mode is the first output mode, the current delay parameter group is a first delay parameter group, and the first delay parameter group comprises a second delay parameter of an input end to an output end of the first-stage clock buffer and the first delay parameter of the input end to the output end of the second-stage clock buffer; when the clock output mode is the second output mode, the current delay parameter group is a second delay parameter group, and the second delay parameter group comprises an output clock skew parameter and the first delay parameter of the input end to the output end of the second-stage clock buffer;

[0202] calculating the current delay time by using all parameters in the current delay parameter group.

[0203] In some embodiments, the process of determining the current delay parameter group corresponding to the clock transmission link in the clock output mode comprises:

[0204] When the clock output mode is the first output mode, a second delay parameter of an input end to an output end of the first stage clock buffer, a first delay parameter of an input end to an output end of the second stage clock buffer, a third delay parameter of a phase-locked loop in the chipset to an output pin of the chipset, a fourth delay parameter corresponding to a first transmission line between the chipset and the first stage clock buffer, a fifth delay parameter corresponding to a second transmission line between the first stage clock buffer and the peripheral slot, a sixth delay parameter corresponding to a third transmission line between the second stage clock buffer and the end device on the external card, and a seventh delay parameter corresponding to the bus data link are obtained;

[0205] A first delay parameter group is constructed based on the first delay parameter, the second delay parameter, the third delay parameter, the fourth delay parameter, the fifth delay parameter, the sixth delay parameter, and the seventh delay parameter.

[0206] The first delay parameter group is taken as a current delay parameter group corresponding to the clock transmission link in the first output mode.

[0207] In some embodiments, the process of calculating the current delay time by using all the parameters in the current delay parameter group comprises:

[0208] A first calculation relationship is established based on all the parameters in the current delay parameter group.

[0209] The current delay time is calculated by using the first calculation relationship.

[0210] The first calculation relationship is: T1=t delay1 +t clkpcb1 +tclkbuffer1+t clkpcb2 +tclkbuffer2+t clkpcb3 +t data ;

[0211] Wherein, T1 is the current delay time, tclkbuffer1 is the first delay parameter, tclkbuffer2 is the second delay parameter, t delay1 is the third delay parameter, t clkpcb1 is the fourth delay parameter, t clkpcb2 is the fifth delay parameter, t clkpcb3 is the sixth delay parameter, and t data is the seventh delay parameter.

[0212] In some embodiments, the process of determining the current delay parameter group corresponding to the clock transmission link in the clock output mode comprises:

[0213] When the clock output mode is the second output mode, the output clock skew parameter, the second delay parameter between the input end and the output end of the second stage clock buffer, the first line delay parameter corresponding to the second transmission line between the first stage clock buffer and the peripheral slot, the second line delay parameter corresponding to the third transmission line between the first stage clock buffer and the chipset, the third line delay parameter corresponding to the third transmission line between the second stage clock buffer and the external card, the seventh delay parameter corresponding to the bus data link, and the eighth delay parameter corresponding to the clock delay in the chipset are acquired;

[0214] The second delay parameter group is constructed based on the output clock skew parameter, the second delay parameter, the seventh delay parameter, the eighth delay parameter, the first line delay parameter, the second line delay parameter, and the third line delay parameter;

[0215] The second delay parameter group is taken as the current delay parameter group corresponding to the clock transmission link of the second output mode.

[0216] In some embodiments, the process of calculating the current delay time by using all the parameters in the current delay parameter group comprises:

[0217] The second calculation relationship corresponding to the chipset as the sending end and the third calculation relationship corresponding to the external card as the sending end are established based on all the parameters in the current delay parameter group;

[0218] The first delay time is calculated by using the second calculation relationship;

[0219] The second delay time is calculated by using the third calculation relationship;

[0220] The maximum value between the first delay time and the second delay time is taken as the current delay time.

[0221] In some embodiments, the second calculation relationship is: a = | (t delay2 + t clkpcb4 + t data ) - (t clkpcb5 + tclkbuffer2 + t clkpcb6 ) | + t clkskew ;

[0222] wherein, T a is the first delay time, t delay2 is the eighth delay parameter, t data is the seventh delay parameter, t clkskew is the output clock skew parameter, tclkbuffer2 is the second delay parameter, t clkpcb4 is the first line delay parameter, t clkpcb5 is the second line delay parameter, and t clkpcb6a third line delay parameter.

[0223] In some embodiments, the third calculation relationship is: b = | (t delay2 + t clkpcb4 ) - (t clkpcb5 + tclkbuffer2+ t clkpcb6 + t data ) | + t clkskew ;

[0224] wherein T b is a second delay time, t delay2 is an eighth delay parameter, t data is a seventh delay parameter, t clkskew is an output clock skew parameter, tclkbuffer2 is a second delay parameter, t clkpcb4 is a first line delay parameter, t clkpcb5 is a second line delay parameter, and t clkpcb6 is a third line delay parameter.

[0225] In some embodiments, the configuration system further comprises:

[0226] a second calculation module configured to calculate a time difference between a current transmission delay time and a constraint time corresponding to a clock constraint of a server clock architecture;

[0227] a second judgment module configured to judge whether the time difference is less than or equal to a preset difference value, and generate a second trigger instruction if the time difference is less than or equal to the preset difference value;

[0228] a second adjustment module configured to adjust a position of the first level clock buffer on a server mainboard to make the time difference greater than the preset difference value after receiving the second trigger instruction.

[0229] In some embodiments, the process of calculating the current transmission delay time of the clock transmission link in the clock output mode comprises:

[0230] calculating the current transmission delay time of the clock transmission link in the clock output mode and when the working mode of the first level clock buffer and the working mode of the second level clock buffer are both bypass modes.

[0231] In some embodiments, the process of adjusting the working mode of the first level clock buffer and / or the working mode of the second level clock buffer to make the current transmission delay time of the clock transmission link in the clock output mode satisfy the clock constraint comprises:

[0232] determining any one of the first level clock buffer and the second level clock buffer as a first adjustment buffer and the other as a second adjustment buffer;

[0233] switching the working mode of the first adjustment buffer from the bypass mode to the phase-locked loop mode;

[0234] calculating the current transmission delay time of the clock transmission link in the clock output mode and when the working mode of the first adjustment buffer is the phase-locked loop mode and the working mode of the second adjustment buffer is the bypass mode;

[0235] judging whether the current transmission delay time meets the clock constraint of the server clock architecture;

[0236] if yes, determining that the configuration of the server clock architecture is completed;

[0237] if no, switching the working mode of the second adjustment buffer from the bypass mode to the phase-locked loop mode;

[0238] calculating the current transmission delay time of the clock transmission link in the clock output mode and when the working mode of the first adjustment buffer and the working mode of the second adjustment buffer are both the phase-locked loop mode;

[0239] judging whether the current transmission delay time meets the clock constraint of the server clock architecture;

[0240] if yes, determining that the configuration of the server clock architecture is completed;

[0241] if no, prompting configuration error information.

[0242] In some embodiments, the process of determining any one of the first-stage clock buffer and the second-stage clock buffer as the first adjustment buffer and the other as the second adjustment buffer comprises:

[0243] determining the second-stage clock buffer as the first adjustment buffer and the first-stage clock buffer as the second adjustment buffer.

[0244] In a fourth aspect, the present application further provides a computer readable instruction product comprising computer readable instructions, which, when executed by a processor, implement the steps of the configuration method of the server clock architecture described in any one of the above embodiments.

[0245] For the computer readable instruction product provided by the present application, refer to the above embodiments, which will not be repeated here.

[0246] The computer readable instruction product provided by the present application has the same beneficial effects as the above-mentioned configuration method of the server clock architecture.

[0247] In a fifth aspect, referring to FIG. 8, the present application further provides an electronic device comprising:

[0248] a memory 21 configured to store computer readable instructions;

[0249] The processor 22 is configured to execute computer readable instructions to implement the steps of the method for configuring the server clock architecture as described in any one of the above embodiments.

[0250] The electronic device further comprises:

[0251] The input interface 23 is connected to the processor 22 via the communication bus 26, and is configured to acquire computer readable instructions and parameters and instructions imported from outside, and save the computer readable instructions and parameters and instructions into the memory 21 under the control of the processor 22. The input interface can be connected to an input device to receive parameters or instructions manually input by a user. The input device can be a touch layer overlaid on a display screen, or a key, trackball or touchpad arranged on a terminal shell.

[0252] The display unit 24 is connected to the processor 22 via the communication bus 26, and is configured to display data sent by the processor 22. The display unit can be a liquid crystal display screen or an electronic ink display screen, etc.

[0253] The network port 25 is connected to the processor 22 via the communication bus 26, and is configured to be communicatively connected to external terminal devices. The communication technology used by the communication connection can be wired communication technology or wireless communication technology, such as mobile high-definition link technology, universal serial bus, high-definition multimedia interface, wireless fidelity technology, Bluetooth communication technology, low-power Bluetooth communication technology, IEEE 802.11s-based communication technology, etc.

[0254] For the electronic device provided in the present application, refer to the above embodiments, which will not be repeated here.

[0255] The electronic device provided in the present application has the same beneficial effects as the method for configuring the server clock architecture.

[0256] In the sixth aspect, referring to FIG. 9, the present application further provides a computer readable storage medium 30, and the computer readable storage medium 30 stores computer readable instructions 31. The computer readable instructions 31 are executed by a processor to implement the steps of the method for configuring the server clock architecture as described in any one of the above embodiments.

[0257] The computer readable storage medium 30 can include a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, etc.

[0258] For the computer readable storage medium provided in the present application, refer to the above embodiments, which will not be repeated here.

[0259] The computer readable storage medium provided in the present application has the same beneficial effects as the configuration method of the server clock architecture.

[0260] It should also be noted that the relationship terms such as first and second and the like in the present description are only used to distinguish one entity or operation from another, and do not necessarily require or imply that there is any such actual relationship or order between these entities or operations. Moreover, the terms "include", "contain" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such process, method, article or device. Without more limitations, the element defined by the statement "including a" does not exclude the presence of other identical elements in the process, method, article or device including the element.

[0261] The above description of the disclosed embodiments enables a person skilled in the art to implement or use the present application. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to the embodiments shown herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A server clock architecture, characterized in that, The system includes a main control component, chipset, crystal oscillator circuit, and first-level clock buffer located on the server motherboard, and a second-level clock buffer located on an external card. The server motherboard also includes peripheral slots for connecting the external card, wherein: The chipset is connected to the first-level clock buffer via a first transmission line; the first-level clock buffer is connected to the peripheral slot via a second transmission line; the second-level clock buffer is connected to the peripheral slot via a third transmission line; the second-level clock buffer is connected to each terminal device of the external card; and the crystal oscillator circuit is connected to either the first-level clock buffer or the chipset. The main control component is used to adjust the working mode of the first-level clock buffer and / or the working mode of the second-level clock buffer when the current transmission delay time of the clock transmission link of the server clock architecture does not meet the clock constraint corresponding to the server clock architecture, so as to make the current transmission delay time of the clock transmission link meet the clock constraint.

2. The server clock architecture according to claim 1, characterized in that, The server clock architecture also includes a slave control component located on the external card; The main control component is specifically used to generate a configuration instruction corresponding to the target working mode of the second-level clock buffer when the current transmission delay time of the clock transmission link of the server clock architecture does not meet the clock constraint corresponding to the server clock architecture, so as to make the current transmission delay time of the clock transmission link meet the clock constraint. The slave control component is used to adjust the current working mode of the second-level clock buffer to the target working mode according to the configuration instruction after receiving the configuration instruction; The current transmission delay time of the clock transmission link is determined based on the first delay parameter from the input to the output of the second-level clock buffer, and the duration of the first delay parameter of the second-level clock buffer varies in different operating modes.

3. The server clock architecture according to claim 1 or 2, characterized in that, The chipset is connected to the crystal oscillator circuit; The chipset is used to output a first clock signal according to the signal output by the crystal oscillator circuit; The first-stage clock buffer is used to fan out multiple second clock signals according to the first clock signal; and The second-level clock buffer is used to fan out multiple third clock signals to multiple end devices on the external card according to the second clock signal, so that the multiple end devices all operate under the third clock signal.

4. The server clock architecture according to claim 1 or 2, characterized in that, The first-stage clock buffer is connected to the crystal oscillator circuit; The first-stage clock buffer is used to fan out multiple fourth clock signals based on the signal output by the crystal oscillator circuit. The chipset is used to operate under the fourth clock signal; and The second-level clock buffer is used to fan out multiple fifth clock signals to the end devices on the external card according to the fourth clock signal, so that the multiple end devices can operate under the fifth clock signal.

5. A method for configuring a server clock architecture, characterized in that, The server clock architecture is the server clock architecture as described in any one of claims 1-4, and the configuration method includes: Determine the clock output mode of the server clock architecture; the clock output mode is either a first output mode corresponding to the clock signal output by the chipset in the server clock architecture or a second output mode corresponding to the clock signal output by the first-level clock buffer in the server clock architecture. Calculate the current transmission delay time of the clock transmission link in the clock output mode; the current transmission delay time is determined based on the first delay parameter from the input to the output of the second-level clock buffer in the server clock architecture; When the current transmission delay time does not meet the clock constraints of the server clock architecture, the operating mode of the first-level clock buffer and / or the operating mode of the second-level clock buffer are adjusted so that the current transmission delay time of the clock transmission link in the clock output mode meets the clock constraints; the first delay parameter of the second-level clock buffer corresponds to different durations in different operating modes.

6. The configuration method for the server clock architecture according to claim 5, characterized in that, The calculation of the current transmission delay time of the clock transmission link in the clock output mode includes: Determine the current delay parameter group corresponding to the clock transmission link in the clock output mode; when the clock output mode is the first output mode, the current delay parameter group is the first delay parameter group, which includes the second delay parameter from the input to the output of the first-stage clock buffer and the first delay parameter from the input to the output of the second-stage clock buffer; when the clock output mode is the second output mode, the current delay parameter group is the second delay parameter group, which includes the output clock skew parameter and the first delay parameter from the input to the output of the second-stage clock buffer. Calculate the current delay time using all parameters in the current delay parameter group.

7. The configuration method for the server clock architecture according to claim 6, characterized in that, The server clock architecture includes a server motherboard, which has peripheral slots. The process of determining the current latency parameter group corresponding to the clock transmission link in the clock output mode includes: When the clock output mode is the first output mode, the following parameters are obtained: the second delay parameter from the input to the output of the first-level clock buffer, the first delay parameter from the input to the output of the second-level clock buffer, the third delay parameter from the phase-locked loop in the chipset to the output pin of the chipset, the fourth delay parameter corresponding to the first transmission line between the chipset and the first-level clock buffer, the fifth delay parameter corresponding to the second transmission line between the first-level clock buffer and the peripheral slot, the sixth delay parameter corresponding to the third transmission line between the second-level clock buffer and the terminal device on the external card, and the seventh delay parameter corresponding to the bus data link. The first delay parameter group is constructed based on the first delay parameter, the second delay parameter, the third delay parameter, the fourth delay parameter, the fifth delay parameter, the sixth delay parameter, and the seventh delay parameter; and The first delay parameter group is used as the current delay parameter group corresponding to the clock transmission link of the first output mode.

8. The configuration method for the server clock architecture according to claim 7, characterized in that, The process of calculating the current delay time using all parameters in the current delay parameter group includes: Establish the first calculation formula based on all parameters in the current delay parameter group; Calculate the current delay time using the first calculation formula; The first calculation formula is: T1=t delay1 +t clkpcb1 +tclkbuffer1+t clkpcb2 +tclkbuffer2+t clkpcb3 +t data ; Where T1 is the current delay time, tclkbuffer1 is the first delay parameter, tclkbuffer2 is the second delay parameter, and t delay1 The third delay parameter, t clkpcb1 For the fourth delay parameter, t clkpcb2 For the fifth delay parameter, t clkpcb3 For the sixth delay parameter, t data This refers to the seventh delay parameter.

9. The configuration method for the server clock architecture according to claim 6, characterized in that, The server clock architecture includes a server motherboard, which has peripheral slots. Determining the current latency parameter group corresponding to the clock transmission link in the clock output mode includes: When the clock output mode is the second output mode, the following parameters are obtained: the output clock skew parameter, the second delay parameter between the input and output of the second-level clock buffer, the first line delay parameter corresponding to the second transmission line between the first-level clock buffer and the peripheral slot, the second line delay parameter corresponding to the third transmission line between the first-level clock buffer and the chipset, the third line delay parameter corresponding to the third transmission line between the second-level clock buffer and the external card, the seventh delay parameter corresponding to the bus data link, and the eighth delay parameter corresponding to the clock delay within the chipset. A second delay parameter group is constructed based on the output clock skew parameter, the second delay parameter, the seventh delay parameter, the eighth delay parameter, the first line delay parameter, the second line delay parameter, and the third line delay parameter; and The second delay parameter group is used as the current delay parameter group corresponding to the clock transmission link of the second output mode.

10. The configuration method for the server clock architecture according to claim 9, characterized in that, The calculation of the current delay time using all parameters in the current delay parameter group includes: Based on all parameters in the current delay parameter group, establish a second calculation relationship corresponding to the chipset as the transmitting end and a third calculation relationship corresponding to the external card as the transmitting end; The first delay time is calculated using the second calculation formula; The second delay time is calculated using the third calculation formula; and The maximum value between the first delay time and the second delay time is taken as the current delay time.

11. The configuration method for the server clock architecture according to claim 10, characterized in that, The second calculation formula is: T a =|(t) delay2 +t clkpcb4 +t data )-(t clkpcb5 +tclkbuffer2+t clkpcb6 )|+t clkskew ; Among them, T a Let t be the first delay time. delay2 For the eighth delay parameter, t data For the seventh delay parameter, t clkskew The output clock skew parameter is tclkbuffer2, which is the second delay parameter. clkpcb4 The first line delay parameter, t clkpcb5 The second line delay parameter, t clkpcb6 The delay parameter for the third line.

12. The configuration method for the server clock architecture according to claim 10, characterized in that, The third calculation formula is: T b =|(t) delay2 +t clkpcb4 )-(t clkpcb5 +tclkbuffer2+t clkpcb6 +t data )|+t clkskew ; Among them, T b t is the second delay time. delay2 For the eighth delay parameter, t data For the seventh delay parameter, t clkskew The output clock skew parameter is tclkbuffer2, which is the second delay parameter. clkpcb4 The first line delay parameter, t clkpcb5 The second line delay parameter, t clkpcb6 The delay parameter for the third line.

13. The configuration method for the server clock architecture according to claim 5, characterized in that, The server clock architecture includes a server motherboard. After determining whether the current transmission delay time meets the clock constraints of the server clock architecture, the configuration method further includes: Calculate the time difference between the current transmission delay and the constraint time corresponding to the clock constraint of the server clock architecture; and When the time difference is less than or equal to a preset difference, the position of the first-level clock buffer on the server motherboard is adjusted so that the time difference is greater than the preset difference.

14. The method for configuring a server clock architecture according to any one of claims 5-13, characterized in that, The calculation of the current transmission delay time of the clock transmission link in the clock output mode includes: Calculate the current transmission delay time of the clock transmission link when the clock output mode is in effect and both the first-level clock buffer and the second-level clock buffer are in bypass mode.

15. The configuration method for the server clock architecture according to claim 14, characterized in that, Adjusting the operating mode of the first-level clock buffer and / or the second-level clock buffer to ensure that the current transmission delay of the clock transmission link in the clock output mode meets the clock constraint includes: Either the first-level clock buffer or the second-level clock buffer is designated as the first adjustment buffer, and the other is designated as the second adjustment buffer; Switch the operating mode of the first adjustment buffer from the bypass mode to the phase-locked loop mode; Calculate the current transmission delay time of the clock transmission link when the clock output mode is in the clock output mode, and the first adjustment buffer is in the phase-locked loop mode and the second adjustment buffer is in the bypass mode; When the current transmission delay time meets the clock constraints of the server clock architecture, the server clock architecture configuration is determined to be complete. When the current transmission delay time does not meet the clock constraints of the server clock architecture, the operating mode of the second adjustment buffer is switched from the bypass mode to the phase-locked loop mode.

16. The configuration method for the server clock architecture according to claim 15, characterized in that, The method further includes: Calculate the current transmission delay time of the clock transmission link when the clock output mode is in effect and both the first adjustment buffer and the second adjustment buffer are in the phase-locked loop mode. When the current transmission delay time meets the clock constraints of the server clock architecture, the server clock architecture configuration is deemed complete; and When the current transmission delay time does not meet the clock constraints of the server clock architecture, a configuration error message is displayed.

17. The configuration method for the server clock architecture according to claim 15, characterized in that, The step of determining either the first-level clock buffer or the second-level clock buffer as the first adjustment buffer and the other as the second adjustment buffer includes: The second-level clock buffer is designated as the first adjustment buffer, and the first-level clock buffer is designated as the second adjustment buffer.

18. A computer-readable instruction product, comprising computer-readable instructions, characterized in that, When executed by a processor, the computer-readable instructions implement the steps of the configuration method for the server clock architecture according to any one of claims 5-17.

19. An electronic device, characterized in that, include: Memory, used to store computer-readable instructions; and A processor, configured to implement the steps of the configuration method for the server clock architecture as described in any one of claims 5-17 when executing the computer-readable instructions.

20. A non-volatile computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer-readable instructions, which, when executed by a processor, implement the steps of the server clock architecture configuration method as described in any one of claims 5-17.

Images