Array substrate, display panel, and display apparatus

Abstract

An array substrate, a display panel, and a display apparatus. The array substrate comprises: a base substrate (101), the base substrate (101) comprising a display area (AA) and a non-display area located on at least one side of the display area; multiple data lines (102), extending along a first direction and arranged along a second direction in the display area (AA), the second direction intersecting with the first direction; multiple binding terminal groups (104), located in the non-display area, each binding terminal group (104) comprising multiple first binding terminals (pd1) electrically connected to the multiple data lines (102), and multiple second binding terminals (pd2) located on at least one side of the multiple first binding terminals (pd1); multiple gate driving circuit signal lines (105), located in the non-display area, the multiple gate driving circuit signal lines (105) being electrically connected to a portion of the second binding terminals (pd2); and at least one detection line (106), located in the non-display area, the at least one detection line (106) being electrically connected to at least a portion of the second binding terminals (pd2) which do not correspond to the multiple gate driving circuit signal lines (105).

Description

Array substrate, display panel and display device

[0001] Cross-reference of related applications

[0002] This application claims priority to Chinese Patent Application No. PCT / CN2024 / 095814, filed on May 28, 2024, entitled "Array Substrate, Display Panel and Display Device", and Chinese Patent Application No. 202410831197.7, filed on June 25, 2024, entitled "Array Substrate, Display Panel and Display Device", the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to the field of display technology, and in particular to an array substrate, a display panel, and a display device. Background Technology

[0004] Over the decades, the television industry has undergone a dramatic transformation, much like the mobile phone industry, evolving from bulky black-and-white TVs to color TVs, and now to large-screen smart displays. Technological innovation has been relentless. With product updates and the increasing demands of users for monitors, there's a need to constantly break with traditional technologies. Beyond advancements in low cost, high transmittance, and high contrast, the integration of sensors into display products—such as adding light and temperature sensors—aims to enhance the user experience. Summary of the Invention

[0005] The array substrate, display panel, and display device provided in this disclosure are specifically designed as follows:

[0006] On one hand, embodiments of this disclosure provide an array substrate, comprising:

[0007] A substrate, the substrate including a display area and a non-display area located on at least one side of the display area;

[0008] Multiple data lines extend along a first direction and are arranged along a second direction in the display area, the second direction intersecting the first direction;

[0009] Multiple bonding terminal groups are located in the non-display area. Each bonding terminal group includes multiple first bonding terminals electrically connected to the multiple data lines, and multiple second bonding terminals located on at least one side of the multiple first bonding terminals.

[0010] Multiple gate drive circuit signal lines are located in the non-display area, and the multiple gate drive circuit signal lines are electrically connected to a portion of the second bonding terminals;

[0011] At least one detection line is located in the non-display area, and the at least one detection line is electrically connected to at least a portion of the second bonding terminals that do not correspond to the plurality of gate drive circuit signal lines.

[0012] In some embodiments, in the array substrate provided in the present disclosure, a plurality of bonding terminal groups are arranged along the second direction, the first and last two bonding terminal groups are the first bonding terminal groups, and the remaining bonding terminal groups are the second bonding terminal groups;

[0013] The plurality of second bonding terminals of the same bonding terminal group are located on both sides of the plurality of first bonding terminals in the second direction;

[0014] The plurality of gate drive circuit signal lines are electrically connected to at least a portion of the second bonding terminals in at least one of the first bonding terminal groups that are far from the second bonding terminal group;

[0015] The at least one detection line is electrically connected to at least one of the second bonding terminals in the first bonding terminal group that is close to the second bonding terminal group and to at least a portion of the second bonding terminal group.

[0016] In some embodiments, in the array substrate provided in the present disclosure, the non-display area includes a first non-display area and a second non-display area placed opposite each other, and two third non-display areas connecting the first non-display area and the second non-display area;

[0017] The plurality of said bonding terminal groups are arranged along the second direction within the first non-display area;

[0018] One end of the at least one detection line is electrically connected to a second binding terminal of a first binding terminal group near the second binding terminal group, and the other end is electrically connected to a second binding terminal of another first binding terminal group near the second binding terminal group, and the display area is surrounded by the second non-display area and the third non-display area.

[0019] In some embodiments, the array substrate provided in the present disclosure further includes a gate driving circuit located in the non-display area, and the at least one detection line is disposed between the gate driving circuit and the display area.

[0020] In some embodiments, the array substrate provided in this disclosure further includes multiple shielding lines between the gate driving circuit and the display area, the multiple shielding lines being disposed on at least one side of at least a portion of the detection lines.

[0021] In some embodiments, in the array substrate provided in the present disclosure, the at least one detection line includes a temperature detection line, the shielding line is in the same layer and made of the same material as the temperature detection line, and the shielding line is located on both sides of the temperature detection line.

[0022] In some embodiments, in the array substrate provided in the present disclosure, the distance between the shielding line and the temperature sensing line is greater than or equal to 4 μm.

[0023] In some embodiments, the array substrate provided in this disclosure further includes a low-level signal line that is on the same layer and made of the same material as the temperature sensing line. The low-level signal line is located between the shielded line on the side of the temperature sensing line away from the display area and the gate driving circuit.

[0024] In some embodiments, the array substrate provided in the present disclosure further includes a gate signal output line electrically connected to the gate driving circuit. The gate signal output line includes a first gate signal output portion located in the source / drain metal layer. The orthographic projection of the temperature sensing line on the substrate intersects with the orthographic projection of the first gate signal output portion on the substrate.

[0025] In some embodiments, in the array substrate provided in the present disclosure, the temperature sensing line includes a bent structure, and at least a portion of the bent structure is a repeating unit.

[0026] In some embodiments, the array substrate provided in this disclosure further includes multiple electrostatic discharge structures, multiple dummy lines, and a common electrode line;

[0027] The dummy line is provided within the area enclosed by the temperature sensing line, the plurality of electrostatic discharge structures, and the common electrode line; and the dummy line is provided on both sides of the temperature sensing line on the side of the plurality of electrostatic discharge structures facing the display area.

[0028] In some embodiments, in the array substrate provided in this disclosure, the at least one detection line includes a temperature sensing detection line;

[0029] The array substrate also includes a ground line and a common electrode line located in the non-display area, and the temperature sensing line is disposed between the ground line and the common electrode line.

[0030] In some embodiments, in the array substrate provided in the present disclosure, at least some of the detection lines include a plurality of sub-detection lines that are disposed in different layers and electrically connected, and the switching position between the sub-detection lines is located at at least one corner of the non-display area.

[0031] In some embodiments, in the array substrate provided in the present disclosure, the at least one detection line includes a temperature sensing detection line, and the ratio of the resistance of the longest sub-detection line among the plurality of sub-detection lines to the total resistance of the temperature sensing detection line is greater than or equal to 90% and less than 100%.

[0032] In some embodiments, in the array substrate provided in the present disclosure, the at least one detection line includes a temperature detection line and a light detection line, wherein the temperature detection line is located on the side of the light detection line away from the display area.

[0033] In some embodiments, in the array substrate provided in the present disclosure, the non-display area includes a plurality of fan-out areas arranged along the second direction, and a plurality of bonding areas located on the side of the plurality of fan-out areas away from the display area;

[0034] The plurality of binding terminal groups are located in the plurality of binding areas;

[0035] At least a portion of the detection lines are located between at least a portion of the fan-out areas and are connected between the second bonding terminals of two adjacent bonding terminal groups.

[0036] In some embodiments, in the array substrate provided in the present disclosure, the at least one detection line includes a temperature detection line, the temperature detection line including a straight portion that is substantially parallel to the edge of the adjacent fan-out area, and a zigzag portion integrally disposed with the straight portion.

[0037] In some embodiments, in the array substrate provided in the present disclosure, the at least one detection line includes a temperature sensing detection line, and the temperature sensing detection line is continuously disposed in the same conductive layer.

[0038] On the other hand, this disclosure provides a display panel including the array substrate provided in this disclosure and a counter substrate disposed opposite to the array substrate.

[0039] On the other hand, this disclosure provides a display device, including the display panel provided in this disclosure and a backlight module located on the light-incident side of the display panel. Attached Figure Description

[0040] Figure 1 is a schematic diagram of detecting the temperature of a display panel in related technologies;

[0041] Figure 2 is a schematic diagram of an array substrate provided in an embodiment of this disclosure;

[0042] Figure 3 is a structural schematic diagram of the first binding terminal group from the left in Figure 2;

[0043] Figure 4 is a schematic diagram of the binding terminal at the non-edge location in Figure 2;

[0044] Figure 5 is a structural schematic diagram of the first binding terminal group from the right in Figure 2;

[0045] Figure 6 is an enlarged structural diagram of region Z1 in Figure 2;

[0046] Figure 7 is an enlarged structural diagram of region Z2 in Figure 6;

[0047] Figure 8 is an enlarged structural diagram of region Z3 in Figure 2;

[0048] Figure 9 is an enlarged structural diagram of region Z4 in Figure 8;

[0049] Figure 10 is an enlarged structural diagram of region Z5 in Figure 2;

[0050] Figure 11 is an enlarged structural diagram of region Z6 in Figure 10;

[0051] Figure 12 is an enlarged structural diagram of region Z7 in Figure 2;

[0052] Figure 13 is an enlarged structural diagram of region Z8 in Figure 12;

[0053] Figure 14 is a schematic diagram of another structure of the array substrate provided in the embodiments of this disclosure;

[0054] Figure 15 is a schematic diagram of another structure of the array substrate provided in the embodiments of this disclosure;

[0055] Figure 16 is a schematic diagram of another structure of the array substrate provided in the embodiments of this disclosure;

[0056] Figure 17 is a schematic diagram of another structure of the array substrate provided in the embodiments of this disclosure;

[0057] Figure 18 is a schematic diagram of the temperature sensing line in the array substrate shown in Figure 17;

[0058] Figure 19 is a schematic diagram of the structure of the display panel provided in an embodiment of this disclosure;

[0059] Figure 20 is a schematic diagram of the structure of the display device provided in the embodiment of this disclosure. Detailed Implementation

[0060] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. It should be noted that, for clarity, the thickness of layers, films, panels, regions, etc., is enlarged in the drawings. Exemplary embodiments are described in this disclosure with reference to cross-sectional views as schematic diagrams of idealized embodiments. Thus, deviations from the shape of the figures will be expected as a result of, for example, manufacturing techniques and / or tolerances. Therefore, the embodiments described in this disclosure should not be construed as limited to the specific shape of the regions shown in this disclosure, but rather include deviations in shape caused, for example, by manufacturing processes. For example, a region illustrated or described as flat may typically have rough and / or non-linear characteristics; a sharp corner illustrated may be rounded, etc. Therefore, the regions shown in the figures are schematic in nature, and their dimensions and shapes are not intended to illustrate the precise shape of the regions or reflect true proportions; their purpose is merely to illustrate the content of this disclosure. And throughout, the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions. To keep the following description of the embodiments of this disclosure clear and concise, detailed descriptions of known functions and known components are omitted.

[0061] Unless otherwise defined, the technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure and the claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that the element or object preceding the word covers the element or object listed following the word and its equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “inner,” “outer,” “upper,” and “lower” are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described object changes.

[0062] In the following description, when an element or layer is referred to as "on" or "connected to" another element or layer, the element or layer may be directly on or directly connected to the other element or layer, or there may be intermediate elements or intermediate layers. When an element or layer is referred to as "located on one side of" another element or layer, the element or layer may be directly on or directly connected to the other element or layer, or there may be intermediate elements or intermediate layers. However, when an element or layer is referred to as "directly on" or "directly connected to" another element or layer, no intermediate elements or intermediate layers are present. The term "and / or" includes any and all combinations of one or more of the related listed items.

[0063] While pursuing high image quality, related LCD products are also gradually developing towards intelligence and multi-functionality. In some embodiments, Figure 1 is a schematic diagram of detecting the display panel temperature in related technologies. As shown in Figure 1, the panel temperature can be detected by integrating the thermistor onto the panel's printed circuit board (XPCB) or timing control board (TCON) as an external device, and the driving voltage can be adjusted according to the detected temperature to improve the display effect. However, the main drawback of the external device is that it cannot truly reflect the temperature inside the liquid crystal cell. Moreover, given the impact of the external device on the product's appearance, it is impractical to add thermistors to different locations on the panel. In addition, due to the continuous charging and discharging of the clock signal, the temperature of the gate drive circuit area of ​​the panel is likely to be higher than that of the display area. However, it may be impossible to add external thermistors to locations like the gate drive circuit area that require key temperature monitoring, making it impossible to identify the temperature in these locations.

[0064] To at least improve the aforementioned technical problems existing in related technologies, this disclosure provides an array substrate. Figure 2 is a structural schematic diagram of an array substrate provided in this disclosure. Figure 3 is a structural schematic diagram of the first bonding terminal group from the left in Figure 2. Figure 4 is a structural schematic diagram of the bonding terminals at the non-edge location in Figure 2. Figure 5 is a structural schematic diagram of the first bonding terminal group from the right in Figure 2. Figure 6 is an enlarged structural schematic diagram of the Z1 region in Figure 2. Figure 7 is an enlarged structural schematic diagram of the Z2 region in Figure 6. Figure 8 is an enlarged structural schematic diagram of the Z3 region in Figure 2. Figure 9 is an enlarged structural schematic diagram of the Z4 region in Figure 8. Figure 10 is an enlarged structural schematic diagram of the Z5 region in Figure 2. Figure 11 is an enlarged structural schematic diagram of the Z6 region in Figure 10. Figure 12 is an enlarged structural schematic diagram of the Z7 region in Figure 2. Figure 13 is an enlarged structural schematic diagram of the Z8 region in Figure 12.

[0065] In some embodiments, as shown in Figures 2 to 13, the array substrate provided in this disclosure may include:

[0066] The substrate 101 includes a display area AA and a non-display area located on at least one side of the display area AA. The non-display area may include a first non-display area BB1 and a second non-display area BB2 disposed on opposite sides of the display area AA, and two third non-display areas BB3 connecting the first non-display area BB1 and the second non-display area BB2. The first non-display area BB1 may be provided with at least one bonding area and at least one fan-out area FA, and at least one third non-display area BB3 may be provided with a gate driving circuit GOA. In some embodiments, the display area AA includes an array of red sub-pixel areas, green sub-pixel areas, blue sub-pixel areas, etc. The substrate 101 is a substrate that allows visible light to pass through, such as glass, quartz, plastic, etc.

[0067] Multiple data lines 102 and multiple gate lines 103 are intersecting within the display area AA; wherein, the data lines 102 extend along a first direction Y, and the gate lines 103 extend along a second direction X; the data lines 102 may be located in the source / drain metal layer (SD), and the gate lines 103 may be located in the gate metal layer (Gate), or the data lines 102 may be located in the gate metal layer (Gate), and the gate lines 103 may be located in the source / drain metal layer (SD). In some embodiments, the material of the source / drain metal layer (SD) may include metals such as molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), chromium (Cr), and nickel (Ni), and the source / drain metal layer (SD) may be a single-layer structure or a stacked structure, for example, the source / drain metal layer (SD) may be a stacked structure composed of a titanium metal layer / aluminum metal layer / titanium metal layer. The material of the gate metal layer can include metals such as molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), chromium (Cr), and nickel (Ni). The gate metal layer can be a single-layer structure or a stacked structure. For example, the gate metal layer is a single-layer structure composed of a molybdenum metal layer.

[0068] Multiple bonding terminal groups 104 are located in the non-display area. The bonding terminal groups 104 can be electrically connected to the chip-on-film (COF) film. In some embodiments, the multiple bonding terminal groups 104 can be arranged in the first non-display area BB1 along the second direction X. Optionally, the bonding terminal group 104 includes multiple first bonding terminals pd1 electrically connected to multiple data lines 102, and multiple second bonding terminals pd2 located on at least one side of the multiple first bonding terminals pd1. In some embodiments, in order to simplify the design of the bonding terminal group 104 and the COF bonding process of the panel, the bonding terminal group 104 can be designed with a symmetrical shape. Therefore, in this disclosure, the second bonding terminals pd2 can be provided on both the left and right sides of the first bonding terminals pd1.

[0069] Multiple gate drive circuit signal lines 105 are located in the non-display area and are electrically connected to a portion of the second bonding terminals pd2. In some embodiments, the gate drive circuit signal lines 105 are located in the gate metal layer and may include frame start signal lines STV1A and STV1B, and a total reset signal line. The system includes one or more of the following: reset signal line STV0, clock signal lines CLK1 to CLK12 (the number of clock signal lines is not limited, but this example uses 12 lines), noise reduction signal lines VDDO and VDDE, and low-level signal lines. The frame start signal line can be one or more, and is not limited here. This example uses two frame start signal lines: frame start signal lines STV1A and STV1B are the trigger input signals for odd and even rows, respectively. Clock signal lines CLK1 to CLK12 provide the output voltage for each row's gate. Noise reduction signal lines VDDO and VDDE provide input signals to the noise reduction unit of the gate drive circuit, with a 50% duty cycle and alternating high and low levels. The first low-level signal line provides an internal low-level voltage to the gate drive circuit.

[0070] At least one detection line 106 is located in the non-display area, and at least one detection line 106 is electrically connected to at least a portion of the second bonding terminals pd2 that are not corresponding to the multiple gate drive circuit signal lines 105. In some embodiments, the detection line 106 may be integrated into the source / drain metal layer (SD) and / or the gate metal layer (Gate), and the detection line 106 may include a temperature sensing line 1061 to determine the current temperature by monitoring the change in resistance value of the temperature sensing line 1061, taking advantage of the characteristic that the metal resistance value changes with temperature.

[0071] In the array substrate provided in this embodiment, by integrating the detection line 106, including the temperature sensing detection line 1061, into the array substrate, the panel temperature can be monitored more accurately compared to an external solution. Furthermore, the detection line 106 is electrically connected to the idle second bonding terminal pd2 in the bonding terminal group 104, eliminating the need to modify the structure of the bonding terminal group 104 and the COF (Chip-on-Foil) film. Therefore, it has high compatibility with related products and can effectively save costs.

[0072] In some embodiments, in the array substrate provided in the present disclosure, as shown in Figures 2 to 5, a plurality of bonding terminal groups 104 are arranged along the second direction X, the first and last bonding terminal groups 104 are the first bonding terminal groups 1041, and the remaining bonding terminal groups 104 are the second bonding terminal groups 1042; a plurality of second bonding terminals pd2 of the same bonding terminal group 104 are located on both sides of a plurality of first bonding terminals pd1 in the second direction X; a plurality of gate drive circuit signal lines 105 are electrically connected to at least a portion of the second bonding terminals pd2 in at least one first bonding terminal group 1041 that are far from the second bonding terminal group 1042; in some embodiments, gate drive circuit signal lines 105 are provided in both the left and right third non-display areas BB3, the gate drive circuit signal lines 105 in the left third non-display area BB3 are electrically connected to the second bonding terminals pd2 on the left edge of the left first bonding terminal group 1041, and the gate drive circuit signal lines 105 in the right third non-display area BB3 are electrically connected to the second bonding terminals pd2 on the right edge of the right first bonding terminal group 1041. Optionally, portions of the second binding terminal pd2 at the right edge of the left-end first binding terminal group 1041, the second binding terminal pd2 at the left edge of the right-end first binding terminal group 1041, and the second binding terminals pd2 at the left and right edges of the middle second binding terminal group 1042 are electrically connected to the common electrode lead 107. The detection line 106 can be electrically connected to the idle terminals (e.g., terminals not connected to the common electrode lead 107) of the second binding terminal pd2 at the right edge of the left-end first binding terminal group 1041, and / or the second binding terminal pd2 at the left edge of the right-end first binding terminal group 1041, and / or the second binding terminals pd2 at the left and right edges of the middle second binding terminal group 1042. Optionally, after the terminals and the detection line 106 are connected, some terminals remain.

[0073] To improve the accuracy of temperature detection in display area AA, the temperature sensing line 1061 should be positioned close to display area AA. This is because the temperature sensing drive also has traces on the printed circuit board (PCB). The temperature coefficient of resistance (TCR) of the traces on the PCB and the temperature sensing line 1061 inside the panel enclosure may not be the same. To minimize temperature detection errors, the resistance of the temperature sensing traces inside the enclosure should be as high as possible. The greater the difference between the TCR and the drive signal traces on the PCB, the better the accuracy of temperature detection inside the enclosure. In some embodiments, as shown in Figures 2 to 13, to ensure that the temperature sensing line 1061 has a large resistance, one end of the temperature sensing line 1061 can be electrically connected to the second binding terminal pd2 of the left first binding terminal group 1041 near the second binding terminal group 1042, and the other end can be electrically connected to the second binding terminal pd2 of the right first binding terminal group 1041 near the second binding terminal group 1042, thus surrounding display area AA within the second non-display area BB2 and the third non-display area BB3. Since the second non-display area BB2 has only a few wirings such as ground line 109 and common electrode line 110, there is ample wiring space. To increase the resistance of the temperature detection line 1061, a bend can be made within the second non-display area BB2, as shown in Figures 6 and 7. The temperature detection line 1061 includes a bend structure 1061', at least part of which is a repeating unit. Furthermore, to ensure that the temperature detection line 1061 is as close as possible to the AA area, it can be positioned between the display area AA and the gate drive circuit GOA.

[0074] In some embodiments, as shown in Figures 8 and 9, the temperature detection line 1061 needs to cross the gate signal output line 108 within the two third non-display areas BB3 on the left and right. Optionally, within the third non-display area BB3, the temperature detection line 1061 is located in the gate metal layer, and the gate signal output line 108 includes a first gate signal output portion 108' located in the source-drain metal layer (SD) and a second gate signal output portion 108" located in the gate metal layer (Gate). The temperature detection line 1061 intersects with the first gate signal output portion 108', and the second gate signal output portion 108" is located on the side of the temperature detection line 1061 closer to the display area AA. The disturbance of the first gate signal output section 108' to the temperature detection line 1061 may cause an increase in temperature detection error. In addition, there are many other signal lines (such as low-level signal line 111 and light detection line 1062) in the two third non-display areas BB3 on the left and right sides of the panel. Shielding lines 112 of the same layer and material and floating arrangement can be added to both sides of the temperature detection line 1061 in the two third non-display areas BB3. This allows the low-level signal line 111, shielding line 112, temperature detection line 1061, and light detection line 1062 to be arranged sequentially in the direction close to the display area AA, so as to shield the electromagnetic interference caused by the low-level signal line 111 and light detection line 1062 to the temperature detection line 1061 and improve the accuracy of temperature detection. Optionally, the low-level signal line 111 is electrically connected to at least a portion of the transistors in the gate drive circuit GOA to provide noise reduction for the pull-up node and / or output of the gate drive circuit GOA. In some embodiments, to avoid short-circuiting the temperature sensing line 1061 and the shielding line 112, the spacing between the temperature sensing line 1061 and the shielding line 112 needs to be greater than the process limit value, for example, greater than 4μm.

[0075] Referring to Figures 6 to 9, it can be seen that the photosensitive detection line 1062 intersects with the second gate signal output section 108”. However, in the direction from the first non-display area BB1 to the second non-display area BB2, the photosensitive detection line 1062 becomes less dense, resulting in different numbers of photosensitive detection lines 1062 coupled to different second gate signal output sections 108”, which affects the display performance. This disclosure can add a load compensation design to the second gate signal output section 108”, designing at least some of the photosensitive detection lines 1062 to include a main line TL and a branch line BL, and ensuring that the sum of the number of main lines TL and the number of branch lines BL crossing on different second gate signal output sections 108” is the same, so that the coupling pull effect is the same and no display abnormality problem occurs.

[0076] In some embodiments, in the array substrate provided in the present disclosure, as shown in Figures 10 to 13, in order to improve etching uniformity, a first dummy line 114 can be provided in the area enclosed by the temperature sensing line 1061, multiple electrostatic discharge structures 113, and common electrode line 110. The first dummy line 114 is provided on both sides of the temperature sensing line 1061 on the side of the multiple electrostatic discharge structures 113 facing the display area AA, and a second dummy line 115 is provided between the common electrode line 110 and the low-level signal line 111.

[0077] In some embodiments, as shown in Figures 10 and 11, the array substrate may further include a fan-out line 116 electrically connected to the data line 102. The fan-out line 116 includes a first fan-out portion 116' located on the source / drain metal layer (SD) and a second fan-out portion 116" located on the gate metal layer (Gate). The first fan-out portion 116' and the second fan-out portion 116" are electrically connected to an electrostatic discharge structure 113. The photosensitive detection line 1062 includes a first detection portion 1062' located on the gate metal layer (Gate) and a second detection portion 1062" located on the source / drain metal layer (SD). The first fan-out portion 116' and the first detection portion 1062' are intersecting.

[0078] The first detection unit 1062' causes the load on the data line 102 connected to the first fan-out unit 116' to be greater than the load on the corresponding data line 102 of the second bonding terminal group 1042, affecting the display effect. Therefore, as shown in Figures 12 and 13, a compensation line 117 intersecting with the fan-out line 116 connected to the second bonding terminal group 1042 can be provided. The compensation line 117 can be located in the gate metal layer and electrically connected to the second bonding terminal pd2 of the second bonding terminal group 1042. The extension line of the compensation line 117 in the second direction X is approximately coincident with the detection line 106. In other words, the line width and line spacing of the compensation line 117 can be approximately the same as the line width and line spacing of the detection line 106.

[0079] It should be noted that, in the embodiments provided in this disclosure, due to limitations in process conditions or the influence of other factors such as measurement, "approximately coincident" may be exactly coincident, or there may be some deviation (e.g., a deviation of ±2μm). Therefore, as long as the relationship of "approximately coincident" between related features meets the allowable error, it falls within the protection scope of this disclosure. "Approximately identical" may be completely identical, or there may be some deviation (e.g., a deviation of ±5%). Therefore, as long as the relationship of "approximately identical" between related features meets the allowable error, it falls within the protection scope of this disclosure.

[0080] In some embodiments, to improve etching uniformity, as shown in Figures 10 to 13, a third dummy line 119 may be provided on the side of the inclined portion of the first fan-out portion 116' near the first detection portion 1062', between the second fan-out portion 116" and the common electrode line 110, between the detection line 106 and the common electrode line 110, between the detection line 106 and the second fan-out portion 116", between the detection line 106 and the first common electrode connection line 118, between the compensation line 117 and the common electrode line 110, between the compensation line 117 and the first common electrode connection line 118, and on the side of the inclined portion of the first fan-out portion 116' near the first common electrode connection line 118.

[0081] In some embodiments, FIG14 is a schematic diagram of another structure of the array substrate provided in this disclosure. As shown in FIG14, the temperature sensing line 1061 can also be disposed between the ground line 109 and the common electrode line 110. The common electrode line 110 and the ground line 109 are both stable DC when the panel is working, which will not cause disturbance to the temperature sensing line 1061, thus improving the accuracy of temperature sensing.

[0082] In the design of the detection line 106, if it is necessary to cross with other metal signal lines on the same layer, it is not possible to use only one type of metal wiring throughout the entire process. In this case, multiple conductive layers can be used for wiring, and the crossing position can be selected in a corner with a large wiring space. Based on this, as shown in Figures 15 and 16, at least a portion of the detection line 106 of this disclosure may include multiple sub-detection lines SL that are arranged on different layers and electrically connected. The crossing position between the sub-detection lines SL is located at at least one corner C in the non-display area.

[0083] It should be noted that, in order to ensure a high resistance of the temperature sensing line 1061, the temperature sensing line 1061 in this disclosure can be continuously routed on a single conductive layer (e.g., a gate metal layer). However, in some embodiments, the temperature sensing line 1061 can also be routed using different conductive layers. In this case, to better ensure temperature sensing accuracy, this disclosure limits the resistance ratio of the main metal (which can be understood as the longest sub-sensor line) to be greater than or equal to 90% and less than 100% of the total resistance of the temperature sensing line 1061.

[0084] In some embodiments, FIG17 shows another structural schematic diagram of the array substrate provided in the present disclosure. As shown in FIG17, the present disclosure may also place the detection line 106 in the region between two fan-out regions FA. The advantage of this design is that the detection line 106 does not need to cross any other signals, and is subject to minimal interference. In some embodiments, the temperature sensing detection line 1061 is placed between two fan-out regions FA. In order to ensure a large resistance of the temperature sensing detection line 1061, the temperature sensing detection line 1061 may be designed with a broken line along the edge of the wiring of the fan-out region FA. Specifically, as shown in FIG17 and FIG18, the temperature sensing detection line 1061 includes a straight portion 611 that is substantially parallel to the edge of the adjacent fan-out region FA, and a broken line portion 612 integrally formed with the straight portion 611.

[0085] It should be noted that, in the embodiments provided by the present invention, due to limitations of process conditions or the influence of other factors such as measurement, the above-mentioned "approximately parallel" may be exactly parallel, or there may be some deviation (e.g., the included angle is in the range of 0° to 5°). Therefore, as long as the "approximately parallel" relationship between the above-mentioned features satisfies the allowable error, it is within the protection scope of the present invention.

[0086] In some embodiments, as shown in Figures 6 to 13, the array substrate provided in this disclosure may further include a second common electrode connection line (com), a data test line (add), etc. The data test line (add) is used to detect the applied voltage signal during array substrate testing, improving the array test yield. Specifically, if a data line is open, the ESD connection on the DP side (i.e., the side where the first non-display area BB1 is located) will be a high-level signal, and the ESD connection on the DPO side (i.e., the side where the second non-display area BB2 is located) will be a low-level signal. Other essential components of the array substrate are understood by those skilled in the art and will not be described in detail here, nor should they be construed as limiting this disclosure.

[0087] Based on the same inventive concept, this disclosure provides a display panel. Figure 19 is a schematic diagram of the structure of the display panel provided in this disclosure. As shown in Figure 19, the display panel of this disclosure includes the array substrate 001 provided in this disclosure embodiment, and a counter substrate 002 disposed opposite to the array substrate 001. Since the principle by which this display panel solves the problem is similar to the principle by which the array substrate solves the problem, the implementation of this display panel can refer to the embodiment of the array substrate described above, and repeated details will not be described again.

[0088] In some embodiments, as shown in FIG19, in the display panel provided in the present disclosure, a liquid crystal layer 003 may be disposed between the array substrate 001 and the opposing substrate 002. A first polarizer 004 may be disposed on the side of the array substrate 001 away from the opposing substrate 002, and a second polarizer 005 may be disposed on the side of the opposing substrate 002 away from the array substrate 001. The polarization direction of the first polarizer 004 and the polarization direction of the second polarizer 005 are perpendicular to each other. Other essential components of the display panel are understood by those skilled in the art and will not be described in detail here, nor should they be construed as limiting the present disclosure.

[0089] Based on the same inventive concept, this disclosure provides a display device, as shown in FIG20, including the display panel PNL provided in this disclosure and a backlight module BLU located on the light-incident side of the display panel PNL. The backlight module BLU can be a direct-lit backlight module or an edge-lit backlight module. Optionally, the edge-lit backlight module may include LED strips, stacked reflective sheets, light guide plates, diffusers, prism groups, etc., with the LED strips located on one side of the thickness direction of the light guide plate. The direct-lit backlight module may include a matrix light source, a reflective sheet, a diffuser plate, and a brightness enhancement film stacked on the light-emitting side of the matrix light source, with the reflective sheet including openings directly opposite the positions of the LEDs in the matrix light source. The LEDs in the LED strips and the LEDs in the matrix light source can be light-emitting devices (LEDs), such as quantum dot LEDs.

[0090] In some embodiments, the LEDs can also be micro-light-emitting devices (such as Mini LEDs and Micro LEDs). Sub-millimeter or even micrometer-scale micro-light-emitting devices, like organic light-emitting devices (OLEDs), are self-emissive devices. Like OLEDs, they offer advantages such as high brightness, ultra-low latency, and ultra-wide viewing angles. Furthermore, because inorganic light-emitting devices emit light based on more stable and lower-resistance metal semiconductors, they offer advantages over organic light-emitting devices (based on organic materials) in terms of lower power consumption, greater resistance to high and low temperatures, and longer lifespan. Moreover, when micro-light-emitting devices are used as backlights, they can achieve more precise dynamic backlighting effects, effectively improving screen brightness and contrast while also solving the glare problem caused by traditional dynamic backlighting between bright and dark areas of the screen, thus optimizing the visual experience.

[0091] In some embodiments, the display device provided in this disclosure can be any product or component with display function, such as a monitor, projector, 3D printer, virtual reality device, mobile phone, tablet computer, television, laptop computer, digital photo frame, navigator, smartwatch, fitness wristband, personal digital assistant, etc. Optionally, the display device provided in this disclosure includes, but is not limited to, components such as: radio frequency unit, network module, audio output & input unit, sensor, display unit, user input unit, interface unit, and control chip. Optionally, the control chip is a central processing unit, digital signal processor, system-on-a-chip (SoC), etc. For example, the control chip may also include memory, power module, etc., and achieve power supply and signal input / output functions through additionally provided wires, signal lines, etc. For example, the control chip may also include hardware circuits and computer-executable code. The hardware circuit may include conventional very large-scale integrated circuits (VLSI) or gate arrays, as well as existing semiconductors or other discrete components such as logic chips, transistors, etc.; the hardware circuit may also include field-programmable gate arrays, programmable array logic, programmable logic devices, etc. Furthermore, the above structure does not constitute a limitation on the display device provided in the embodiments of this disclosure. In other words, the display device provided in the embodiments of this disclosure may include more or fewer of the above components, or combine certain components, or arrange different components.

[0092] Although preferred embodiments of this disclosure have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this disclosure.

[0093] Obviously, those skilled in the art can make various modifications and variations to the embodiments of this disclosure without departing from the spirit and scope of the embodiments of this disclosure. Therefore, if these modifications and variations to the embodiments of this disclosure fall within the scope of the claims of this disclosure and their equivalents, this disclosure is also intended to include these modifications and variations.

Claims

1. An array substrate, wherein, include: A substrate, the substrate including a display area and a non-display area located on at least one side of the display area; Multiple data lines extend along a first direction and are arranged along a second direction in the display area, the second direction intersecting the first direction; Multiple bonding terminal groups are located in the non-display area. Each bonding terminal group includes multiple first bonding terminals electrically connected to the multiple data lines, and multiple second bonding terminals located on at least one side of the multiple first bonding terminals. Multiple gate drive circuit signal lines are located in the non-display area, and the multiple gate drive circuit signal lines are electrically connected to a portion of the second bonding terminals; At least one detection line is located in the non-display area, and the at least one detection line is electrically connected to at least a portion of the second bonding terminals that do not correspond to the plurality of gate drive circuit signal lines.

2. The array substrate as claimed in claim 1, wherein, The plurality of the bonding terminal groups are arranged along the second direction, with the first and last two bonding terminal groups being the first bonding terminal groups and the remaining bonding terminal groups being the second bonding terminal groups; The plurality of second bonding terminals of the same bonding terminal group are located on both sides of the plurality of first bonding terminals in the second direction; The plurality of gate drive circuit signal lines are electrically connected to at least a portion of the second bonding terminals in at least one of the first bonding terminal groups that are far from the second bonding terminal group; The at least one detection line is electrically connected to at least one of the second bonding terminals in the first bonding terminal group that is close to the second bonding terminal group and to at least a portion of the second bonding terminal group.

3. The array substrate as described in claim 2, wherein, The non-display area includes a first non-display area and a second non-display area that are opposite to each other, and two third non-display areas that connect the first non-display area and the second non-display area; The plurality of said bonding terminal groups are arranged along the second direction within the first non-display area; One end of the at least one detection line is electrically connected to a second binding terminal of a first binding terminal group near the second binding terminal group, and the other end is electrically connected to a second binding terminal of another first binding terminal group near the second binding terminal group, and the display area is surrounded by the second non-display area and the third non-display area.

4. The array substrate according to any one of claims 1 to 3, wherein, It also includes a gate driving circuit located in the non-display area, and the gate driving circuit and the display area are provided with the at least one detection line.

5. The array substrate as claimed in claim 4, wherein, It also includes multiple shielding lines between the gate driving circuit and the display area, the multiple shielding lines being disposed on at least one side of at least a portion of the detection lines.

6. The array substrate as claimed in claim 5, wherein, The at least one detection line includes a temperature sensing detection line, the shielding line is in the same layer and made of the same material as the temperature sensing detection line, and the shielding line is located on both sides of the temperature sensing detection line.

7. The array substrate as claimed in claim 6, wherein, The distance between the shielding wire and the temperature sensing wire is greater than or equal to 4μm.

8. The array substrate as claimed in claim 6 or 7, wherein, It also includes a low-level signal line that is on the same layer and made of the same material as the temperature sensing line, and the low-level signal line is located between the shielded line on the side of the temperature sensing line away from the display area and the gate driving circuit.

9. The array substrate according to any one of claims 6 to 8, wherein, It also includes a gate signal output line electrically connected to the gate driving circuit. The gate signal output line includes a first gate signal output section located in the source and drain metal layer. The orthographic projection of the temperature sensing line on the substrate intersects with the orthographic projection of the first gate signal output section on the substrate.

10. The array substrate according to any one of claims 6 to 9, wherein, The temperature sensing line includes a bent structure, and at least a portion of the bent structure is a repeating unit.

11. The array substrate according to any one of claims 6 to 10, wherein, It also includes multiple electrostatic discharge structures, multiple dummy lines, and a common electrode line; The dummy line is provided within the area enclosed by the temperature sensing line, the plurality of electrostatic discharge structures, and the common electrode line; and the dummy line is provided on both sides of the temperature sensing line on the side of the plurality of electrostatic discharge structures facing the display area.

12. The array substrate according to any one of claims 1 to 3, wherein, The at least one detection line includes a temperature-sensing detection line; The array substrate also includes a ground line and a common electrode line located in the non-display area, and the temperature sensing line is disposed between the ground line and the common electrode line.

13. The array substrate according to any one of claims 1 to 12, wherein, At least a portion of the detection lines include multiple sub-detection lines that are arranged in different layers and electrically connected, and the switching positions between the sub-detection lines are located at at least one corner of the non-display area.

14. The array substrate as claimed in claim 13, wherein, The at least one detection line includes a temperature sensing detection line, and the ratio of the resistance of the longest sub-detection line to the total resistance of the temperature sensing detection line is greater than or equal to 90% and less than 100%.

15. The array substrate according to any one of claims 1 to 14, wherein, The at least one detection line includes a temperature detection line and a light detection line, wherein the temperature detection line is located on the side of the light detection line away from the display area.

16. The array substrate according to any one of claims 1 to 3, wherein, The non-display area includes a plurality of fan-out areas arranged along the second direction, and a plurality of binding areas located on the side of the plurality of fan-out areas away from the display area; The plurality of binding terminal groups are located in the plurality of binding areas; At least a portion of the detection lines are located between at least a portion of the fan-out areas and are connected between the second bonding terminals of two adjacent bonding terminal groups.

17. The array substrate as claimed in claim 16, wherein, The at least one detection line includes a temperature-sensing detection line, which includes a straight section that is substantially parallel to the edge of the adjacent fan-out area and a broken section integrally formed with the straight section.

18. The array substrate according to any one of claims 1 to 17, wherein, The at least one detection line includes a temperature sensing detection line, which is continuously arranged in the same conductive layer.

19. A display panel, wherein, It includes an array substrate as described in any one of claims 1 to 18, and a counter substrate positioned opposite to the array substrate.

20. A display device, wherein, It includes the display panel as described in claim 19, and a backlight module located on the light-incident side of the display panel.

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