Computing system

Abstract

The present invention relates to a computing system, comprising a plurality of computing devices. Each computing device is configured with a plurality of computing modules and a plurality of optical interconnect expansion cards, and each optical interconnect expansion card is provided with an on-chip optical switch and at least one first optical switching unit. The optical interconnect expansion cards of the plurality of computing devices communicate by means of optical fiber connections. At least one computing device among the plurality of computing devices serves as a backup device, and the remaining computing devices are working devices that operate normally. When one or more working devices among the plurality of working devices fail, the connection topology of the plurality of computing devices is reconstructed by controlling the first optical switching units and / or the on-chip optical switches on the optical interconnect expansion cards of the plurality of computing devices, so that the backup devices as many as the failed working devices become the working devices that operate normally.

Description

Computing System

[0001] Cross-references to related applications

[0002] This application claims priority and other benefits to Chinese invention patent application No. 2024106783564, filed on May 28, 2024, entitled "Chip, Module, Apparatus and System Using Optical Interconnect Module", and Chinese invention patent application No. 2024108679300, filed on June 29, 2024, entitled "Computing System", the entire contents of which are incorporated herein by reference. Technical Field

[0003] This invention relates to computing systems. Background Technology

[0004] According to OpenAI data, the computational load of artificial intelligence models is growing far faster than the computing power of computing hardware. As AI (Artificial Intelligence) accelerators continue to improve their computing power through process technology iterations and chip architecture innovations, the interconnect bandwidth between AI accelerators is also constantly increasing. AI accelerator interconnect networks have become crucial for enhancing overall computing power. The Open Compute Project (OCP) has launched the general-purpose OCP Accelerator Module (OAM), which has been adopted by leading GPU (Graphics Processing Unit) vendors. Currently, to enhance communication between computing modules, eight computing modules are fully interconnected point-to-point on a universal base board (UBB) via PCB (printed circuit board) traces. Due to the need for long PCB traces, computing modules generally require long-range (LR) SerDes interfaces similar to CEI. For full connectivity, each SerDes interface needs to access a specific single computing module, which further reduces the bandwidth between each pair of computing modules.

[0005] Furthermore, with the ever-increasing number of large model parameters, conventional single-node GPUs (8 GPUs per machine) can no longer meet performance demands. Large-scale GPU supernodes formed through RoCE networks (e.g., 32 / 64 GPUs per supernode) inevitably suffer from bandwidth bottlenecks, leading to significant data communication latency and consequently low GPU MFU (Model FLOPs Utilization). Therefore, point-to-point interconnection between supernode GPUs has become crucial for improving the overall computing power and utilization of the cluster.

[0006] Furthermore, in current mainstream supernodes, when a computing module fails during training, the usual practice is to remove the entire supernode from the system, replace it with a backup supernode to continue training, and then repair the failed computing module offline. This deployment model requires the backup supernode as the smallest unit, which increases deployment costs. As the scale of supernodes increases, such as TP32 which contains 32 computing modules, the failure of one computing module requires the removal of all 32 computing modules, which significantly increases the cost of backup computing modules. Summary of the Invention

[0007] This invention provides a computing system that improves bandwidth and reduces latency through reconfigurable optical interconnects via optical interconnect expansion cards, and uses on-chip optical switches and optical switching units to change the connection topology in real time to replace faulty computing devices or faulty computing modules therein with backup computing devices, thus avoiding the need to replace all computing modules in a supernode.

[0008] According to an embodiment of the present invention, a computing system includes a plurality of computing devices, each computing device being configured with a plurality of computing modules and a plurality of optical interconnect expansion cards, each optical interconnect expansion card having an on-chip optical switch and at least one first optical switching unit; the optical interconnect expansion cards of the plurality of computing devices communicate via optical fiber connections; at least one of the plurality of computing devices serves as a backup device, and the remaining computing devices are operating devices in normal operation; when one or more of the plurality of operating devices fail, the connection topology of the plurality of computing devices is reconstructed by controlling the first optical switching unit and / or the on-chip optical switch on the optical interconnect expansion cards of the plurality of computing devices, so that an equal number of backup devices as the failed operating devices become operating devices in normal operation.

[0009] In some embodiments, the plurality of computing devices includes N computing devices, where N is an integer greater than 1; the plurality of computing devices are ordered from 1 to N; wherein, for any computing device M, where M is an integer greater than 1 and less than N, a first portion of the plurality of optical interconnect expansion cards of computing device M is connected to a portion of the plurality of optical interconnect expansion cards of computing device M-1 via optical fiber, and a second portion of the plurality of optical interconnect expansion cards of computing device M is connected to a portion of the plurality of optical interconnect expansion cards of computing device M+1 via optical fiber; a first portion of the plurality of optical interconnect expansion cards of computing device N is connected to a portion of the plurality of optical interconnect expansion cards of computing device N-1 via optical fiber, and a second portion of the plurality of optical interconnect expansion cards of computing device N is connected to a portion of the plurality of optical interconnect expansion cards of computing device 1 via optical fiber; a first portion of the plurality of optical interconnect expansion cards of computing device 1 is connected to a portion of the plurality of optical interconnect expansion cards of computing device N via optical fiber, and a second portion of the plurality of optical interconnect expansion cards of computing device 1 is connected to a portion of the plurality of optical interconnect expansion cards of computing device 2 via optical fiber.

[0010] In some implementations, the first portion and the second portion are equal, each being half of the plurality of optical interconnect expansion cards of the corresponding computing device.

[0011] In some implementations, by controlling the first optical switching unit and / or the on-chip optical switch on the optical interconnect expansion card of the computing system, the computing modules in computing device 1 to computing device K form a supernode with a predetermined topology, where K is an integer less than N.

[0012] In some embodiments, when any one of computing devices J among computing devices 1 to K fails, the connection topology of multiple computing devices is changed by controlling the on-chip optical switch and / or the first optical switching unit in the computing system, so that the backup device joins the connection topology and becomes a normally operating device, allowing the computing modules in any consecutive computing devices other than computing device J to reorganize into a new supernode. In some embodiments, the repaired computing device J is used as a new backup device by controlling the first optical switching unit on the optical interconnect expansion card of the computing system and / or the on-chip optical switch.

[0013] In some embodiments, controlling the first optical switching unit and / or the on-chip optical switch on the optical interconnect expansion card of the plurality of computing devices includes:

[0014] By controlling the first optical switching unit, the signal from the computing module can be selected to be transmitted to the on-chip optical switch or the optical fiber;

[0015] The on-chip optical switching unit is controlled to select the transmission path for communication between the multiple computing modules within the same computing device.

[0016] In some embodiments, by controlling the first optical switching unit and / or the on-chip optical switch on the optical interconnect expansion card of the computing system, a one-dimensional ring topology is formed in the communication links of the computing modules in computing device 1 to computing device N-1, with computing device N serving as a backup device.

[0017] In some embodiments, when any one of the computing devices M (from computing devices 1 to N-1) fails, the connection topology of multiple computing devices is changed by controlling the on-chip optical switch and / or the first optical switching unit in the computing system. This allows computing device N to join the connection topology and become a normally operating device, thus reorganizing the computing modules in computing devices 1 to M-1 and computing devices M+1 to N into a new one-dimensional ring topology. In some embodiments, the repaired computing device M is used as a new backup device by controlling the first optical switching unit on the optical interconnect expansion card and / or the on-chip optical switch in the computing system.

[0018] In some embodiments, the step of changing the connection topology of multiple computing devices by controlling the on-chip optical switch and / or the first optical switching unit in the computing system includes:

[0019] By changing the on-chip optical switches and the first optical switching unit of computing devices M-1, M, and M+1, the communication between computing devices M-1 and M, and between computing devices M and M+1, is disconnected, thus adjusting the communication links of the internal computing modules of computing devices M-1 and M+1. By changing the on-chip optical switches and the first optical switching unit of computing devices 1 and N, the communication between computing devices 1 and N is restored, thus adjusting the communication links of the internal computing modules of computing devices 1 and N.

[0020] In some embodiments, by controlling the on-chip optical switch and / or the first switching unit in the computing system to change the connection topology of multiple computing devices, a portion of the multiple computing devices enters a working state and forms multiple independent supernodes, while the remaining computing devices serve as backup devices. The multiple independent supernodes include one or more first supernodes and one or more second supernodes. Each first supernode includes one or more computing devices; each second supernode includes one or more computing devices. The topology of the first supernode differs from that of the second supernode. In some embodiments, if any computing device in a working state fails, the connection topology of the multiple computing devices is changed by controlling the on-chip optical switch and / or the first optical switching unit in the computing system. This isolates the failed computing device from communication, activates an equal number of backup devices to become working devices in a new working state, and allows any consecutive working devices in a working state to reorganize into the multiple first supernodes and the multiple second supernodes.

[0021] In some embodiments, the plurality of independent supernodes further includes one or more third supernodes, each comprising one or more computing devices; the topology of the third supernode differs from that of the first and second supernodes. In some embodiments, if any computing device in operation fails, the connection topology of the plurality of computing devices is changed by controlling the on-chip optical switch and / or the first optical switching unit in the computing system. This isolates the failed computing device from communication, activates an equal number of backup devices to become working devices in a new operational state, and allows any consecutively operating working devices to reassemble into the one or more first supernodes, the one or more second supernodes, and the one or more third supernodes.

[0022] Furthermore, this invention also provides a computing system comprising multiple computing devices, each computing device being configured with multiple computing modules and multiple optical interconnect expansion cards, each optical interconnect expansion card having an on-chip optical switch and at least one first optical switching unit; the optical interconnect expansion cards of the multiple computing devices communicating via optical fiber connections; at least a portion of the computing modules of at least one of the multiple computing devices serving as backup modules, and the remaining computing modules serving as normally operating working modules; when one or more of the multiple working modules fail, the connection topology of the multiple working modules is reconstructed by controlling the first optical switching unit and / or the on-chip optical switch on the optical interconnect expansion cards of the multiple computing devices, so that an equal number of backup modules become normally operating working modules.

[0023] In some embodiments, the plurality of computing devices includes N computing devices, where N is an integer greater than 1; the plurality of computing devices are ordered from 1 to N; wherein, a first portion of a plurality of optical interconnect expansion cards of computing device M is connected to a portion of a plurality of optical interconnect expansion cards of computing device M-1 via optical fiber, and a second portion of a plurality of optical interconnect expansion cards of computing device M is connected to a portion of a plurality of optical interconnect expansion cards of computing device M+1 via optical fiber, wherein M is an integer greater than 1 and less than N; a first portion of a plurality of optical interconnect expansion cards of computing device N is interconnected with a portion of a plurality of optical interconnect expansion cards of computing device N-1 via optical fiber, and a second portion of a plurality of optical interconnect expansion cards of computing device N is interconnected with a portion of a plurality of optical interconnect expansion cards of computing device 1 via optical fiber; a first portion of a plurality of optical interconnect expansion cards of computing device 1 is connected to a portion of a plurality of optical interconnect expansion cards of computing device N via optical fiber, and a second portion of a plurality of optical interconnect expansion cards of computing device 1 is connected to a portion of a plurality of optical interconnect expansion cards of computing device 2 via optical fiber.

[0024] In some implementations, the first portion and the second portion are equal, each being half of the plurality of optical interconnect expansion cards of the corresponding computing device.

[0025] In some implementations, by controlling the on-chip optical switch and / or the first optical switching unit in the computing system to change the connection topology of multiple computing modules in the computing system, a portion of the multiple computing modules enters a working state and forms one or more independent supernodes, while the remaining computing modules serve as backup modules; the multiple independent supernodes include one or more first supernodes, each of which includes any consecutive multiple computing modules, and by controlling the on-chip optical switch and / or the first optical switching unit in the computing system, the multiple computing modules within the first supernode form a first target topology.

[0026] In some implementations, the one or more independent supernodes include one or more second supernodes, each of which includes an arbitrary number of consecutive computing modules. By controlling the on-chip optical switch and / or the first optical switching unit in the computing system, the multiple computing modules within the second supernode form a second target topology. The first target topology of the first supernode is different from the second target topology of the second supernode.

[0027] In some embodiments, the plurality of independent supernodes further includes: one or more third supernodes, each third supernode comprising an arbitrary number of consecutive computing modules. The computing modules within the third supernode are configured to form a third target topology by controlling the on-chip optical switch and / or the first optical switching unit in the computing system. The third target topology of the third supernode differs from the first target topology of the first supernode and the second target topology of the second supernode. Optionally, the first target topology, the second target topology, and the third target topology are one-dimensional ring topologies with varying numbers of computing modules.

[0028] In some implementations, if any computing module in the working state fails, the connection topology of multiple computing modules is changed by controlling the on-chip optical switch and / or the first optical switching unit in the computing system. This causes the failed computing module to be communication isolated, an equal number of backup modules to be enabled as new computing modules in the working state, and any consecutive computing modules in the working state to be reorganized into a new set of multiple supernodes with the same topology as the original multiple supernodes.

[0029] In some implementations, the backup modules are distributed at any location adjacent to the one or more supernodes.

[0030] According to embodiments of the present invention, reconfigurable optical interconnects are achieved through optical interconnect expansion cards to improve system bandwidth and reduce latency. Furthermore, on-chip optical switches and / or optical switching units can be used to change the connection topology in real time to form different supernodes (including supernodes), allowing for flexible configuration to meet diverse computing needs. For example, by controlling the on-chip optical switches and / or optical switching units, vertical supernodes can be flexibly combined or split, achieving millisecond-level topology switching. This supports (but is not limited to) TP16 (i.e., a supernode comprising 16 compute modules (XPUs)), TP32, TP64, TP128, etc.

[0031] Multiple computing devices can be connected via reconfigurable optical interconnect expansion cards and direct fiber optic connections, avoiding the use of external electrical and optical switches and saving interconnection costs.

[0032] According to embodiments of the present invention, redundancy granularity can be a single computing device (each computing device includes multiple computing modules). By reconstructing the connection topology using a reconfigurable optical interconnect expansion card, faulty computing devices can be removed / isolated, and any number of other consecutive computing devices can form a new supernode without affecting system operation. Redundancy granularity can also be a single computing module. By reconstructing the connection topology using a reconfigurable optical interconnect expansion card to bypass / isolate faulty computing modules, and using backup modules to reassemble a new supernode, reducing module deployment costs. Furthermore, compared to replacing the entire supernode, millisecond-level topology reset time can be achieved, resulting in low latency and high cluster operating efficiency.

[0033] Furthermore, the optical interconnect structure of this invention breaks through the interconnection distance limitation of PCB board traces. Through long-distance optical fiber connection, it can decouple the existing multi-card computing system, so that the computing power and improvement of nodes, i.e. node computing devices, are no longer hierarchical, and the bandwidth within and between nodes is more uniform, which is conducive to the large-scale expansion of computing modules.

[0034] The optical interconnect structure of this invention allows the interconnection between computing modules to be reconfigurable in the field, rather than static. This offers numerous advantages, the most significant being the ability to adapt the topology to specific artificial intelligence models. From a topology perspective, the data flow requirements of different artificial intelligence models can be broadly categorized into three types: data parallelism, where each chip loads the entire model and different chips process different data within the dataset; model parallelism, where some layers in the model are particularly large, and each chip handles only a portion of the computation within these large layers; and pipeline parallelism, where different layers in the model are assigned to different chips for computation. These different data flows correspond to different computational interconnection topologies. Using reconfigurable optical interconnects allows for rapid switching between different interconnection topologies between computing modules, effectively improving bandwidth utilization and enhancing the scalability of the artificial intelligence computing system. This enables multiple computing modules to collaborate efficiently and reliably to accelerate such large models.

[0035] Various aspects, features, and advantages of the embodiments of the present invention will be described in detail below with reference to the accompanying drawings. Attached Figure Description

[0036] Figure 1 is a cross-sectional schematic diagram showing an example structure of an optical interconnect module according to an embodiment of the present invention.

[0037] Figure 2A is a schematic diagram showing an example of the photonic circuit structure formed on the photonic integrated circuit chip in the optical interconnect module shown in Figure 1; Figure 2B is a schematic diagram showing another example of the photonic circuit structure formed on the photonic integrated circuit chip in the optical interconnect module shown in Figure 1.

[0038] Figure 3 is a schematic diagram showing the photonic circuit structure of the on-chip optical switch in the photonic integrated circuit chip shown in Figures 2A and 2B.

[0039] Figure 4 is a schematic diagram showing an example structure of the first optical switching unit on the photonic integrated circuit chip shown in Figures 2A and 2B.

[0040] Figure 5 is a schematic diagram showing an example structure of the second optical switching unit in the on-chip optical switch shown in Figure 3.

[0041] Figure 6 is a schematic diagram showing the planar layout of a reconfigurable optical interconnect expansion card according to an embodiment of the present invention.

[0042] Figure 7 is a schematic diagram showing the package structure of the reconfigurable optical interconnect expansion card shown in Figure 6.

[0043] Figure 8 is a schematic diagram illustrating an example structure of a computing device according to an embodiment of the present invention.

[0044] Figures 9A to 9D are schematic diagrams of the reconfigurable topology among the computing modules in the computing device of the present invention.

[0045] Figure 10 is a schematic diagram illustrating an example structure of a computing system according to another embodiment of the present invention.

[0046] Figure 11 is a schematic diagram illustrating the connection topology changes of a computing system according to an embodiment of the present invention.

[0047] Figure 12 is a schematic diagram illustrating the connection topology changes of a computing system with redundant design at the computing device level according to an embodiment of the present invention.

[0048] Figure 13 is a schematic diagram illustrating the connection topology changes of a computing system with redundant design based on computing modules according to an embodiment of the present invention. Detailed Implementation

[0049] Exemplary embodiments will now be described in more detail with reference to the accompanying drawings. Certain terms may be used in the description for reference only and are not intended to limit the scope of protection. For example, terms such as “top,” “bottom,” “upper,” “lower,” “above,” and “below” may be used to refer to orientations in the accompanying drawings, which are referenced. Terms such as “front,” “back,” “rear,” “side,” “outer,” and “inner” may be used to describe the orientation and / or position of various parts of a component within a consistent but arbitrary frame of reference, which can be clearly understood by referring to the text describing the component under discussion and the associated drawings. Unless the context clearly indicates otherwise, “first,” “second,” and other similar numerical terms do not imply order or sequence.

[0050] It should be understood that when an element or feature is referred to as "on another element or layer," "connected to," or "attached to" another element or layer, it may be directly on, connected to, or attached to the other element or feature, or there may be one or more intermediate elements or features. Furthermore, it should be understood that when an element or feature is referred to as "between" two elements or features, it may be the only element or feature between the two elements or features, or there may be one or more intermediate elements or features.

[0051] The terminology used herein is for the purpose of describing particular embodiments and is not intended to limit the invention. Such terms may include words specifically mentioned herein, derivatives thereof, and words with similar meanings. As used herein, the singular forms “a” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the terms “comprising,” “including,” and “having” specify the presence of the stated features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or collections thereof. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. Expressions such as “at least one of…” modify the entire list of elements when preceding it, rather than individual elements of the list.

[0052] As used herein, the terms “basically,” “about,” and similar terms are used as approximations rather than as terms of degree, and are intended to take into account the inherent variations in measured or calculated values ​​that would be recognized by one of ordinary skill in the art. As used herein, the terms “use,” “being used,” and “being used” are to be regarded as synonymous with the terms “utilization,” “being utilized,” and “being exploited,” respectively.

[0053] Referring to Figures 1 to 5, an exemplary embodiment of an optical interconnect module according to the present invention is shown. In an exemplary embodiment, the optical interconnect module includes a photonic integrated circuit chip 201 and a transceiver analog electrical chip 202. In some embodiments, as shown in Figure 1, the photonic integrated circuit chip 201 is disposed on a substrate 204, and the transceiver analog electrical chip 202 is disposed on the photonic integrated circuit chip 201. As shown in Figure 2A, the photonic integrated circuit chip includes one or more photonic integrated circuit sub-modules, each of which includes multiple modulators 302, multiple wavelength multiplexers 303, multiple first optical switching units 304, at least one on-chip optical switch 300, multiple demultiplexers 305, multiple detectors 306, a first optical coupler 307, and a second optical coupler 308, etc.

[0054] In an exemplary embodiment, a group of modulators (which may also be configured as a "modulator array") among a plurality of modulators 302 are optically connected to a first optical switching unit 304 via a wavelength multiplexer 303. Specifically, the wavelength multiplexer 303 has a plurality of optical input ports and an optical output port. Each of the plurality of optical input ports of the wavelength multiplexer is connected to one of the modulators 302, and one of the optical output ports of the wavelength multiplexer is connected to one of the first optical switching units 304.

[0055] Each of the plurality of first optical switching units 304 is optically connected to a set of modulators 302 via a wavelength multiplexer 303. Specifically, each first optical switching unit 304 includes a first optical input port, a first optical output port, and a second optical output port. The first optical input port of the first optical switching unit 304 is connected to the optical output port of the wavelength multiplexer 303, and the first optical output port of the first optical switching unit 304 is connected to a first optical coupler 307. The first optical coupler 307 is configured to optically connect the first optical output ports of the plurality of first optical switching units 304 to external fiber optics. The second optical output ports of the first optical switching units 304 are connected to an on-chip optical switch 300. Each first optical switching unit 304 is configured to selectively output the optical signal input to its first optical input port via its first optical output port or its second optical output port.

[0056] The on-chip optical switch 300 has multiple optical input ports and multiple optical output ports. The multiple optical input ports of the on-chip optical switch 300 are optically connected to the second optical output ports of multiple first optical switching units 304, respectively. The on-chip optical switch 300 is configured to selectively output an optical signal from any one of its multiple optical input ports via at least one of its multiple optical output ports, thereby changing the output path of the optical signal and thus altering the topology of the optical transmission network. The multiple optical output ports of the on-chip optical switch 300 are respectively connected to multiple demultiplexers 305. Each demultiplexer 305 is connected to a group of detectors (or a "detector array") among multiple detectors 306. Specifically, each demultiplexer 305 has one optical input port and multiple optical output ports. One optical input port of the demultiplexer 305 is connected to one optical output port of the on-chip optical switch 300, and each of the multiple optical output ports of the demultiplexer 305 is connected to one detector 306.

[0057] In an exemplary embodiment, each modulator array modulates light waves of different wavelengths, and each modulator 302 modulates the input light 301 according to the electrical signal received from the transceiver analog electrical chip 202, thereby loading the information carried by the electrical signal into the input light to obtain an optical signal carrying information. A wavelength multiplexer 303 integrates the optical signals of different wavelengths into a single optical signal, which is then path-selected by the first optical switching unit 304 and enters either the first external optical fiber array (not shown) or the on-chip switch 300 via the first optical coupler 307. If it enters the on-chip optical switch 300, it is demultiplexed into optical signals of different wavelengths by the demultiplexer 305, and then transmitted to different detectors 306 of a detector array for photoelectric conversion. If it enters the first external optical fiber array, it passes through the external optical fiber to a demultiplexer and detector array on another chip. For example, in some embodiments, the photonic integrated circuit chip 201 further includes a second optical coupler 308, which is optically connected to the demultiplexer 305 and configured to transmit optical signals from a second external fiber array (not shown) to the demultiplexer and detector array in the photonic integrated circuit chip 201.

[0058] In some embodiments, the transceiver analog electrical chip 202 is configured to convert a received first digital electrical signal into a driving analog electrical signal and transmit the driving analog electrical signal carrying the information to at least one of the plurality of modulators 302 in the photonic integrated circuit chip 201, or to receive a received analog electrical signal output by at least one of the plurality of detectors 306 in the photonic integrated circuit chip 201 and convert the received analog electrical signal into a second digital electrical signal; the modulator 302 is configured to modulate the information carried by the driving analog electrical signal into the optical signal.

[0059] In some embodiments, as shown in FIG1, the transceiver analog electrical chip 202 is disposed above the photonic integrated circuit chip 201, and receives the first digital electrical signal and / or transmits the second digital electrical signal through conductive vias penetrating the photonic integrated circuit chip 201. Specifically, the transceiver analog electrical chip 202 is mounted on the opposite side of the photonic integrated circuit optical chip 201 relative to the substrate 204.

[0060] In an optional implementation, when the input light 301 is single-wavelength light, the photonic integrated circuit chip 201 can be configured without the required wavelength multiplexer 303 and demultiplexer 305. Specifically, as shown in FIG2B, a first optical switching unit 304 corresponds to a modulator 302 and two detectors on the other side. One of the two detectors is directly connected to the on-chip optical switch 300, such as detector 306 in this chip, and the other is connected to a first external fiber array connected to a first optical coupler 307. For example, a second optical coupler 308 can be directly connected to detector 306, so that detector 306 can be connected to the first optical switching unit of another chip through a second external fiber array.

[0061] In some other embodiments, as shown in FIG2B, the photonic integrated circuit chip includes multiple photonic integrated circuit sub-modules, each of which has the same circuit structure.

[0062] In an optional embodiment, the photonic integrated circuit chip 201 further includes a third optical coupler (not shown) and an optical power splitter (not shown). The third optical coupler is configured to input light from an off-chip light source into the photonic integrated circuit chip 201. The optical power splitter is optically connected to the third optical coupler and is configured to split one input light into multiple output lights, each of which has substantially the same power, and the multiple output lights are transmitted to respective modulators 302.

[0063] In some embodiments, the first optical switching unit 304 may be a 1x2 optical switching unit. In some embodiments, the first optical switching unit 304 may be a MEMS optical path switching unit or a Mach-Zehnder interferometer (MZI) optical path switching unit. As shown in FIG4, the first optical switching unit 304 may adopt a Mach-Zehnder interferometer structure, specifically including: a first beam splitter 408 having one optical input port and two optical output ports; a second beam splitter 407 having two optical input ports and two optical output ports; and two phase shifters 406, which are respectively connected between the two optical output ports of the first beam splitter 408 and the two optical input ports of the second beam splitter 407. In some embodiments, the phase shifter 406 is an electro-optic or thermo-optic phase shifter, and by controlling the upper and lower arms of the electro-optic or thermo-optic phase shifter 406, the phase of the optical signal can be changed and the output port of the optical signal can be selected by using the interference effect.

[0064] In some embodiments, as shown in FIG3, the on-chip optical switch 300 includes a plurality of second optical switching units 405. The optical interconnect module further includes an optical switching control analog electrical chip (not shown), configured to control the plurality of second optical switching units 405 to select the transmission path of the optical signal input to the on-chip optical switch, so that the optical signal is output from at least one of the plurality of optical output ports of the on-chip optical switch. In some embodiments, the on-chip optical switch 300 is an 8×8 strictly non-blocking optical switch, consisting of 64 2×2 optical switching units 405. By controlling the signal output port of each switching unit, any path combination between the 8 input channels and 8 output channels in FIG3 can be realized, and the insertion loss on each path is path-independent. Thus, the topology from the input end to the output end of the system can be changed. In specific applications, the 8×8 silicon photonics switch can be further laterally repeated to meet greater bandwidth switching requirements. The optical switch structure in this embodiment is an exemplary structure; depending on actual needs, it can be any n×n non-blocking optical switch. Reconfigurable optical interconnects can change network topology for different artificial intelligence applications, optimize data migration efficiency, and improve computing system performance.

[0065] In some embodiments, the second optical switching unit 405 may be an MZI optical path switching unit.

[0066] In some embodiments, as shown in Figure 5, the second optical switching unit employs an MZI optical path switching unit, which includes two beam splitters 407, each beam splitter 407 having two optical input ports and two optical output ports; and two phase shifters 406, which are respectively connected between the two optical output ports of one beam splitter 407 and the two optical input ports of the other beam splitter 407. It can be seen that the second optical switching unit can also employ a Mach-Zehnder interferometer structure, where the phase of the input optical signal can be changed by controlling the phase shifters 406 in the upper and lower arms, and the output port of the output optical signal can be selected using the interference effect.

[0067] In some embodiments, the modulator 302 includes at least one of the following: a micro-ring modulator, a Mach-Zehnder modulator, and an electroabsorption modulator. The detector 306 includes a micro-ring detector or a photodiode.

[0068] In some embodiments, each photonic integrated circuit submodule further includes a third optical switching unit (not shown). The detector or demultiplexer is optically connected to the on-chip optical switch and the second optical coupler through the third optical switching unit. The number of detectors or detector arrays is equal to the number of modulators or modulator arrays. Specifically, the third optical switching unit includes a first optical input port, a second optical input port, and an optical output port. The first optical input port of the third optical switching unit is connected to the second optical coupler. The second optical input port of the third optical switching unit is connected to an optical output port of the on-chip optical switch. The optical output port of the third optical switching unit is connected to the detector or the demultiplexer. By controlling the third optical switching unit, the first optical input port of the third optical switching unit can be connected to the optical output port of the third optical switching unit, or the second optical input port of the third optical switching unit can be connected to the optical output port of the third optical switching unit.

[0069] In some embodiments, the third optical switching unit is disposed on the optical path connecting the detector or detector array to the on-chip optical switch, and on the optical path connecting the detector or detector array to the second optical coupler.

[0070] In some implementations, the third optical switching unit is a MEMS optical path switching unit or an MZI optical path switching unit. By setting up the third optical switching unit, a detector / detector array can be used to receive optical signals from the on-chip optical switch and optical signals from the second optical coupler at different times, thereby reducing the number of detectors / detector arrays.

[0071] Considering that existing technologies achieve point-to-point full interconnection between computing modules on a general-purpose motherboard via PCB traces, which cannot meet the bandwidth requirements between each pair of computing modules, the aforementioned optical interconnect module can be used. This allows for more uniform bandwidth distribution within and between nodes, facilitating large-scale expansion of computing modules. Furthermore, reconfigurable optical interconnects can modify network topology for different artificial intelligence applications, optimize data migration efficiency, and improve computing system performance.

[0072] In some embodiments, the aforementioned optical interconnect module can be housed in an optical interconnect expansion card for connection (e.g., plug-and-play) with a corresponding computing device. Figures 6 and 7 illustrate an exemplary embodiment of an optical interconnect expansion card. Because the optical interconnect module features reconfigurable optical interconnect, this optical interconnect expansion card can also be referred to as a reconfigurable optical interconnect expansion card. As shown in Figures 6 and 7, the reconfigurable optical interconnect expansion card 100 includes a PCB board 207, an optical interconnect module 200, a laser module 205, an optical fiber interface 206, an electrical communication interface (e.g., a high-speed interface 211), a retimer 208, a voltage regulation module 209 (e.g., 54V to 12V), a voltage regulation module 210 (12V to a voltage rail (i.e., the maximum voltage input range)), etc.

[0073] The optical interconnect module 200 is disposed on the PCB board 207 and can be any of the optical interconnect modules described in the above embodiments or implementations, including a photonic integrated circuit chip 201, a transceiver analog electrical chip 202, and a corresponding substrate 204. The laser module 205 is disposed on the PCB board 207 and is optically connected to the optical interconnect module 200 via a third fiber array 203 to input light into the optical interconnect module 200. The fiber optic interface 206 is disposed on the PCB board 207 and is optically connected to the optical interconnect module 200 via additional first and second external fiber arrays to achieve optical communication with the optical interconnect module 200. The high-speed interface 211 is disposed on the PCB board 207 and is used to receive the first digital signal and / or transmit a second digital electrical signal. A re-timer 208 is mounted on the PCB board 207 and is communicatively connected to the high-speed interface 211 and the optical interconnect module 200. It is used to reshape a first digital electrical signal and transmit the reshaped signal to the optical interconnect module 200; and / or to reshape a second digital electrical signal received from the optical interconnect module 200 and transmit it via the electrical communication interface. Each re-timer 208 has multiple communication channels, and multiple electrical communication interfaces have multiple communication channels. The total number of communication channels of the re-timers 208 is equal to the total number of telecommunication channels of the electrical communication interfaces. The re-timers 208 are communicatively connected to the optical interconnect module 200 via PCB board traces.

[0074] The high-speed interface 211 receives electrical signals from an information transmitting device, such as a computing module. These signals are re-formed via a re-timer 208. The re-formed high-speed electrical signal is then transmitted to the edge of the optical interconnect module 200 via traces on the packaging substrate and a shorter PCB board 207. It is further transmitted to the corresponding transceiver analog electrical chip 202 via metal traces and through-silicon vias 212 on the substrate 204. After signal amplification and electro-optic / photoelectric conversion by the components of the analog electrical chip 202 and the photonic integrated circuit chip 201, the signal is transmitted via optical fiber, and optical path reconstruction is performed within the photonic integrated circuit chip 201. For example, the optical interconnect module 200 receives a laser generated by a laser module 205, and the electrical signal received by the transceiver analog electrical chip 202 is modulated into the laser by a modulator to obtain an information-carrying optical signal. This optical signal undergoes optical path reconstruction via a first optical switching unit and an on-chip optical switch within the photonic integrated circuit chip, and is then output to the communication peer (e.g., another computing module) via optical fiber and optical fiber interface 206. On the other hand, the optical signal received through the optical fiber interface 206 and the optical fiber is photoelectrically converted by the detector of the optical interconnect module 200, and the resulting electrical signal is sent to the receiving end (e.g., a computing module) through the transceiver analog electrical chip 202, the retimer 208 and the high-speed interface 211.

[0075] In one exemplary embodiment, the optical interconnect expansion card 100 can be used to communicatively connect multiple computing modules to form a computing device. As shown in FIG8, the computing device includes: multiple computing modules 101 (for example, in this embodiment, a computing module is formed by carrying one or more computing chips on an OAM board; the example in FIG8 is eight OAM boards carrying computing chips, numbered 0, 1, 2, 3, 4, 5, 6, and 7 respectively), multiple reconfigurable optical interconnect expansion cards 100 (for example, eight optical interconnect expansion cards), and a PCB board 102. The PCB board 102 can be a UBB universal motherboard. In some embodiments, the eight computing modules 101 are connected to the reconfigurable optical interconnect expansion cards 100 through PCB board traces 103 on the PCB board 102 to form an eight-card system. The computing modules 101 have high-speed long-distance SerDes interfaces to communicate with the high-speed interface 211 of the reconfigurable optical interconnect expansion cards 100. The reconfigurable optical interconnect expansion card 100 (specifically, the first optical switching unit 204 and the on-chip optical switch 200) can reconfigure the connection topology between the eight computing modules 101. For example, the connection topology between computing modules 101 (numbered 0, 1, 2, 3, 4, 5, 6, and 7) can be changed in real time to be fully interconnected externally (Figure 9A), fully interconnected internally (Figure 9B), a ring (Figure 9C), or point-to-point (Figure 9D). Therefore, the communication bandwidth between computing module 0 and computing module 1 can be switched in real time between bandwidth B (Figure 9B: full interconnection), bandwidth 4B (Figure 9C: ring), and bandwidth 8B (Figure 9D: point-to-point). This can match the bandwidth requirements of different communication algorithms, improve bandwidth utilization, and thus improve the overall operating efficiency of the artificial intelligence computing system.

[0076] Furthermore, in some embodiments of the present invention, multiple computing devices are directly connected via corresponding optical interconnect expansion cards and optical fibers, eliminating the need for external switches. Reconfigurable optical interconnects via optical interconnect expansion cards can also improve bandwidth, reduce latency, and allow for real-time changes in the connection topology through on-chip optical switches and optical switching units to form different supernodes, enabling flexible configuration to meet diverse computing needs.

[0077] In an exemplary embodiment, a computing system includes multiple computing devices, each computing device being configured with multiple computing modules and multiple optical interconnect expansion cards. Each optical interconnect expansion card includes an on-chip optical switch and at least one first optical switching unit. The on-chip optical switch is configured for communication between the multiple computing modules within the same computing device. The optical interconnect expansion cards of the multiple computing devices communicate via optical fiber connections. The first optical switching unit is configured to selectively transmit signals from the computing modules to the on-chip optical switch or the optical fiber. In some embodiments, the optical interconnect expansion card may be the optical interconnect expansion card 100 described in any of the above embodiments or implementations, or have the structure and configuration of the optical interconnect expansion card described in any of the above embodiments or implementations, which will not be repeated here. In some embodiments, the computing device may be the computing device described in any of the above embodiments or implementations, or have the structure and configuration of the computing device described in any of the above embodiments or implementations, which will not be repeated here.

[0078] In some embodiments, the plurality of computing devices includes a first computing device, a second computing device, and a third computing device. A first portion of a plurality of optical interconnect expansion cards of the first computing device is interconnected with a portion of a plurality of optical interconnect expansion cards of the second computing device via optical fiber; a second portion of the plurality of optical interconnect expansion cards of the first computing device is interconnected with a portion of a plurality of optical interconnect expansion cards of the third computing device via optical fiber. In some embodiments, the first portion is half of the plurality of optical interconnect expansion cards of the first computing device, and the second portion is the other half of the plurality of optical interconnect expansion cards of the first computing device.

[0079] As shown in Figure 10, in some embodiments, the computing system includes N computing devices, where N is an integer greater than 1. Each computing device includes 8 computing modules (OAM) and 8 optical interconnect expansion cards 100, with the computing modules connected to their respective optical interconnect expansion cards via metal traces. It should be understood that the invention is not limited thereto, and each computing device may include any number of computing modules and optical interconnect expansion cards. The N computing devices are ordered from 1 to N, wherein a first portion of the plurality of optical interconnect expansion cards 100 of computing device M is interconnected with a portion of the plurality of optical interconnect expansion cards 100 of computing device M-1 via optical fiber 501, and a second portion of the plurality of optical interconnect expansion cards 100 of computing device M is interconnected with a portion of the plurality of optical interconnect expansion cards 100 of computing device M+1 via optical fiber 501. Here, M is an integer greater than 1 and less than N. Furthermore, a first portion of the plurality of optical interconnect expansion cards 100 of computing device 1 is interconnected with a portion of the plurality of optical interconnect expansion cards 100 of computing device N via optical fiber 501; a second portion of the plurality of optical interconnect expansion cards 100 of computing device 1 is interconnected with a portion of the plurality of optical interconnect expansion cards 100 of computing device 2 via optical fiber 501; a first portion of the plurality of optical interconnect expansion cards 100 of computing device N is interconnected with a portion of the plurality of optical interconnect expansion cards 100 of computing device N-1 via optical fiber 501; and a second portion of the plurality of optical interconnect expansion cards 100 of computing device N is interconnected with a portion of the plurality of optical interconnect expansion cards 100 of computing device 1 via optical fiber 501. In some embodiments, the first portion and the second portion are equal, each being half of the plurality of optical interconnect expansion cards of the corresponding computing device. That is, half of the optical interconnect expansion card of each computing device is connected to half of the optical interconnect expansion card of the computing device adjacent on one side via optical fiber, and the other half of the optical interconnect expansion card is connected to half of the optical interconnect expansion card of the computing device adjacent on the other side via optical fiber, thereby enabling the computing system to form a one-dimensional (1D) ring structure.

[0080] In some embodiments, the topology of the plurality of computing devices can be changed by controlling the first optical switching unit and / or on-chip optical switch on the optical interconnect expansion card of the plurality of computing devices. In some embodiments, by controlling the first optical switching unit and / or on-chip optical switch on the optical interconnect expansion card of the plurality of computing devices, the topology of the plurality of computing devices can be changed to: a one-dimensional ring structure; or multiple independent ring structures, each independent ring structure including the same or different numbers of computing devices.

[0081] In some embodiments, each computing device includes multiple computing modules, and the multiple computing modules of each computing device are connected to corresponding multiple optical interconnect expansion cards via metal traces. The topology of the multiple computing modules of the computing system can be changed by controlling the first optical switching unit and / or on-chip optical switch on the optical interconnect expansion card. As shown in Figure 11, in Figure (a), the multiple computing modules in N computing devices form a 1D ring topology. In this embodiment, taking a computing device with 8 computing modules as an example, in this topology, for the 8 computing modules in computing device 1, by controlling the first optical switching unit, half of the links of computing modules OAM6 and OAM7 are used to communicate with computing modules OAM6 and OAM7 in computing device 2, respectively. By controlling the first optical switching unit and / or on-chip optical switch, the other half of the links of computing modules OAM6 and OAM7 are used to communicate with adjacent computing modules in computing device 1, respectively. By controlling the first optical switching unit and / or on-chip optical switch, half of the links of the remaining computing modules in computing device 1 are used to communicate with two adjacent computing modules. For the eight computing modules in computing device N, by controlling the first optical switching unit, half of the links of computing modules OAM0 and OAM1 are used to communicate with computing modules OAM0 and OAM1 in computing device N-1, respectively. By controlling the first optical switching unit and / or the on-chip optical switch, the other half of the links of computing modules OAM0 and OAM1 are used to communicate with adjacent computing modules in computing device N, respectively. By controlling the first optical switching unit and / or the on-chip optical switch, half of the links of the remaining computing modules in computing device N are used to communicate with two adjacent computing modules, respectively. For the remaining computing devices M (computing devices 2 to N-1), by controlling the first optical switching unit, half of the links of computing modules OAM6 and OAM7 are used to communicate with computing modules OAM6 and OAM7 in computing device M+1, respectively, and the other half of the links of computing modules OAM6 and OAM7 are used to communicate with adjacent computing modules in computing device M; by controlling the first optical switching unit, half of the links of computing modules OAM0 and OAM1 are used to communicate with computing modules OAM0 and OAM1 in computing device M-1, respectively, and the other half of the links of computing modules OAM0 and OAM1 are used to communicate with adjacent computing modules in computing device M; and half of the links of computing modules OAM2, OAM3, OAM4, and OAM5 are used to communicate with two adjacent computing modules.

[0082] By controlling the first optical switching unit and / or on-chip optical switch on the optical interconnect expansion card, without changing the physical connection of the optical fiber, the topology of multiple computing modules of the computing system can be changed into multiple independent ring topologies, as shown in Figure (b). Each independent ring includes 32 computing modules, and each ring topology can constitute a supernode, such as TP32. The computing system also includes a backup node. In this embodiment, any four adjacent computing devices constitute a supernode. For example, computing devices 1-4 constitute the first supernode, computing devices 5-8 constitute the second supernode, and so on. Alternatively, computing devices 1-4 can constitute the first supernode, computing devices 6-9 can constitute the second supernode, and device 5 can serve as a backup supernode. Any other form of four adjacent computing devices can form a supernode. In each supernode, taking computing devices 1-4 as the first supernode and computing devices 5-8 as the second supernode as an example, for the eight computing modules in computing device 1, by controlling the first optical switching unit, half of the links of computing modules OAM6 and OAM7 are used to communicate with computing modules OAM6 and OAM7 in computing device 2, respectively. By controlling the first optical switching unit and / or the on-chip optical switch, the other half of the links of computing modules OAM6 and OAM7 are used to communicate with adjacent computing modules in computing device 1, respectively. By controlling the first optical switching unit and / or the on-chip optical switch, half of the links of the remaining computing modules in computing device 1 are used to communicate with two adjacent computing modules, respectively. For the eight computing modules in computing device 4, by controlling the first optical switching unit, half of the links of computing modules OAM0 and OAM1 are used to communicate with computing modules OAM0 and OAM1 in computing device 3, respectively. By controlling the first optical switching unit and / or the on-chip optical switch, the other half of the links of computing modules OAM0 and OAM1 are used to communicate with adjacent computing modules in computing device 4, respectively. By controlling the first optical switching unit and / or the on-chip optical switch, half of the links of the remaining computing modules in computing device 4 are used to communicate with two adjacent computing modules, respectively. The communication configuration between computing devices 2 and 3 is the same as the 1D ring topology in the previous embodiment. In this topology, by controlling the first optical switching units in computing devices 4 and 5, the optical fibers connecting the two computing devices do not communicate, thus placing computing devices 4 and 5 in different supernodes.

[0083] In optional implementations, different independent ring topologies include different numbers of computing modules, as shown in Figure (c). The computing system may include a supernode TP64 with 64 computing modules and a supernode TP32 with 32 computing modules. The communication configuration is similar to the topology in Figure (c), except that the positions where the optical fibers in adjacent computing devices do not communicate are different, achieved by controlling the first optical switching unit.

[0084] In some embodiments, by controlling the first optical switching unit and / or on-chip optical switch on the optical interconnect expansion card of the plurality of computing devices, the topology of the plurality of computing modules of the computing system can be changed to include multiple supernodes, as shown in Figure (d). These multiple supernodes include TP16, TP12, TP20, TP32, and backup nodes, etc. The multiple supernodes include a first supernode, such as TP16(FC), where a first-layer computing module is formed by interconnecting multiple computing modules, and a second-layer computing module is formed by interconnecting at least two first-layer computing modules. Furthermore, the multiple supernodes include a second supernode, such as TP16(3D), where the second supernode includes a third-layer computing module formed by interconnecting at least two second-layer computing modules, where the second-layer computing module is formed by interconnecting at least two first-layer computing modules, and the first-layer computing module is formed by interconnecting multiple computing modules. Further, the multiple supernodes include a third supernode, such as TP12, TP20, TP32, etc., which includes multiple computing modules arranged in a one-dimensional ring topology. In this embodiment, the first supernode of TP16(FC) includes computing device 1 and computing device 2. By controlling the first optical switching unit and / or on-chip optical switch on the optical interconnect expansion card of the computing device, the eight computing modules inside computing device 1 and computing device 2 are made to form a fully connected pairwise communication, and the corresponding computing modules of computing device 1 and computing device 2 communicate with each other through optical fiber (for example, computing module OAM1 of computing device 1 and computing module OAM1 of computing device 2 communicate directly through optical fiber). The second supernode of TP16(3D) includes computing device 3 and computing device 4. By controlling the first optical switching unit and / or on-chip optical switch on the optical interconnect expansion card of the computing device, the eight computing modules inside computing device 3 and computing device 4 are divided into two groups of four computing modules within the same computing device. Each group forms a first-layer computing module with a fully interconnected structure through an on-chip optical switch. The corresponding computing modules of the first-layer computing modules communicate with each other to form a second-layer computing module. The corresponding computing modules of the two second-layer computing modules communicate with each other through optical fiber to form a third-layer computing module.For the third supernode, such as TP12, which consists of eight computing modules of computing device 5 and four computing modules of computing device 6 (e.g., computing modules OAM4-OAM7), in this topology, for the eight computing modules in computing device 5, by controlling the first optical switching unit, half of the links of computing modules OAM6 and OAM7 are used to communicate with computing modules OAM6 and OAM7 in computing device 6, respectively. By controlling the first optical switching unit and / or the on-chip optical switch, the other half of the links of computing modules OAM6 and OAM7 are used to communicate with adjacent computing modules in computing device 5, respectively. By controlling the first optical switching unit and / or the on-chip optical switch, half of the links of the remaining computing modules in computing device 5 are used to communicate with two adjacent computing modules, respectively. For the four computing modules in computing device 6, by controlling the first optical switching unit, half of the links of computing modules OAM6 and OAM7 are used to communicate with computing modules OAM6 and OAM7 in computing device 5, respectively. By controlling the first optical switching unit and / or the on-chip optical switch, the other half of the links of computing modules OAM6 and OAM7 are used to communicate with computing modules OAM4 and OAM5 in computing device 6, respectively. By controlling the first optical switching unit and / or the on-chip optical switch, the other half of the links of computing modules OAM4 and OAM5 in computing device 6 are interconnected and communicated. At this time, the remaining computing modules in computing device 6 are used as supernodes in other topologies.

[0085] In the different embodiments shown in Figures 11(a)-(c), the changes in topology do not require manual alteration of the fiber optic connections between different computing devices. Instead, the switching of link connectivity is achieved by controlling the first optical switching unit and the on-chip optical switch on the optical interconnect expansion card, which is convenient and quick, achieving millisecond-level topology switching latency. Specifically, enabling communication between computing modules within a computing device by controlling the first optical switching unit and / or the on-chip optical switch means: controlling the first optical switching unit on the output computing module side to transmit optical signals to the on-chip optical switch (disconnecting the link to the optical coupling interface connected to the fiber optic cable); the on-chip optical switch then transmits the optical signals to the detector on the target computing module side by selecting the transmission path. Enabling communication between corresponding computing modules in different computing devices by controlling the first optical switching unit means controlling the first optical switching unit on the output computing module side to transmit optical signals to the optical coupling interface connected to the fiber optic cable (disconnecting the link to the on-chip optical switch); the optical signals are then transmitted via optical fiber to the detector on the target computing module side of another computing device.

[0086] Furthermore, embodiments of the present invention also provide a computing system comprising multiple computing devices, each computing device being configured with multiple computing modules and multiple optical interconnect expansion cards, each optical interconnect expansion card having an on-chip optical switch and at least one first optical switching unit; the optical interconnect expansion cards of the multiple computing devices communicating via optical fiber connections; at least one of the multiple computing devices serving as a backup device, and the remaining computing devices serving as normally operating devices; when one or more of the multiple operating devices fail, the connection topology of the multiple computing devices is reconstructed by controlling the first optical switching unit and / or the on-chip optical switch on the optical interconnect expansion cards of the multiple computing devices, so that an equal number of backup devices become normally operating devices.

[0087] In some embodiments, the plurality of computing devices includes N computing devices, where N is an integer greater than 1; the plurality of computing devices are ordered from 1 to N; wherein, a first portion of a plurality of optical interconnect expansion cards of computing device M is connected to a portion of a plurality of optical interconnect expansion cards of computing device M-1 via optical fiber, and a second portion of a plurality of optical interconnect expansion cards of computing device M is connected to a portion of a plurality of optical interconnect expansion cards of computing device M+1 via optical fiber, where M is an integer greater than 1 and less than N; a first portion of a plurality of optical interconnect expansion cards of computing device N is connected to a portion of a plurality of optical interconnect expansion cards of computing device N-1 via optical fiber, and a second portion of a plurality of optical interconnect expansion cards of computing device N is connected to a portion of a plurality of optical interconnect expansion cards of computing device 1 via optical fiber; a first portion of a plurality of optical interconnect expansion cards of computing device 1 is connected to a portion of a plurality of optical interconnect expansion cards of computing device N via optical fiber, and a second portion of a plurality of optical interconnect expansion cards of computing device 1 is connected to a portion of a plurality of optical interconnect expansion cards of computing device 2 via optical fiber. The first portion and the second portion are equal, each being half of the plurality of optical interconnect expansion cards of the corresponding computing device.

[0088] In some implementations, by controlling the first optical switching unit and / or the on-chip optical switch on the optical interconnect expansion card of the computing system, the computing modules in computing device 1 to computing device K form a supernode with a predetermined topology, where K is an integer less than N.

[0089] In some embodiments, when any one of computing devices J among computing devices 1 to K fails, the connection topology of multiple computing devices is changed by controlling the on-chip optical switch and / or the first optical switching unit in the computing system, so that the backup device joins the connection topology and becomes a normally operating device, allowing the computing modules in any consecutive computing devices other than computing device J to reorganize into a new supernode. In some embodiments, the repaired computing device J is used as a new backup device by controlling the first optical switching unit on the optical interconnect expansion card of the computing system and / or the on-chip optical switch.

[0090] In some embodiments, controlling the first optical switching unit and / or the on-chip optical switch on the optical interconnect expansion card of the plurality of computing devices includes: controlling the first optical switching unit to select the transmission of signals from the computing modules to the on-chip optical switch or the optical fiber; and controlling the on-chip optical switching unit to select the transmission path for communication between the plurality of computing modules within the same computing device.

[0091] In some embodiments, by controlling the first optical switching unit and / or the on-chip optical switch on the optical interconnect expansion card of the computing system, a one-dimensional ring topology is formed in the communication links of the computing modules in computing device 1 to computing device N-1, with computing device N serving as a backup device.

[0092] In some embodiments, when any one of the computing devices M (from computing devices 1 to N-1) fails, the connection topology of multiple computing devices is changed by controlling the on-chip optical switch and / or the first optical switching unit in the computing system. This allows computing device N to join the connection topology and become a normally operating device, thus reorganizing the computing modules in computing devices 1 to M-1 and computing devices M+1 to N into a new one-dimensional ring topology. In some embodiments, the repaired computing device M is used as a new backup device by controlling the first optical switching unit on the optical interconnect expansion card and / or the on-chip optical switch in the computing system.

[0093] In some embodiments, the step of controlling the on-chip optical switch and the first optical switching unit in the computing system to change the connection topology of multiple computing devices includes: changing the on-chip optical switch and / or the first optical switching unit of computing device M-1, computing device M, and computing device M+1 to disconnect the communication between computing device M-1 and computing device M, and between computing device M and computing device M+1, thereby adjusting the communication links of the internal computing modules of computing device M-1 and computing device M+1; and changing the on-chip optical switch and / or the first optical switching unit of computing device 1 and computing device N to connect the communication between computing device 1 and computing device N, thereby adjusting the communication links of the internal computing modules of computing device 1 and computing device N.

[0094] As shown in Figure 12, in an exemplary embodiment, 16 computing devices according to any one embodiment of the present invention are connected via the optical interconnect expansion card and optical fiber to form a computing system. The connection topology of the 16 computing devices is changed by controlling the on-chip optical switch and / or the first optical switching unit in the computing system. As shown in Figure (1), the 16 computing devices are arranged in order from 1 to 16, and their connection topology is a 1D ring. By controlling the on-chip optical switch and / or the first optical switching unit in the computing system, the connection topology can be changed to include multiple independent rings (each serving as a supernode) and backup nodes. Specifically, as shown in Figure (2), computing devices 1 to 15 serve as working devices and are configured to include multiple independent supernodes, while computing device 16 serves as a backup device. The plurality of independent supernodes include a first supernode (e.g., a supernode containing 16 computing modules) TP16, a second supernode (e.g., a supernode containing 8 computing modules) TP8, and three third supernodes (e.g., a supernode containing 32 computing modules): first third supernode TP32_1, second third supernode TP32_2, and third third supernode TP32_3; wherein, the first supernode TP16 includes computing device 1 and computing device 2; the second supernode TP8 includes computing device 3; the first third supernode TP32_1 includes computing devices 4 to 7, the second third supernode TP32_2 includes computing devices 8 to 11, and the third third supernode TP32_3 includes computing devices 12 to 15. Computing device 16 serves as a backup device.

[0095] In some implementations, as shown in Figure (3), if computing device 1 malfunctions, the connection topology of multiple computing devices is changed by controlling the on-chip optical switch and / or the first optical switching unit in the computing system. This results in the first supernode TP16 including computing devices 2 and 3, the second supernode TP8 including computing device (original backup device) 16, and the three third supernodes TP32_1, TP32_2, and TP32_3 remaining unchanged. In other words, when computing device 1 of the first supernode TP16 is damaged, the backup device becomes the new second supernode TP8, computing devices 3 and 2 are reassembled into the new first supernode TP16, and the other computing devices remain connected. When computing device 1 is repaired, it can serve as a new backup device.

[0096] In some implementations, as shown in Figure (4), if computing device 2 malfunctions, the connection topology of multiple working devices is changed by controlling the on-chip optical switch and / or the first optical switching unit in the computing system. This results in the first supernode TP16 including computing devices 3 and 4, the second supernode TP8 including computing device 1, the first and third supernodes TP32_1 including computing devices 5 to 8, the second and third supernodes TP32_2 including computing devices 9 to 12, and the third and third supernodes TP32_3 including computing devices 13 to 16. In other words, when computing device 2 is damaged, computing device 1 of the original first supernode TP16 is replaced by the second supernode TP8, and the new first supernode TP16 and the three third supernodes are one unit further down the original computing device structure. Once computing device 2 is repaired, it can serve as a new backup device.

[0097] In some implementations, as shown in Figure (5), if computing device 5 malfunctions, the connection topology of multiple working devices is changed by controlling the on-chip optical switch and / or the first optical switching unit in the computing system. This results in the first supernode TP16 including computing devices 6 and 7, the second supernode TP8 including computing device 16, the first and third supernodes TP32_1 including computing devices 1 to 4, and the second and third supernodes TP32_2 and TP32_3 remaining unchanged. That is, when computing device 5 is damaged, the backup device is replaced by the second supernode TP8, and the third supernodes TP32_1, TP32_2, and the first supernode TP16 form a new topology according to the device labels shown in Figure (5), while the others remain unchanged. When computing device 5 is repaired, it can serve as a new backup device.

[0098] In some implementations, as shown in Figure (6), if computing device 8 malfunctions, the connection topology of multiple working devices is changed by controlling the on-chip optical switch and / or the first optical switching unit in the computing system. This ensures that the first supernode TP16, the second supernode TP8, and the first and third supernodes TP32_1 remain unchanged, while the second and third supernodes TP32_2 include computing devices 9 to 12, and the third supernode TP32_3 includes computing devices 13 to 16. That is, when computing device 8 is damaged, the third supernodes TP32_2 and TP32_3 form a new topology according to the device labels shown in Figure (6), while the others remain unchanged. Once computing device 8 is repaired, it can serve as a new backup device.

[0099] In some implementations, as shown in Figure (7), if computing device 10 malfunctions, the connection topology of multiple working devices is changed by controlling the on-chip optical switch and / or the first optical switching unit in the computing system. This results in the first supernode TP16 including computing devices 11 and 12, the second supernode TP8 including computing device 1, the first and third supernodes TP32_1 including computing devices 2 to 5, the second and third supernodes TP32_2 including computing devices 6 to 9, and the third and third supernodes TP32_3 including computing devices 13 to 16. Therefore, when computing device 10 is damaged, all 16 servers will form a new topology according to the device labels shown in Figure (7). Once computing device 10 is repaired, it can serve as a new backup device.

[0100] In some implementations, as shown in FIG. (8), if computing device 13 fails, the connection topology of multiple working devices is changed by controlling the on-chip optical switch and / or the first optical switching unit in the computing system. This results in the first supernode TP16 including computing devices 15 and 16, the second supernode TP8 including computing device 14, the first and third supernodes TP32_1 including computing devices 1 to 4, the second and third supernodes TP32_2 including computing devices 5 to 8, and the third and third supernodes TP32_3 including computing devices 9 to 12. That is, when computing device 13 is damaged, all 16 servers will form a new topology according to the device labels shown in FIG. (8). Once computing device 13 is repaired, it can serve as a new backup device.

[0101] As can be seen from the above, when a single computing device (which may be a server) is damaged and needs to be replaced, the system will automatically switch the connection topology between the devices of each supernode in real time through the on-chip optical switch and / or the first optical switching unit, so that any consecutive number of devices can form a new supernode, thereby improving the overall operating efficiency of the computing system.

[0102] In some embodiments, by controlling the on-chip optical switch and / or the first switching unit in the computing system to change the connection topology of multiple computing devices, a portion of the multiple computing devices enters a working state and forms multiple independent supernodes, while the remaining computing devices serve as backup devices. The multiple independent supernodes include one or more first supernodes and one or more second supernodes. Each first supernode includes one or more computing devices; each second supernode includes one or more computing devices. The topology of the first supernode differs from that of the second supernode. In some embodiments, if any computing device in a working state fails, the connection topology of the multiple computing devices is changed by controlling the on-chip optical switch and / or the first optical switching unit in the computing system. This isolates the failed computing device from communication, activates an equal number of backup devices to become working devices in a new working state, and allows any consecutive working devices in a working state to reorganize into the multiple first supernodes and the multiple second supernodes.

[0103] In some embodiments, the plurality of independent supernodes further includes one or more third supernodes, each comprising one or more computing devices; the topology of the third supernode differs from that of the first and second supernodes. In some embodiments, if any computing device in operation fails, the connection topology of the plurality of computing devices is changed by controlling the on-chip optical switch and / or the first optical switching unit in the computing system. This isolates the failed computing device from communication, activates an equal number of backup devices to become working devices in the new operational state, and allows any consecutively operating devices to reassemble into the one or more first supernodes, the one or more second supernodes, and the one or more third supernodes. In some embodiments, the topology of the first supernode, the second supernode, and the third supernode is a one-dimensional ring topology with varying numbers of computing modules.

[0104] Furthermore, in some embodiments, each computing device includes multiple computing modules, and the multiple computing modules of each computing device are connected to corresponding multiple optical interconnect expansion cards via metal traces. Each of the optical interconnect expansion cards is provided with an on-chip optical switch and at least one first optical switching unit; the optical interconnect expansion cards of the multiple computing devices communicate via optical fiber connections; at least a portion of the computing modules of at least one of the multiple computing devices serve as backup modules, while the remaining computing modules are normally operating working modules; when one or more of the multiple working modules fail, the connection topology of the multiple working modules is reconstructed by controlling the first optical switching unit and / or the on-chip optical switch on the optical interconnect expansion cards of the multiple computing devices, so that an equal number of backup modules as the failed working modules become normally operating working modules.

[0105] In some embodiments, the plurality of computing devices includes N computing devices, where N is an integer greater than 1; the plurality of computing devices are ordered from 1 to N; wherein, for any computing device M, where M is an integer greater than 1 and less than N, a first portion of the plurality of optical interconnect expansion cards of computing device M is connected to a portion of the plurality of optical interconnect expansion cards of computing device M-1 via optical fiber, and a second portion of the plurality of optical interconnect expansion cards of computing device M is connected to a portion of the plurality of optical interconnect expansion cards of computing device M+1 via optical fiber; a first portion of the plurality of optical interconnect expansion cards of computing device N is interconnected with a portion of the plurality of optical interconnect expansion cards of computing device N-1 via optical fiber, and a second portion of the plurality of optical interconnect expansion cards of computing device N is interconnected with a portion of the plurality of optical interconnect expansion cards of computing device 1 via optical fiber; a first portion of the plurality of optical interconnect expansion cards of computing device 1 is connected to a portion of the plurality of optical interconnect expansion cards of computing device N via optical fiber, and a second portion of the plurality of optical interconnect expansion cards of computing device 1 is connected to a portion of the plurality of optical interconnect expansion cards of computing device 2 via optical fiber. In some implementations, the first portion and the second portion are equal, each being half of the plurality of optical interconnect expansion cards of the corresponding computing device.

[0106] In some embodiments, by controlling the on-chip optical switch and / or the first optical switching unit in the computing system to change the connection topology of multiple computing modules in the computing system, a portion of the multiple computing modules enters a working state and forms one or more independent supernodes, while the remaining computing modules serve as backup modules. The multiple independent supernodes include one or more first supernodes, each comprising an arbitrary number of consecutive computing modules. By controlling the on-chip optical switch and / or the first optical switching unit in the computing system, the multiple computing modules within the first supernode form a first target topology. In some embodiments, the one or more independent supernodes include one or more second supernodes, each comprising an arbitrary number of consecutive computing modules. By controlling the on-chip optical switch and / or the first optical switching unit in the computing system, the multiple computing modules within the second supernode form a second target topology. The first target topology of the first supernode differs from the second target topology of the second supernode. In some embodiments, the plurality of independent supernodes further includes: one or more third supernodes, each comprising an arbitrary contiguous plurality of computing modules. The multiple computing modules within the third supernode are configured to form a third target topology by controlling the on-chip optical switch and / or the first optical switching unit in the computing system. The third target topology of the third supernode differs from the first target topology of the first supernode and the second target topology of the second supernode. In some embodiments, if any computing module in operation fails, the connection topology of the multiple computing modules is changed by controlling the on-chip optical switch and the first optical switching unit in the computing system. This isolates the failed computing module from communication, activates an equal number of backup modules as new operating computing modules, and allows the arbitrary contiguous operating computing modules to reassemble into a new plurality of supernodes with the same topology as the original plurality of supernodes.

[0107] In some implementations, the first target topology, the second target topology, and the third target topology are one-dimensional ring topologies with different numbers of computing modules.

[0108] As shown in Figure 13, taking the interconnection of 16 computing devices as an example, a reconfigurable topology is constructed using reconfigurable optical interconnect modules. Similar to Figure 13, it includes three independent TP32 supernodes, one TP16 supernode, one TP8 supernode, and a backup device. When one or more computing modules in the system fail, the system will automatically switch the communication links between the computing modules of each supernode in real time through the on-chip optical switch and / or the first optical switching unit, isolate the faulty module, and use the backup module in the backup device to replace the faulty module by adding it to the connection topology. This can improve the overall operating efficiency of the artificial intelligence computing system.

[0109] In some implementations, the backup module is not limited to a single backup device and can be distributed at any location adjacent to the one or more supernodes.

[0110] Those skilled in the art should understand that the above-disclosed embodiments are merely implementations of the present invention and should not be construed as limiting the scope of the patent protection claimed in this invention. Equivalent variations made according to the embodiments of the present invention are still within the scope of the claims of the present invention.

[0111] Furthermore, the technical solution of the present invention can also be described as follows:

[0112] Example 1: A photonic integrated circuit chip, comprising one or more photonic integrated circuit sub-modules, each of the photonic integrated circuit sub-modules comprising:

[0113] A plurality of first optical switching units, each first optical switching unit including a first optical input port, a first optical output port and a second optical output port, and each first optical switching unit configured to selectively output an optical signal input to its first optical input port via its first optical output port or its second optical output port;

[0114] At least one on-chip optical switch having multiple optical input ports and multiple optical output ports, wherein the multiple optical input ports are optically connected to the second optical output ports of multiple first optical switching units respectively, and the on-chip optical switch is configured to selectively output an optical signal input from any one of its multiple optical input ports via at least one of its multiple optical output ports;

[0115] Multiple modulators are optically connected to the corresponding first optical input ports of the multiple first optical switching units and configured to modulate information carried by electrical signals into the optical signals;

[0116] Multiple detectors, at least a portion of which are optically connected to multiple optical output ports of the on-chip optical switch;

[0117] A plurality of first optical couplers configured to optically connect the first optical output ports of a plurality of first optical switching units to a first external fiber array; and

[0118] A second optical coupler, which is optically connected to at least a portion of the plurality of detectors, is configured to transmit optical signals from a second external fiber array to that portion of the plurality of detectors.

[0119] Example 2: The photonic integrated circuit chip as described in Example 1, characterized in that each photonic integrated circuit sub-module further includes multiple wavelength multiplexers and multiple demultiplexers;

[0120] The plurality of modulators are configured into a plurality of modulator arrays, and the plurality of detectors are configured into a plurality of detector arrays;

[0121] The modulator array is optically connected to the corresponding first optical switching unit through the wavelength multiplexer. Each wavelength multiplexer has multiple optical input ports and one optical output port. Each of the multiple optical input ports of the wavelength multiplexer is connected to a modulator in the modulator array, and one optical output port of the wavelength multiplexer is connected to a first optical input port of the first optical switching unit.

[0122] The detector array is optically connected to the corresponding optical output port of the on-chip optical switch or the second optical coupler via the demultiplexer. Each demultiplexer has one optical input port and multiple optical output ports. One optical input port of the demultiplexer is connected to one optical output port of the on-chip optical switch or the second optical coupler. Each of the multiple optical output ports of the demultiplexer is connected to one of the detectors in the detector array.

[0123] Example 3: The photonic integrated circuit chip as described in Example 1 or 2, characterized in that,

[0124] The number of detectors or detector arrays is twice that of modulators or modulator arrays, wherein a portion of the detectors or detector arrays is connected to the on-chip optical switch and another portion is connected to the second optical coupler.

[0125] Example 4: The photonic integrated circuit chip as described in Example 1 or 2, characterized in that each photonic integrated circuit submodule further includes a third optical switching unit, the detector or demultiplexer is optically connected to the on-chip optical switch and the second optical coupler through the third optical switching unit, and the number of the detector or detector array is equal to the number of the modulator or modulator array.

[0126] Example 5: The photonic integrated circuit chip as described in Example 4, characterized in that the third optical switching unit includes a first optical input port, a second optical input port, and an optical output port. The first optical input port of the third optical switching unit is connected to the second optical coupler. The second optical input port of the third optical switching unit is connected to an optical output port of the on-chip optical switch. The optical output port of the third optical switching unit is connected to the detector or the demultiplexer. By controlling the third optical switching unit, the first optical input port of the third optical switching unit is connected to the optical output port of the third optical switching unit, or the second optical input port of the third optical switching unit is connected to the optical output port of the third optical switching unit.

[0127] Example 6: The photonic integrated circuit chip as described in Example 4, characterized in that the third optical switching unit is respectively disposed on the optical path connecting the detector or detector array to the on-chip optical switch, and disposed on the optical path connecting the detector or detector array to the second optical coupler.

[0128] Example 7: The photonic integrated circuit chip as described in Example 4, characterized in that the third optical switching unit is a MEMS optical path switching unit or an MZI optical path switching unit.

[0129] Example 8: The photonic integrated circuit chip as described in Example 1 or 2, characterized in that the on-chip optical switch includes a plurality of second optical switching units;

[0130] The plurality of second optical switching units select the transmission path of the optical signal input to the on-chip optical switch, so that the optical signal is output from at least one of the plurality of optical output ports of the on-chip optical switch.

[0131] Example 9: The photonic integrated circuit chip as described in Example 8, characterized in that the first optical switching unit is a MEMS optical path switching unit or an MZI optical path switching unit; and / or

[0132] The second optical switching unit is an MZI optical path switching unit.

[0133] Example 10: The photonic integrated circuit chip as described in Example 9, characterized in that the first optical switching unit is an MZI optical path switching unit, which includes:

[0134] The first beam splitter has one optical input port and two optical output ports;

[0135] The second beam splitter has two optical input ports and two optical output ports; and

[0136] Two phase shifters are respectively connected between the two optical output ports of the first beam splitter and the two optical input ports of the second beam splitter.

[0137] Example 11: The photonic integrated circuit chip as described in Example 8, characterized in that the second optical switching unit comprises:

[0138] Two beam splitters, each beam splitter having two optical input ports and two optical output ports, the two beam splitters including a first beam splitter and a second beam splitter;

[0139] Two phase shifters are respectively connected between the two optical output ports of the first beam splitter and the two optical input ports of the second beam splitter.

[0140] Example 12: The photonic integrated circuit chip as described in Example 1 or 2, characterized in that the modulator includes at least one of the following: a micro-ring modulator, a Mach-Zehnder modulator, and an electroabsorption modulator;

[0141] And / or, the detector includes a microring detector or a photodiode.

[0142] Example 13: The photonic integrated circuit chip as described in Example 1 or 2, characterized in that each photonic integrated circuit sub-module further includes:

[0143] A third optical coupler is configured to input light from an off-chip light source into the photonic integrated circuit submodule;

[0144] An optical power splitter, which is optically connected to the third optical coupler, is configured to split an input light into multiple output lights, each of which has substantially the same power, and the multiple output lights are transmitted to modulators.

[0145] Example 14: An optical interconnect module comprising a photonic integrated circuit chip and a transceiver analog electrical chip as described in any one of Examples 1 to 13;

[0146] The transceiver analog electrical chip is configured to convert a received first digital electrical signal into a driving analog electrical signal and transmit the driving analog electrical signal carrying the information to at least one of a plurality of modulators in the photonic integrated circuit chip, or to receive a received analog electrical signal output by at least one of a plurality of detectors in the photonic integrated circuit chip and convert the received analog electrical signal into a second digital electrical signal.

[0147] The modulator is configured to modulate the information carried by the driving analog electrical signal into the optical signal.

[0148] Example 15: The optical interconnect module as described in Example 14, characterized in that the transceiver analog electrical chip is disposed above the photonic integrated circuit chip, and receives the first digital electrical signal and / or transmits the second digital electrical signal through a conductive via penetrating the photonic integrated circuit chip.

[0149] Example 16: The optical interconnect module as described in Example 14, characterized in that the optical interconnect module further includes an optical switching control analog electrical chip, which is configured to correspond to the on-chip optical switch in the photonic integrated circuit chip, and is configured to control a plurality of second optical switching units of the on-chip optical switch to select the optical signal input to the on-chip optical switch according to a preset transmission path, so that the optical signal is output from a preset optical output port among a plurality of optical output ports of the on-chip optical switch.

[0150] Example 17: The optical interconnect module as described in Example 16, characterized in that the optical switching control analog electrical chip is disposed above the photonic integrated circuit, and receives the optical switching control analog signal through a conductive via penetrating the photonic integrated circuit chip.

[0151] Example 18: The optical interconnect module as described in Example 14 is characterized in that it further includes a substrate, the photonic integrated circuit chip is mounted on the substrate, and the transceiver analog electrical chip is mounted on the photonic integrated circuit optical chip on the other side of the substrate.

[0152] Example 19: An optical interconnect expansion card, comprising:

[0153] First PCB board;

[0154] The optical interconnect module as described in any one of Embodiments 14 to 18 is disposed on the first PCB board;

[0155] Multiple fiber optic interfaces are mounted on the first PCB board and are optically connected to the optical interconnect module via the first external fiber optic array and the second external fiber optic array to achieve optical communication with the optical interconnect module.

[0156] Multiple electrical communication interfaces are disposed on the first PCB board for receiving the first digital signal and / or transmitting the second digital electrical signal;

[0157] Multiple re-timers, mounted on the first PCB board, are communicatively connected to the electrical communication interface and the optical interconnect module. They are used to reshape the first digital electrical signal and transmit the reshaped electrical signal to the optical interconnect module; and / or reshape the second digital electrical signal received from the optical interconnect module and transmit it through the electrical communication interface.

[0158] Example 20: The optical interconnect expansion card as described in Example 19, characterized in that,

[0159] Each of the retimers has multiple communication channels, and the multiple electrical communication interfaces have multiple communication channels. The total number of communication channels of the retimers is equal to the total number of telecommunication channels of the electrical communication interfaces.

[0160] Example 21: The optical interconnect expansion card as described in Example 19, characterized in that,

[0161] The re-timer is communicatively connected to the optical interconnect module via traces on the first PCB board.

[0162] Example 22: The optical interconnect expansion card as described in Example 19 is characterized in that it further includes a laser module, which is disposed on the first PCB board and optically connected to the optical interconnect module through a third fiber array to input a laser beam to the optical interconnect module.

[0163] Example 23: A computing device comprising:

[0164] Multiple computing modules;

[0165] Multiple optical interconnect expansion cards as described in any one of Examples 19 to 22;

[0166] The plurality of computing modules are communicatively connected to the plurality of optical interconnect expansion cards.

[0167] Example 24: The computing device as described in Example 23, characterized in that it further includes a second PCB board.

[0168] The multiple computing modules are mounted on the second PCB board.

[0169] The multiple optical interconnect expansion cards are plugged into the second PCB board.

[0170] The multiple computing modules are communicatively connected to the multiple optical interconnect expansion cards via traces on the second PCB board.

[0171] Example 25: A computing system comprising:

[0172] Multiple computing devices as described in Embodiment 23 or 24;

[0173] At least one switch;

[0174] The multiple optical interconnect expansion cards of the multiple computing devices are communicatively connected to the at least one switch via optical fiber to connect the multiple computing devices.

[0175] Example 26: The computing system as described in Example 25, characterized in that the switch includes: an optical path switch or an electrical switch with an optical module, wherein the optical module is used for optical communication with the optical interconnect expansion card.

Claims

A computing system comprising a plurality of computing devices, each of the computing devices being configured with a plurality of computing modules and a plurality of optical interconnect expansion cards, each of the optical interconnect expansion cards being provided with an optical switch on chip and at least one first optical switch unit; the optical interconnect expansion cards of the plurality of computing devices are in communication through fiber connections; at least one of the plurality of computing devices is a backup device, and the rest of the computing devices are working devices in normal operation; when one or more of the working devices in the plurality of working devices fails, the connection topology of the plurality of computing devices is reconfigured by controlling the first optical switch units and / or the optical switches on chip on the optical interconnect expansion cards of the plurality of computing devices, so that an equal number of backup devices to the failed working devices become working devices in normal operation. The computing system of claim 1, wherein the plurality of computing devices comprises N computing devices, N being an integer greater than 1; the plurality of computing devices are ordered from 1 to N; wherein, for any computing device M, M being an integer greater than 1 and less than N, a first portion of the plurality of optical interconnect expansion cards of the computing device M are in fiber connection with a portion of the plurality of optical interconnect expansion cards of the computing device M-1, and a second portion of the plurality of optical interconnect expansion cards of the computing device M are in fiber connection with a portion of the plurality of optical interconnect expansion cards of the computing device M+1; a first portion of the plurality of optical interconnect expansion cards of the computing device N are in fiber connection with a portion of the plurality of optical interconnect expansion cards of the computing device N-1, and a second portion of the plurality of optical interconnect expansion cards of the computing device N are in fiber connection with a portion of the plurality of optical interconnect expansion cards of the computing device 1; a first portion of the plurality of optical interconnect expansion cards of the computing device 1 are in fiber connection with a portion of the plurality of optical interconnect expansion cards of the computing device N, and a second portion of the plurality of optical interconnect expansion cards of the computing device 1 are in fiber connection with a portion of the plurality of optical interconnect expansion cards of the computing device 2. The computing system of claim 2, wherein, The first portion and the second portion are equal, each being half of the plurality of optical interconnect expansion cards of the corresponding computing device. The computing system of claim 2, wherein By controlling the first optical switch units and / or the optical switches on chip on the optical interconnect expansion cards of the computing system, the computing modules in the computing devices 1 to K form a supernode with a predetermined topology, K being an integer less than N. The computing system of claim 4, wherein When any computing device J in the computing devices 1 to K fails, by controlling the optical switches on chip and / or the first optical switch units in the computing system, the connection topology of the plurality of computing devices is changed so that the backup devices join the connection topology and become working devices in normal operation, and the computing modules in any continuous computing device other than the computing device J reorganize into a new supernode. The computing system of claim 5, wherein By controlling the first optical switch units and / or the optical switches on chip on the optical interconnect expansion cards of the computing system, the repaired computing device J becomes a new backup device. The computing system of claim 1, wherein controlling the first optical switch unit and / or the on-chip optical switch on the optical interconnection expansion card of the plurality of computing devices comprises: controlling the first optical switch unit to select transmission of signals from the computing module to the on-chip optical switch or the optical fiber; controlling the on-chip optical switch to select transmission paths for the plurality of computing modules within the same computing device to communicate with each other. The computing system of claim 2, wherein changing the connection topology of the plurality of computing devices by controlling the on-chip optical switch and / or the first switch unit in the computing system, so that a part of the plurality of computing devices enters a working state to become working devices and forms a plurality of independent supernodes, and the remaining computing devices become backup devices; the plurality of independent supernodes comprises one or more first supernodes and one or more second supernodes; the first supernode comprises one or more computing devices; the second supernode comprises one or more computing devices; wherein the topology of the first supernode is different from the topology of the second supernode. The computing system of claim 8, wherein If any computing device in a working state fails, the connection topology of the plurality of computing devices is changed by controlling the on-chip optical switch and / or the first optical switch unit in the computing system, so that the failed computing device is communicationally isolated, an equal number of backup devices are enabled to become new working devices in a working state, and any continuous working devices in a working state are reorganized into the plurality of first supernodes and the plurality of second supernodes. The computing system of claim 8, wherein the plurality of independent supernodes further comprises: one or more third supernodes, the third supernode comprising one or more computing devices; the topology of the third supernode is different from the topology of the first supernode and the second supernode. The computing system of claim 10, wherein If any computing device in a working state fails, the connection topology of the plurality of computing devices is changed by controlling the on-chip optical switch and / or the first optical switch unit in the computing system, so that the failed computing device is communicationally isolated, an equal number of backup devices are enabled to become new working devices in a working state, and any continuous working devices in a working state are reorganized into the one or more first supernodes, the one or more second supernodes, and the one or more third supernodes. The computing system of claim 11, wherein: the first supernode comprises one computing device, the second supernode comprises two computing devices, and the third supernode comprises four computing devices. A computing system comprising a plurality of computing devices, each of the computing devices being configured with a plurality of computing modules and a plurality of optical interconnection expansion cards, each of the optical interconnection expansion cards being provided with an on-chip optical switch and at least one first optical switch unit; the optical interconnection expansion cards of the plurality of computing devices are connected for communication by optical fibers; at least a part of the computing modules of at least one of the plurality of computing devices are backup modules, and the remaining computing modules are working modules in normal operation. When one or more of the plurality of working modules fails, the connection topology of the plurality of computing modules is reconfigured by controlling the first optical switching unit and / or the on-chip optical switch on the optical interconnection expansion card of the plurality of computing devices, so that the backup modules equivalent to the failed working modules become normal working modules. The computing system of claim 13, wherein, The plurality of computing devices includes N computing devices, N being an integer greater than 1; The plurality of computing devices is sorted in 1 to N; For any computing device M, M is an integer greater than 1 and less than N, a first part of the plurality of optical interconnection expansion cards of the computing device M is connected to a part of the plurality of optical interconnection expansion cards of the computing device M-1 through optical fibers, and a second part of the plurality of optical interconnection expansion cards of the computing device M is connected to a part of the plurality of optical interconnection expansion cards of the computing device M+1 through optical fibers; A first part of the plurality of optical interconnection expansion cards of the computing device N is connected to a part of the plurality of optical interconnection expansion cards of the computing device N-1 through optical fibers, and a second part of the plurality of optical interconnection expansion cards of the computing device N is connected to a part of the plurality of optical interconnection expansion cards of the computing device 1 through optical fibers; A first part of the plurality of optical interconnection expansion cards of the computing device 1 is connected to a part of the plurality of optical interconnection expansion cards of the computing device N through optical fibers, and a second part of the plurality of optical interconnection expansion cards of the computing device 1 is connected to a part of the plurality of optical interconnection expansion cards of the computing device 2 through optical fibers. The computing system of claim 14, wherein, The first part and the second part are equal, each being half of the plurality of optical interconnection expansion cards of the corresponding computing device. The computing system of claim 14, wherein The connection topology of the plurality of computing modules in the computing system is changed by controlling the on-chip optical switch and / or the first optical switching unit in the computing system, so that a part of the plurality of computing modules enters a working state and forms one or more independent supernodes, and the remaining computing modules serve as backup modules. The plurality of independent supernodes includes one or more first supernodes, and the first supernode includes any continuous plurality of computing modules, and the plurality of computing modules in the first supernode form a first target topology structure by controlling the on-chip optical switch and / or the first optical switching unit in the computing system. The computing system of claim 16, wherein The one or more independent supernodes includes one or more second supernodes, and the second supernode includes any continuous plurality of computing modules, and the plurality of computing modules in the second supernode form a second target topology structure by controlling the on-chip optical switch and / or the first optical switching unit in the computing system; wherein, The first target topology structure of the first supernode is different from the second target topology structure of the second supernode. The computing system of claim 17, wherein The plurality of independent supernodes further includes: one or more third supernodes, the third supernode includes any continuous plurality of computing modules, and the plurality of computing modules in the third supernode form a third target topology structure by controlling the on-chip optical switch and / or the first optical switching unit in the computing system; wherein, The third target topology of the third supernode is different from the first target topology of the first supernode and the second target topology of the second supernode. The computing system of any of claims 16-18, wherein, The first target topology, the second target topology, and the third target topology are one-dimensional ring topologies with different numbers of computing modules. The computing system of any of claims 16-18, wherein, If any computing module in the working state fails, the connection topology of multiple computing modules is changed by controlling the on-chip optical switch and / or the first optical switching unit in the computing system. This isolates the failed computing module from communication, enables an equal number of backup modules to become new computing modules in the working state, and allows any consecutive computing modules in the working state to be reorganized into a new set of multiple supernodes with the same topology as the original multiple supernodes. The computing system of claim 20, wherein The backup modules are located at any position adjacent to the one or more supernodes.

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