Service processing component and service processing device

Abstract

A service processing component and a service processing device. The service processing component comprises a first processing board, a second processing board and a first interconnection board; the first processing board comprises n1 computing nodes and a first connector, the n1 computing nodes are connected to the first connector, and n1 is an integer greater than 1; the second processing board comprises n2 computing nodes and a second connector, the n2 computing nodes are connected to the second connector, and n2 is an integer greater than 1; the first interconnection board comprises a third connector and a fourth connector; the first connector is connected to the third connector, the second connector is connected to the fourth connector, and the third connector is connected to the fourth connector; the n1 computing nodes and the n2 computing nodes are used for implementing service data processing. By means of the solution, capacity expansion requirements for computing node clusters can be satisfied.

Description

Business processing components and business processing equipment

[0001] This application claims priority to Chinese Patent Application No. 202410704041.2, filed with the China National Intellectual Property Administration on May 31, 2024, entitled "Business Processing Components and Business Processing Equipment", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of communication technology, specifically to service processing components and service processing equipment. Background Technology

[0003] As business demands continue to evolve, the amount of data requiring processing is also increasing. This necessitates building computing node clusters capable of meeting these business processing requirements. For example, in the field of intelligent vehicles, with the deepening development of intelligent driving services, it is necessary to deploy business processing systems such as data storage, algorithm training, or vehicle-cloud collaborative processing in the cloud. Because these systems require processing large amounts of data and involve massive computational demands, they need to be deployed in a computing node cluster composed of multiple computing nodes. During specific business processing, the computing nodes in the cluster need to interact and communicate to achieve contextual interconnection of data, thereby completing the entire business processing process. However, with the rapid increase in the amount of data to be processed and the growing number of computing nodes in the cluster, how to achieve interconnection between these computing nodes has become an urgent problem to be solved. Summary of the Invention

[0004] This application provides a business processing component and a business processing device that can realize the interconnection between a large number of computing nodes in a computing node cluster, thereby meeting the expansion needs of the computing node cluster.

[0005] In a first aspect, this application provides a business processing component, which includes a first processing board, a second processing board, and a first interconnect board; the first processing board includes n1 computing nodes and a first connector, the n1 computing nodes being connected to the first connector, where n1 is an integer greater than 1; the second processing board includes n2 computing nodes and a second connector, the n2 computing nodes being connected to the second connector, where n2 is an integer greater than 1; the first interconnect board includes a third connector and a fourth connector; the first connector is connected to the third connector, the second connector is connected to the fourth connector, and the third connector is connected to the fourth connector; the n1 computing nodes and the n2 computing nodes are used to process business data.

[0006] Exemplarily, the aforementioned third connector and the aforementioned fourth connector are connected via cables or printed circuit board (PCB) traces. Exemplarily, the aforementioned computing nodes are central processing units (CPUs), graphics processing units (GPUs), neural network processing units (NPUs), tensor processing units (TPUs), or deep learning processing units (DPUs). It is understood that the description of computing nodes herein is merely illustrative and does not constitute a limitation on the embodiments of this application. Exemplarily, the aforementioned n1 computing nodes may be some or all of the computing nodes on the first processing board; similarly, the aforementioned n2 computing nodes may be some or all of the computing nodes on the second processing board.

[0007] In the above scheme, computing nodes can be mounted on multiple processing boards and configured with interconnect boards. The processing boards and interconnect boards are connected via connectors. After the processing boards are connected to the interconnect boards, the connectors within the interconnect boards can be connected, for example, via cables or PCB traces, to connect computing nodes between different processing boards, facilitating the formation of computing node clusters. This scheme, through this connection method between connectors in the interconnect board, overcomes the limitations of existing schemes that connect computing nodes via network chips or switching chips, enabling interconnection between more computing nodes and meeting the expansion needs of computing node clusters. It also saves on the cost of network chips or switching chips. Furthermore, compared to PCB trace connections, the cable connection method between connectors in the interconnect board eliminates the need for special PCB materials in the interconnect board manufacturing, further reducing manufacturing costs. Cable connections also improve signal bandwidth and reduce insertion loss. This allows for high-speed interconnection of high-performance computing node clusters (e.g., clusters with a large number of computing nodes). It makes the contextual business interactions between computing nodes appear to run on a single computing node, meaning the computing node cluster can be viewed as a high-performance supernode, thereby significantly improving business processing efficiency.

[0008] In one possible implementation, the aforementioned first connector and the aforementioned third connector form an orthogonal connector, and the aforementioned first processing board and the aforementioned interconnect board are orthogonally connected; the aforementioned second connector and the aforementioned fourth connector form an orthogonal connector, and the aforementioned second processing board and the aforementioned interconnect board are orthogonally connected.

[0009] In the above scheme, the processing board and the interconnect board are orthogonally connected, which can reduce the line length and reduce data transmission latency and loss.

[0010] In one possible implementation, any two nodes among the aforementioned n1 computing nodes are interconnected, and any two nodes among the aforementioned n2 computing nodes are interconnected.

[0011] In the above scheme, multiple computing nodes on the processing board form a full-mesh topology, which eliminates the need for additional network chips to relay data, saving costs and reducing data transmission latency.

[0012] In one possible implementation, the aforementioned business processing component further includes a third processing board, which includes n3 computing nodes and a fifth connector. The n3 computing nodes are connected to the fifth connector, where n3 is an integer greater than 1. The aforementioned first interconnect board further includes a sixth connector. The aforementioned fifth connector is connected to the aforementioned sixth connector, and the aforementioned third connector and / or the aforementioned fourth connector are connected to the aforementioned sixth connector.

[0013] For example, the aforementioned third connector and the aforementioned sixth connector are connected by a cable or PCB trace, and / or the aforementioned fourth connector and the aforementioned sixth connector are connected by a cable or PCB trace.

[0014] The above solution enables interconnection between computing nodes on more processing boards, thereby meeting the expansion needs of larger computing node clusters.

[0015] In one possible implementation, the aforementioned business processing component further includes a second interconnect board; the aforementioned first processing board further includes a seventh connector, and the aforementioned n1 computing nodes are connected to the aforementioned seventh connector; the aforementioned second processing board further includes an eighth connector, and the aforementioned n2 computing nodes are connected to the aforementioned eighth connector; the aforementioned second interconnect board includes a ninth connector and a tenth connector; the aforementioned seventh connector is connected to the aforementioned ninth connector, the aforementioned eighth connector is connected to the aforementioned tenth connector, and the aforementioned ninth connector is connected to the aforementioned tenth connector.

[0016] In the above scheme, the interconnection between computing nodes in the processing board can be achieved through multiple interconnect boards. This method can flexibly realize the connection of the required computing node cluster topology and has strong scalability.

[0017] In one possible implementation, the aforementioned first interconnect board further includes a network chip and an external interface; the aforementioned third connector and the aforementioned fourth connector are also connected to the aforementioned network chip, and the aforementioned network chip is also connected to the aforementioned external interface; the aforementioned external interface is used to connect to another of the aforementioned service processing components.

[0018] In the above solution, a network chip and external interface can be set on the interconnect board to connect with another business processing component, thereby further expanding the number of computing node clusters to build a more powerful computing cluster.

[0019] In one possible implementation, the aforementioned first connector and the aforementioned third connector can be connected via a backplane. For example, the aforementioned third connector and the aforementioned fourth connector are connected via a first cable, which is bundled onto the aforementioned backplane.

[0020] In the above solution, the connectors of the processing board and the interconnect board can be connected via a backplane. For example, the connectors of the processing board and the interconnect board can be first connected to the connectors of the backplane, and the connection between the connectors of the processing board and the interconnect board is achieved through the connectors of the backplane. In addition, the backplane can also be used to bundle the cables between the interconnect board connectors, solving the cable placement problem and reducing the difficulty of engineering implementation.

[0021] In one possible implementation, the aforementioned third connector is located on the first surface of the aforementioned first interconnect board, and the aforementioned fourth connector is located on the second surface of the aforementioned first interconnect board, with the aforementioned first surface and the aforementioned second surface facing away from each other.

[0022] In the above solution, this design allows some cables to be placed on the first surface of the interconnect board, while others can be placed on the second surface. This significantly reduces the number of cables on the same surface, making it easier to distinguish the correspondence between cables and connectors. This improves connection efficiency and reduces the probability of connection errors during the connection process, and also alleviates the difficulties in subsequent maintenance caused by excessive and improperly placed cables.

[0023] In one possible implementation, the aforementioned n1 computing nodes include a first computing node, and the aforementioned n2 computing nodes include a second computing node; the aforementioned first computing node is used to process the first data to obtain a first processing result, and send the aforementioned first processing result to the aforementioned second computing node; the aforementioned first processing result is transmitted to the aforementioned second computing node through the aforementioned first connector, the aforementioned third connector, the aforementioned fourth connector and the aforementioned second connector; the aforementioned second computing node is used to process the aforementioned first processing result.

[0024] In the above scheme, based on the aforementioned connection relationships, nodes on different processing boards can communicate with each other. In particular, the implementation of cable connections between connectors in the interconnect board enables high-bandwidth, low-insertion-loss data transmission between nodes on different processing boards, thereby significantly improving service processing efficiency.

[0025] In one possible implementation, the aforementioned n1 computing nodes include a third computing node, the aforementioned n2 computing nodes include a fourth computing node, and the aforementioned n3 computing nodes include a fifth computing node;

[0026] The aforementioned third computing node is used to process the second data to obtain a second processing result, and sends the aforementioned second processing result to the aforementioned fifth computing node; the aforementioned second processing result is transmitted to the aforementioned fifth computing node through the aforementioned first connector, the aforementioned third connector, the aforementioned sixth connector and the aforementioned fifth connector;

[0027] The aforementioned fourth computing node is used to process the third data to obtain a third processing result, and sends the aforementioned third processing result to the aforementioned fifth computing node; the aforementioned third processing result is transmitted to the aforementioned fifth computing node through the aforementioned second connector, the aforementioned fourth connector, the aforementioned sixth connector and the aforementioned fifth connector;

[0028] The aforementioned fifth computing node is used to process the aforementioned second processing result and the aforementioned third processing result.

[0029] In the above scheme, based on the aforementioned connection relationship, nodes on the two processing boards can jointly transmit data to nodes on the third processing board. In particular, for the implementation where connectors in the interconnect board are connected via cables, high-bandwidth, low-insertion-loss data transmission can be achieved between nodes on different processing boards through this cable connection. This can greatly improve service processing efficiency.

[0030] Secondly, this application provides a service processing component, which includes a first processing board, a second processing board, and a first interconnect board; the first processing board includes n1 computing nodes and a first connector, the n1 computing nodes being connected to the first connector, where n1 is an integer greater than 1; the second processing board includes n2 computing nodes and a second connector, the n2 computing nodes being connected to the second connector, where n2 is an integer greater than 1; the first interconnect board includes a third connector, a fourth connector, and a network chip; the first connector and the second connector are connected by cables, the first connector and the third connector are connected by cables, the second connector and the fourth connector are connected by cables, and the third connector and the fourth connector are connected to the network chip; the network chip is used to connect to another of the aforementioned service processing components; the n1 computing nodes and the n2 computing nodes are used to process service data.

[0031] In the above solution, processing boards are directly connected by cables, and the interconnect board includes mesh panels for connecting to other service processing components. This implementation method can also overcome the limitation of connecting computing nodes through network chips within the same service processing component, enabling interconnection between more computing nodes and meeting the expansion needs of computing node clusters. Furthermore, mesh panels can be added to the interconnect board to further support the expansion of even larger computing node clusters. Moreover, compared to PCB trace connections, direct cable connections between processing boards eliminate the need for special PCB materials in the interconnect board fabrication, further reducing manufacturing costs. Cable connections also improve signal bandwidth and reduce insertion loss. This effectively enables high-speed interconnection of high-performance computing node clusters (e.g., clusters with a large number of computing nodes). It allows the contextual service relationships between computing nodes to function as if they were running on a single computing node, meaning the computing node cluster can be viewed as a high-performance supernode, thereby significantly improving service processing efficiency.

[0032] In one possible implementation, the aforementioned business processing component also includes a backplane, on which the aforementioned cables are bundled.

[0033] In the above solution, the backplane can also be used to bundle cables between interconnect board connectors, solving the cable placement problem and reducing the difficulty of engineering implementation.

[0034] Thirdly, this application provides a service processing device, which includes a chassis and a service processing component, wherein the service processing component is disposed in the chassis; the service processing component is the service processing component described in any of the first aspects above. Attached Figure Description

[0035] Figures 1 to 5 show schematic diagrams of the connection topology of the computing node cluster.

[0036] Figure 6 shows a schematic diagram of the business processing component provided in an embodiment of this application.

[0037] Figure 7 shows a possible structural diagram of the connector in the interconnect board.

[0038] Figure 8 shows a schematic diagram of the connectors in the interconnect board.

[0039] Figure 9 shows a schematic diagram of the overall appearance and structure of the business processing component.

[0040] Figure 10 shows another structural schematic diagram of the business processing component provided in the embodiment of this application.

[0041] Figure 11 shows a schematic diagram of the overall appearance and structure of the business processing component.

[0042] Figures 12 and 13 show schematic diagrams of the interconnect board's surface structure.

[0043] Figure 14 shows another structural schematic diagram of the business processing component provided in an embodiment of this application.

[0044] Figure 15 shows a schematic diagram of the back panel's structure.

[0045] Figure 16 shows another structural schematic diagram of the business processing component provided in an embodiment of this application.

[0046] Figures 17 to 20 are schematic diagrams showing the connection between the two business processing components.

[0047] Figure 21 shows a schematic diagram of the overall appearance and structure of the business processing component.

[0048] Figures 22 and 23 show schematic diagrams illustrating how computing nodes between processing boards communicate through interconnect boards. Detailed Implementation

[0049] In this application embodiment, "multiple" refers to two or more. In this application embodiment, "and / or" is used to describe the association relationship of related objects, indicating three relationships that can exist independently. For example, A and / or B can mean: A exists alone, B exists alone, or A and B exist simultaneously. The description methods used in this application embodiment, such as "at least one of a1, a2, ... and an (or at least one of them)," include the case where any one of a1, a2, ... and an exists alone, as well as the case where any combination of any multiple of a1, a2, ... and an exists alone. Each case can exist alone. For example, the description method of "at least one of a, b, and c" includes the cases where a, b, c, a and b combined, a and c combined, b and c combined, or a, b, and c combined.

[0050] In this application, the terms "first," "second," etc., are used to distinguish identical or similar items with substantially the same function. It should be understood that there is no logical or temporal dependency between "first," "second," and "nth," nor does it limit the quantity or order of execution. It should also be understood that although the following description uses the terms "first," "second," etc., to describe various elements, these elements should not be limited by the terms. These terms are merely used to distinguish one element from another.

[0051] In the various embodiments of this application, unless otherwise specified or in case of logical conflict, the terminology and / or descriptions between the various embodiments are consistent and can be referenced by each other. Technical features in different embodiments can be combined to form new embodiments according to their inherent logical relationships.

[0052] To meet the expansion requirements of computing node clusters in business processing systems, embodiments of this application provide a business processing component and a business processing device. Before introducing the business processing component and the business processing device, the connection topology of the computing node cluster is illustrated in Figures 1 to 5.

[0053] First, refer to Figure 1 for an example, which shows a two-dimensional mesh (2D mesh) topology. Figure 1 uses a 4*4 grid, or 16 compute nodes, as an example. As can be seen, these 16 compute nodes are arranged in a two-dimensional mesh, with any two adjacent compute nodes connected together.

[0054] See Figure 2 for an example, which illustrates a 2Dtours topology. Figure 2 uses a 4x4 structure, or 16 compute nodes, as an example. As can be seen, the 2Dtours topology is formed by connecting the first and last compute nodes of each row and the first and last compute nodes of each column, based on the topology in Figure 1.

[0055] Referring to Figure 3, a 3D mesh topology is shown. In a specific implementation, a 3D mesh topology is obtained by superimposing multiple 2D mesh topologies and connecting corresponding computing nodes in adjacent 2D mesh topologies. For example, Figure 3 illustrates three 2D mesh topologies, each containing 4*4, or 16 computing nodes. As shown in Figure 3, computing nodes with the same labels in the first and second 2D mesh topologies are connected, as are computing nodes with the same labels in the second and third 2D mesh topologies.

[0056] Referring to Figure 4, a 3Dtours topology is shown. Figure 4 is based on the topology of Figure 3, with the first and last computational nodes of each row and each column connected to form the 3Dtours topology. In Figure 4, to reduce the complexity of the connections, only the connection lines between the first and last computational nodes of two columns are shown as an example. For example, see the dashed line connecting computational node 13 of the first 2D mesh topology and computational node 13 of the third 2D mesh topology. And see the dashed line connecting computational node 4 of the first 2D mesh topology and computational node 4 of the third 2D mesh topology.

[0057] See Figure 5 for an example, which illustrates a full-mesh topology. Figure 5 uses eight compute nodes as an example. As can be seen, each of these eight compute nodes is connected to the other seven compute nodes. That is, any two nodes are interconnected.

[0058] It is understood that the connection topology of the computing node cluster shown in Figures 1 to 5 above is only an example and does not constitute a limitation on the embodiments of this application. In specific implementations, the computing node cluster can adopt any topology for connection, which is determined according to the actual application requirements, and the embodiments of this application do not impose any restrictions on this.

[0059] For example, in specific implementations, the computing node cluster described in this application embodiment can be used to process various business data. These include, but are not limited to, data storage, data processing, or algorithm model training. For example, taking the field of intelligent vehicles, the data processing may include vehicle-cloud collaborative data processing, high-precision map data processing, or sensor (e.g., radar or camera) data processing. The algorithm model training may include the training of various AI models, machine learning models, neural network models, and deep learning models. It is understood that the description of the application scenarios of the computing node cluster herein is merely illustrative and does not constitute a limitation on the embodiments of this application.

[0060] Regardless of the specific topology of the compute node cluster, as the number of compute nodes in the cluster increases, how to interconnect these compute nodes within the physical components becomes a further problem that needs to be solved. In some existing solutions, these compute nodes can be interconnected via switching chips or network chips. However, due to the limitations in the number of interfaces and performance of the switching chips or network chips themselves, the number of compute nodes interconnected via these chips is limited. As the number of compute nodes in the compute node cluster increases, interconnecting these compute nodes via switching chips or network chips can no longer meet the expansion needs of the compute node cluster. Using multiple switching chips or network chips to interconnect these compute nodes results in high implementation costs. On the other hand, in practical implementations, the switching chips or network chips are mounted on a physical board (e.g., a network board). These switching chips or network chips are connected to connectors on the physical board via PCB traces, and then connected to the compute nodes via connectors. To implement these PCB traces, the physical board needs to be made of special PCB materials (e.g., polytetrafluoroethylene), which is costly.

[0061] Based on the above description, embodiments of this application provide a service processing component and a service processing device. These can enable interconnection between a large number of computing nodes in a computing node cluster, meeting the expansion requirements of the computing node cluster. Furthermore, they can save implementation costs. The following is an exemplary description with reference to the accompanying drawings.

[0062] For example, Figure 6 illustrates a schematic diagram of the structure of a service processing component provided in an embodiment of this application. As can be seen, the service processing component may include m1 processing boards (represented as processing board 1, processing board 2, ..., processing board m1) and m2 interconnect boards (represented as interconnect board 1, interconnect board 2, ..., interconnect board m2). Here, m1 is an integer greater than 1, and m2 is an integer greater than 0. Each processing board includes multiple computing nodes and m2 connectors. Each interconnect board may include m1 connectors.

[0063] For example, the aforementioned computing node can be a circuit with data processing capabilities. In one implementation, the computing node can be a circuit with instruction read and execute capabilities, such as a central processing unit (CPU), microprocessor, graphics processing unit (GPU) (which can be understood as a type of microprocessor), or digital signal processor (DSP). In another implementation, the computing node can implement certain functions through the logical relationships of hardware circuits. These logical relationships are fixed or reconfigurable. For example, the computing node is a hardware circuit implemented using an application-specific integrated circuit (ASIC) or a programmable logic device (PLD), such as a field-programmable gate array (FPGA). In a reconfigurable hardware circuit, the process of the computing node loading a configuration document and configuring the hardware circuit can be understood as the process of the computing node loading instructions to implement some or all of the functions of the aforementioned units. Furthermore, the computing node can also be a hardware circuit designed for artificial intelligence, which can be understood as an ASIC, such as a neural network processing unit (NPU), tensor processing unit (TPU), deep learning processing unit (DPU), etc. Alternatively, the processor 1801 can be a combination of at least two of these processor forms, etc. It is understood that the description of the computing node herein is merely illustrative and does not constitute a limitation on the embodiments of this application.

[0064] For example, in Figure 6, the m2 connectors on processing board i can be represented by numbers i-1, i-2, ..., i-m2, where i takes values ​​from 1 to m1. The specific numbering positions can be seen in Figure 6. For example, the m2 connectors on processing board 1 can be represented by numbers 1-1, 1-2, ..., 1-m2, and the same applies to other processing boards. Similarly, the m1 connectors on interconnect board j can be represented by numbers 1-j, 2-j, ..., m1-j, where j takes values ​​from 1 to m2. The specific numbering positions can be seen in Figure 6. For example, the m1 connectors on interconnect board 1 can be represented by numbers 1-1, 2-1, ..., m1-1, and the same applies to other interconnect boards.

[0065] For example, multiple computing nodes in each processing board can be connected according to the above-described 2Dmesh, 2Dtours, or fullmesh topologies. Alternatively, the multiple computing nodes can be connected according to any other arbitrary topology. This application embodiment does not impose any limitations on this. The connection relationship of the multiple computing nodes is not specifically shown in Figure 6. For example, the topologies of multiple computing nodes in different processing boards can be the same or different, and this application embodiment does not impose any limitations on this.

[0066] For example, multiple computing nodes in each processing board can be partially or fully connected to any one of the connectors in the processing board. For instance, consider processing board 1. Figure 6 illustrates an example where multiple computing nodes of processing board 1 are all connected to connector 1-1 of processing board 1. In another implementation, some of the multiple computing nodes of processing board 1 can be connected to connector 1-1 of processing board 1. Alternatively, in one possible implementation, the multiple computing nodes in processing board 1 can be divided into m² groups, each group including at least one computing node. The computing node of the kth group in the m² groups is connected to the kth connector in the m² connectors of processing board 1, i.e., there is a one-to-one correspondence between the m² groups and the m² connectors. The value of k is from 1 to m². It is understood that the connection methods listed herein are merely examples and do not constitute a limitation on the embodiments of this application.

[0067] The connectors in the aforementioned processing board are used to connect with the connectors in the interconnect boards. For example, in Figure 6 above, the connectors in the processing board can connect with connectors in the interconnect boards that have the same numbering. For instance, taking processing board 1 as an example, the connectors in processing board 1 are numbered 1-1, 1-2, ..., 1-m2. Then, connector 1-1 in processing board 1 can connect with connector 1-1 in interconnect board 1; connector 1-2 in processing board 1 can connect with connector 1-2 in interconnect board 2; and connector 1-m2 in processing board 1 can connect with connector 1-m2 in interconnect board m2. That is, connector 1-j in processing board 1 can connect with connector 1-j in interconnect board j. Similarly, connector ij in processing board i can connect with connector ij in interconnect board j. It can be seen that the m2 connectors on the processing board are respectively used to connect with the aforementioned m2 interconnect boards.

[0068] For example, each of the m1 processing boards can be orthogonally connected to the m2 interconnect boards. That is, each processing board is perpendicularly connected to each interconnect board. In a specific implementation, to achieve the orthogonal connection between the processing board and the interconnect board, the connectors in the processing board and the corresponding connectors in the interconnect board form an orthogonal connector. For example, taking the processing board 1 as an example: Connector 1-1 in processing board 1 and connector 1-1 in interconnect board 1 form an orthogonal connector; the connection of these two connectors makes processing board 1 and interconnect board 1 orthogonal. Connector 1-2 in processing board 1 and connector 1-2 in interconnect board 2 form an orthogonal connector; the connection of these two connectors makes processing board 1 and interconnect board 2 orthogonal. Connector 1-m2 in processing board 1 and connector 1-m2 in interconnect board m2 form an orthogonal connector; the connection of these two connectors makes processing board 1 and interconnect board m2 orthogonal. That is, connector 1-j in processing board 1 and connector 1-j in interconnect board j form an orthogonal connector; the connection of these two connectors makes processing board 1 and interconnect board j orthogonal. Similarly, connector ij in processing board i and connector ij in interconnect board j form an orthogonal connector; the connection of these two connectors makes processing board i and interconnect board j orthogonally connected.

[0069] For example, the m1 connectors in the same interconnect board can be connected according to a preset connection rule. For example, any two connectors in the m1 connectors of the interconnect board can be connected. Or, for example, any two adjacent connectors in the m1 connectors of the interconnect board can be connected. Alternatively, the m1 connectors in the interconnect board can be connected using any other connection rule, which is not limited in this embodiment. For example, Figure 6 above illustrates the example of any two connectors in the m1 connectors of the interconnect board being connected. For example, the connection rules for the m1 connectors in different interconnect boards can be the same or different, which is not limited in this embodiment.

[0070] In one possible implementation, the connection between the connectors in the interconnect board is a direct connection, meaning there are no other adapters between the two connected connectors. Exemplarily, the connectors in the interconnect board can be connected via cables or printed circuit board (PCB) traces. For example, Figure 6 illustrates a cable connection between connectors in the interconnect board. Exemplarily, one or more cables or PCB traces can be connected between two connectors in the interconnect board; the specific number of cables or PCB traces connected depends on the actual application, and this application does not impose any limitations on this.

[0071] The connection method between connectors in the aforementioned interconnect board breaks through the limitations of existing solutions that connect computing nodes via network chips or switching chips. It enables interconnection between more computing nodes, meeting the expansion needs of computing node clusters and saving on network chip costs. Furthermore, compared to PCB trace connections, the cable connection method eliminates the need for special PCB materials, further reducing manufacturing costs. Cable connections also improve signal bandwidth and reduce insertion loss. This allows for high-speed interconnection of high-performance computing node clusters (e.g., clusters with a large number of computing nodes). It makes the contextual business interactions between computing nodes appear to run on a single computing node, meaning the cluster can be viewed as a high-performance supernode, significantly improving business processing efficiency.

[0072] In one possible implementation, if the connectors in the interconnect board are connected by cables, then the cables can be pre-installed in the connectors on the interconnect board. For ease of understanding, please refer to Figure 7. Figure 7 shows a possible structural diagram of the connector in the aforementioned interconnect board. It can be seen that the connector includes multiple fixing pins, multiple connecting ends, and multiple cables. Exemplarily, the multiple fixing pins can be used to fix the connector to the interconnect board. The multiple connecting ends are used to connect with the connectors on the processing board, for example, for plug-in connections. The multiple cables can be crimped onto the connector, for example. The multiple cables enable connection between the connectors in the interconnect board. Exemplarily, the number of fixing pins, connecting ends, and cables in the connector can be set according to actual applications, and this application embodiment does not limit this. It is understood that the connector shown in Figure 7 is only an example and does not constitute a limitation on the embodiments of this application.

[0073] In one possible implementation, if the connectors in the interconnect board are connected by cables, then the cables can be bundled together on the interconnect board. For clarity, refer to Figure 8. Figure 8 illustrates an interconnect board containing eight connectors. In Figure 8, these eight connectors are connected by cables according to a preset connection rule. As can be seen, the number of cables is relatively large, thus requiring bundling and securing. Therefore, these cables can be bundled together on the interconnect board.

[0074] In one possible implementation, through the connections between multiple computing nodes in each of the m1 processing boards, the connections between these multiple computing nodes and m2 connectors in their respective processing boards, the connections between the connectors in the m1 processing boards and the connectors in the m2 interconnect boards, and the connections between the m1 connectors in each of the m2 interconnect boards, the computing nodes in the m1 processing boards can form computing node clusters with topologies such as 2Dmesh, 2Dtours, 3Dmesh, 3Dtours, or fullmesh. Alternatively, the computing nodes in the m1 processing boards can form computing node clusters with any other arbitrary topology. This application does not impose any limitations on this.

[0075] In one possible implementation, the structure of the connected m1 processing boards and m2 interconnecting boards can be exemplified as shown in Figure 9. It can be seen that the m1 processing boards can be placed parallel to each other, and the m2 interconnecting boards can also be placed parallel to each other. The orientation of the m1 processing boards is perpendicular to the orientation of the m2 interconnecting boards. That is, the m1 processing boards and the m2 interconnecting boards are perpendicularly connected.

[0076] As shown in Figures 6 and 9 above, all m1 processing boards are located on the same side of the m2 interconnecting boards. In another possible implementation, the processing boards in the service processing component can be divided into two processing board groups, and the interconnecting board can be located between the two processing board groups. For ease of understanding, please refer to Figure 10, which shows another structural schematic diagram of the service processing component provided in the embodiments of this application.

[0077] As shown in Figure 10, the service processing component may include a first processing board group, a second processing board group, and w interconnect boards (denoted as interconnect board 1, interconnect board 2, ..., interconnect board w). The first processing board group may include p processing boards, and the second processing board group may include q processing boards. The values ​​of p, q, and w can be integers greater than 1. For a detailed description of the processing boards shown in Figure 10, as well as the connection relationships between the computing nodes and connectors within the processing boards, please refer to the description in Figure 6 above; it will not be repeated here.

[0078] The interconnect board shown in Figure 10 differs from the interconnect board shown in Figure 6 in that, in the service processing component shown in Figure 6, all m1 processing boards are located on the same side of the m2 interconnect boards. However, in the service processing component shown in Figure 10, the aforementioned w interconnect boards are positioned between the first processing board group and the second processing board group. Furthermore, the connectors in the same interconnect board shown in Figure 6 are uniformly located on the same side of the interconnect board's edge. In contrast, the connectors in the same interconnect board shown in Figure 10 are divided into two connector groups, referred to as the first connector group and the second connector group. The first connector group and the second connector group are respectively located on two opposite edges of the interconnect board. The first connector group may include p connectors for connecting to the connectors in the first processing board group, and the second connector group may include q connectors for connecting to the connectors in the second processing board group. For ease of understanding, please refer to the interconnect board 1 shown in Figure 10 as an example. Taking interconnect board 1 as an example, the first connector group in interconnect board 1 includes p connectors numbered 1-1, 2-2, ..., p-1 located on the same edge (referred to as the first edge) of interconnect board 1. The first connector group in interconnect board 1 includes q connectors numbered 1-1, 2-2, ..., q-1 located on another edge of interconnect board 1 (referred to as the second edge). The connectors in this first connector group are used to connect with connectors of the same number in the first processing board group, and the connectors in this second connector group are used to connect with connectors of the same number in the second processing board group. Examples of connections for connectors of the same number can be exemplified in the description related to Figure 6 above, and will not be repeated here.

[0079] For example, the p connectors in the first connector group of the interconnect board can be connected according to a preset connection rule. Similarly, the q connectors in the second connector group of the interconnect board can be connected according to a preset connection rule. Furthermore, these connectors can be connected via cables or PCB traces. For details, please refer to the description in Figure 6 above; it will not be repeated here.

[0080] The service processing component shown in Figure 10 divides the connectors on the interconnect board into two groups, which are respectively located on the two edges of the interconnect board, making full use of the interconnect board area. This also significantly reduces the number of cables on the same edge, making it easier to distinguish the correspondence between cables and connectors, thereby improving connection efficiency and reducing the probability of connection errors during the connection process.

[0081] In one possible implementation, the structure of the connected service processing components shown in Figure 10 can be exemplarily illustrated in Figure 11. It can be seen that the p processing boards in the first processing board group can be placed parallel to each other, the q processing boards in the first processing board group can also be placed parallel to each other, and the w interconnecting boards can also be placed parallel to each other. The direction in which the processing boards are placed is perpendicular to the direction in which the interconnecting boards are placed. The w interconnecting boards are positioned between the p processing boards and the q processing boards, as shown in Figure 11.

[0082] In one possible implementation, if the connectors in the interconnect board are connected by cables, the large number of cables leads to low efficiency and a high risk of connection errors. Furthermore, improper cable placement can cause difficulties in subsequent maintenance. To address this issue, in this embodiment, the connectors in the interconnect board can be divided into two parts and disposed on two separate surfaces of the interconnect board. For clarity, please refer to Figures 12 and 13.

[0083] First, refer to Figure 12, which is a variation of the interconnect board of the service processing component shown in Figure 6. Figure 12 shows one of the m2 interconnect boards in the service processing component shown in Figure 6 as an example. As shown in Figures 12(a) and (b), schematic diagrams of the connector arrangement on the first and second surfaces of the interconnect board are shown respectively. The first and second surfaces of the interconnect board are two back-to-back surfaces. In addition, as shown in Figures 12(a) and (b), the interconnect board also includes two edges, referred to as the first edge and the second edge, respectively. Exemplarily, in a specific implementation, the m1 connectors in the interconnect board shown in Figure 6 can be divided into two parts, and the number of connectors in the two parts can be equal or unequal. Then, one part of the connectors is placed on the first surface of the interconnect board, and the other part of the connectors is placed on the second surface of the interconnect board. For example, referring to Figures 12(a) and (b), taking the case where the number of connectors in the two parts is equal, i.e., m1 / 2, as an example. As shown in Figure 12(a), m1 / 2 connectors can be arranged along the first edge of the interconnect board and on the first board surface. As shown in Figure 12(b), m1 / 2 connectors can be arranged along the first edge of the interconnect board and on the second board surface. Combining Figures 12(a) and (b), the connectors on the first panel can be staggered with the connectors on the second panel to facilitate connection with the connectors on the corresponding processing board. The connectors in the first panel shown in Figure 12(a) and the connectors in the second panel shown in Figure 12(b) can be connected via cables according to a preset connection rule. For details, please refer to the relevant description in Figure 6 above, which will not be repeated here.

[0084] Referring again to Figure 13, Figure 13 is derived from the interconnect board of the service processing component shown in Figure 10. Figure 13 illustrates one of the w interconnect boards of the service processing component shown in Figure 10. As shown in Figures 13(a) and (b), schematic diagrams of the connector arrangement on the first and second surfaces of the interconnect board are shown, respectively. The first and second surfaces of the interconnect board are two back-to-back surfaces. In addition, as shown in Figures 13(a) and (b), the interconnect board also includes two edges, referred to as the first edge and the second edge, respectively. Exemplarily, in a specific implementation, the first connectors in the interconnect board shown in Figure 10 can be grouped and placed on the first surface of the interconnect board, and the second connectors in the interconnect board shown in Figure 10 can be grouped and placed on the second surface of the interconnect board. For example, as seen in Figure 13(a), p connectors of the first connector group can be placed on the first edge and the first surface of the interconnect board. As seen in Figure 13(b), q connectors of the second connector group can be placed on the second edge and the second surface of the interconnect board. For example, the connectors on the first panel may or may not be staggered with the connectors on the second panel. The connectors in the first panel shown in Figure 13(a) and the connectors in the second panel shown in Figure 13(b) can be connected by cables according to a preset connection rule. For details, please refer to the description related to Figure 6 above, which will not be repeated here.

[0085] As can be seen, this design allows some cables to be bundled and placed on the first surface of the interconnect board, while other cables can be bundled and placed on the second surface. This significantly reduces the number of cables on the same surface, making it easier to distinguish the correspondence between cables and connectors. This improves connection efficiency and reduces the probability of connection errors during the connection process, and also alleviates the difficulties in subsequent maintenance caused by excessive and improperly placed cables.

[0086] In one possible implementation, the aforementioned service processing component can be placed within a chassis, which can then secure and protect the component. Exemplarily, the processing board of the service processing component can be inserted horizontally into the chassis, and the interconnect board can be inserted vertically into the chassis. Alternatively, conversely, the processing board of the service processing component can be inserted vertically into the chassis, and the interconnect board can be inserted horizontally into the chassis. This application does not impose limitations on this aspect.

[0087] In one possible implementation, the service processing component provided in this application embodiment may further include a backplane. This backplane can be used to implement the connection between the processing boards and interconnect boards. For ease of understanding, please refer to Figures 14 and 15. First, refer to the service processing component shown in Figure 14, which is a variation of the service processing component shown in Figure 6. In addition to including the m1 processing boards and m2 interconnect boards shown in Figure 6, this service processing component also includes a backplane. Connectors are also provided on the backplane. The m1 processing boards can first be connected to the backplane, and then the backplane can be connected to the m2 interconnect boards, thereby realizing the connection between the m1 processing boards and the m2 interconnect boards. For example, the connectors in the m1 processing boards can be connected to the connectors in the backplane, and the connectors in the m2 interconnect boards can also be connected to the connectors in the backplane. The connectors in the backplane that connect to the processing boards and the connectors that connect to the interconnect boards are correspondingly connected. Alternatively, one end of the connector in the backplane is used to connect to the connector of the processing board, and the other end is used to connect to the connector of the interconnect board. For ease of understanding, the following description is based on Figures 14 and 15.

[0088] As shown in Figure 15, the backplane includes multiple connectors on both the side facing the processing board (see Figure 15(a)) and the side facing the interconnect board (see Figure 15(b)). Exemplarily, both the side facing the processing board and the side facing the interconnect board can include m1*m2 connectors, with the specific connector numbers shown in Figure 15. In a specific implementation, connector ij in processing board i can be connected to connector ij on the side of the backplane facing the processing board. For example, taking processing board 1 as an example, connector 1-1 in processing board 1 can be connected to connector 1-1 on the side of the backplane facing the processing board; connector 1-2 in processing board 1 can be connected to connector 1-2 on the side of the backplane facing the processing board; and connector 1-m2 in processing board 1 can be connected to connector 1-m2 on the side of the backplane facing the processing board. The same applies to other processing boards, and will not be described further. For example, the connector ij in the processing board i and the connector ij on the side of the back plate facing the processing board can form an orthogonal connector, so that the processing board i can be orthogonally connected to the back plate.

[0089] Furthermore, in a specific implementation, connector ij in interconnect board j can be connected to connector ij on the backplane facing the interconnect board. For example, taking i=1, connector 1-1 in interconnect board 1 can be connected to connector 1-1 on the backplane facing the interconnect board. Connector 1-2 in interconnect board 2 can be connected to connector 1-2 on the backplane facing the interconnect board. Connector 1-m2 in interconnect board m2 can be connected to connector 1-m2 on the backplane facing the interconnect board. Other values ​​of i are similar and will not be elaborated further. Exemplarily, connector ij in interconnect board j and connector ij on the backplane facing the interconnect board can form an orthogonal connector, allowing interconnect board j to be orthogonally connected to the backplane.

[0090] For example, connector ij on the side of the backplane facing the processing board is connected to connector ij on the side of the backplane facing the interconnect board. Alternatively, connector ij on the side of the backplane facing the processing board and connector ij on the side of the backplane facing the interconnect board belong to two sides of the same connector, with one side used to connect to the processing board and the other side used to connect to the interconnect board.

[0091] In one possible implementation, if the connectors in the interconnect board are connected by a cable, then the cable can be bundled onto the backplate.

[0092] In another possible implementation, the service processing component shown in Figure 14 can be modified to obtain a service processing component with a different structure. For example, see Figure 16. Compared to Figure 14, the service processing component shown in Figure 16 can remove the m2 interconnect boards from the service processing component shown in Figure 14, and connect them to the connectors on the opposite side of the backplane facing the processing board via cables or PCB traces according to preset connection rules to achieve interconnection between the computing nodes in the m1 processing boards. Figure 16 shows a cable connection as an example; these cables can be bundled on the backplane. The opposite side facing the processing board is the side of the backplane facing the interconnect board shown in Figure 15. For example, the backplane in the service processing component shown in Figure 16 can also be called an interconnect board. It is understood that the names of the various physical boards in the service processing component are only examples; different names are mainly used to distinguish physical boards with different functions and do not constitute a limitation on the embodiments of this application.

[0093] The business processing component shown in Figure 16 above can save on the number of interconnect boards and further reduce costs because it can realize the topological connection between computing nodes in multiple processing boards on a single backplane (or interconnect board).

[0094] For example, the service processing component shown in Figures 14 and 16 above can also be placed inside the chassis to fix and protect the service processing component. This application embodiment will not elaborate further on this.

[0095] In one possible implementation, one or more interconnect boards in the aforementioned service processing components may further include a network chip and an external interface. This network chip and external interface can be used to connect to another service processing component. For illustrative purposes, please refer to Figures 17 to 19.

[0096] Figure 17 illustrates an example of the service processing component shown in Figure 6 above. Figure 18 illustrates an example of the service processing component shown in Figure 10 above. Figure 19 illustrates an example of the service processing component shown in Figure 14 above. In the service processing component 1710 shown in Figure 17, the service processing component 1810 shown in Figure 18, or the service processing component 1910 shown in Figure 19, the interconnect board (shown as interconnect board 1) may further include one or more mesh panels and one or more external interfaces. Figures 17 to 19 illustrate an example where interconnect board 1 includes two mesh panels and two external interfaces. In a specific implementation, the mesh panels on the interconnect board may be connected to some or all of the connectors in the interconnect board. Figures 17 to 19 illustrate an example where the mesh panels are connected to all the connectors in interconnect board 1. In addition, the mesh panels are also used to connect to the external interfaces in the interconnect board. For example, one mesh panel in the interconnect board may be connected to one or more external interfaces in the interconnect board. Figures 17 to 19 illustrate an example where one mesh panel in interconnect board 1 is connected to one external interface in interconnect board 1. For example, the mesh in the interconnect board can be connected to the connectors and external interfaces in the interconnect board via PCB traces.

[0097] The external interface in the aforementioned interconnect board can be connected to the external interface of the interconnect board in another service processing component. For example, referring to Figure 17, the external interface of interconnect board 1 in service processing component 1710 can be connected to the external interface in service processing component 1720. Exemplarily, the specific structure of service processing component 1720 can be referenced from the structure of service processing component 1710, and will not be repeated here. The external interface in service processing component 1720 is the external interface on the interconnect board in service processing component 1720. Similarly, the external interface on the interconnect board in service processing component 1720 is also connected to the mesh on the interconnect board; the mesh is also connected to the connector on the interconnect board; the connector on the interconnect board is also connected to the connector in the processing board of service processing component 1720; and the connector in the processing board is also connected to the computing node in the processing board. The specific implementation of these connections can be referred to the foregoing description, and will not be repeated here. Similarly, in Figures 18 and 19, the external interface of the interconnect board 1 in the service processing component 1810 in Figure 18 can be connected to the external interface in the service processing component 1820, and the external interface of the interconnect board 1 in the service processing component 1910 in Figure 19 can be connected to the external interface in the service processing component 1920. For a detailed description, please refer to the relevant introduction in Figure 17, which will not be repeated here.

[0098] For example, the external interfaces of the two service processing components described above can be connected via cables. For instance, the external interface on the interconnect board 1 of service processing component 1710 shown in Figure 17 can be connected to the external interface on service processing component 1720 via cables. Figures 18 and 19 are similar and will not be described further.

[0099] Based on the above introduction, by connecting to another business processing component through network chips and external interfaces, the number of computing node clusters can be further expanded to build a more powerful computing cluster.

[0100] In another possible implementation, in the business processing component 1910 shown in Figure 19 above, the cables used to connect the connectors in the interconnect board can be bundled on the backplane. This frees up a larger area on the interconnect board to accommodate the mesh and the PCB traces between the mesh and the connectors, reducing the engineering complexity of the implementation.

[0101] In another possible implementation, the structure of the service processing component 1910 shown in Figure 19 can be modified to obtain another service processing component structure, as exemplarily shown in Figure 20. In Figure 20, the connectors between different processing boards are directly connected by cables, and the connection can be implemented according to a preset connection rule, which is not limited in this embodiment. These cables used to connect different processing boards can be bundled on a backplate. The backplate is mainly used to bundle the cables and no longer provides connectors to connect to the processing boards and interconnect boards. In addition, the connectors in the processing boards can also be connected to the connectors in the interconnect boards via cables. Exemplarily, the connectors in the multiple processing boards and the connectors in the multiple interconnect boards can be connected according to a preset rule. For example, the connectors in the processing boards can be connected to the connectors with the same number in the interconnect boards, that is, the connector ij in processing board i can be connected to the connector ij in interconnect board j. For details, please refer to the description related to Figure 6 above, which will not be repeated here. Exemplarily, the cables connecting the processing boards and interconnect boards can also be bundled on a backplate.

[0102] Furthermore, as shown in Figure 20 above, one or more interconnect boards in the aforementioned service processing component 2010 may also include a network chip and an external interface. This network chip and external interface can be used to connect to another service processing component, such as the service processing component 2020 in Figure 20. Exemplarily, the specific structure of the service processing component 2020 can be referenced from the structure of the service processing component 2010, and will not be repeated here. The implementation method of connecting to another service processing component via a network chip and external interface can be exemplarily referred to in the relevant description shown in Figure 17 above, and will not be repeated here. This implementation method can save on connectors on the backplane, thus saving material costs. Furthermore, bundling the cables to the backplane allows for a larger free area on the interconnect board to accommodate the mesh and the PCB traces between the mesh and the connectors, reducing the engineering difficulty of implementation.

[0103] In one possible implementation, the structure of the connected service processing components 2010 can be exemplarily shown in Figure 21. It can be seen that the m1 processing boards can be placed parallel to each other, and the m2 interconnecting boards can also be placed parallel to each other. The orientation of the m1 processing boards is perpendicular to the orientation of the m2 interconnecting boards. That is, a backplate with bundled cables is placed between the m1 processing boards and the m2 interconnecting boards. The backplate, processing boards, and interconnecting boards are all placed perpendicularly. For example, if the cables used to connect the connectors in the interconnecting boards in the service processing component 1910 shown in Figure 19 are bundled on the backplate, then the structure of the connected service processing component 1910 can also be exemplarily shown in Figure 21.

[0104] For example, in a specific implementation, two or more business processing components can be connected in the manner described above to form a high-performance computing node cluster required for practical applications. For example, the topology of this high-performance computing node cluster can be, for example, the aforementioned 2Dmesh, 2Dtours, 3Dmesh, 3Dtours, or fullmesh topologies. Alternatively, it can be any other topology; this application embodiment does not limit this.

[0105] In one possible implementation, the high-performance computing node cluster formed by connecting nodes in the above manner can be used to process business data serially, in parallel, or in a combination of parallel and serial processing (i.e., a serial-parallel approach). During the processing of business data, communication between computing nodes is necessary to maintain the contextual relationships within the data.

[0106] For example, in a high-performance computing node cluster formed by the connection method described above, data from computing nodes in different processing boards is transmitted through connectors in the processing boards, connectors in the interconnect boards, and cables or PCB traces connecting the connectors in the interconnect boards. For example, see Figure 22.

[0107] Figure 22 illustrates an example using two processing boards (referred to as the first processing board and the second processing board) and an interconnect board in a business processing component. As shown in Figure 22, data from the computing nodes in the first processing board can be transmitted to the computing nodes in the second processing board via the connectors of the first processing board, the connectors of the interconnect board, the cables (or PCB traces) connecting the interconnect board connectors, and the connectors in the second processing board. For example, if a computing node in the first processing board processes certain data, and the resulting data needs to be sent to a computing node in the second processing board for further processing, then the processing result obtained by the computing node in the first processing board can be sent to the computing node in the second processing board via the path described above.

[0108] For example, see Figure 23. Figure 23 illustrates this using three processing boards (referred to as the first processing board, the second processing board, and the third processing board) and one interconnect board in a business processing component. For instance, if a computing node (referred to as the first computing node) in the first processing board processes first data to obtain a processing result (referred to as the first processing result), and a computing node (referred to as the second computing node) in the second processing board processes second data to obtain a processing result (referred to as the second processing result), and the first and second processing results need to be sent to a computing node (referred to as the third computing node) in the third processing board for further processing, then, referring to Figure 23, the first computing node can send the aforementioned first processing result to the third computing node of the third processing board via connector ① of the first processing board, connector ② of the interconnect board connected to connector ①, connector ⑥ of the interconnect board, the cable or PCB trace connecting connector ② and connector ⑥, and connector ⑤ of the third processing board. Similarly, the second computing node can send the aforementioned second processing result to the third computing node on the third processing board via connector ③ of the second processing board, connector ④ of the interconnect board connected to connector ③, connector ⑥ of the interconnect board, the cable or PCB trace connecting connector ④ and connector ⑥, and connector ⑤ of the third processing board. After receiving the first and second processing results, the third computing node continues to perform the next step of processing, which will not be elaborated here.

[0109] It is understood that Figures 22 and 23 above are merely examples and do not constitute a limitation on the embodiments of this application.

[0110] Alternatively, if the connectors on different processing boards are directly connected by cables, data from the computing nodes on different processing boards can be transmitted through the connectors on the processing boards and the cables connecting those connectors. Refer to the descriptions in Figures 22 and 23 above for examples; they will not be repeated here.

[0111] Alternatively, for a computing node cluster consisting of two or more business processing components, data transmission between computing nodes in different business processing components can be achieved through the aforementioned mesh and external interfaces.

[0112] In summary, in this embodiment, computing nodes can be mounted on multiple processing boards and configured with interconnect boards. The processing boards and interconnect boards are connected via connectors. After a processing board is connected to an interconnect board, the connectors on the interconnect boards are directly connected to enable connectivity between computing nodes on different processing boards, facilitating the formation of a computing node cluster. This solution overcomes the limitation of connecting computing nodes via network chips in existing solutions through direct connection, enabling interconnection between more computing nodes and meeting the expansion needs of computing node clusters. Furthermore, it saves on the cost of network chips.

[0113] It should be understood that in the various embodiments of this application, the sequence number of each process does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0114] It should also be understood that the term “comprising” (also referred to as “includes”, “including”, “comprises” and / or “comprising”) as used in this specification specifies the presence of the stated features, integers, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0115] It should also be understood that the phrases "an embodiment," "an embodiment," and "a possible implementation" used throughout the specification mean that a specific feature, structure, or characteristic related to an embodiment or implementation is included in at least one embodiment of this application. Therefore, the phrases "in an embodiment," "an embodiment," or "a possible implementation" appearing throughout the specification do not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments.

[0116] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A business processing component, characterized in that, The service processing component includes a first processing board, a second processing board, and a first interconnection board; The first processing board includes n1 computing nodes and a first connector, wherein the n1 computing nodes are connected to the first connector, and n1 is an integer greater than 1; The second processing board includes n2 computing nodes and a second connector, wherein the n2 computing nodes are connected to the second connector, and n2 is an integer greater than 1; The first interconnect board includes a third connector and a fourth connector; The first connector is connected to the third connector, the second connector is connected to the fourth connector, and the third connector and the fourth connector are connected; The n1 computing nodes and the n2 computing nodes are used to process business data.

2. The business processing component according to claim 1, characterized in that, The third connector and the fourth connector are connected by cables or printed circuit board (PCB) traces.

3. The business processing component according to claim 1 or 2, characterized in that, The first connector and the third connector form an orthogonal connector, and the first processing board and the interconnect board are orthogonally connected; The second connector and the fourth connector form an orthogonal connector, and the second processing board and the interconnect board are orthogonally connected.

4. The business processing component according to any one of claims 1-3, characterized in that, Any two nodes in the n1 computing nodes are interconnected, and any two nodes in the n2 computing nodes are interconnected.

5. The business processing component according to any one of claims 1-4, characterized in that, The business processing component also includes a third processing board, which includes n3 computing nodes and a fifth connector. The n3 computing nodes are connected to the fifth connector, where n3 is an integer greater than 1. The first interconnect board also includes a sixth connector; The fifth connector is connected to the sixth connector, and the third connector and / or the fourth connector is connected to the sixth connector.

6. The business processing component according to claim 5, characterized in that, The third connector is connected to the sixth connector via a cable or PCB trace, and / or the fourth connector is connected to the sixth connector via a cable or PCB trace.

7. The business processing component according to any one of claims 1-6, characterized in that, The service processing component also includes a second interconnect board; The first processing board also includes a seventh connector, to which the n1 computing nodes are connected; The second processing board includes an eighth connector, and the n2 computing nodes are connected to the eighth connector; The second interconnect board includes a ninth connector and a tenth connector; The seventh connector is connected to the ninth connector, the eighth connector is connected to the tenth connector, and the ninth connector is connected to the tenth connector.

8. The business processing component according to any one of claims 1-7, characterized in that, The first interconnect board also includes a network chip and an external interface; The third connector and the fourth connector are also connected to the network chip, which is also connected to the external interface; the external interface is used to connect to another of the service processing components.

9. The business processing component according to any one of claims 1-8, characterized in that, The computing node is a central processing unit (CPU), graphics processing unit (GPU), neural network processing unit (NPU), tensor processing unit (TPU), or deep learning processing unit (DPU).

10. The business processing component according to any one of claims 1-9, characterized in that, The first connector and the third connector can be connected via a backplate.

11. The business processing component according to claim 10, characterized in that, The third connector and the fourth connector are connected by a first cable, which is bundled on the back plate.

12. The business processing component according to any one of claims 1-11, characterized in that, The third connector is located on the first surface of the first interconnect board, and the fourth connector is located on the second surface of the first interconnect board, with the first and second surfaces facing each other.

13. The business processing component according to any one of claims 1-12, characterized in that, The n1 computing nodes include a first computing node, and the n2 computing nodes include a second computing node; The first computing node is used to process the first data to obtain a first processing result, and send the first processing result to the second computing node; The first processing result is transmitted to the second computing node through the first connector, the third connector, the fourth connector, and the second connector; The second computing node is used to process the first processing result.

14. The business processing component according to claim 5 or 6, characterized in that, The n1 computing nodes include a third computing node, the n2 computing nodes include a fourth computing node, and the n3 computing nodes include a fifth computing node; The third computing node is used to process the second data to obtain a second processing result, and send the second processing result to the fifth computing node; The second processing result is transmitted to the fifth computing node through the first connector, the third connector, the sixth connector, and the fifth connector; The fourth computing node is used to process the third data to obtain a third processing result, and send the third processing result to the fifth computing node; The third processing result is transmitted to the fifth computing node through the second connector, the fourth connector, the sixth connector, and the fifth connector; The fifth computing node is used to process the second processing result and the third processing result.

15. A business processing component, characterized in that, The service processing component includes a first processing board, a second processing board, and a first interconnection board; The first processing board includes n1 computing nodes and a first connector, wherein the n1 computing nodes are connected to the first connector, and n1 is an integer greater than 1; The second processing board includes n2 computing nodes and a second connector, wherein the n2 computing nodes are connected to the second connector, and n2 is an integer greater than 1; The first interconnect board includes a third connector, a fourth connector, and a network chip; The first connector and the second connector are connected by a cable, the first connector is connected to the third connector by a cable, the second connector is connected to the fourth connector by a cable, and the third connector and the fourth connector are connected to the network chip; the network chip is used to connect to another of the service processing components. The n1 computing nodes and the n2 computing nodes are used to process business data.

16. The business processing component according to claim 15, characterized in that, The service processing component also includes a backplane, on which the cables are bundled.

17. A business processing device, characterized in that, The service processing device includes a chassis and a service processing component, wherein the service processing component is disposed in the chassis; the service processing component is the service processing component according to any one of claims 1-16.

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