Data prefetching method and apparatus, electronic device and readable storage medium

Abstract

Embodiments of the present application relate to the technical field of computers, and provide a data prefetching method and apparatus, an electronic device, and a readable storage medium. The method comprises: determining a stride memory access instruction in a program to be processed, using an index value of the stride memory access instruction as a first index value, and updating, in a first record table, a record entry corresponding to a destination register of the determined stride memory access instruction from an initial value to the first index value; for any other memory access instruction in said program, when a target record entry of the other memory access instruction is not the initial value, determining the other memory access instruction as an instruction to be prefetched, and on the basis of the target record entry of the instruction to be prefetched, determining a base instruction corresponding to the instruction to be prefetched; and on the basis of the base instruction and a base address of the instruction to be prefetched, determining a prefetch address of the instruction to be prefetched, and prefetching data to be prefetched corresponding to the prefetch address into a cache, so as to implement data prefetching for indirect array-type memory access instructions.

Description

Data prefetching methods, apparatus, electronic devices and readable storage media

[0001] Cross-references to related applications

[0002] This application claims priority to Chinese Patent Application No. 202410703408.9, filed on May 31, 2024, entitled “Data Prefetching Method, Apparatus, Electronic Device and Readable Storage Medium”, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This application relates to the field of computer technology, and in particular to a data prefetching method, apparatus, electronic device, and readable storage medium. Background Technology

[0004] With the development of computer technology, processor computing speed has greatly improved, but the memory access speed of storage systems has only improved relatively little, which has constrained the development of processor performance and created the "memory wall" problem. Currently, hardware prefetchers are commonly used to predict programs and prefetch the predicted data to alleviate the "memory wall" problem.

[0005] When a program performs data computation and processing in fields such as big data or artificial intelligence, there are often indirect array-type memory access instructions in the program. The addressing process of such memory access instructions depends on the actual stored data, and the address changes irregularly. Existing hardware prefetchers have poor prefetching performance for such memory access instructions. Summary of the Invention

[0006] This application provides a data prefetching method, apparatus, electronic device, and readable storage medium, which can solve the problem of how to prefetch data for indirect array-type memory access instructions in related technologies.

[0007] On one hand, embodiments of this application disclose a data prefetching method, the method comprising:

[0008] The step memory access instruction in the program to be processed is identified, and the index value of the step memory access instruction is used as the first index value. The record entry corresponding to the destination register of the identified step memory access instruction is updated from the initial value to the first index value in the first record table. The first record table contains multiple record entries, and different record entries correspond to different registers.

[0009] For any other memory access instruction in the program to be processed, if the target record of the other memory access instruction is not the initial value, the other memory access instruction is determined as a prefetch instruction, and the base instruction corresponding to the prefetch instruction is determined based on the target record of the prefetch instruction; the target record is the record corresponding to the source register of the other memory access instruction in the first record table;

[0010] Based on the base instruction and the base address of the instruction to be prefetched, the prefetch address of the instruction to be prefetched is determined, and the data to be prefetched corresponding to the prefetch address is prefetched into the cache.

[0011] On the other hand, embodiments of this application disclose a data prefetching device, the device comprising:

[0012] The first determining module is used to determine the step memory access instruction in the program to be processed, and use the index value of the step memory access instruction as the first index value. In the first record table, the record entry corresponding to the destination register of the determined step memory access instruction is updated from the initial value to the first index value. The first record table contains multiple record entries, and different record entries correspond to different registers.

[0013] The second determining module is configured to, for any other memory access instruction in the program to be processed, determine the other memory access instruction as a prefetch instruction if the target record of the other memory access instruction is not the initial value, and determine the base instruction corresponding to the prefetch instruction based on the target record of the prefetch instruction; the target record is the record corresponding to the source register of the other memory access instruction in the first record table;

[0014] The prefetch module is used to determine the prefetch address of the instruction to be prefetched based on the base instruction and the base address of the instruction to be prefetched, and prefetch the data to be prefetched corresponding to the prefetch address into the cache.

[0015] In another aspect, embodiments of this application also disclose an electronic device, which includes a processor, a memory, a communication interface, and a communication bus. The processor, the memory, and the communication interface communicate with each other through the communication bus. The memory is used to store executable instructions, which cause the processor to execute the aforementioned data prefetching method.

[0016] This application also discloses a readable storage medium, which, when the instructions in the readable storage medium are executed by the processor of an electronic device, enables the electronic device to perform the aforementioned data prefetching method.

[0017] This application also discloses a computer program product containing instructions that, when run on a computer, cause the computer to perform the aforementioned data prefetching method.

[0018] This application also discloses a chip, which includes a processor and a communication interface. The communication interface is coupled to the processor, and the processor is used to run programs or instructions to implement the aforementioned data prefetching method.

[0019] This application also discloses a data prefetching apparatus / device, which is configured to implement the aforementioned data prefetching method.

[0020] The embodiments of this application have the following advantages:

[0021] This application provides a data prefetching method. By identifying straddle memory access instructions in a program to be processed and using the index value of the straddle memory access instruction as a first index value, the record entry corresponding to the destination register of the identified straddle memory access instruction is updated from its initial value to the first index value in a first record table. The first record table contains multiple record entries, with different record entries corresponding to different registers. For any other memory access instruction in the program to be processed, if the target record entry of the other memory access instruction is not the initial value, the other memory access instruction is identified as a prefetching instruction, and the base instruction corresponding to the prefetching instruction is determined based on the target record entry of the prefetching instruction. The target record entry is the record entry corresponding to the source register of the other memory access instruction in the first record table. Based on the base instruction and the base address of the prefetching instruction, the prefetch address of the prefetching instruction is determined, and the data to be prefetched corresponding to the prefetch address is prefetched into the cache. This application, through the first record table, can identify indirect array memory access instructions in the program to be processed that depend on straddle memory access instructions, and realize data prefetching of indirect array memory access instructions. Meanwhile, based on the dependency relationship between the source register and the destination register, indirect array memory access instructions can be identified, which can ensure the accuracy and coverage of the identification. It can locate the instructions that really need to be prefetched while avoiding issuing invalid prefetches and wasting resources. Attached Figure Description

[0022] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the description of the embodiments of this application will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1 is a flowchart of the steps of an embodiment of a data prefetching method according to this application;

[0024] Figure 2 is a schematic diagram of an anti-interference mechanism of this application;

[0025] Figure 3 is a structural block diagram of a data prefetching embodiment of this application;

[0026] Figure 4 is a structural block diagram of an indirect pattern recognition module of this application;

[0027] Figure 5 is a structural block diagram of an embodiment of a data prefetching device according to this application;

[0028] Figure 6 is a structural block diagram of an electronic device for data prefetching provided in this application example. Detailed Implementation

[0029] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0030] The terms "first," "second," etc., used in the specification and claims of this application are used to distinguish similar objects and not to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first," "second," etc., are generally of the same class and are not limited in number; for example, a first object can be one or more. Furthermore, the term "and / or" in the specification and claims is used to describe the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, and B alone. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. In the embodiments of this application, the term "multiple" refers to two or more, and other quantifiers are similar.

[0031] Method Implementation Examples

[0032] Referring to Figure 1, a flowchart of an embodiment of a data prefetching method according to this application is shown. The method may specifically include the following steps:

[0033] Step 101: Determine the step memory access instruction in the program to be processed, and use the index value of the step memory access instruction as the first index value. In the first record table, update the record entry corresponding to the destination register of the determined step memory access instruction from the initial value to the first index value. The first record table contains multiple record entries, and different record entries correspond to different registers.

[0034] Step 102: For any other memory access instruction in the program to be processed, if the target record of the other memory access instruction is not the initial value, determine the other memory access instruction as a prefetch instruction, and determine the base instruction corresponding to the prefetch instruction based on the target record of the prefetch instruction; the target record is the record corresponding to the source register of the other memory access instruction in the first record table.

[0035] Step 103: Based on the base instruction and the base address of the instruction to be prefetched, determine the prefetch address of the instruction to be prefetched, and prefetch the data to be prefetched corresponding to the prefetch address into the cache.

[0036] It should be noted that the embodiments of this application can be applied to any processor (Central Processing Unit, CPU) for steps 101 to 103 above. Accordingly, the cache in the embodiments of this application refers to the cache of the current processor, which can be the cache closest to the CPU (e.g., L1D Cache).

[0037] The aforementioned program to be processed can be a program decoded and executed by the processor. It can be a program related to matrix calculations and graph search, or it can be a program from other applications in fields such as big data and artificial intelligence. The program to be processed can be obtained according to actual needs, and this application embodiment does not impose any limitations on this. The aforementioned stride memory access instruction refers to a memory access instruction identified by the stride prefetcher. The memory access address of this instruction changes in a stride manner, for example:

[0038] Instruction A: lw a5, 4, a4;

[0039] Here, lw represents a load instruction. Instruction A instructs to add 4 to the value of register a5 and then store it in register a4. If there is an instruction B preceding instruction A that instructs to add a fixed value to the value of register a5 and then store it in a5, then the memory access address of instruction A changes in a step-like manner, with each step being the fixed value indicated by instruction B. In this case, instruction A can be identified as a step-like memory access instruction.

[0040] In this embodiment, step 101 described above can obtain straddle memory access instructions through a straddle prefetcher configured in the processor. The straddle prefetcher can identify memory access instructions contained in the program to be processed, identify each straddle memory access instruction, and record the program counter (PC) of the identified straddle memory access instruction into the straddle instruction table. Thus, in this embodiment, the straddle memory access instructions in the program to be processed can be determined by reading the straddle instruction table.

[0041] Here, the index value refers to the PC value of the instruction, which is equivalent to a unique identifier for each instruction; different instructions have different index values. The first record table can be a pre-constructed storage table, which may contain multiple record entries, each corresponding to a different register. Specifically, in this embodiment, a first record table corresponding to each register of the processor can be pre-created. The register identifiers of different registers can be used as identifiers for each record entry, and different record entries can be set to the same initial value. For example, the initial value can be 0, or it can be 1, and can be set according to actual needs; this embodiment does not impose any restrictions on this.

[0042] Furthermore, after determining the step memory access instruction in the program to be processed, this embodiment of the application can obtain the index value of the step memory access instruction, as well as parameters such as the source register and destination register of the step memory access instruction. At this time, this embodiment of the application can update the record entry corresponding to the destination register of the step memory access instruction from its initial value to the PC value of the step memory access instruction in the first record table. For example, taking the PC value of instruction A as 0x1a310, its destination register is a4, and the record entry of a4 in the first record table can be recorded as headPC[a4] = 0x1a310.

[0043] In this context, "other memory access instructions" refers to memory access instructions that are not straddle memory access instructions. Further, if the other memory access instructions in the program to be processed are indirect memory accesses to straddle memory access instructions, their source registers often depend on the destination register of the straddle memory access instruction. Therefore, this embodiment can traverse the records of the source registers of the other memory access instructions in the program to be processed to determine whether the record corresponding to the source register of the other memory access instruction in the first record table is an initial value. It is understood that if it is an initial value, it indicates that the other memory access instruction is not an indirect memory access dependent on straddle memory access instructions. Correspondingly, if it is not an initial value, it indicates that the other memory access instruction is an indirect memory access dependent on straddle memory access instructions. In this case, the other memory access instruction can be identified as a prefetch instruction, and the base instruction corresponding to the prefetch instruction can be determined based on the record corresponding to the source register of the prefetch instruction in the first record table. That is, the PC value of the base instruction is obtained based on the value of the target record, and thus the base instruction can be obtained.

[0044] Optionally, before step 102 above, the following may also be included:

[0045] Step 1011: For any other type of instruction in the program to be processed, if the source record entry of the other type of instruction is not the initial value, update the record entry corresponding to the destination register of the other type of instruction in the first record table from the initial value to the index value of the other type of instruction. Here, the aforementioned source record entry is the record entry corresponding to the source register of the other type of instruction in the first record table.

[0046] The base instruction mentioned above refers to the instruction that the instruction to be prefetched depends on. If the source record of another type of instruction is not initialized, it indicates that the other type of instruction depends on a straddle memory access instruction, or that there are other types of instructions following the determined straddle memory access instruction. In one case, if there are no other types of instructions following the straddle memory access instruction, the base instruction mentioned above often refers to the straddle memory access instruction that the instruction to be prefetched depends on. The other types of instructions mentioned above refer to instructions whose instruction type is not a memory access type, such as shift type instructions, calculation type instructions, etc.

[0047] In another scenario, if other types of instructions exist after the step memory access instruction, and the entry corresponding to the source register of those other types of instructions in the first record table is not an initial value, this indicates that the value of the destination register of the step memory access instruction has undergone other processing operations. In this embodiment, the entry of the destination register of those other types of instructions in the first record table can be further updated to the PC value of those other types of instructions. Correspondingly, if the target entry of another memory access instruction is not an initial value, and if the instruction type corresponding to the target entry is not a memory access type, the base instruction corresponding to the instruction to be prefetched includes other types of instructions and the step memory access instruction that those other types of instructions depend on. The step memory access instruction that other types of instructions depend on can be obtained from the entry corresponding to the source register of those other types of instructions.

[0048] Furthermore, after obtaining the base instruction and the instruction to be prefetched, the instruction dependency relationship starting with the step memory access instruction can be obtained. It is understood that in the first record table, the records corresponding to registers existing in the instruction dependency relationship are not initial values, while the records corresponding to registers not existing in the instruction dependency relationship are initial values. In this embodiment, the base instruction and the instruction to be prefetched can be determined as an instruction pair with indirect array dependency. The base instruction can be used as the header instruction, and the instruction to be prefetched can be used as the tail instruction. Data prefetching is performed on the tail instruction through this instruction. For example, taking an instruction pair A[B[i]] with indirect array dependency as an example, the instruction accessing B[i] is the header instruction, and the instruction accessing A[B[i]] is the tail instruction.

[0049] Here, the base address refers to the base address of the instruction to be prefetched, which is often fixed. In this embodiment, it can be obtained directly from the instruction parameters of the instruction to be prefetched, or it can be calculated from the historical access address of the instruction to be prefetched. The specific setting can be customized according to actual needs, and this embodiment does not impose any restrictions on this. Furthermore, in this embodiment, the step memory access instruction can be prefetched first. That is, the prefetch data of the step memory access instruction is prefetched according to its step size. Then, the data of other base instructions in the dependency chain, excluding shift type instructions, is prefetched according to the prefetch data of the step memory access instruction. Finally, the prefetch address is determined based on the prefetch data of all base instructions and the base address of the instruction to be prefetched. Specifically, it can be determined using the following formula:

[0050] Prefetch address = base + Value << shift.

[0051] In this context, "base" refers to the base address of the instruction to be prefetched, "Value" refers to the prefetch data of other base instructions besides shift-type instructions, and "shift" refers to the shift offset value of the shift-type instruction included in the base instructions. In this embodiment, the sign of "shift" can be set according to the shift direction of the shift-type instruction; for example, when the shift-type instruction indicates a left shift of two bits, "shift" is recorded as +2, and when it indicates a right shift of one bit, "shift" is recorded as -1. When the base instructions only include straddle memory access instructions, "shift" can be 0, and "Value" refers to the prefetch data of the straddle memory access instruction. When the base instructions also include shift-type instructions, "shift" can be determined based on the instruction parameters of the shift-type instructions.

[0052] Furthermore, in this embodiment, after obtaining the prefetch address of the instruction to be prefetched, the prefetch address can be accessed, and the data corresponding to the prefetch address can be stored in the cache as the data to be prefetched. In this way, when the processor executes the instruction to be prefetched later, it can directly obtain the data to be prefetched from the cache. Since the cache has a fast memory access speed, it can greatly improve the processing efficiency of the instruction.

[0053] The data prefetching method provided in this application embodiment determines straddle memory access instructions in the program to be processed, and uses the index value of the straddle memory access instruction as a first index value. In a first record table, the record entry corresponding to the destination register of the determined straddle memory access instruction is updated from its initial value to the first index value. The first record table contains multiple record entries, with different record entries corresponding to different registers. For any other memory access instruction in the program to be processed, if the target record entry of the other memory access instruction is not the initial value, the other memory access instruction is determined as a prefetch instruction, and the base instruction corresponding to the prefetch instruction is determined based on the target record entry of the prefetch instruction. The target record entry is the record entry corresponding to the source register of the other memory access instruction in the first record table. Based on the base instruction and the base address of the prefetch instruction, the prefetch address of the prefetch instruction is determined, and the prefetch data corresponding to the prefetch address is prefetched into the cache. This application embodiment, through the first record table, can identify indirect array memory access instructions in the program to be processed that depend on straddle memory access instructions, and realize data prefetching of indirect array memory access instructions. Meanwhile, based on the dependency relationship between the source register and the destination register, indirect array memory access instructions can be identified, which can ensure the accuracy and coverage of the identification. It can locate the instructions that really need to be prefetched while avoiding issuing invalid prefetches and wasting resources.

[0054] In one optional embodiment of this application, after the above-described operation of determining the step memory access instruction in the program to be processed, the embodiment of this application may further include the following steps:

[0055] S21. Determine the offset value corresponding to the step memory access instruction, and record the offset value in the record entry corresponding to the destination register of the offset value in the second record table.

[0056] The operation of determining the prefetch address of the instruction to be prefetched based on the base instruction and the base address of the instruction to be prefetched, as described above, may specifically include the following in embodiments of this application:

[0057] S22. Obtain the target offset value corresponding to the base instruction from the second record table, and determine the target prefetch value based on the base instruction and the target offset value.

[0058] S23. Determine the prefetch address of the instruction to be prefetched based on the base address of the instruction to be prefetched and the target prefetch value.

[0059] Here, the offset value refers to the number of bits shifted in the shift operation following the step memory access instruction. The second record table can also be a pre-built memory table used to store the number of bits shifted in shift operations that occur in the dependency relationship. Furthermore, the destination register of the offset value refers to the destination register of the shift type instruction. For example, taking Reduced Instruction Set Computing (RISC-CV) as an example, the shift type instruction may include instructions such as sll and sh2add.

[0060] Accordingly, the second record table mentioned above can also contain multiple record entries, with different record entries corresponding to different registers. Each offset value can be recorded in the record entry corresponding to the destination register of the shift-type instruction. Specifically, in this embodiment, the left shift number can be recorded as a positive number and the right shift number as a negative number, depending on the shift direction of the shift-type instruction.

[0061] Furthermore, in this embodiment, if the record corresponding to the source register of any instruction in the first record table is not an initial value, the record corresponding to the source register in the first record table can be added to the record of the destination register of the instruction in the first record table. Simultaneously, the record corresponding to the source register in the second record table can be added to the record of the destination register of the instruction in the second record table, thus enabling the transfer of dependencies and offset values. Conversely, if the record corresponding to the source register of the instruction in the first record table is an initial value, then the records corresponding to the destination register of the instruction in both the first and second record tables can be kept at their initial values.

[0062] Optionally, before step 102 above, the following may also be included:

[0063] Step A: For any shift instruction in the program to be processed, if the source record of the shift instruction is not the initial value, update the record corresponding to the destination register of the shift instruction in the first record table from the initial value to the index value of the shift instruction. Here, the source record is the record corresponding to the source register of the shift instruction in the first record table.

[0064] Step B: Determine the offset value corresponding to the step memory access instruction based on the source operands of each shift instruction contained in the first record table.

[0065] Specifically, in this embodiment, shift instructions can be obtained based on the opcode of the instruction. Specifically, different instruction sets for different architectures define different shift instructions. In this embodiment, the opcode of the shift instruction defined by the instruction set corresponding to the current processor architecture is compared with the opcodes of each instruction in the program to be processed to obtain the shift instruction. Simultaneously, the record entry of the source register of the shift instruction in the first record table is checked to see if it is an initial value. If it is not an initial value, the shift instruction exists in the dependency relationship of the step memory access instruction and depends on the execution of the step memory access instruction. The record entry of the destination register of the shift instruction in the first record table can be updated from its initial value to the index value of the shift instruction. Correspondingly, if the source record entry is an initial value, the shift instruction does not exist in the dependency relationship of the step memory access instruction. Thus, this embodiment can also obtain the dependency chain of shift instructions that depend on the step memory access instruction through the first record table.

[0066] The shift instructions included in the first record table refer to the instructions indicated by the index values ​​corresponding to shift type instructions. It is understood that after the above steps, the records in the first record table fall into three categories: initial values, index values ​​of memory access instructions, and index values ​​of other types of instructions. Therefore, in this embodiment, the shift instructions included in the first record table can be obtained by reading the records belonging to the index values ​​of shift type instructions from the records of other type instruction index values. At this time, these shift instructions all belong to the dependency chain of straddle memory access instructions. It is understood that the number of shift instructions included in the first record table can be 0, 1, 2, etc., and varies depending on the program to be processed. This embodiment does not impose any limitations on this.

[0067] Furthermore, in determining the prefetch address in this embodiment, the target offset value corresponding to the base instruction can be obtained from the second record table first, and the target prefetch value can be determined based on the base instruction and the target offset value. Specifically, the prefetch data Value corresponding to the base instruction can be prefetched according to the step memory access instruction in the base instruction, and then the target offset value can be obtained by adding the offset values ​​that have appeared in the dependency relationship. After shifting the prefetch data to the left by the target offset value (shift), the target prefetch value Value << shift is obtained.

[0068] Furthermore, the prefetch address can be obtained by adding the target prefetch value to the base address.

[0069] In this embodiment of the application, by recording the offset value corresponding to the step memory access instruction in the second record table, the target offset value in the indirect memory access process can be conveniently obtained through the second record table when determining the prefetch address, thereby improving the efficiency of determining the prefetch address.

[0070] In one optional embodiment of this application, the embodiment may further include the following steps:

[0071] S31. Record the historical access address, historical target offset value, and historical access data of the step memory access instruction corresponding to each instruction to be prefetched as record items of each instruction to be prefetched into the third record table.

[0072] S32. For any of the prefetch instructions, if there is a record entry corresponding to the prefetch instruction in the third record table, obtain two adjacent historical access data from the record entry corresponding to the prefetch instruction, and obtain the difference between the two adjacent historical access data as a first difference; and obtain the difference between two adjacent historical access addresses as a second difference.

[0073] S33. Based on the first difference and the historical target offset value, determine the comparison value, and if the comparison value is consistent with the second difference, determine the current base address of the instruction to be prefetched based on the historical access data, historical access address and the historical target offset value that match the first difference and the second difference.

[0074] S34. If the number of times the current base address matches the historical base address recorded in the third record table is greater than a preset threshold, the current base address is used as the base address of the instruction to be prefetched, and the operation of determining the prefetch address of the instruction to be prefetched is then performed.

[0075] The aforementioned third record table can also be a pre-built storage table used to record the access data of each execution of the header instruction as historical access data, and the access address of each execution of the tail instruction as historical access address. Additionally, this embodiment can also record the target offset value of each execution of the tail instruction in the third record table as a historical offset value.

[0076] Specifically, in this embodiment, different record entries can be created in the third record table for each instruction to be prefetched. Each record entry can include the PC value of the instruction to be prefetched, the PC value of the corresponding straddle memory access instruction, the target offset value, the access data of the straddle memory access instruction, and the access address of the instruction to be prefetched. Optionally, the number of historical access data stored in each record entry can not exceed a preset upper limit. For example, a maximum of three historical access data entries can be stored. If the preset upper limit is exceeded, the stored historical access data can be deleted according to a first-in-first-out rule.

[0077] Here, the aforementioned current access address refers to the determined new prefetch address. Further, for any instruction to be prefetched, if a record corresponding to the instruction exists in the third record table, the difference between two adjacent historical access data entries can be obtained to get a first difference value, and the difference between two adjacent historical access addresses can be obtained to get a second difference value. The first difference value is shifted left by the number of bits indicated by the target offset value and compared with the second difference value. If they match, it indicates a successful pairing, and the base address can be determined based on the matched historical access address and historical access data. Optionally, the aforementioned second difference value can be the difference between two adjacent different historical access addresses.

[0078] Specifically, due to the complexity of current processors, instruction execution is often out of order and may involve multiple branches. This can lead to the execution of the first instruction followed by the last instruction, potentially causing misalignment between memory access data and prefetch addresses. To avoid this problem, embodiments of this application can implement an anti-interference mechanism based on records in a third record table.

[0079] For example, taking a third record table containing historical access data 10 and 6, a target offset value of 2, and historical access addresses of 0x108 and 0x118, we can use values(10, 6) and addrs(0x118, 0x108) for matching. The second difference is (0x118 - 0x108), and the value to be compared is ((10 - 6) << 2). The matching process is (10 - 6) << 2 = 0x118 - 0x108. It can be seen that the match is successful. At this point, the current base address can be determined based on the matched historical access addresses, historical access data, and historical target offset values. Here, the matched historical access data and historical access addresses refer to historical access data and historical access addresses that are recorded earlier or later in the time dimension.

[0080] Specifically, the determination method can be historical access address - historical access data << historical target offset value. For example, taking the second difference as (0x118-0x108) and the value to be compared as ((10-6)<<2), the matching process is (10-6)<<2=0x118-0x108. The base address can be calculated as 0x108-6<<2=0x108-0x18=0xF0.

[0081] Furthermore, after calculating the current base address, the current base address can be compared with the historical base addresses recorded in the third record table. If the number of matches exceeds a preset threshold, the current base address is used as the base address of the instruction to be prefetched, and the above-mentioned operation of determining the prefetch address of the instruction to be prefetched is performed. The preset threshold can be set arbitrarily, for example, it can be set to 1, 2, 3, etc., and this embodiment does not impose any limitations on it.

[0082] Optionally, embodiments of this application may further include:

[0083] S41. If the historical base address corresponding to the instruction to be prefetched does not exist in the third record table, the current base address is recorded as the historical base address corresponding to the instruction to be prefetched in the third record table.

[0084] If there is no historical base address corresponding to the instruction to be prefetched in the third record table, the current base address can be recorded in the third record table as the historical base address corresponding to the instruction to be prefetched.

[0085] Furthermore, by recording historical base addresses in the third record table, this embodiment of the application can perform the operation of determining the prefetch address of the instruction to be prefetched only when the number of times the current base address matches the historical base address exceeds a preset threshold. This can avoid prefetch errors caused by out-of-order execution of the processor.

[0086] Optionally, embodiments of this application may further include:

[0087] S51. If the current base address is consistent with the historical base address recorded in the third record table, increment the confidence level of the instruction to be prefetched in the third record table by 1.

[0088] When the number of times the current base address matches the historical base address recorded in the third record table exceeds a preset threshold, the current base address is used as the base address of the instruction to be prefetched, and then the operation of determining the prefetch address of the instruction to be prefetched is performed. Specifically, this application embodiment may include:

[0089] S52. If the current base address is consistent with the historical base address recorded in the third record table, and the confidence level corresponding to the instruction to be prefetched in the third record table is greater than a preset threshold, then the current base address is used as the base address of the instruction to be prefetched, and the operation of determining the prefetch address of the instruction to be prefetched is performed again.

[0090] Specifically, in this embodiment of the application, a confidence level can also be set for the instruction to be prefetched in the third record table. If the current base address is consistent with the historical base address in the third record table, the confidence level corresponding to the instruction to be prefetched is incremented by 1.

[0091] Accordingly, if the current base address is consistent with the historical base address recorded in the third record table, and the confidence level corresponding to the instruction to be prefetched in the third record table is greater than the preset threshold, then the current base address can be used as the base address of the instruction to be prefetched, and the operation of determining the prefetch address can be performed.

[0092] For example, Figure 2 illustrates a schematic diagram of an anti-interference mechanism of this application. As shown in Figure 2, the third record table (indirect table) in Figure 2 is used to record the index value (tail_pc) of the instruction to be prefetched, the index value of the straddle memory access instruction corresponding to the instruction to be prefetched (i.e., the first index value (head_pc), the target offset value (shift), the access data (head_value) of the straddle memory access instruction, the access address (first access address, head_addr), and the access address (second access address, tail_addr) and the base address (base_addr) of the instruction to be prefetched. It may also include the confidence level (conf) of the instruction to be prefetched.

[0093] Furthermore, when the processor executes memory access instructions, due to out-of-order execution, the execution order of prefetch instructions and straddle memory access instructions is uncertain. Figure 2 shows the execution results of several memory access instructions, where the execution results marked by the underline are the prefetch instructions. In the figure, the straddle memory access instructions load value (=10) and load value (=11) are executed before the prefetch instructions hit 0x118 and miss 0x11c, and load value (=4) is the latest execution result.

[0094] Meanwhile, the record entry for the instruction to be prefetched, 0x1a318, in Figure 2 contains three execution records, the corresponding step memory access instruction being 0x1a310. As shown in Figure 2, the historical access address for all three execution records is 0x108, and the execution results of the three step memory access instructions, in the order of execution, are: 6, 10, and 11, with a confidence level of 0.

[0095] In this embodiment of the application, when a prefetch instruction 0x11C is accessed, the difference between any two memory access data points, shifted left by the bits corresponding to 'shit', can be compared to see if it equals the difference in the memory access address. If they are equal, the base address can be calculated. For example, if values(10, 6) and addrs(0x118, 0x108) are successfully paired, the pairing process is (10-6)<<2=0x118-0x108. Then, based on the tail instruction address 0x108 and the head instruction value 6, the base address 0x108-6<<2=0x108-0x18=0xF0 can be calculated.

[0096] Furthermore, if the calculated base address is not found in the corresponding entry, it is stored. Otherwise, the newly calculated result is compared with the stored result; if they are equal, the confidence level of the corresponding entry is incremented by 1.

[0097] Optionally, if the current base address is inconsistent with the historical base address recorded in the third record table, the confidence level of the instruction to be prefetched in the third record table is decremented by 1, and the historical base address recorded in the third record table is updated to the current base address.

[0098] Thus, by setting a confidence level in the third record table and using historical memory access data and historical access addresses for judgment, this embodiment of the application avoids the training failure caused by execution misalignment due to out-of-order execution, and can guarantee the accuracy of the obtained base address to a certain extent.

[0099] Optionally, embodiments of this application can be implemented in hardware, and an indirect array-type recognition module and a base address value training module can be set up. These need to be used together with a step-type prefetcher and are both deployed on the data cache closest to the CPU (referred to as L1D Cache in this application).

[0100] Figure 3 shows a structural block diagram of a data prefetching embodiment of this application. As shown in Figure 3, when the processor executes the instruction stream of the program to be processed, it can send the instruction index (PC), opcode, and register identifiers to the indirect identification module. The indirect pattern identification module can identify the step memory access instruction through the step instruction table, obtain the index value of the step memory access instruction, i.e., the first index value, and update the record of the target register of the step memory access instruction in the first record table with the index value of the step memory access instruction, and then pass the index value of the dependency chain through the record. At the same time, it can also update the offset value of the step memory access instruction in the second record table until the instruction to be prefetched is identified, the indirect memory access pattern is identified, an identification signal (issue) occurs, and the indirect pattern dependency chain information is sent to the base address training module. The step instruction table can be obtained by reading the first index value through the step-type prefetcher.

[0101] For example, Figure 4 shows a structural block diagram of an indirect pattern recognition module of this application. As shown in Figures 3 and 4, the input of the indirect pattern recognition module is the transmitted instruction information (including instruction PC, opcode and three register numbers), and the recognition process is as follows:

[0102] If the input instruction is a memory access (load) instruction, and the corresponding entries in the source register (headPC entries) are all initialized to 0, the PC of the input instruction is searched in the step instruction table to identify whether it is a step instruction, and the entry in the destination register of the step instruction is set to the PC value of the step instruction.

[0103] If the current input instruction is identified as a step instruction, the index value of the step memory access instruction is updated to the corresponding record, that is, the instruction PC is stored in the record related to the destination register (e.g., headPC[a4] = 0x1a310).

[0104] If the current input instruction is a shift instruction (such as sll and sh2add in the RISC-V instruction set), the shift operation information is recorded in the shift entry of the corresponding destination register. Left shift bits are counted as positive numbers, and right shift bits are counted as negative numbers.

[0105] The transitive dependency chain and offset information, specifically the transitive headPC and shift information, are handled as follows: if the headPC entry for any source register is not 0, then both headPC and shift information for that source register are updated in the corresponding entry of the destination register. Otherwise, both information in the destination register are set to their initial values ​​of 0. If the input instruction is a memory access (load) instruction, and the record (headPC entry) for any source register is not 0, then the instruction PC is stored in the relevant headPC entry of the destination register.

[0106] After obtaining the dependency chain from the step memory access instruction to other memory access instructions, the indirect mode dependency chain information can be sent to the base address training module. This indirect mode dependency chain information may include the index values ​​of the instructions included in the dependency chain, the source register identifier of the step memory access instruction, the source register identifier of the offset, the destination register identifier, and the index value of the current instruction.

[0107] Furthermore, the base address training module can record the access value of the header instruction and the memory address of the tail instruction in the corresponding entries of the third record table (indirect table). Each entry can record a maximum of three memory access values; if more than three values ​​are recorded, they are replaced according to the first-in-first-out rule.

[0108] The second step involves calculating the difference between any two adjacent memory access values ​​in the recorded memory access table, shifting this difference left by the `shift` pointer in the table entry, and comparing this difference with the difference between the recorded address and the current address. If they are equal, the base address is calculated and stored. The purpose of subtracting any two memory access values ​​here is to prevent out-of-order execution from causing misalignment between the memory access values ​​and the memory access addresses, which could lead to training failure.

[0109] When a tail instruction access occurs again, the second step above is repeated. If a match is successful and the calculated base address is equal to the already stored base address, the confidence level of the corresponding entry is incremented by 1 to avoid identification errors; otherwise, the confidence level is decremented by 1. When the confidence level in the entry is 3, a cache hit or cache miss of the header instruction will trigger the prefetch mechanism. Based on the offset and base address, the location of the data that will be used by the tail instruction in the future is calculated, and the corresponding prefetch is issued. The prefetched data can be prefetched into the Level 1 prefetch queue (L1D prefetch queue), and the prefetched data can be pre-stored into the Level 1 cache (L1DCache) through the prefetch queue. In this way, when the processor executes indirect mode memory access instructions, it can first access the cache. When a hit occurs in the L1D Cache, it does not need to access the next level cache or memory (L1D MSHR, L2 Cache) through the Miss Status Handling Register (MSHR) to fill the data, thereby improving the cache hit rate, reducing the corresponding memory access latency, and thus improving the performance of indirect array-type instruction-intensive applications such as graph applications.

[0110] It should be noted that, for the sake of simplicity, the method embodiments are all described as a series of actions. However, those skilled in the art should understand that the embodiments of this application are not limited to the described order of actions, because according to the embodiments of this application, some steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also understand that the embodiments described in the specification are all preferred embodiments, and the actions involved are not necessarily required by the embodiments of this application.

[0111] Device Examples

[0112] Referring to Figure 5, a structural block diagram of an embodiment of a data prefetching device according to this application is shown. The device 20 may specifically include:

[0113] The first determining module 201 is used to determine the step memory access instruction in the program to be processed, and use the index value of the step memory access instruction as the first index value. In the first record table, the record entry corresponding to the destination register of the determined step memory access instruction is updated from the initial value to the first index value. The first record table contains multiple record entries, and different record entries correspond to different registers.

[0114] The second determining module 202 is configured to, for any other memory access instruction in the program to be processed, determine the other memory access instruction as a prefetch instruction if the target record of the other memory access instruction is not the initial value, and determine the base instruction corresponding to the prefetch instruction based on the target record of the prefetch instruction; the target record is the record corresponding to the source register of the other memory access instruction in the first record table;

[0115] The prefetch module 203 is used to determine the prefetch address of the instruction to be prefetched based on the base instruction and the base address of the instruction to be prefetched, and prefetch the data to be prefetched corresponding to the prefetch address into the cache.

[0116] Optionally, the device further includes:

[0117] The third determining module is used to determine the offset value corresponding to the step memory access instruction and record the offset value in the record entry corresponding to the destination register of the offset value in the second record table;

[0118] The prefetch module includes:

[0119] The fourth determining submodule is used to obtain the target offset value corresponding to the base instruction from the second record table, and determine the target prefetch value based on the base instruction and the target offset value;

[0120] The fifth determining submodule is used to determine the prefetch address of the instruction to be prefetched based on the base address of the instruction to be prefetched and the target prefetch value.

[0121] Optionally, the device further includes:

[0122] The first recording module is used to record the historical access address, historical target offset value and historical access data of the step memory access instruction corresponding to each instruction to be prefetched as the record items of each instruction to be prefetched into the third recording table;

[0123] The first acquisition module is configured to, for any of the prefetch instructions, if there is a record item corresponding to the prefetch instruction in the third record table, acquire two adjacent historical access data from the record item corresponding to the prefetch instruction, and acquire the difference between the two adjacent historical access data as a first difference; and acquire the difference between two adjacent historical access addresses as a second difference.

[0124] The fifth determining module is used to determine the comparison value based on the first difference and the historical target offset value, and when the comparison value is consistent with the second difference, to determine the current base address of the instruction to be prefetched based on the historical access data, historical access address and the historical target offset value that match the first difference and the second difference.

[0125] The execution module is configured to, when the number of times the current base address matches the historical base address recorded in the third record table exceeds a preset threshold, use the current base address as the base address of the instruction to be prefetched, and then execute the operation of determining the prefetch address of the instruction to be prefetched.

[0126] Optionally, the device further includes:

[0127] The second recording module is used to record the current base address as the historical base address corresponding to the instruction to be prefetched in the third recording table when the historical base address corresponding to the instruction to be prefetched does not exist in the third recording table.

[0128] Optionally, the device further includes:

[0129] The first confidence module is used to increment the confidence level of the instruction to be prefetched in the third record table by 1 when the current base address is consistent with the historical base address recorded in the third record table.

[0130] The execution module is specifically used for:

[0131] If the current base address is consistent with the historical base address recorded in the third record table, and the confidence level corresponding to the instruction to be prefetched in the third record table is greater than a preset threshold, then the current base address is used as the base address of the instruction to be prefetched, and the operation of determining the prefetch address of the instruction to be prefetched is performed again.

[0132] Optionally, the device further includes:

[0133] The second confidence module is used to decrement the confidence of the instruction to be prefetched in the third record table by 1 and update the historical base address recorded in the third record table to the current base address when the current base address is inconsistent with the historical base address recorded in the third record table.

[0134] Optionally, the third determining module includes:

[0135] The update submodule is used to update the record corresponding to the destination register of the shift instruction in the first record table from the initial value to the index value of the shift instruction for any shift instruction in the program to be processed, provided that the source record entry of the shift instruction is not the initial value; the source record entry is the record corresponding to the source register of the shift instruction in the first record table.

[0136] The sixth determining submodule is used to determine the offset value corresponding to the step memory access instruction based on the source operands of each shift instruction contained in the first record table.

[0137] In summary, this application provides a data prefetching apparatus. It determines a straddle memory access instruction in a program to be processed, and uses the index value of the straddle memory access instruction as a first index value. In a first record table, the record entry corresponding to the destination register of the determined straddle memory access instruction is updated from its initial value to the first index value. The first record table contains multiple record entries, with different record entries corresponding to different registers. For any other memory access instruction in the program to be processed, if the target record entry of the other memory access instruction is not the initial value, the other memory access instruction is determined as a prefetch instruction, and the base instruction corresponding to the prefetch instruction is determined based on the target record entry of the prefetch instruction. The target record entry is the record entry in the first record table corresponding to the source register of the other memory access instruction. Based on the base instruction and the base address of the prefetch instruction, the prefetch address of the prefetch instruction is determined, and the prefetch data corresponding to the prefetch address is prefetched into the cache. This application embodiment uses a first record table to identify indirect array memory access instructions in the program to be processed that depend on step memory access instructions, thereby enabling data prefetching of indirect array memory access instructions. Simultaneously, by identifying indirect array memory access instructions based on the dependency relationship between the source register and the destination register, the accuracy and coverage of the identification can be guaranteed. This allows for locating the instructions that truly need to be prefetched while avoiding issuing invalid prefetches and wasting resources.

[0138] As the system implementation is basically similar to the method implementation, it is described in a relatively simple way. For relevant details, please refer to the description of the method implementation.

[0139] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0140] Regarding the data prefetching apparatus in the above embodiments, the specific manner in which each module performs its operation has been described in detail in the embodiments related to the method, and will not be elaborated upon here.

[0141] This application also provides an electronic device, including: a processor and a memory for storing processor-executable instructions, wherein the processor is configured to execute the above-described data prefetching method.

[0142] Referring to Figure 6, which is a schematic diagram of the structure of an electronic device provided in an embodiment of this application, the electronic device includes a processor, a memory, a communication interface, and a communication bus. The processor, the memory, and the communication interface communicate with each other through the communication bus. The memory is used to store at least one executable instruction, which causes the processor to execute the data prefetching method of the aforementioned embodiment.

[0143] It should be noted that the electronic devices in the embodiments of this application include mobile electronic devices and non-mobile electronic devices.

[0144] The processor can be a CPU (Central Processing Unit), a general-purpose processor, a DSP (Digital Signal Processor), an ASIC (Application Specific Integrated Circuit), a FPGA (Field Programmable Gate Array), or other programmable devices, transistor logic devices, hardware components, or any combination thereof. The processor can also be a combination that implements computational functions, such as a combination of one or more microprocessors, a combination of a DSP and a microprocessor, etc.

[0145] The communication bus may include a path for transmitting information between the memory and the communication interface. The communication bus may be a PCI (Peripheral Component Interconnect) bus or an EISA (Extended Industry Standard Architecture) bus, etc. The communication bus can be divided into address bus, data bus, control bus, etc. For ease of illustration, only one line is used in Figure 6, but this does not indicate that there is only one bus or one type of bus.

[0146] The memory may be ROM (Read Only Memory) or other types of static storage devices that can store static information and instructions, RAM (Random Access Memory) or other types of dynamic storage devices that can store information and instructions, or it may be EEPROM (Electrically Erasable Programmable Read Only Memory), CD-ROM (Compact Disk Read Only), magnetic tape, floppy disk and optical data storage devices, etc.

[0147] This application also provides a non-transitory computer-readable storage medium that, when the instructions in the storage medium are executed by the processor of an electronic device (server or terminal), enables the processor to execute the data prefetching method shown in FIG1.

[0148] This application also provides a computer program product containing instructions that, when run on a computer, cause the computer to execute the data prefetching method shown in FIG1.

[0149] This application also provides a chip, which includes a processor and a communication interface. The communication interface is coupled to the processor. The processor is used to run programs or instructions to implement the various processes of the above-described data prefetching method embodiments and achieve the same technical effect. To avoid repetition, it will not be described again here.

[0150] It should be understood that the chip mentioned in the embodiments of this application may also be referred to as a system-on-a-chip, system chip, chip system, or system-on-a-chip, etc.

[0151] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0152] Those skilled in the art will understand that the embodiments of this application can be provided as methods, apparatus, or computer program products. Therefore, the embodiments of this application can be implemented entirely or partially by software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented entirely or partially as a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of this application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that integrates one or more available media. The available media may be magnetic media (e.g., floppy disks, hard disks, magnetic tapes), optical media (e.g., DVDs), or semiconductor media (e.g., solid state disks (SSDs)).

[0153] This application describes embodiments with reference to flowchart illustrations and / or block diagrams of methods, terminal devices (systems), and computer program products according to embodiments of this application. It should be understood that each block of the flowchart illustrations and / or block diagrams, as well as combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing terminal device to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing terminal device, create means for implementing the functions specified in one or more blocks of the flowchart illustrations and / or one or more blocks of the block diagrams.

[0154] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing terminal device to operate in a predictive manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means that implement the functions specified in one or more flowcharts and / or one or more block diagrams.

[0155] These computer program instructions may also be loaded onto a computer or other programmable data processing terminal equipment to cause a series of operational steps to be performed on the computer or other programmable terminal equipment to produce a computer-implemented process, such that the instructions, which execute on the computer or other programmable terminal equipment, provide steps for implementing the functions specified in one or more flowcharts and / or one or more block diagrams.

[0156] Although preferred embodiments of the present application have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of the embodiments of the present application.

[0157] The various embodiments in this specification are described in a related manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the system embodiments are basically similar to the method embodiments, so the description is relatively simple; relevant parts can be referred to the descriptions of the method embodiments.

[0158] It should be noted that the various data-related processes in the embodiments of this application are carried out in compliance with the relevant data protection laws and policies of the country where the location is located, and with the authorization granted by the owner of the corresponding device.

[0159] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this disclosure.

[0160] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0161] In the embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative. For instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0162] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0163] In addition, the functional units in the various embodiments of this disclosure can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0164] It is understood that the embodiments described in this disclosure can be implemented using hardware, software, firmware, middleware, microcode, or a combination thereof. For hardware implementation, modules, units, and subunits can be implemented in one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field-programmable gate arrays (FPGAs), general-purpose processors, controllers, microcontrollers, microprocessors, other electronic units for performing the functions described in this disclosure, or combinations thereof.

[0165] For software implementation, the techniques described in the embodiments of this disclosure can be implemented by modules (e.g., procedures, functions, etc.) that perform the functions described in the embodiments of this disclosure. The software code can be stored in memory and executed by a processor. The memory can be implemented in the processor or external to the processor.

[0166] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or terminal device that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or terminal device. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or terminal device that includes said element.

[0167] The above provides a detailed description of a data prefetching method, apparatus, electronic device, and readable storage medium provided in this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only for the purpose of helping to understand the method and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A data prefetching method, wherein, The method comprises: determining a cross-step memory access instruction in a to-be-processed program, and taking an index value of the cross-step memory access instruction as a first index value, and updating a record item corresponding to a destination register of the determined cross-step memory access instruction in a first record table from an initial value to the first index value; the first record table comprises a plurality of record items, and different record items correspond to different registers; for any other memory access instruction in the to-be-processed program, if a target record item of the other memory access instruction is not the initial value, the other memory access instruction is determined as a to-be-prefetched instruction, and a base instruction corresponding to the to-be-prefetched instruction is determined based on the target record item of the to-be-prefetched instruction; the target record item is a record item corresponding to a source register of the other memory access instruction in the first record table; based on the base instruction and a base address of the to-be-prefetched instruction, a prefetch address of the to-be-prefetched instruction is determined, and to-be-prefetched data corresponding to the prefetch address is prefetched into a cache.

2. The method of claim 1, wherein, After the cross-step memory access instruction in the to-be-processed program is determined, the method further comprises: determining an offset value corresponding to the cross-step memory access instruction, and recording the offset value into a record item corresponding to a destination register of the offset value in a second record table; the determination of the prefetch address of the to-be-prefetched instruction based on the base instruction and the base address of the to-be-prefetched instruction comprises: obtaining a target offset value corresponding to the base instruction from the second record table, and determining a target prefetch value based on the base instruction and the target offset value; determining the prefetch address of the to-be-prefetched instruction based on the base address of the to-be-prefetched instruction and the target prefetch value.

3. The method of claim 2, wherein, The method further comprises: recording, into a third record table, a historical access address, a historical target offset value of each to-be-prefetched instruction, and historical access data of a cross-step memory access instruction corresponding to the to-be-prefetched instruction as a record item of each to-be-prefetched instruction; for any to-be-prefetched instruction, if there is a record item corresponding to the to-be-prefetched instruction in the third record table, two adjacent historical access data corresponding to the to-be-prefetched instruction are obtained from the record item, and a difference value of the two adjacent historical access data is obtained as a first difference value; and a difference value of two adjacent historical access addresses is obtained as a second difference value; based on the first difference value and the historical target offset value, a to-be-compared value is determined, and if the to-be-compared value is consistent with the second difference value, a current base address of the to-be-prefetched instruction is determined based on the first difference value, the second difference value, matching historical access data, historical access addresses, and the historical target offset value; if the number of times that the current base address is consistent with historical base addresses recorded in the third record table is greater than a preset number threshold, the current base address is taken as the base address of the to-be-prefetched instruction, and the operation of determining the prefetch address of the to-be-prefetched instruction is performed again.

4. The method according to claim 3, wherein, After the current base address of the to-be-prefetched instruction is determined, the method further comprises: In a case where the current base address is inconsistent with the historical base address recorded in the third record table, the confidence of the to-be-pre-fetched instruction in the third record table is decreased by 1, and the historical base address recorded in the third record table is updated to the current base address.

5. The method of claim 3, wherein, After the current base address of the to-be-pre-fetched instruction is determined, the method further includes: In a case where the current base address is consistent with the historical base address recorded in the third record table, the confidence of the to-be-pre-fetched instruction corresponding to the to-be-pre-fetched instruction in the third record table is increased by 1. In a case where the number of times that the current base address is consistent with the historical base address recorded in the third record table is greater than a preset number threshold, the current base address is taken as the base address of the to-be-pre-fetched instruction, and the operation of determining the pre-fetch address of the to-be-pre-fetched instruction is performed again, including: In a case where the current base address is consistent with the historical base address recorded in the third record table, if the confidence of the to-be-pre-fetched instruction corresponding to the to-be-pre-fetched instruction in the third record table is greater than a preset threshold, the current base address is taken as the base address of the to-be-pre-fetched instruction, and the operation of determining the pre-fetch address of the to-be-pre-fetched instruction is performed again.

6. The method of claim 5, wherein, The method further includes: In a case where the current base address is inconsistent with the historical base address recorded in the third record table, the confidence of the to-be-pre-fetched instruction in the third record table is decreased by 1, and the historical base address recorded in the third record table is updated to the current base address.

7. The method of claim 2, wherein, The operation of determining the offset value corresponding to the stride memory access instruction includes: For any shift instruction in the to-be-processed program, in a case where a source record item of the shift instruction is not the initial value, a record item corresponding to a destination register of the shift instruction in the first record table is updated from the initial value to an index value of the shift instruction; the source record item is a record item corresponding to a source register of the shift instruction in the first record table; The offset value corresponding to the stride memory access instruction is determined based on source operands of each shift instruction included in the first record table.

8. The method of claim 1, wherein, The method further includes: For any other type instruction in the to-be-processed program, in a case where a source record item of the other type instruction is not the initial value, a record item corresponding to a destination register of the other type instruction in the first record table is updated from the initial value to an index value of the other type instruction; The other type instruction refers to an instruction whose instruction type is not a memory type; and the source record item is a record item corresponding to a source register of the other type instruction in the first record table.

9. A data prefetching apparatus, wherein, The apparatus includes: A first determination module is configured to determine a stride memory access instruction in a to-be-processed program, take an index value of the stride memory access instruction as a first index value, and update a record item corresponding to a destination register of the determined stride memory access instruction in a first record table from an initial value to the first index value; the first record table includes a plurality of record items, and different record items correspond to different registers. The second determining module is configured to, for any other memory access instruction in the to-be-processed program, determine the other memory access instruction as a to-be-prefetched instruction if a target record item of the other memory access instruction is not the initial value, and determine a base instruction corresponding to the to-be-prefetched instruction based on the target record item of the to-be-prefetched instruction; the target record item is a record item corresponding to a source register of the other memory access instruction in the first record table; The prefetching module is configured to determine a prefetch address of the to-be-prefetched instruction based on the base instruction and a base address of the to-be-prefetched instruction, and prefetch to-be-prefetched data corresponding to the prefetch address into a cache.

10. The apparatus of claim 9, wherein, The apparatus further includes: The third determining module is configured to determine an offset value corresponding to the stride memory access instruction, and record the offset value into a record item corresponding to a destination register of the offset value in a second record table; The prefetching module includes: The fourth determining submodule is configured to acquire a target offset value corresponding to the base instruction from the second record table, and determine a target prefetch value based on the base instruction and the target offset value; The fifth determining submodule is configured to determine a prefetch address of the to-be-prefetched instruction based on the base address of the to-be-prefetched instruction and the target prefetch value.

11. The apparatus of claim 10, wherein, The apparatus further includes: The first recording module is configured to record, as a record item of each to-be-prefetched instruction, a historical access address, a historical target offset value of each to-be-prefetched instruction, and historical access data of a stride memory access instruction corresponding to the to-be-prefetched instruction into a third record table; The first acquiring module is configured to, for any to-be-prefetched instruction, acquire, from a record item corresponding to the to-be-prefetched instruction, two adjacent historical access data and a difference value of the two adjacent historical access data as a first difference value if the record item corresponding to the to-be-prefetched instruction exists in the third record table, and acquire a difference value of two adjacent historical access addresses as a second difference value; The fifth determining module is configured to determine a to-be-compared value based on the first difference value and a historical target offset value, and determine a current base address of the to-be-prefetched instruction based on the first difference value, the second difference value, matching historical access data, matching historical access addresses, and the historical target offset value if the to-be-compared value is consistent with the second difference value; The executing module is configured to, if a number of times that the current base address is consistent with historical base addresses recorded in the third record table is greater than a preset number threshold, take the current base address as a base address of the to-be-prefetched instruction, and perform the operation of determining the prefetch address of the to-be-prefetched instruction again.

12. The apparatus of claim 11, wherein, The apparatus further includes: The second recording module is configured to record the current base address as a historical base address corresponding to the to-be-prefetched instruction into the third record table if the historical base address corresponding to the to-be-prefetched instruction does not exist in the third record table.

13. The apparatus of claim 11, wherein, The apparatus further includes: The first confidence degree module is configured to, if the current base address is consistent with the historical base addresses recorded in the third record table, increase a confidence degree corresponding to the to-be-prefetched instruction in the third record table by 1. The execution module is specifically configured to: In a case where the current base address is consistent with the historical base address recorded in the third record table, if the confidence corresponding to the to-be-pre-fetched instruction in the third record table is greater than a preset threshold, taking the current base address as the base address of the to-be-pre-fetched instruction, and then performing the operation of determining the pre-fetch address of the to-be-pre-fetched instruction.

14. The apparatus of claim 13, wherein, The apparatus further includes: The second confidence module is configured to, in a case where the current base address is inconsistent with the historical base address recorded in the third record table, decrease the confidence of the to-be-pre-fetched instruction in the third record table by 1, and update the historical base address recorded in the third record table to the current base address.

15. The apparatus of claim 10, wherein, The third determination module includes: The updating submodule is configured to, for any shift instruction in the to-be-processed program, in a case where a source record item of the shift instruction is not the initial value, update a record item corresponding to a destination register of the shift instruction in the first record table from the initial value to an index value of the shift instruction; the source record item is a record item corresponding to a source register of the shift instruction in the first record table. The sixth determination submodule is configured to determine the offset value corresponding to the stride memory access instruction based on source operands of each shift instruction included in the first record table.

16. The apparatus of claim 9, wherein, The apparatus is further configured to: For any other type of instruction in the to-be-processed program, in a case where a source record item of the other type of instruction is not the initial value, update a record item corresponding to a destination register of the other type of instruction in the first record table from the initial value to an index value of the other type of instruction. The other type of instruction refers to an instruction whose instruction type is not a memory type; the source record item is a record item corresponding to a source register of the other type of instruction in the first record table.

17. An electronic device, comprising: The electronic device includes a processor, a memory, a communication interface, and a communication bus, the processor, the memory, and the communication interface complete communication with each other through the communication bus; the memory is used to store executable instructions, and the executable instructions make the processor execute the data pre-fetching method in any one of claims 1 to 8.

18. A readable storage medium, wherein, When the instructions in the readable storage medium are executed by the processor of the electronic device, the processor can execute the data pre-fetching method in any one of claims 1 to 8.

19. A chip, including a processor and a communication interface, the communication interface and the processor are coupled, the processor is used to run a program or an instruction, and the data pre-fetching method in any one of claims 1 to 8 is realized.

20. A synchronization control apparatus / device, including the apparatus / device (configured to) execute the data pre-fetching method in any one of claims 1 to 8.

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