Method and device for determining an error state in a semiconductor module

Abstract

The present invention relates to a method and a device for determining an error state in a semiconductor module, the method comprising: measuring a first capacitance value which represents a capacitance (C1) between a gate terminal (10) and a source terminal (20) of the semiconductor module, wherein the gate terminal (10) and the source terminal (20) are in each case terminals of the semiconductor module which can be contacted from the outside and which are connected within the semiconductor module to respective gate contacts (G1, G2, G3, G4) and source contacts (S1, S2, S3, S4) of semiconductor switches (T1, T2, T3, T4) connected in parallel; measuring a second capacitance value which represents a capacitance (C2) between the gate terminal (10) and a drain terminal (30) of the semiconductor module, wherein the drain terminal (30) is a terminal of the semiconductor module which can be contacted from the outside and which is connected within the semiconductor module to respective drain contacts (D1, D2, D3, D4) of the semiconductor switches (T1, T2, T3, T4); determining a number of faulty semiconductor switches (T1, T2, T3, T4) and / or respective causes of faults based on a comparison of the measured first capacitance value and the measured second capacitance value with expected values; and outputting information representing the number of faulty semiconductor switches (T1, T2, T3, T4) and / or respective causes of faults within the semiconductor module.

Description

[0001] Description

[0002] title

[0003] Method and apparatus for determining a fault condition of a

[0004] semiconductor module

[0005] State of the art

[0006] The present invention relates to a method and a device for determining a fault condition of a semiconductor module.

[0007] Power modules are known from the state of the art, which are used, for example, in inverters of battery-electric vehicles.

[0008] Since these are central components of such vehicles, ensuring the flawless functionality of these power modules is of particular importance, which is why, for example, vibration tests are carried out to check the reliability of bond wire connections, which are usually used between contact surfaces of the respective power semiconductor switches of the power modules and external connections of the power modules.

[0009] It is known to check the fault-free operation of power modules based on a voltage from a voltage source which is applied to the semiconductor switches of the power modules in order to determine the state of the semiconductor switches based on a value of a voltage measured across the semiconductor switches.

[0010] Disclosure of the invention

[0011] According to a first aspect of the present invention, a method for determining a fault condition of a semiconductor module is proposed, wherein the semiconductor module contains a plurality of parallel-connected semiconductor switches (e.g., two, three, four, or more). The semiconductor module can be used, for example, in a bridge circuit of an inverter or in a different configuration.

[0012] Particularly advantageous is the large number of parallel-connected semiconductor switches, each configured as a power semiconductor switch and / or FETs and / or MOSFETs and / or IGBTs and / or bipolar transistors and / or in a different configuration.

[0013] The steps of the method according to the invention, described below, are carried out, for example, on the basis of an evaluation unit, which can be configured, among other things, as a processor, ASIC, FPGA, digital signal processor, microcontroller, or similar device. Furthermore, it is possible for the steps of the method according to the invention to be carried out on the basis of a computer program that can be executed by the evaluation unit. For this purpose, the computer program is stored, for example, in a storage unit that is connected to the evaluation unit via information technology.

[0014] It should be generally noted that the method according to the invention can be carried out by a unit and / or component that differs from the evaluation unit described above, but that the following description is based on the use of such an evaluation unit as a representative example, without thereby restricting it to such a unit.

[0015] In a first step of the method according to the invention, a first capacitance value is measured, which represents a first capacitance between a gate terminal and a source terminal of the semiconductor module, wherein the gate terminal and the source terminal are each externally contactable terminals of the semiconductor module, which are electrically connected within the semiconductor module to respective gate contacts and source contacts of the parallel-connected semiconductor switches.

[0016] For this purpose, for example, a capacity measuring device known from the prior art can be used, which can be connected to the evaluation unit described above via information technology and / or be designed together with it in one unit in order to enable the evaluation unit to process the measured first capacity value.

[0017] In a second step of the inventive method, a second capacitance value is measured, which represents a second capacitance between the gate terminal and a drain terminal of the semiconductor module, wherein the drain terminal is an externally contactable terminal of the semiconductor module, which is electrically connected within the semiconductor module to the respective drain contacts of the parallel-connected semiconductor switches.

[0018] It should be generally noted that the respective source, drain, and gate contacts (e.g., contact surfaces, also referred to as "pads") of the respective semiconductor switches are preferably electrically connected to their respective corresponding externally contactable source, drain, and gate terminals by means of bond wires, without thereby restricting the use to such bond wire connections.

[0019] It should be further noted that the measurement of the second capacitance value can be performed using the aforementioned capacitance meter and / or a different, alternative capacitance meter. Furthermore, it is possible to perform the measurements of the first and second capacitances simultaneously or sequentially. For example, if only one capacitance meter is available for measuring both the first and second capacitances, it is possible to automatically connect the meter to the first capacitance and then to the second capacitance (or vice versa) via switches controlled by the evaluation unit to perform the respective measurements.

[0020] In a third step of the method according to the invention, a number of defective semiconductor switches and / or the respective causes of defects within the semiconductor module are determined based on a comparison of the measured first capacitance value and the measured second capacitance value with predefined expected values. For this purpose, for example, a first expected value, which is compared with the first capacitance value, and a second expected value, which is compared with the second capacitance value, are stored in a storage unit (e.g., in the aforementioned storage unit) which is connected to the evaluation unit via information technology, so that the evaluation unit can retrieve and use the respective expected values ​​from the storage unit as needed. The expected values ​​preferably represent capacitance values ​​that would be expected during a measurement if no defect were present within the semiconductor module.

[0021] A particularly advantageous feature is the storage of a corresponding tolerance range for each expected value (e.g., a first tolerance range for the first expected value and / or a second tolerance range for the second expected value), which can be taken into account when comparing the respective measured capacitance values ​​with the corresponding expected values. In other words, deviations between the expected values ​​and the measured values ​​can occur due to component, manufacturing, and / or measurement tolerances and / or external influences such as the ambient temperature, etc., without necessarily indicating a defect in the semiconductor module.

[0022] As long as the first and second measured values ​​remain within the specified tolerance range around the respective expected value, it can be assumed that the semiconductor module is in a fault-free state.

[0023] Furthermore, it may be useful to provide different tolerances or tolerance ranges depending on the respective range in which the first capacitance value and / or the second capacitance value lie, in order to achieve an optimized adaptation of the respective tolerances or tolerance ranges to a number of currently faulty semiconductor switches.

[0024] Alternatively or additionally to using a first tolerance range for the first expected value and a second tolerance range for the second expected value, it is also conceivable to define and use a multitude of first expected values ​​with a multitude of corresponding first tolerance ranges and a multitude of second expected values ​​with a multitude of corresponding second tolerance ranges. These could be stored, for example, in a lookup table in a memory unit and selected based on a current temperature. For measuring the current temperature, a temperature sensor could be placed in the thermal environment of the semiconductor module, capable of providing the evaluation unit with current temperature values ​​of the semiconductor module.Alternatively or additionally, it is also possible for the temperature sensor to be integrated with the semiconductor module and to be contactable with the evaluation unit via information technology.

[0025] Conversely, a fault condition of the semiconductor module can be assumed if the first capacitance value and / or the second capacitance value are outside the respective tolerance range for the respective expected values.

[0026] A cause of error can be determined in particular on the basis of a type and / or magnitude of a deviation of the capacity values ​​from the respective expected values ​​or corresponding tolerance ranges, which will be explained in more detail below in the course of describing advantageous embodiments of the present invention.

[0027] In a fourth step of the method according to the invention, information representing the number of defective semiconductor switches and / or the respective causes of the defects with respect to the semiconductor module is output. The output of this information is based, for example, on a signal that transmits the information from the evaluation unit to another component (e.g., an optical display such as a screen, a light source, and / or a transducer for acoustic output, and / or a control unit, etc.). Alternatively or additionally, it is also conceivable that the signal is used for automatic identification and / or sorting of the defective semiconductor module, etc.

[0028] It should be noted that the method according to the invention can be carried out in an active and / or inactive and / or test mode of the semiconductor module. For example, the method according to the invention can be carried out during a vibration test to which the semiconductor module can be subjected by attaching the semiconductor module to a vibration device (e.g., a so-called "shaker cube," etc.) which is subjected, for example, to a standardized vibration pattern in order to verify the robustness and / or reliability of internal connections (in particular bond wire connections) of the semiconductor module. During such a test, the method according to the invention can preferably be carried out repeatedly, for example, to correlate measurements and / or to determine the time of occurrence of a defect, etc.

[0029] Alternatively or additionally, it is possible to carry out the method according to the invention at different temperatures and / or at different strengths of magnetic coupling into the semiconductor module in order to be able to check the reliability of the semiconductor module also with regard to different boundary conditions.

[0030] Apart from such a test operation, it is of course possible to check the condition of the semiconductor module or other semiconductor modules in a real application of the semiconductor modules (e.g. in a vehicle), preferably on a recurring basis, and to take appropriate fault handling measures if necessary.

[0031] The method according to the invention offers the particular advantage that fault conditions in a semiconductor module can be detected regardless of the type of semiconductor switches housed in the module, even in inactive (i.e., uncontrolled) operation of the semiconductor switches. This makes it advantageously possible to reliably test FET semiconductors, etc., even in inactive operation.

[0032] This can be advantageous for purely test-based operation, in which no active control of the semiconductor switches of the semiconductor module according to the invention is possible, and also in real-world use, since the state of the semiconductor module can be checked, for example, before the semiconductor module is activated.

[0033] The dependent claims describe preferred embodiments of the invention. In an advantageous embodiment of the present invention, the number of defective semiconductor switches within the semiconductor module is determined by calculating by what multiple of a predefined expected individual capacitance of a single semiconductor switch the measured first capacitance value and / or the measured second capacitance value is smaller than the respective expected value of the first capacitance value and / or the second capacitance value. In a case where, for example, four semiconductor switches are connected in parallel in the semiconductor module, a defective connection to one of the semiconductor switches leads, for example, to only three-quarters of an expected total capacitance value (which results accordingly from the sum of four expected individual capacitance values) being measured as the first capacitance value or as the second capacitance value.In a case where, for example, connections between two semiconductor switches are defective, the result is half of the expected total capacitance value, etc.

[0034] In a further advantageous embodiment of the present invention, an interruption between the source terminal of the semiconductor module and all source contacts of the plurality of semiconductor switches is identified as the cause of the fault if the first capacitance value is essentially zero and the second capacitance value is essentially a multiple of an expected gate-drain single capacitance of a single semiconductor switch. This does not preclude the possibility that, in the event of a deviation of the second capacitance value from the expected value, there may also be a problem with respect to one or more drain connections. However, in such a case, the connection to all drain contacts of the semiconductor switches is not interrupted.

[0035] In a further advantageous embodiment of the present invention, an interruption between the drain terminal of the semiconductor module and all drain contacts of the plurality of semiconductor switches is identified as the cause of a fault if the second capacitance value is essentially zero and the first capacitance value is essentially a multiple of an expected gate-source capacitance of a single semiconductor switch. The same applies to the first capacitance value as described above for the second capacitance value.

[0036] Furthermore, based on the method according to the invention, an open circuit between the gate terminal of the semiconductor module and all gate contacts of the plurality of semiconductor switches can be determined if the first capacitance value and the second capacitance value each essentially correspond to a value of zero. Alternatively or additionally, an open circuit between the source terminal and all source contacts and between the drain terminal and all drain contacts of the plurality of semiconductor switches can be determined if the first capacitance value and the second capacitance value each essentially correspond to a value of zero.

[0037] Alternatively or additionally, based on the method according to the invention, a defect within an assembly of a semiconductor switch of a plurality of semiconductor switches is determined if the first capacitance value and the second capacitance value are each greater than zero and do not substantially correspond to a multiple of an expected gate-source capacitance and / or do not substantially correspond to a multiple of an expected gate-drain capacitance of a single semiconductor switch of the plurality of semiconductor switches. "Substantially" here refers in particular to a deviation from a multiple of the expected individual capacitance that lies outside a specified tolerance range for the respective multiples.

[0038] Preferably, the method according to the invention further comprises a step for identifying defective semiconductor switches among the plurality of semiconductor switches within the semiconductor module, in a case where the respective gate contacts of the plurality of semiconductor switches are electrically connected to one another in a chain (e.g., by means of a continuously contacted single gate bond wire) and one end of the chain connection is electrically connected to the gate terminal of the semiconductor module, by determining the location of an interruption in the chain connection based on the first capacitance value and / or the second capacitance value. In other words, with such a configuration of the gate connections, it is possible to determine between which gate contacts of the respective semiconductor switches a defect exists.

[0039] As described above, each expected value of the first capacitance value and / or the second capacitance value is assigned corresponding tolerances (one or more), which are taken into account when comparing the measured capacitance values ​​with the expected capacitances. Alternatively or additionally, the respective expected values ​​of the first capacitance value and / or the second capacitance value and / or their respective assigned tolerances are predefined depending on the current temperature of the semiconductor module and / or at least one of the semiconductor switches of the semiconductor module and / or depending on disturbances currently acting on the semiconductor module (e.g., the magnetic coupling described above by a test setup) and / or are adjusted accordingly.

[0040] In an advantageous embodiment of the present invention, the control of the semiconductor module during active operation is adapted depending on the number of faulty semiconductor switches and / or the respective cause of the fault. In this way, for example, the operation of a higher-level component using the semiconductor module, such as an inverter, can still be maintained even if some of the semiconductor switches and / or some of their electrical connections within the semiconductor module are faulty, by operating the semiconductor module at a correspondingly lower power to prevent damage to the semiconductor module. Determining a fault condition of the semiconductor module is particularly advantageous when the semiconductor module is inactive, so that the fault can be identified even before activation (i.e.,Before switching on and / or energizing the semiconductor module, information about potentially existing faults in the semiconductor module is available. This allows subsequent activation to be performed taking into account any currently existing faults in the semiconductor module. Among other things, this makes it possible to implement fault-dependent restricted operation of the semiconductor module and / or to implement fault handling measures that deviate from this. According to a second aspect of the present invention, a device for determining a fault state of a semiconductor module is proposed, wherein the semiconductor module contains a plurality of parallel-connected semiconductor switches and wherein the device is configured to execute a method according to the first aspect of the invention. For this purpose, the device includes, for example, an evaluation unit as described above, which is configured to execute the method.The features, combinations of features and the advantages arising from them correspond so clearly to those described in connection with the first-mentioned aspect of the invention that reference is made to the above statements to avoid repetition.

[0041] Brief description of the drawings

[0042] An embodiment of the invention is described in detail below with reference to the accompanying drawing. The drawing shows:

[0043] Figure 1 shows an exemplary embodiment of a device according to the invention for determining a fault condition of a semiconductor module which contains a plurality of parallel-connected semiconductor switches.

[0044] embodiment of the invention

[0045] Figure 1 shows an exemplary embodiment of a device according to the invention for determining a fault condition of a semiconductor module which contains a plurality of parallel-connected semiconductor switches T1 , T2, T3, T4.

[0046] The device here includes an evaluation unit 40 designed as a microcontroller, which is set up on the basis of a computer program to execute a method according to the invention for determining a fault condition of the semiconductor module.

[0047] The evaluation unit 40 is connected to a storage unit 50 via information technology, in which, for example, instructions and / or predefined values ​​and / or calculated and / or measured values ​​etc. specified by the computer program can be stored or can be stored, which are required in the course of carrying out the method according to the invention.

[0048] The evaluation unit 40 is set up in conjunction with a first capacitance measuring device 60 to measure a first capacitance value, which represents a first capacitance C1 (i.e., a total capacitance) between a gate terminal 10 and a source terminal 20 of the semiconductor module, wherein the gate terminal 10 and the source terminal 20 are each externally contactable terminals of the semiconductor module, which are electrically connected within the semiconductor module to the respective gate contacts G1, G2, G3, G4 and source contacts S1, S2, S3, S4 of the parallel-connected semiconductor switches T1, T2, T3, T4.

[0049] The first capacitance C1 measured by the first capacitance measuring device 60 corresponds in a fault-free state of the semiconductor module to four times the gate-source single capacitance Cgs of a single semiconductor switch T1, T2, T3, T4, since the single capacitances Cgs are also connected in parallel.

[0050] The evaluation unit 40 is further configured on the basis of a second capacitance measuring device 65 to measure a second capacitance C2 (i.e., a total capacitance) between the gate terminal 10 and a drain terminal 30 of the semiconductor module, wherein the drain terminal 30 is an externally contactable terminal of the semiconductor module, which is electrically connected within the semiconductor module to the respective drain contacts D1, D2, D3, D4 of the parallel-connected semiconductor switches T1, T2, T3, T4.

[0051] The second capacitance C1 measured by means of the second capacitance measuring device 65 thus corresponds in a fault-free state of the semiconductor module to four times a gate-drain single capacitance Cgd of a single semiconductor switch T1, T2, T3, T4, since the single capacitances Cgd are also connected in parallel.

[0052] The evaluation unit 40 is further set up to determine a number of faulty semiconductor switches T1, T2, T3, T4 and respective causes of fault within the semiconductor module on the basis of a comparison of the measured first capacitance value and the measured second capacitance value with respective predefined expected values.

[0053] For this purpose, a large number of expected values ​​for the respective capacities C1, C2 are stored in the storage unit 50, each with its associated tolerance ranges, whereby for different temperature ranges, corresponding expected values ​​and tolerance ranges are stored.

[0054] Since the evaluation unit 40 is additionally connected to a temperature sensor 70 integrated in the semiconductor module via information technology, the evaluation unit 40 is able to select the expected values ​​and tolerance ranges for the first capacitance C1 and the second capacitance C2 depending on a temperature currently present in the semiconductor module, in order to be able to determine potential deviations from the expected values ​​and their tolerance ranges particularly reliably on this basis, which indicate errors in the semiconductor module.

[0055] Finally, the evaluation unit 40 is set up to generate an output signal SA, which represents information about the number of faulty semiconductor switches T1, T2, T3, T4 and the respective causes of the faults within the semiconductor module.

[0056] In a case where the device according to the invention is used, for example, in a test device for the semiconductor module, it is possible, based on the output signal SA, to display a test result via a display connected to the test device, from which the number and type of potentially detected errors can be seen.

[0057] It is understood that the configuration described above can also be intended for multiple semiconductor modules of an electrical circuit, for example for a low-side semiconductor module and a high-side semiconductor module of a bridge circuit, etc.

Claims

Claims 1. Method for determining a fault condition of a semiconductor module comprising a plurality of parallel-connected semiconductor switches (T1, T2, T3, T4): - a first step to measure a first capacitance value, which represents a first capacitance (C1) between a gate terminal (10) and a source terminal (20) of the semiconductor module, wherein the gate terminal (10) and the source terminal (20) are each externally contactable terminals of the semiconductor module, which are electrically connected within the semiconductor module to respective gate contacts (G1, G2, G3, G4) and source contacts (S1, S2, S3, S4) of the parallel-connected semiconductor switches (T1, T2, T3, T4), - a second step for measuring a second capacitance value, which represents a second capacitance (C2) between the gate terminal (10) and a drain terminal (30) of the semiconductor module, wherein the drain terminal (30) is an externally contactable terminal of the semiconductor module, which is electrically connected within the semiconductor module to the respective drain contacts (D1, D2, D3, D4) of the parallel-connected semiconductor switches (T1, T2, T3, T4), - a third step to determine a number of faulty semiconductor switches (T1, T2, T3, T4) and / or their respective causes of failure within the semiconductor module based on a comparison of the measured first capacitance value and the measured second capacitance value with the respective predefined expected values, and - a fourth step to output information representing the number of faulty semiconductor switches (T1 , T2, T3, T4) and / or respective fault causes within the semiconductor module.

2. The method of claim 1, wherein the number of defective The semiconductor switches (T1, T2, T3, T4) within the semiconductor module are determined by calculating the multiple of a predefined value. The expected single capacitance of a single semiconductor switch (T1 , T2, T3, T4) is that the measured first capacitance value and / or the measured second capacitance value is smaller than the respective expected value of the first capacitance value and / or the second capacitance value.

3. Method according to one of the preceding claims, wherein an interruption between the source terminal (20) of the semiconductor module and all source contacts (S1, S2, S3, S4) of the plurality of semiconductor switches (T1, T2, T3, T4) is identified as the cause of the fault if the first capacitance value is substantially zero and the second capacitance value is substantially a multiple of an expected gate-drain single capacitance (Cgd) of a single semiconductor switch (T1, T2, T3, T4).

4. Method according to one of the preceding claims, wherein an interruption between the drain terminal (30) of the semiconductor module and all drain contacts (D1, D2, D3, D4) of the plurality of semiconductor switches (T1, T2, T3, T4) is identified as the cause of the fault if the second capacitance value is substantially zero and the first capacitance value is substantially a multiple of an expected gate-source single capacitance (Cgs) of a single semiconductor switch (T1, T2, T3, T4).

5. Method according to any one of the preceding claims, wherein an interruption - between the gate terminal (10) of the semiconductor module and all gate contacts (G1, G2, G3, G4) of the plurality of semiconductor switches (T1, T2, T3, T4) and / or - between the source terminal (20) and all source contacts (S1 , S2, S3, S4) and between the drain terminal (30) and all drain contacts (D1 , D2, D3, D4) of the plurality of semiconductor switches (T1 , T2, T3, T4) is determined when the first capacitance value and the second capacitance value are essentially each equal to a value of zero.

6. Method according to one of the preceding claims, wherein a fault within an assembly of a semiconductor switch (T1, T2, T3, T4) of the The plurality of semiconductor switches (T1, T2, T3, T4) will be determined if the first capacitance value and the second capacitance value are each greater than zero and are not substantially a multiple of an expected gate-source single capacitance (Cgs) and / or not substantially a multiple of an expected gate-drain single capacitance (Cgd) of a single semiconductor switch (T1, T2, T3, T4) of the plurality of semiconductor switches (T1, T2, T3, T4).

7. A method according to one of the preceding claims further comprising a step for identifying defective semiconductor switches (T1, T2, T3, T4) of the plurality of semiconductor switches (T1, T2, T3, T4) within the semiconductor module in a case in which the respective gate contacts (G1, G2, G3, G4) of the plurality of semiconductor switches (T1, T2, T3, T4) are electrically connected to each other in a chain and one end of the chain connection is electrically connected to the gate terminal (10) of the semiconductor module, by determining a location of an interruption of the chain connection on the basis of the first capacitance value and / or the second capacitance value.

8. Method according to any one of the preceding claims, wherein - corresponding tolerances are assigned to the respective expected values ​​of the first capacity value and / or the second capacity value, which are taken into account when comparing the measured capacities with the expected capacities, and / or - the respective expected values ​​of the first capacity value and / or the second capacity value and / or their respective assigned tolerances depending on - a current temperature of the semiconductor module and / or at least one of the semiconductor switches (T1, T2, T3, T4) of the semiconductor module, and / or - disturbances currently affecting the semiconductor module are predefined and / or adapted.

9. Method according to one of the preceding claims, wherein the semiconductor module is controlled in an active operation of the semiconductor module depending on a number of defective Semiconductor switches (T1, T2, T3, T4) and / or adapted to a respective cause of fault.

10. Device for determining a fault condition of a semiconductor module which contains a plurality of parallel-connected semiconductor switches (T1 , T2, T3, T4), wherein the device is configured to carry out a method according to one of the preceding claims.

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