Method and device for processing information associated with multiple chiplets

Abstract

A method for processing information associated with multiple chiplets, comprising: managing configuration information for at least one chiplet system having multiple chiplets; configuring the multiple chiplets to form the chiplet system based on at least some of the configuration information.

Description

[0001] Description

[0002] title

[0003] Method and apparatus for processing information associated with multiple chiplets

[0004] State of the art

[0005] The disclosure relates to a method for processing information associated with multiple chiplets.

[0006] The disclosure also relates to a device for processing information associated with multiple chiplets.

[0007] Disclosure of the invention

[0008] Some examples refer to a method, such as a computer-implemented method, for processing information associated with multiple chiplets, comprising: managing configuration information for at least one chiplet system comprising multiple chiplets, and configuring the multiple chiplets to the chiplet system based on at least some of the configuration information. In some examples, this enables flexible, for example, dynamic, provisioning of one or more chiplet systems, for example, each with different configurations.

[0009] In some examples, managing the configuration information includes at least one of the following elements: a) storing the configuration information, or b) receiving the configuration information, or c) copying the configuration information, or d) generating the configuration information, or e) sending the configuration information. In some examples, configuring the multiple chiplets includes at least one of the following elements: a) establishing data connections between the multiple chiplets, for example, by interconnecting them, according to at least some of the configuration information, or b) establishing at least one data connection between at least one component, for example, at least one chiplet, of the chiplet system and at least one device, for example, external to the chiplet system.

[0010] In some examples, it is provided that at least one of the multiple chiplets has or represents at least one of the following elements: a) processor, for example processor core, or b) memory, or c) graphics processor, for example GPU, or d) accelerator device, for example computational accelerator and / or AI accelerator, or e) encoder and / or decoder, for example codec.

[0011] In some examples, the procedure is designed to include: operating the chiplet system.

[0012] In some examples, the operation of the chiplet system is provided for to include at least one of the following elements: a) controlling, for example, activating and / or deactivating, an electrical power supply for at least one chiplet, or b) controlling a data flow between at least one chiplet and at least one other component, for example, at least one other chiplet or an external device, or c) determining, for example, acquiring, information regarding the operation of the chiplet system.

[0013] In some examples, the procedure includes: receiving control information, for example from an external device; optionally controlling at least one aspect, for example the operation, of the chiplet system based on at least that control information. In some examples, the procedure includes: retrieving information regarding the operation of the chiplet system; and sending at least some of that information, for example to an external device.

[0014] Some examples refer to a device for carrying out the process according to the disclosure.

[0015] In some examples, the device may be in the form of a card, such as an expansion card or interface card, for example for a target system, such as a computer, where, for example, the computer may represent a host system.

[0016] Some examples refer to a system comprising at least one device according to the disclosure and a plurality of chiplets.

[0017] In some examples, the system is designed to include a device, for example external to the chiplets, such as a computer, personal computer, or host system.

[0018] In some examples, the system may include a computer, e.g. a personal computer, and an interface card for the computer, for example with a PCIe interface or the like, wherein, for example, the interface card may include a device according to the disclosure, and / or several chiplets.

[0019] In some examples, the system is provided for to have at least one virtual machine, wherein, for example, the at least one virtual machine is configured to exchange information with at least one chiplet of the plurality of chiplets and / or with the device.

[0020] Some examples refer to a computer-readable storage medium, comprising instructions that, when executed by a computer, cause it to perform the procedure according to the disclosure. Some examples refer to a computer program, comprising instructions that, when the program is executed by a computer, cause it to perform the procedure according to the disclosure.

[0021] Some examples refer to a data carrier signal that transmits and / or characterizes the computer program according to the disclosure.

[0022] Some examples relate to a use of the method according to the disclosure and / or the device according to the disclosure and / or the system according to the disclosure and / or the computer-readable storage medium according to the disclosure and / or the computer program according to the disclosure and / or the data carrier signal according to the disclosure for at least one of the following elements: a) providing, for example, flexibly and / or dynamically providing, at least one chiplet system, or b) dynamically interconnecting several chiplets to form a chiplet system, or c) testing a configuration comprising several chiplets, or d) testing software for a chiplet system, or e) reducing the effort and / or costs associated with a hardware prototype, f) providing samples of chiplet systems, or f) providing a system on a chip, for example, at least partially virtual.

[0023] Further features, applications, and advantages will become apparent from the following description of examples illustrated in the figures of the drawing. All described or illustrated features, individually or in any combination, constitute the subject matter of the disclosure, irrespective of their aggregation in the claims or their cross-reference, and irrespective of their formulation or representation in the description or in the drawing.

[0024] The drawing shows:

[0025] Fig. 1 schematically shows a simplified flowchart,

[0026] Fig. 2 schematically shows a simplified block diagram, Fig. 3 schematically shows a simplified flowchart,

[0027] Fig. 4 schematically shows a simplified flowchart,

[0028] Fig. 5 schematically shows a simplified block diagram,

[0029] Fig. 6 schematically shows a simplified block diagram,

[0030] Fig. 7 schematically shows aspects of uses according to further exemplary embodiments.

[0031] Some examples, Fig. 1, 2, relate to a method, for example a computer-implemented method, for processing information associated with multiple chiplets 11, 12, 13, ... (Fig. 2), comprising: managing 100 (Fig. 1) configuration information l-CFG for at least one chiplet system 10a comprising multiple chiplets 11, 12, 13, ..., and configuring 102 the multiple chiplets 11, 12, 13, ... to the chiplet system 10a based on at least one l-CFG-10a part of the configuration information l-CFG. In some examples, this enables a flexible, for example dynamic, provisioning of one or more chiplet systems 10a, for example with different configurations.

[0032] In some examples, Fig. 1, it is provided that managing 100 of the configuration information l-CFG includes at least one of the following elements: a) storing 100a of the configuration information l-CFG, or b) receiving 100b of the configuration information l-CFG (for example, from an external facility 20), or c) copying 100c of the configuration information l-CFG (for example, to create further, e.g., modified, configuration information based on the copy), or d) creating 100d of the configuration information l-CFG, or e) sending 100e of the configuration information l-CFG.

[0033] In some examples, Fig. 1, it is provided that the configuration 102 of the multiple chiplets includes at least one of the following elements: a) Establishing 102a data connections DV-10a (Fig. 2) between the, for example, interconnecting 102b of the, multiple chiplets 11, 12, 13, for example according to at least one part l-CFG-10a of the configuration information l-CFG, or b) Establishing 102c at least one data connection DV-10a-ext between at least one component, for example at least one chiplet 12, of the chiplet system 10a and at least one, for example with respect to the chiplet system 10a, device 20.

[0034] In some examples, Fig. 2, it is provided that at least one of the several chiplets 11, 12, 13 has or represents at least one of the following elements: a) Processor PROC, for example processor core, or b) Memory MEM, or c) Graphics processor GPU, or d) Accelerator ACC, for example computational accelerator and / or AI accelerator, or e) Encoder COD and / or decoder DEC, for example codec CODEC.

[0035] In some examples, Fig. 1, the method is provided to include: operating 105 of the chiplet system 10a.

[0036] In some examples, Fig. 1, the operation 105 of the chiplet system 10a is provided for to include at least one of the following elements: a) controlling 105a, for example activating and / or deactivating, an electrical power supply EV-10a for at least one chiplet, or b) controlling 105b a data flow DF-10a between at least one chiplet 11 and at least one other component, for example at least one other chiplet 12, 13, ... or an external device 20, or c) determining 105c, for example acquiring, information l-BETR regarding an operation of the chiplet system 10a, for example to evaluate an operating behavior of the chiplet system 10a or at least one component thereof.

[0037] The optional block 200 according to Fig. 2 symbolizes an optional device 200 for carrying out at least some aspects of the disclosure.

[0038] In some examples, Fig. 3, the method is provided to: receive 110 of control information l-CTRL, for example from an external device 20, optionally control 112 at least one aspect, for example the operation, of the chiplet system 10a based at least on the control information l-CTRL.

[0039] In some examples, Fig. 4, the method is provided to: determine 120 of information l-BETR' regarding an operation of the chiplet system 10a, send 122 at least some part of the information l-BETR', for example to an external device 20.

[0040] Fig. 5 schematically shows a block diagram according to some examples. Element E1 symbolizes a device for carrying out aspects according to the disclosure, for example at least similar to the optional block 200 according to Fig. 2. In some examples, block E1 can be considered a controller.

[0041] Element E2 symbolizes an external device, e.g., at least similar to the optional block 20 in Fig. 2. For example, element E2 is a host system, e.g., in the form of a computer. Elements E3, E4, ... symbolize virtual machines that run, e.g., on the host system E2, i.e., on hardware of the host system E2.

[0042] The elements 11 a, 11 b, 12a, 12b, 13a, 13b, 14a, 15a, 15b, 15c, 15d, 15e each symbolize chiplets that can be configured by the controller E1, for example based on the respective configuration information l-CFG-10a, l-CFG-10b, i.e., that can be interconnected according to the respective configuration information l-CFG-10a, l-CFG-10b. Figure 5 shows, as an example, a state in which chiplets 11a, 12a, 13a, 14a are configured to form a first chiplet system 10a, for example based on the configuration information l-CFG-10a, and in which chiplets 11b, 12b, 13b are configured to form a second chiplet system 10b, for example based on the configuration information I-CFG-1Ob. The other chiplets 15a, 15b, 15c, 15d, 15e according to Figure 5 are, for example, not yet configured, but can be used in the future to form at least one further chiplet system.

[0043] Some examples, Fig. 5, refer to a device for carrying out the method according to the disclosure. In some examples, for instance, the device 200 according to Fig. 2 and / or the controller E1 according to Fig. 5 can represent or form such a device.

[0044] In some examples, Fig. 5, the device may, for example, be in the form of a card, for example an expansion card E10, for example an interface card, for example for a target system, for example for a computer, or be provided on an interface card E10, wherein, for example, the computer may represent a host system E2.

[0045] In other words, in some examples several chiplets 11 a, 11 b, ... and the device 200 or E1 can be arranged on an interface card E10 (Fig. 5) for a computer 20, E2, and the computer 20, E2 can, for example under the control of appropriate software, exchange information with the controller E1 or at least one of the chiplets or chiplet systems 10a, 10b.

[0046] Some examples, Fig. 2, 5, refer to a system 1000, 1000a comprising at least one device 200, E1, E10 according to the disclosure and a plurality of chiplets 11, 11a, 11b, ..., 15e.

[0047] In some examples, Fig. 5, it is provided that the system 1000a has a device, for example with respect to the chiplets 11a, 11b, ..., 15e, external, for example a computer, for example a personal computer, for example a host system E2.

[0048] In some examples, Fig. 5, the system 1000a may, for example, comprise a computer, e.g., a personal computer, E2, and an interface card E10 for the computer E2, for example with a PCIe interface or the like, wherein, for example, the interface card E10 may comprise a device E1 according to the disclosure, and / or several chiplets 11a, 11b, ....

[0049] In some examples, Fig. 5, it is provided that the system 1000a has at least one virtual machine E3, E4, ... wherein, for example, the at least one virtual machine E3, E4, ... is configured to exchange information with at least one chiplet 11 a, 11 b, ... of the plurality of chiplets and / or with the device E1, for example under control of the controller E1 and / or based on a configuration by the controller E1.

[0050] Fig. 6 schematically shows a device 200 for carrying out the method according to the disclosure according to some examples.

[0051] In further examples, Fig. 6, the device 200 is provided to have: a computing device ("computer") 202 having at least one computing core 202a, a storage device 204 associated with the computing device 202 for at least temporary storage of at least one of the following elements: a) data DAT (e.g. data associated with the configuration information l-CFG), b) computer program PRG, for example for carrying out the method according to the embodiments.

[0052] In other examples, the memory device 204 includes volatile memory (e.g., main memory (RAM)) 204a, and / or non-volatile (NVM) memory (e.g., flash EEPROM) 204b, or a combination thereof or with other memory types not explicitly mentioned.

[0053] Further examples relate to a computer-readable storage medium SM, comprising instructions PRG which, when executed by a computer 202, cause it to execute the method according to the embodiments.

[0054] Further examples relate to a computer program PRG, comprising instructions which, when the program PRG is executed by a computer 202, cause it to execute the method according to the embodiments.

[0055] Further examples relate to a data carrier signal DCS, which characterizes and / or transmits the computer program PRG according to the embodiments. The data carrier signal DCS can be received, for example, via an optional data interface 206 of the device 200.

[0056] Some examples, Fig. 7, refer to a use of 300 of the

[0057] Method according to the disclosure and / or the device 200, E1, E10 according to the disclosure and / or the system 1000, 1000a according to the disclosure and / or the computer-readable storage medium SM according to the disclosure and / or the computer program PRG according to the disclosure and / or the data carrier signal DCS according to the disclosure for at least one of the following elements: a) providing 301, for example, flexibly and / or dynamically providing at least one chiplet system 10a, or b) dynamically interconnecting 302 several chiplets 11, 12, 13, ... to form a chiplet system 10a, or c) testing 303 a configuration comprising several chiplets, or d) testing 304 software for a chiplet system, or e) reducing 305 the effort and / or costs associated with a hardware prototype, f) providing 306 samples for chiplet systems, or g) providing 307 of a system on a chip, for example at least partially virtual (e.g.B. in the form of a combination of a virtual machine E3 (Fig. 5) together with a chiplet system 10a).

[0058] In some examples, the principle according to the disclosure can be used, for example, to replicate as accurately as possible the runtime behavior of a hardware or system that can be represented, for example, by the chiplet system 10a or a target system for the chiplet system 10a (e.g., vehicle electronics).

[0059] For example, the virtual machines E3, E4, ... according to Fig. 5 can use real hardware, for example for software execution, which is represented by the configured chiplet systems 10a, 10b. In some examples, this hardware 10a, 10b is advantageously not, for example, permanently bound to the respective virtual machine E3, E4, so that in some examples it is possible to share this hardware 10a, 10b, for example, between several virtual machines, whereby, for example, a first virtual machine E3 uses the chiplet system 10a at times, and at other times, for example, another chiplet system 10b, etc.

[0060] In some examples, Fig. 5, the principle according to the disclosure can be used, for example, to test a complete system comprising, for example, software and hardware, where the software in some examples is executable using, for example, a virtual machine E3, and where the hardware, for example, in the form of at least one chiplet system 10a, 10b, is configurable and at least temporarily connectable to the virtual machine E3 to form the complete system under test. In some examples, this enables, for example, realistic system simulations and / or system tests, where, for example, the special hardware to be tested in the form of the chiplet system 10a is flexibly configurable and / or deployable. In some examples, this can make it possible, particularly in early phases of a development project, to test the complete system (e.g., "unit test").

[0061] In some examples, this makes it possible to investigate and / or understand the runtime behavior of the overall system relatively early in a development process, because the hardware, for example in the form of the chiplet system 10a, can be provided and is therefore available for testing, e.g. together with software, even in relatively early project or development phases.

[0062] In some examples, Fig. 2, the use of chiplets 11, 12, 13, ... in combination with the principle according to the disclosure allows for the relatively quick provision of different hardware systems (chiplet systems 10a, ...), e.g. on a common substrate, e.g. carrier chip, so that from these functional units represented by the chiplets 11, 12, 13, ... a new device can be manufactured, which in some examples is e.g. easier and faster to configure than a conventional custom SoC (System on Chip).

[0063] In some examples, Fig. 5, aspects of the disclosure can be realized by a controller E1 and several chiplets 11a, 11b, ..., 15e, which can be provided, for example, in the form of an interface card, for instance, for a host system, e.g., a computer, E2. In some examples, the system consisting of the controller E1 and at least some of the several chiplets 11a, 11b, ..., 15e is, for example, controllable by the computer E2.

[0064] In some examples, applying the principle according to the disclosure makes it possible, for example with software, e.g. for the controller E1 and / or for the computer E2, to select components, e.g. in the form of chiplets 11a, 12a, 13a, 14a, and to connect them, e.g., in a targeted manner, based on corresponding configuration information l-CFG-10a. In some examples, these connections can result in new hardware components 10a, 10b, ... on-the-fly, which in some examples are also referred to as a virtual system on a chip (VSOC). In some examples, a VSOC can be used to flexibly and / or efficiently recreate a, e.g., "finished", chiplet SOC (e.g., for later mass production) using the chiplet system 10a, 10b, for example, for relatively early phases of product development.

[0065] In some examples, such a VSOC has, for example, a comparatively similar performance parameter and / or functionality to a conventional chiplet-SOC with the same subcomponents (e.g., chiplets), since, for example, all subcomponents (chiplets) are not emulated (as in some conventional approaches), but are real "target hardware", represented by the physically existing chiplets 11a, 11b, ..., which are flexibly configurable to chiplet systems 10a, 10b, ... according to the principle of disclosure.

[0066] That is, since the chiplets 11 a, 11 b, ... of the configurable chiplet systems 10a, 10b according to some examples are real hardware (i.e. physical chiplets) that are configured according to the principle of disclosure, e.g. interconnected, the differences of the chiplet systems 10a, 10b to a target product to be developed, e.g., within the framework of mass production, are comparatively small.

[0067] In some examples, according to the principle of disclosure, multiple configurations (e.g., associated with different configuration information l-CFG-10a, l-CFG-10b) can be managed, e.g., in parallel, so that in some examples it is possible to manage several chiplet systems 10a, 10b, ..., for example as VSOCs, simultaneously, which, however, operate separately from each other, see the two chiplet systems 10a, 10b according to Fig. 5.

[0068] In some examples, Fig. 5, the principle according to the disclosure ensures that each component (hardware unit), e.g., each of the physically present chiplets 11a, 11b, ..., 15e, is exclusively assigned to, for example, only one chiplet system 10a, 10b, or VSOC per period under consideration. In some examples, Fig. 5, the principle according to the disclosure provides the host system E2, e.g., on the one hand, at least one function for controlling the connections (e.g., element DV-10a according to Fig. 2) of the chiplets, and on the other hand, e.g., the interfaces to / from the respective chiplet system 10a, 10b, e.g., to the VSOC, e.g., element DV-10a-ext according to Fig. 2, or the elements DV-10a-ext, DV-10b-ext according to Fig. 5.

[0069] In some examples, the principle of disclosure addresses, or improves upon, at least some of the following aspects, at least temporarily or partially: Earlier commencement of software development and testing. Since a chiplet SoC is, for example, built from various existing chiplets, in some examples software can be tested directly on real hardware—namely, a chiplet system 10a configured according to the principle of disclosure, which, for example, replicates the planned chiplet SoC—even before the chiplet SoC goes into production. With conventional approaches, this is only possible if an off-the-shelf SoC could be used, i.e., an existing, commercially available product of the SoC type with the appropriate hardware components. This results in comparatively many limitations for projects with some conventional approaches, as, for example,There is a trade-off between "functions are not available in the target system" (e.g., because the existing off-the-shelf SOC does not have these functions) or a comparatively expensive (new) production of a custom SOC that, for example, has at least some of the desired functions.

[0070] In some examples, the principle of disclosure allows testing, even before a project begins, to determine whether existing components (e.g., software components) will run on the target hardware. This can be achieved, for example, by providing the desired target hardware in the form of a chiplet system 10a, as described in the principle of disclosure, and testing it with the existing software components. These software components can run, for instance, on a virtual machine E3 (Fig. 5), which can be connected to the chiplet system 10a, at least temporarily, via data link DV-10a-ext, for example, using controller E1. This can save on hardware prototype costs in some cases and allow for a better, more flexible hardware selection for the actual target components. This can be accomplished, for example, by flexibly selecting several candidate chiplet systems (e.g.,...) using controller E1.(each with a different configuration) are configured and tested.

[0071] In some cases, the principle described in the disclosure can be used to analyze potential performance bottlenecks. For example, if a performance bottleneck occurs during a project, the principle can be used to test a configuration for a chiplet system 10b with a more powerful component (e.g., a CPU chiplet with higher computing power). As another example, if a currently configured accelerator ACC is insufficient, a different, more powerful accelerator can be integrated into the chiplet system 10b in a new configuration for testing purposes, e.g., to check whether the problems (e.g., the performance bottleneck mentioned above) can be resolved.

[0072] In some examples, the principle according to the disclosure allows for the provision of flexible test and simulation systems. Since, based on the principle according to the disclosure, simulation and test hardware can be provided, for example, at any time, flexibly, as a chiplet system 10a, possibly together with an associated virtual machine E3, e.g., as a VSOC, it is possible in some examples to avoid having to maintain multiple test and simulation hardware, as is the case with some conventional approaches. In some examples, e.g., in the case of a retest, a chiplet system, possibly with an associated virtual machine, e.g., as a VSOC, can be configured, e.g., to investigate system behavior.

[0073] In some examples, the principle according to the disclosure can provide hardware for simulations, e.g., using the chiplet system 10a. Since, in some examples, work can thus be carried out on "real" hardware 10a, in other examples, it is unnecessary to program a simulation in software for the elements 10a that are already available as hardware. In some examples, the principle according to the disclosure can offer advantages for the selection of chiplet SoCs, for example, for sales or development. For example, using the principle according to the disclosure, a "sample case" can be provided, e.g., for potential customers, on the basis of which different chiplet systems 10a, 10b can be flexibly configured using the principle according to the disclosure.In some examples, this makes it possible to determine and / or show relatively accurately what properties a desired chiplet configuration can have or what performance it provides, or how, for example, an offer from different chiplets 11 , 12, 13, ... can be combined.

[0074] In some examples, the principle according to the disclosure can make it possible to provide a comparatively large variety of variants for chiplet systems 10a. For example, if one assumes that three different chiplets 11, 12, 13 can be combined for a chiplet system 10a, and further assumes that there are ten different possibilities, e.g., types (CPU, RAM, accelerator, etc.) for each of the three chiplets 11, 12, 13, then in the present example, for example, already different

[0075] Configurations are possible. It is readily apparent that with conventional approaches, which rely on actually maintaining different physical chiplet systems or SOCs, it is hardly possible to offer a comparable variety of variants as is possible in some examples when applying the principle according to the disclosure.

Claims

Claims 1. Method, for example a computer-implemented method, for processing information associated with multiple chiplets (11 , 12, 13, ...), comprising: managing (100) configuration information (l-CFG) for at least one chiplet system (10a) comprising multiple chiplets (11 , 12, 13, ...), configuring (102) the multiple chiplets (11 , 12, 13, ...) to the chiplet system (10a) based on at least a part (I-CFG-10a) of the configuration information (l-CFG).

2. The method of claim 1, wherein managing (100) the configuration information (l-CFG) comprises at least one of the following elements: a) storing (100a) the configuration information (l-CFG), or b) receiving (100b) the configuration information (l-CFG), or e) copying (100c) the configuration information (l-CFG), or d) generating (100d) the configuration information (l-CFG), or e) sending (100e) the configuration information (l-CFG).

3. A method according to at least one of claims 1 to 2, wherein the configuration (102) of the multiple chiplets (11, 12, 13, ...) comprises at least one of the following elements: a) establishing (102a) data connections (DV-10a) between the, for example, interconnecting (102b) the multiple chiplets (11, 12, 13, ...), for example according to at least one part (l-CFG-10a) of the configuration information (l-CFG), or b) establishing (102c) at least one data connection (DV-10a-ext) between at least one component, for example at least one chiplet (11, 12, 13, ...), of the chiplet system (10a) and at least one device (20), for example, external with respect to the chiplet system (10a).

4. Method according to at least one of the preceding claims, wherein at least one of the several chiplets (11, 12, 13, ...) has at least one which includes or represents the following elements: a) Processor (PROC), for example, processor core, or b) Memory (MEM), or c) Graphics Processor (GPU), for example, GPU, or d) Accelerator Device (ACC), for example, computational accelerator and / or AI accelerator, or e) Encoder (COD) and / or Decoder (DEC), for example, codec (CODEC).

5. Method according to at least one of the preceding claims, comprising: operating (105) the chiplet system (10a).

6. The method of claim 5, wherein the operation (105) of the chiplet system (10a) comprises at least one of the following elements: a) controlling (105a), for example activating and / or deactivating, an electrical power supply (EV-10a) for at least one chiplet, or b) controlling (105b) a data flow (DF-10a) between at least one chiplet and at least one further component, for example at least one further chiplet or an external device (20), or c) determining (105c), for example acquiring, information (l-BETR) regarding an operation of the chiplet system (10a).

7. Method according to at least one of the preceding claims, comprising: receiving (110) control information (1-CTRL), for example from an external device (20), optionally controlling (112) at least one aspect, for example the operation, of the chiplet system (10a) based at least on the control information (1-CTRL).

8. Method according to at least one of the preceding claims, comprising: determining (120) information (l-BETR') regarding an operation of the chiplet system (10a), sending (122) at least a part of the information (l-BETR'), for example to an external device (20).

9. Device (200; E1) for carrying out the method according to at least one of the preceding claims.

10. System (1000) comprising at least one device (200; E1) according to claim 9 and a plurality of chiplets (11 , 12, 13; 11a, 11b, ..., 15e).

11. System (1000) according to claim 10, comprising a device (20), for example external with respect to the chiplets, for example a computer, for example a personal computer, for example a host system (E2).

12. System (1000) according to claim 10 or 11, comprising at least one virtual machine (E3, E4, ...), wherein, for example, the at least one virtual machine (E3, E4, ...) is configured to exchange information with at least one chiplet of the plurality of chiplets (11, 12, 13; 11a, 11b, ..., 15e) and / or with the device (200; E1).

13. Computer-readable storage medium (SM) comprising instructions (PRG) which, when executed by a computer (202), cause it to execute the method according to at least one of claims 1 to 8.

14. Computer program (PRG) comprising instructions which, when the program (PRG) is executed by a computer (202), cause it to execute the method according to at least one of claims 1 to 8.

15. Data carrier signal (DCS) that transmits and / or characterizes the computer program (PRG) according to claim 14.

16. Use (300) of the method according to at least one of claims 1 to 8 and / or the device (200) according to claim 9 and / or the system (1000) according to at least one of claims 10 to 12 and / or the computer-readable storage medium (SM) according to claim 13 and / or the computer program (PRG) according to claim 14 and / or the data carrier signal (DCS) according to claim 15 for at least one of the following elements: a) providing (301), for example, flexibly and / or dynamically providing, at least one chiplet system (10a, 10b), or b) dynamically interconnecting (302) several chiplets (11, 12, 13, ...) to form a chiplet system (10a), or e) testing (303) a configuration comprising several chiplets (11, 12, 13, ...), or d) testing (304) software for a chiplet system, or e) reducing (305) the effort and / or costs associated with a hardware prototype, f) providing (306) samples for chiplet systems, or f) providing (307) a, for example, at least partially virtual systems on a chip, system on chip.

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