Semiconductor device

Abstract

The present invention provides a semiconductor device capable of multiplication including positive or negative numbers or 0. The semiconductor device includes first to third cells and can multiply w and x. In addition, w can be expressed by two parameters wp and wn, and x is a number expressed by two parameters xp and xn. w p is held in the first cell, and wn is held in the second cell. Furthermore, by flowing currents of the amounts corresponding to xp and xn respectively to the third cell, a voltage corresponding to xp and a voltage corresponding to xn can be applied to each of the first cell and the second cell. Thus, in the first cell, calculation of wp × xp and wp × xn is performed, and in the second cell, calculation of wn × xp and wn × xn is performed. When w × x is positive, a current corresponding to wp × xp or wn × xn flows to a first wiring, and when w × x is negative, a current corresponding to wp × xn or wn × xp flows to a second wiring.

Description

Semiconductor Devices

[0001] One embodiment of the present invention relates to a semiconductor device.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. The technical field of the invention disclosed in this specification relates to an object, an operating method, or a manufacturing method. Alternatively, one embodiment of the present invention relates to a process, a machine, manufacture, or a composition of matter. Therefore, specific examples of the technical field of one embodiment of the present invention disclosed in this specification include semiconductor devices, display devices (including liquid crystal display devices), light-emitting devices, power storage devices, imaging devices, memory devices, processing devices, signal processing devices, sensors, arithmetic devices (including processors), electronic devices, systems, driving methods thereof, manufacturing methods thereof, and inspection methods thereof.

[0003] Currently, the development of integrated circuits that mimic the workings of the human brain is actively progressing. Such integrated circuits incorporate the workings of the brain as electronic circuits, and have circuits that mimic the "neurons" and "synapses" of the human brain. For this reason, such integrated circuits are sometimes called "neuromorphic," "brainmorphic," or "brain-inspired." Such integrated circuits have a non-von Neumann architecture, and are expected to be able to perform parallel processing with extremely low power consumption compared to von Neumann architectures, which consume more power as processing speed increases.

[0004] An information processing model that mimics a neural network having "neurons" and "synapses" is called an artificial neural network (ANN). For example, Non-Patent Documents 1 and 2 disclose a computing device that configures an artificial neural network using an SRAM (Static Random Access Memory).

[0005] There are also attempts to use a computing device that configures an artificial neural network, for example, to correct an image displayed on a display device. For example, Patent Document 1 discloses a display device that uses a computing device that configures an artificial neural network to adjust the brightness, color tone, etc. of a displayed image to suit the preferences of the viewer.

[0006] JP 2018-36639 A

[0007] M. Kang et al., "IEEE Journal of Solid-State Circuits", 2018, Volume 53, No. 2, pp. 642-655. J. Zhang et al., "IEEE Journal of Solid-State Circuits", 2017, Volume 52, No. 4, pp. 915-924. Takashi Koida, "High-Mobility Transparent Conductive Film", National Institute of Advanced Industrial Science and Technology, AIST Photovoltaic Power Generation Research Results Report 2019, Internet <URL: https: / / unit.aist.go.jp / jp / rpd-envene / PV / ja / results / 2019 / oral / T13. pdf>

[0008] There are various models of artificial neural networks. For example, a model called a convolutional neural network (CNN) is used in image analysis. A convolutional neural network is a type of artificial neural network that exhibits excellent performance in the field of image recognition, but the amount of calculation is determined by factors such as the image resolution and the filter size. Specifically, for example, the higher the image resolution, the larger the filter size, or the smaller the stride, the greater the amount of calculation in the convolutional neural network, which tends to result in longer processing times by the computing device. Furthermore, the greater the amount of calculation, the higher the power consumption of the computing device.

[0009] In addition, in a convolutional neural network, feature extraction is performed for each of the divided images using the same filter. Since the filter may contain not only positive numbers but also negative numbers and / or 0, it is preferable that the above-mentioned calculation device is capable of not only calculations between positive numbers but also calculations containing negative numbers and / or 0.

[0010] Furthermore, in the case of a convolutional neural network, multiple filters are frequently read from a memory circuit or the like. Because the power consumption of both the read operation and the data transmission operation of the filters and the like is high, it is desirable for the arithmetic circuit that performs the calculations of the convolutional neural network to have a configuration called in-memory computing, which has a function of retaining the filter value, which is a multiplier, for a long period of time in addition to the calculation function. It is also desirable to have a configuration that reduces the number of data transmission operations such as files.

[0011] An object of one embodiment of the present invention is to provide a semiconductor device capable of performing an operation including positive or negative numbers or 0. Another object of one embodiment of the present invention is to provide a semiconductor device with reduced power consumption. Another object of one embodiment of the present invention is to provide a semiconductor device that can hold a multiplier used in an operation for a long period of time. Another object of one embodiment of the present invention is to provide a semiconductor device that can multiply one multiplier by each of a plurality of multiplicands at once. Another object of one embodiment of the present invention is to provide a novel semiconductor device. Another object of one embodiment of the present invention is to provide an electronic device including the above-described semiconductor device.

[0012] Note that the problem of one embodiment of the present invention is not limited to the above problem. The above problem does not preclude the existence of other problems. Note that the other problems are problems not mentioned in this section, which will be described below. Problems not mentioned in this section can be derived by a person skilled in the art from the description in the specification or drawings, and can be appropriately extracted from these descriptions. Note that one embodiment of the present invention solves at least one of the above problem and other problems, and does not necessarily solve all of the above problem and other problems.

[0013] First, consider the case where the first data w is multiplied by the second data x. The first data w is a positive or negative number or 0, and similarly, the second data x is a positive or negative number or 0. The first data w can be expressed by two parameters w ｐ And lol ｎ Similarly, two parameters x can be defined to represent the second data x. ｐ and x ｎ In this specification, two parameters w ｐ and w ｎ These two parameters x may be referred to as the first value and the second value, respectively. ｐ and x ｎ These may be referred to as the third value and the fourth value, respectively.

[0014] Specifically, when the first data w is positive (w ｐ , w ｎ ) = (w, 0), and when w is negative, (w ｐ , w ｎ ) = (0, -w), and when w is 0, (w ｐ , w ｎ ) = (0, 0). Similarly, when the second data x is positive, (x ｐ , x ｎ ) = (x, 0), and when x is negative, (x ｐ , x ｎ ) = (0, -x), and when x is 0, (x ｐ , x ｎ ) = (0,0).

[0015] Also, w ｐ ×xｐ And, lol ｐ ×x ｎ And, lol ｎ ×x ｐ And, lol ｎ ×x ｎ Here, when the first data w is a positive or negative number and the second data x is also a positive or negative number, w ｐ ×x ｐ And, lol ｐ ×x ｎ And, lol ｎ ×x ｐ And, lol ｎ ×x ｎ In each of the above, one of the first data w and the second data x is w×x or -w×x, and the remaining three are 0. Also, when one or both of the first data w and the second data x is 0, w ｐ ×x ｐ And, lol ｐ ×x ｎ And, lol ｎ ×x ｐ And, lol ｎ ×x ｎ and are all 0.

[0016] In particular, ｐ ×x ｐ Or w ｎ ×x ｎ One of them is w×x, and w ｐ ×x ｐ Or w ｎ ×x ｎ The other side of w ｐ ×x ｎ And, lol ｎ ×x ｐ When each of w and x is 0, the multiplication result of the first data w and the second data x is a positive number. ｎ ×x ｐ Or w ｐ ×x ｎ One of the two is -w × x, and w ｎ ×x ｐ Or w ｐ ×x ｎ The other side of w ｐ ×x ｐ And, lol ｎ ×x ｎWhen each of w and x is 0, the multiplication result of the first data w and the second data x is a negative number. ｐ ×x ｐ And, lol ｐ ×x ｎ And, lol ｎ ×x ｐ And, lol ｎ ×x ｎ If both and are 0, then w×x is regarded as 0.

[0017] w ｐ ×x ｐ And, lol ｐ ×x ｎ And, lol ｎ ×x ｐ And, lol ｎ ×x ｎ Consider the circuit configuration for performing the operations of and. ｐ And lol ｎ In order to handle this, the calculation cell for the calculation is w ｐ a first cell holding w ｎ and a second cell for holding w ｐ x ｐ and x ｎ Since and are multiplied separately, the first cell contains w ｐ ×x ｐ and the hold node corresponding to the operation of w ｐ ×x ｎ and the hold node corresponding to the operation of are required. ｎ x ｐ and x ｎ Since and are multiplied separately, the second cell contains w ｎ ×x ｐ and the hold node corresponding to the operation of w ｎ ×x ｎ The hold nodes corresponding to the operations of x and x for the first and second cells are required. ｐ and x ｎ The inputs of and are made via capacitance elements. ｐ ×x ｐ The holding node corresponding to the operation of x ｐ A capacitance element for the input of w is connected. ｐ×x ｎ The holding node corresponding to the operation of x ｎ In the second cell, a capacitance element for the input of w ｎ ×x ｐ The holding node corresponding to the operation of x ｐ A capacitance element for the input of w is connected. ｎ ×x ｎ The holding node corresponding to the operation of x ｎ The first cell is connected to a capacitance element for the input of w ｐ ×x ｐ a first wiring for outputting w ｐ ×x ｎ and a second wiring for outputting w ｎ ×x ｐ a second wiring for outputting w ｎ ×x ｎ and a first wiring for outputting

[0018] A specific configuration of one embodiment of the present invention will be described below.

[0019] (1) One embodiment of the present invention is a semiconductor device including first to third cells. The first cell includes first to sixth transistors, a first capacitor, and a second capacitor. The second cell includes seventh to twelfth transistors, a third capacitor, and a fourth capacitor. The third cell includes thirteenth to eighteenth transistors, a fifth capacitor, and a sixth capacitor.

[0020] The first terminal of the first transistor is electrically connected to the gate of the third transistor and the first terminal of the first capacitance element, the second terminal of the first transistor is electrically connected to the first terminal of the second transistor, the gate of the fifth transistor and the first terminal of the second capacitance element, the first terminal of the third transistor is electrically connected to the first terminal of the fourth transistor, and the first terminal of the fifth transistor is electrically connected to the first terminal of the sixth transistor.

[0021] The first terminal of the seventh transistor is electrically connected to the gate of the ninth transistor and the first terminal of the third capacitance element, the second terminal of the seventh transistor is electrically connected to the first terminal of the eighth transistor, the gate of the eleventh transistor and the first terminal of the fourth capacitance element, the first terminal of the ninth transistor is electrically connected to the first terminal of the tenth transistor, and the first terminal of the eleventh transistor is electrically connected to the first terminal of the twelfth transistor.

[0022] A first terminal of the thirteenth transistor is electrically connected to the gate of the fifteenth transistor and the first terminal of the fifth capacitance element, a second terminal of the thirteenth transistor is electrically connected to the first terminal of the fourteenth transistor, the gate of the seventeenth transistor, and the first terminal of the sixth capacitance element, a first terminal of the fifteenth transistor is electrically connected to the first terminal of the sixteenth transistor, and a first terminal of the seventeenth transistor is electrically connected to the first terminal of the eighteenth transistor.

[0023] The second terminal of the second transistor, the second terminal of the fourth transistor, and the second terminal of the twelfth transistor are each electrically connected to the first wiring. The second terminal of the sixth transistor, the second terminal of the eighth transistor, and the second terminal of the tenth transistor are each electrically connected to the second wiring. The second terminal of the fourteenth transistor, the second terminal of the sixteenth transistor, the second terminal of the first capacitance element, the second terminal of the third capacitance element, and the second terminal of the fifth capacitance element are each electrically connected to the third wiring. The second terminal of the eighteenth transistor, the second terminal of the second capacitance element, the second terminal of the fourth capacitance element, and the second terminal of the sixth capacitance element are each electrically connected to the fourth wiring. The gate of the first transistor, the gate of the second transistor, the gate of the seventh transistor, the gate of the eighth transistor, the gate of the thirteenth transistor, and the gate of the fourteenth transistor are each electrically connected to the fifth wiring.

[0024] (2) Alternatively, according to one embodiment of the present invention, in the above (1), a gate of the fourth transistor and a gate of the tenth transistor may be electrically connected to a sixth wiring, and a gate of the sixth transistor and a gate of the twelfth transistor may be electrically connected to a seventh wiring.

[0025] (3) Alternatively, according to one aspect of the present invention, in the above (1), the channel length of one or more selected from the first transistor, the second transistor, the seventh transistor, the eighth transistor, the thirteenth transistor, and the fourteenth transistor may be longer than the channel length of each of the third to sixth transistors, the ninth to twelfth transistors, and the fifteenth to eighteenth transistors. Also, in the above (1), the channel width of one or more selected from the third to sixth transistors, the ninth to twelfth transistors, and the fifteenth to eighteenth transistors may be longer than the channel width of each of the first transistor, the second transistor, the seventh transistor, the eighth transistor, the thirteenth transistor, and the fourteenth transistor.

[0026] (4) Alternatively, in one embodiment of the present invention, in any one of (1) to (3), each of the transistors included in the first cell to the third cell may include an oxide semiconductor in a channel formation region, and the oxide semiconductor may contain indium.

[0027] (5) In one embodiment of the present invention, in any one of (1) to (3), each of the transistors included in the first cell to the third cell may include an oxide semiconductor in a channel formation region. In particular, the oxide semiconductor preferably includes one or more elements selected from indium, zinc, and an element M.

[0028] The element M is one or more selected from aluminum, gallium, silicon, yttrium, tin, copper, vanadium, chromium, manganese, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, calcium, strontium, barium, cobalt, and antimony.

[0029] (6) Alternatively, in one embodiment of the present invention, the device according to (4) or (5) may include first to fourth driver circuits.

[0030] In particular, the first driving circuit supplies a first value w to the first cell via the first wiring. ｐ and a function of supplying a first current according to a second value w to the second cell via a second wiring. ｎ The second driving circuit preferably has a function of supplying a second current according to a third value x to the third cell via a third wiring. ｐ or a reference current according to the reference data r; and a function of supplying a fourth value x to the third cell via a fourth wiring. ｎ The third driving circuit preferably has a function of supplying a fourth current or a reference current according to the first value w ｐ and write the second value w ｎ and to write reference data r to the third cell, it is preferable that the fifth wiring has a function of transmitting a selection signal to the fifth wiring.

[0031] The fourth driving circuit also includes a current flowing between the first terminal of the third transistor and the first wiring, ｐ ×x ｐ / r, and a fifth current flowing between the first terminal of the eleventh transistor and the first wiring, ｎ ×x ｎ / r, and a function of acquiring a first sum current of the sixth current and the sixth current flowing between the first terminal of the fifth transistor and the second wiring, ｐ ×x ｎ / r, and a seventh current flowing between the first terminal of the ninth transistor and the second wiring, w ｎ ×x ｐIt is preferable that the control circuit has a function of acquiring a second sum current of the eighth current corresponding to / r and a function of generating a difference current between the first sum current and the second sum current.

[0032] The amounts of the first to eighth currents and the reference current are the amounts of current in the subthreshold regions of the third, fifth, ninth, eleventh, fifteenth, and seventeenth transistors, respectively.

[0033] (7) Another embodiment of the present invention is a semiconductor device including a first cell, a second cell, a third cell, a first driver circuit, and a second driver circuit. The first driver circuit transmits a first value w ｐ and a function of supplying a current of a quantity corresponding to a second value w to the second cell via the second wiring. ｎ The second driving circuit has a function of supplying a current of an amount corresponding to the reference data r or the third value x to the third cell via the third wiring. ｐ and a function of supplying a current of an amount corresponding to the reference data r or the fourth value x to the third cell via the fourth wiring. ｎ and a function of passing a current in an amount corresponding to the

[0034] The first cell contains the first value w ｐ and a function of changing the amount of current flowing through the third wiring from the amount according to the reference data r to the third value x ｐ When the potential of the third wiring changes to an amount corresponding to w ｐ ×x ｐ / r, and a function of generating a first current of an amount corresponding to the reference data r and flowing it through the first wiring, and a function of changing the amount of current flowing through the fourth wiring from an amount corresponding to the reference data r to a fourth value x ｎ When the potential of the fourth wiring changes to an amount corresponding to w ｐ ×x ｎ / r and a function of generating a second current in an amount corresponding to the second wiring.

[0035] The second cell contains the second value w ｎ and a function of changing the amount of current flowing through the third wiring from the amount according to the reference data r to the third value x ｐWhen the potential of the third wiring changes to an amount corresponding to w ｎ ×x ｐ / r, and a function of generating a third current of an amount corresponding to the reference data r and flowing it through the second wiring, and a function of changing the amount of current flowing through the fourth wiring from an amount corresponding to the reference data r to a fourth value x ｎ When the potential of the fourth wiring changes to an amount corresponding to w ｎ ×x ｎ / r and causing the fourth current to flow through the first wiring.

[0036] The third cell has a function of holding the reference data r and a function of changing the amount of current flowing through the third wiring from an amount corresponding to the reference data r to a third value x ｐ When the potential of the third wiring changes to an amount corresponding to x ｐ and a function of generating a fifth current of an amount corresponding to the reference data r and a function of generating a fourth current of an amount corresponding to the reference data r. ｎ When the potential of the fourth wiring changes to an amount corresponding to x ｎ and generating a sixth current in an amount corresponding to the sixth current.

[0037] (8) Alternatively, according to one aspect of the present invention, in the above (7), the first cell may include a first transistor and a second transistor, the second cell may include a third transistor and a fourth transistor, and the third cell may include a fifth transistor and a sixth transistor.

[0038] In particular, it is preferable that the first transistor has a function of passing a first current in the subthreshold region, the second transistor has a function of passing a second current in the subthreshold region, the third transistor has a function of passing a third current in the subthreshold region, and the fourth transistor has a function of passing a fourth current in the subthreshold region.

[0039] The fifth transistor is connected to the reference data r or the third value x ｐ and has a function of flowing a current in the subthreshold region in response to the reference data r or the fourth value x ｎIt is preferable that the gate insulating film has a function of flowing a current in the subthreshold region in response to the above-mentioned condition.

[0040] (9) Alternatively, according to one aspect of the present invention, in the above-described (8), a third driver circuit may be provided. In addition, it is preferable that each of the first cell, the second cell, and the third cell includes a seventh transistor.

[0041] The third driving circuit drives the first cell with a first value w ｐ is written to the second cell, and the second value w ｎ is written to the first cell and the reference data r is written to the third cell, the seventh transistor preferably has a function of transmitting a selection signal to each of the first cell, the second cell, and the third cell via the fifth wiring. Furthermore, the seventh transistor preferably has a function of turning on when a selection signal is applied to its gate.

[0042] (10) In another embodiment of the present invention, in the above (9), each of the first to seventh transistors may include an oxide semiconductor in a channel formation region. In particular, the oxide semiconductor preferably contains indium.

[0043] (11) Alternatively, in one embodiment of the present invention, in the above-described (10), the oxide semiconductor may contain one or more elements selected from indium, zinc, and an element M.

[0044] The element M is one or more selected from aluminum, gallium, silicon, yttrium, tin, copper, vanadium, chromium, manganese, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, calcium, strontium, barium, cobalt, and antimony.

[0045] (12) Alternatively, according to one aspect of the present invention, in the above (10) or (11), a fourth drive circuit may be provided. In particular, the fourth drive circuit preferably has a function of generating a seventh current that is the difference between the amount of current flowing through the first wiring and the amount of current flowing through the second wiring.

[0046] As in the configuration of (1) above, in the first cell, the connection point between the first terminal of the first capacitance element and the gate of the third transistor is set as the first holding node, the connection point between the first terminal of the second capacitance element and the gate of the fifth transistor is set as the second holding node, and the first holding node and the second holding node are connected via the first transistor, so that when the first transistor is in an on state, the same w ｐ When the first transistor is in an off state, the first and second holding nodes are written with w ｐ can be held.

[0047] Also, the third transistor and the fifth transistor are each operated in the subthreshold region, and the same w ｐ When the capacitance is held at the second terminal of the first capacitance element and the second terminal of the second capacitance element, ｐ and x ｎ By applying the corresponding potentials to the third and fifth transistors, ｐ ×x ｐ And, lol ｐ ×x ｎ A subthreshold current corresponding to w ｐ ×x ｐ A subthreshold current corresponding to w flows through the first wiring. ｐ ×x ｎ A subthreshold current corresponding to the voltage flows through the second wiring.

[0048] Similarly, in the second cell, the connection point between the first terminal of the third capacitance element and the gate of the ninth transistor is set as a third holding node, the connection point between the first terminal of the fourth capacitance element and the gate of the eleventh transistor is set as a fourth holding node, and the third holding node and the fourth holding node are connected via the seventh transistor. When the seventh transistor is in an on state, the same w ｎWhen the seventh transistor is in an off state, the third and fourth holding nodes can be written with w ｎ can be held.

[0049] Also, the ninth transistor and the eleventh transistor are each operated in the subthreshold region, and the same w ｎ When the capacitance is held at the second terminal of the third capacitance element and the second terminal of the fourth capacitance element, ｐ and x ｎ By applying the corresponding potentials to the ninth and eleventh transistors, ｎ ×x ｐ And, lol ｎ ×x ｎ A subthreshold current corresponding to w ｎ ×x ｐ A subthreshold current corresponding to w flows through the second wiring. ｎ ×x ｎ A subthreshold current corresponding to the voltage flows through the first wiring.

[0050] In this way, with the above configuration, w ｐ ×x ｐ And, lol ｐ ×x ｎ And, lol ｎ ×x ｐ And, lol ｎ ×x ｎ The calculations for and can be performed at the same time. ｐ ×x ｐ And, lol ｐ ×x ｎ And, lol ｎ ×x ｐ And, lol ｎ ×x ｎ From the values ​​of and , the product of the first data w and the second data x and whether the product is positive or negative can be determined.

[0051] Furthermore, with the configuration (3) above, in the on state, the amount of source-drain current of each of the third to sixth transistors, the ninth to twelfth transistors, and the fifteenth to eighteenth transistors can be made larger than the amount of source-drain current of each of the first, second, seventh, eighth, thirteenth, and fourteenth transistors. By increasing the amount of current of each of the third to sixth transistors, the ninth to twelfth transistors, and the fifteenth to eighteenth transistors, the driving speed of the semiconductor device can be increased. In other words, the multiplication speed can be increased. Furthermore, with the configuration (3) above, in the off state, the off current of each of the first, second, seventh, eighth, thirteenth, and fourteenth transistors can be made smaller than the off current of each of the third to sixth transistors, the ninth to twelfth transistors, and the fifteenth to eighteenth transistors. This allows the same multiplier written in each of the first and second holding nodes to be held for a long period of time.

[0052] According to one embodiment of the present invention, a semiconductor device capable of performing an operation including positive or negative numbers or 0 can be provided. According to one embodiment of the present invention, a semiconductor device with reduced power consumption can be provided. According to another embodiment of the present invention, a semiconductor device capable of holding a multiplier used in an operation for a long period of time can be provided. According to one embodiment of the present invention, a semiconductor device capable of multiplying one multiplier by each of a plurality of multiplicands at once can be provided. According to one embodiment of the present invention, a novel semiconductor device can be provided. According to another embodiment of the present invention, an arithmetic device including the above-described semiconductor device can be provided.

[0053] Note that the effects of one embodiment of the present invention are not limited to the above-described effects. The above-described effects do not preclude the existence of other effects. Furthermore, the other effects are effects not mentioned in this section, which will be described below. Effects not mentioned in this section can be derived by a person skilled in the art from the description in the specification or drawings, and can be extracted as appropriate from these descriptions. Note that one embodiment of the present invention has at least one of the above-described effects and other effects. Therefore, one embodiment of the present invention may not have the effects listed above in some cases.

[0054] FIG. 1 is a circuit diagram illustrating an example of the configuration of a arithmetic device. FIG. 2 is a block diagram illustrating an example of the configuration of a arithmetic device. FIGS. 3A to 3C are circuit diagrams illustrating an example of the configuration of a circuit included in the arithmetic device. FIGS. 4A to 4D are circuit diagrams illustrating an example of the configuration of a circuit included in the arithmetic device. FIG. 5 is a circuit diagram illustrating an example of the configuration of a circuit included in the arithmetic device. FIGS. 6A to 6C are circuit diagrams illustrating an example of the configuration of a circuit included in the arithmetic device. FIG. 7 is a circuit diagram illustrating an example of the configuration of a circuit included in the arithmetic device. FIG. 8 is a circuit diagram illustrating an example of the configuration of a circuit included in the arithmetic device. FIG. 9 is a timing chart illustrating an example of the operation of a circuit included in the arithmetic device. FIG. 10 is a timing chart illustrating an example of the operation of the arithmetic device. FIG. 11 is a timing chart illustrating an example of the operation of the arithmetic device. FIG. 12 is a timing chart illustrating an example of the operation of the arithmetic device. FIG. 13 is a timing chart illustrating an example of the operation of the arithmetic device. FIG. 14 is a timing chart illustrating an example of the operation of the arithmetic device. FIG. 15 is a timing chart illustrating an example of the operation of the arithmetic device. FIG. 16 is a circuit diagram illustrating an example of the configuration of a arithmetic device. FIG. 17 is a circuit diagram illustrating an example of the configuration of an arithmetic device. FIG. 18 is a circuit diagram illustrating an example of the configuration of an arithmetic device. FIG. 19 is a circuit diagram illustrating an example of the configuration of an arithmetic device. FIG. 20 is a circuit diagram illustrating an example of the configuration of an arithmetic device. FIG. 21 is a circuit diagram illustrating an example of the configuration of an arithmetic device. FIG. 22 is a circuit diagram illustrating an example of the configuration of an arithmetic device. FIG. 23 is a circuit diagram illustrating an example of the configuration of an arithmetic circuit. FIG. 24 is a circuit diagram illustrating an example of the configuration of an arithmetic circuit. FIG. 25 is a circuit diagram illustrating an example of the configuration of an arithmetic circuit. FIG. 26 is a schematic plan view showing an example of the configuration of an arithmetic circuit. FIG. 27 is a schematic plan view showing an example of the configuration of an arithmetic circuit. FIG. 28 is a schematic plan view showing an example of the configuration of an arithmetic circuit. FIG. 29 is a circuit diagram illustrating an example of the configuration of an arithmetic device. FIG. 30 is a schematic perspective view showing an example of the configuration of an arithmetic device. FIG. 31 is a block diagram showing an example of the configuration of an arithmetic device. FIG. 32 is a schematic cross-sectional view showing an example of the configuration of an arithmetic device. FIGS. 33A and 33B are schematic cross-sectional views showing example configurations of transistors. FIG. 34 is a schematic cross-sectional view showing an example of the configuration of the arithmetic unit.FIG. 35A is a plan view showing an example of the configuration of a transistor, and FIGS. 35B and 35C are cross-sectional views showing an example of the configuration of a transistor. FIG. 36 is a perspective view showing an example of the configuration of a transistor. FIG. 37A is a cross-sectional view showing an example of the configuration of a capacitor, and FIG. 37B is a plan view showing an example of the configuration of a capacitor. FIGS. 38A and 38B are diagrams illustrating the carrier concentration dependence of Hall mobility. FIG. 38C is a cross-sectional view illustrating an indium oxide film. FIGS. 39A to 39D are diagrams illustrating an example of an electronic component. FIGS. 40A and 40B are diagrams illustrating an example of an electronic device, and FIG. 40C is a diagram illustrating an example of a mainframe computer. FIG. 41 is a diagram illustrating an example of space equipment. FIG. 42 is a diagram illustrating an example of a storage system applicable to a data center. FIGS. 43A1 to 43A7 and 43B1 to 43B6 are circuit diagrams illustrating electrical connections.

[0055] (Additional Notes Related to the Present Specification) In the present specification, a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including a semiconductor element (for example, a transistor, a diode, and a photodiode), or a device having such a circuit. A semiconductor device also refers to any device that can function by utilizing semiconductor characteristics. An example of a semiconductor device is an integrated circuit. Another example of a semiconductor device is a chip equipped with an integrated circuit. Another example of a semiconductor device is an electronic component that houses a chip in a package. For example, a memory device, a display device, a light-emitting device, a lighting device, and an electronic device may themselves be a semiconductor device, or may include a semiconductor device.

[0056] In this specification, "connection" includes, for example, "electrical connection."

[0057] When the term "electrical connection" is used to define the connection relationship between circuit elements as an object, it includes, for example, "direct connection" and "indirect connection." For example, "A and B are directly connected" refers to a connection between A and B without the intervention of a circuit element (e.g., a transistor or a switch; wiring is not considered a circuit element). On the other hand, for example, "A and B are indirectly connected" refers to a connection between A and B via one or more circuit elements. Note that A, B, and C, which will be described later, represent objects such as elements, circuits, wiring, electrodes, terminals, semiconductor layers, and conductive layers.

[0058] Here, when "A and B are indirectly connected," it refers to the following connection relationship, for example. That is, assuming that a circuit is operating, if there is a time during the operation of the circuit when electrical signal transmission or potential interaction occurs between A and B, such a circuit can be defined as an entity, and "A and B are indirectly connected." Note that even if there is a time when electrical signal transmission or potential interaction does not occur between A and B, if there is a time during the operation of the circuit when electrical signal transmission or potential interaction occurs between A and B, it can be defined as "A and B are indirectly connected." Note that "A and B are indirectly connected" is a definition of the connection relationship between circuit elements as an entity. Therefore, for example, even when a power supply voltage is not supplied to a circuit and the circuit is not operating, the circuit can be defined as an entity, and "A and B are indirectly connected" (however, for example, this is limited to the case where electrical signal transmission or potential interaction occurs between A and B during the operation of the circuit when a power supply voltage is supplied to the circuit and the circuit is operating).

[0059] Specific examples of "indirect connection" are shown below. First, an example of "A and B are indirectly connected" is when A and B are connected via the source and drain of one or more transistors, as shown in FIGS. 43A1 and 43A2. Another example of "A and B are indirectly connected" is when A and B are connected via one or more switches. When "A and B are indirectly connected," it is assumed that, assuming the circuit is operating, there is at least one time when a transistor between A and B is in an on state, a conductive state, or a state in which a current can flow. Note that "A and B are indirectly connected" also includes cases where a transistor between A and B is in an off state or a non-conductive state. When "A and B are indirectly connected," if multiple transistors are connected between A and B, it is assumed that, assuming the circuit is operating, each of the multiple transistors between A and B is in an on state, a conductive state, or a state in which a current can flow at least one time. In other words, when "A and B are indirectly connected," it is not necessary for all of the multiple transistors to be in an on state, a conductive state, or a state in which current can flow simultaneously. Therefore, when "A and B are indirectly connected," it also includes cases in which the multiple transistors between A and B are in an off state or a non-conductive state at the same time or at different times. As another example, as shown in FIG. 43A3, when A and C are connected via the source and drain of transistor TrP and B and C are connected via the source and drain of transistor TrQ, it can be defined as "A and C are indirectly connected," "B and C are indirectly connected," or "A and B are indirectly connected." However, as will be described later, when a constant potential V is supplied to C from a power supply, GND, or the like, it can be said that "A and C are indirectly connected" or "B and C are indirectly connected," but it cannot be said that "A and B are indirectly connected."

[0060] While we have provided examples of cases where an "indirect connection" can and cannot be established, we will now present another example of a case where an "indirect connection" cannot be established. Even if an electrical signal exchange or potential interaction occurs between A and B during the operation of the circuit, there are exceptional cases where it cannot be said that "A and B are indirectly connected." An example of such an exceptional case is when A and B are connected via an insulator. In other words, when A and B are connected via an insulator, it cannot be said that "A and B are indirectly connected." A specific example of a case where A and B are connected via an insulator is when a capacitive element is connected between A and B, as shown in FIG. 43A4. Another example of a case where A and B are connected via an insulator is when a gate insulating film of a transistor is interposed between A and B, as shown in FIG. 43A5. In this case, it cannot be said that "A (the gate of the transistor) and B (the source or drain of the transistor) are indirectly connected."

[0061] Another example of a case where it cannot be said that "A and B are indirectly connected" is when there is no timing when an electrical signal is exchanged or when potential interaction occurs between A and B. An example of this is when, as shown in Figures 43A6 and 43A7, multiple transistors are connected via their sources and drains to the path from A to B, and a constant potential V is supplied to a node between the transistors from a power supply, GND, or the like. In this case, it cannot be said that "A and B are indirectly connected," but it is possible to say that "A and V are indirectly connected" or "B and V are indirectly connected." In addition, in Figure 43A3, if A and C are connected via the source and drain of transistor TrP, and B and C are connected via the source and drain of transistor TrQ, and a constant potential V is supplied to C from a power supply or GND, etc., the connection relationship will be the same as in Figures 43A6 and 43A7, so it cannot be said that "A and B are indirectly connected," but it can be said that "A and C are indirectly connected" or "B and C are indirectly connected."

[0062] Although an example of "indirect connection" has been given above, as an example, the definition of "indirect connection" is included in the definition of "electrical connection," so if "A and B are indirectly connected," it can also be said that "A and B are electrically connected."

[0063] Next, specific examples of "direct connection" are shown. An example of "A and B are directly connected" is when A and B are connected without any circuit element between them, as shown in FIGS. 43B1, 43B2, and 43B3. When A and B are connected to a power supply that supplies a constant potential V or to GND without any circuit element between them, as shown in FIGS. 43B4 and 43B5, it can be said that "A and B are directly connected," "A and V are directly connected," or "B and V are directly connected." It can also be said that "A and B are directly connected," when A (or B) is connected to a constant potential V via the source and drain of a transistor, as shown in FIG. 43B6. Because A and V or B and V are connected via the source and drain of a transistor, it cannot be said that they are directly connected, but rather that "A and V are indirectly connected" or "B and V are indirectly connected."

[0064] Although an example of "direct connection" has been given above, as an example, the definition of "direct connection" is included in the definition of "electrical connection," so when "A and B are directly connected," it can also be said that "A and B are electrically connected."

[0065] Note that even when independent components are shown as being connected to each other in a circuit diagram, one component may have the functions of multiple components. For example, if part of a wiring also functions as an electrode, one conductive film has the functions of both a wiring and an electrode. Therefore, in this specification, the term "connection" also includes such cases where one conductive film has the functions of multiple components.

[0066] Generally, examples of a "resistance element" include a circuit element having a resistance value higher than 0Ω, wiring having a resistance value higher than 0Ω, etc. Therefore, the "resistance element" described in this specification includes wiring, diodes, or coils having a resistance value. Therefore, the term "resistance element" can sometimes be replaced with the terms "resistance," "load," or "region having a resistance value." Conversely, the terms "resistance," "load," or "region having a resistance value" can sometimes be replaced with the term "resistance element." The resistance value can be, for example, preferably 1 mΩ or more and 10 Ω or less, more preferably 5 mΩ or more and 5 Ω or less, and even more preferably 10 mΩ or more and 1 Ω or less. In addition, for example, 1 Ω or more and 1×10 ９ It can be made smaller than Ω.

[0067] Generally, examples of "capacitance" include a circuit element having a capacitance value higher than 0 F, a region of wiring having a capacitance value higher than 0 F, and a region between a gate or back gate and a source or drain in a transistor having a capacitance value higher than 0 F. Furthermore, the terms "capacitance element," "parasitic capacitance," or "gate capacitance" may sometimes be replaced with the term "capacitance." Conversely, the term "capacitance" may sometimes be replaced with the terms "capacitance element," "parasitic capacitance," or "gate capacitance."

[0068] Furthermore, a "capacitor" (including a "capacitor" with three or more terminals) includes an insulator and a pair of conductors sandwiching the insulator. Therefore, the term "pair of conductors" in a "capacitor" can be rephrased as "pair of electrodes," "pair of conductive regions," "pair of regions," or "pair of terminals." Furthermore, the terms "one of the pair of terminals" and "the other of the pair of terminals" may be referred to as a first terminal and a second terminal, respectively. The value of the electrostatic capacitance of a capacitor can be, for example, 0.05 fF or more and 10 pF or less. Furthermore, it can be, for example, 1 pF or more and 10 μF or less.

[0069] The switches described in this specification are described as having the function of being turned on or off and controlling whether or not a current flows, or as having the function of selecting and switching the path through which a current flows.

[0070] In this specification, a "conductive state" refers to a state in which a current can flow between two input / output terminals, and a "non-conductive state" refers to a state in which the two input / output terminals are considered to be electrically disconnected. In this specification, the on state of a switch falls under the category of a "conductive state," and the off state of a switch falls under the category of a "non-conductive state." Therefore, in this specification, the "conductive state" and the "on state" of a switch are interchangeable, and the "non-conductive state" and the "off state" are interchangeable.

[0071] In addition, in this specification, the terms "conductive" or "conductive state" used when conductive layers are in direct contact with each other refer to a state in which a current can flow between the conductive layers, for example.

[0072] Furthermore, the switch may have two or more terminals for passing current in addition to the control terminal. For example, an electrical switch, a mechanical switch, or the like may be used. In other words, the switch is not limited to a specific type as long as it has the function of controlling current.

[0073] Examples of electrical switches include transistors (e.g., bipolar transistors, MOS transistors, etc.), diodes (e.g., PN diodes, PIN diodes, Schottky diodes, MIM (Metal Insulator Metal) diodes, MIS (Metal Insulator Semiconductor) diodes, and diode-connected transistors), or logic circuits combining these. When a transistor is used as a switch, the "conductive state" or "on state" of the transistor refers to a state in which a current can flow between the source electrode and the drain electrode of the transistor. The "non-conductive state" or "off state" of the transistor refers to a state in which the source electrode and the drain electrode of the transistor can be considered to be electrically disconnected. When a transistor is operated simply as a switch, the polarity (conductivity type) of the transistor is not particularly limited.

[0074] An example of a mechanical switch is a switch that uses MEMS (microelectromechanical systems) technology. This switch has a mechanically movable electrode, and the movement of the electrode controls the conductive and non-conductive states.

[0075] In this specification, a transistor has three terminals called a gate, a source, and a drain. The gate is a control terminal that controls switching between a conductive state and a non-conductive state of the transistor. The two terminals that function as a source or a drain are input / output terminals of the transistor. One of the two input / output terminals serves as a source and the other as a drain depending on the conductivity type (n-channel or p-channel) of the transistor and the level of potential applied to the three terminals of the transistor. Therefore, in this specification, the terms "source" and "drain" are sometimes interchangeable. In addition, in this specification, when describing the connection relationship of a transistor, the terms "one of the source and the drain" and "the other of the source and the drain" are used. In this specification, one of the source and the drain is sometimes referred to as a "first electrode of the transistor" or a "first terminal of the transistor," and the other of the source and the drain is sometimes referred to as a "second electrode of the transistor" or a "second terminal of the transistor." Note that, depending on the structure of a transistor, a backgate may be provided in addition to the three terminals described above. In this case, in this specification, one of the gate or back gate of the transistor may be referred to as a first gate, and the other of the gate or back gate of the transistor may be referred to as a second gate. Furthermore, for the same transistor, the terms "gate" and "back gate" may be interchangeable. Furthermore, in this specification, when a transistor has three or more gates, the respective gates may be referred to as a first gate, a second gate, a third gate, etc.

[0076] For example, an example of a transistor described herein may include a transistor with a multi-gate structure having two or more gate electrodes. The multi-gate structure allows the channel formation regions to be connected in series, resulting in a structure in which multiple transistors are connected in series. Therefore, the multi-gate structure can reduce the off-state current and improve the transistor's breakdown voltage (reliability). Alternatively, the multi-gate structure allows for a voltage-current characteristic with a flat slope to be obtained when operating in the saturation region, since the current between the drain and source does not change significantly even when the voltage between the drain and source changes. By utilizing the voltage-current characteristic with a flat slope, an ideal current source circuit or an active load with a very high resistance value can be realized. As a result, a differential circuit or a current mirror circuit with excellent characteristics can be realized.

[0077] Generally, the threshold voltage of a transistor is a voltage between the subthreshold region (weak inversion region) and the strong inversion region, and can be said to be the voltage at which switching between the subthreshold region and the strong inversion region occurs. In addition, as an example of a method for measuring the threshold voltage, Id is calculated based on the Id (source-drain current) - Vgs (gate-source voltage) characteristics. １／２ -Vgs characteristics are plotted, and Id １／２ Id on the tangent line where the slope of the -Vgs characteristic is maximum １／２ As another example, in the Id-Vgs characteristic where the drain potential is 1.2 V, Id=1.0×10 −１２ A is set as the threshold voltage.

[0078] In this specification, the term "operation in the subthreshold region" in a transistor refers to a case where the gate-source voltage of the transistor is lower than the threshold voltage, more preferably a case where the drain current of the transistor increases exponentially with the gate-source voltage. In this case, the term also refers to a case where the gate potential, source potential, and drain potential applied to the transistor are appropriately applied so that the transistor operates in the subthreshold region.

[0079] In this specification, the subthreshold region refers to a region in a graph showing the Id-Vgs characteristics of a transistor where Vgs is lower than the threshold voltage. Alternatively, the subthreshold region refers to a region where current flows due to carrier diffusion, which deviates from the gradual channel approximation (a model that only considers drift current). Alternatively, the subthreshold region refers to a region where Id increases exponentially with increasing Vgs. Alternatively, the subthreshold region includes regions that can be considered as the regions described above.

[0080] In this specification, the source-drain current when a transistor operates in the subthreshold region is referred to as the “subthreshold current.” The subthreshold current increases exponentially with the gate-source voltage, regardless of the drain potential.

[0081] In general, the off-state current of a transistor may refer to a source-drain current that flows when the gate-source voltage Vgs of the transistor is lower than the threshold voltage. Therefore, the off-state current may include a subthreshold current. Note that, in this specification, since a circuit driven by a subthreshold current is discussed, the off-state current will be described as a current lower than the subthreshold current unless otherwise specified.

[0082] Furthermore, even when a single circuit element is shown on a circuit diagram, the circuit element may include multiple circuit elements. For example, when a circuit diagram shows one resistor, this includes two or more resistors connected in series. For example, when a circuit diagram shows one capacitance element, this includes two or more capacitance elements connected in parallel. For example, when a circuit diagram shows one transistor, this includes two or more transistors connected in series, with the gates of the transistors connected to each other. Similarly, when a circuit diagram shows one switch, this includes two or more transistors connected in series or in parallel, with the gates of the transistors connected to each other.

[0083] In this specification, a node can be referred to as a terminal, a wiring, an electrode, a conductive layer, a conductor, an impurity region, etc. depending on the circuit configuration and device structure. A terminal, a wiring, etc. can also be referred to as a node.

[0084] Furthermore, the selector described in this specification may be, for example, a circuit having multiple input terminals and one output terminal, selecting one of the multiple input terminals, and establishing a conductive state between the selected input terminal and the one output terminal. In other words, the selector described in this specification may be a circuit that selects one of the input signals input to each of the multiple input terminals and outputs the selected input signal to the output terminal. Alternatively, the selector described in this specification may be, for example, a circuit having multiple output terminals and one input terminal, selecting one of the multiple output terminals, and establishing a conductive state between the selected output terminal and the one input terminal. In other words, the selector may be a circuit that selects one of the multiple output terminals and outputs the input signal input to the input terminal to the selected output terminal. In other words, the selector may refer to a multiplexer or a demultiplexer. In particular, when inputting or outputting an analog potential or an analog current, the selector may refer to an analog multiplexer or an analog demultiplexer.

[0085] Furthermore, in this specification, the terms "voltage" and "potential" can be interchanged as appropriate. "Voltage" refers to the potential difference from a reference potential. For example, if the reference potential is the ground potential (earth potential), then "voltage" can be interchanged with "potential." Note that ground potential does not necessarily mean 0 V. Furthermore, potential is relative, and as the reference potential changes, the potential applied to wiring, the potential applied to a circuit, etc., the potential output from a circuit, etc. also changes.

[0086] Furthermore, in this specification, the terms "high-level potential" and "low-level potential" do not mean specific potentials. For example, when two wirings are both described as "functioning as wirings that supply a high-level potential," the high-level potentials applied to the two wirings may be different from each other. Similarly, when two wirings are both described as "functioning as wirings that supply a low-level potential," the low-level potentials applied to the two wirings may be different from each other.

[0087] Furthermore, "current" refers to the phenomenon of charge transfer (electrical conduction). For example, the statement "electrical conduction of a positively charged body is occurring" can be rephrased as "electrical conduction of a negatively charged body is occurring in the opposite direction." Therefore, in this specification, unless otherwise specified, "current" refers to the phenomenon of charge transfer (electrical conduction) associated with the movement of carriers. Examples of carriers here include electrons, holes, anions, cations, and complex ions, and the carriers differ depending on the system through which the current flows (e.g., semiconductor, metal, electrolyte, and vacuum). Furthermore, the "direction of current" in wiring, etc., refers to the direction in which positively charged carriers move and is expressed as a positive current amount. In other words, the direction in which negatively charged carriers move is opposite to the direction of current and is expressed as a negative current amount. Therefore, in this specification, unless otherwise specified regarding the positive / negative sign of the current (or the direction of current), the statement "current flows from element A to element B" can be rephrased as "current flows from element B to element A." Furthermore, the statement "current is input to element A" can be rephrased as "current is output from element A."

[0088] Furthermore, in this specification, ordinal numbers such as "first," "second," and "third" are used to avoid confusion between components. Therefore, they do not limit the number of components. Furthermore, they do not limit the order of components, such as the order of processes or stacking. Furthermore, even if a term does not have an ordinal number in this specification, an ordinal number may be added in the claims to avoid confusion between components. Furthermore, even if a term has an ordinal number in this specification, a different ordinal number may be added in the claims. Furthermore, even if a term has an ordinal number in this specification, the counter may be omitted in the claims. For example, a component with an ordinal number "first" in one embodiment of this specification may be a component with a different ordinal number such as "second" or "third" in other embodiments or claims. Furthermore, for example, a component with an ordinal number "first" in one embodiment of this specification may be omitted in other embodiments or claims.

[0089] Furthermore, in this specification, terms indicating position, such as "above" and "below," may be used for convenience in describing the positional relationship between components with reference to the drawings. Furthermore, the positional relationship between components changes as appropriate depending on the direction in which each configuration is depicted. Therefore, the terms are not limited to those described in the specification, etc., and can be rephrased appropriately depending on the situation. For example, the expression "insulator located on the upper surface of a conductor" can be rephrased as "insulator located on the lower surface of a conductor" by rotating the orientation of the drawing by 180 degrees.

[0090] Furthermore, the terms "above" and "below" do not limit the positional relationship of components to being directly above or below and in direct contact with each other. For example, the expression "electrode B on insulating layer A" does not require that electrode B be formed in direct contact with insulating layer A, and does not exclude the inclusion of other components between insulating layer A and electrode B. Similarly, the expression "electrode B above insulating layer A" does not require that electrode B be formed in direct contact with insulating layer A, and does not exclude the inclusion of other components between insulating layer A and electrode B. Similarly, the expression "electrode B below insulating layer A" does not require that electrode B be formed in direct contact below insulating layer A, and does not exclude the inclusion of other components between insulating layer A and electrode B.

[0091] Furthermore, in this specification, terms such as "row" and "column" may be used to describe components arranged in a matrix and their positional relationships. Furthermore, the positional relationships between components change as appropriate depending on the direction in which each component is depicted. Therefore, the terms are not limited to those used in the specification, and may be rephrased appropriately depending on the situation. For example, the expression "row direction" may be rephrased as "column direction" by rotating the orientation of the drawing by 90 degrees.

[0092] Furthermore, in this specification, the terms "film" and "layer" can be interchanged depending on the situation. For example, the term "conductive layer" can be changed to the term "conductive film". Or, for example, the term "insulating film" can be changed to the term "insulating layer". Or, in some cases or depending on the situation, the terms "film" and "layer" can be replaced with other terms without being used. For example, the term "conductive layer" or "conductive film" can be changed to the term "conductor". Or, for example, the term "insulating layer" or "insulating film" can be changed to the term "insulator".

[0093] Furthermore, in this specification, terms such as "electrode," "wiring," and "terminal" do not limit the functionality of these components. For example, an "electrode" may be used as part of a "wiring," and vice versa. Furthermore, terms such as "electrode" or "wiring" include cases where multiple "electrodes" or "wirings" are integrally formed. Furthermore, for example, a "terminal" may be used as part of a "wiring" or "electrode," and vice versa. Furthermore, the term "terminal" includes cases where one or more selected from "electrode," "wiring," and "terminal" are integrally formed. Therefore, for example, an "electrode" can be part of a "wiring" or "terminal," and a "terminal" can be part of a "wiring" or "electrode." Furthermore, the terms "electrode," "wiring," and "terminal" may be replaced with the term "region" in some cases.

[0094] Furthermore, in this specification, terms such as "wiring," "signal line," and "power line" may be interchangeable depending on the circumstances. For example, the term "wiring" may be changed to the term "signal line." For example, the term "wiring" may be changed to the term "power line." Vice versa, terms such as "signal line" or "power line" may be changed to the term "wiring." A term such as "power line" may be changed to the term "signal line." Vice versa, a term such as "signal line" may be changed to the term "power line." Furthermore, a term "potential" applied to a wiring may be changed to the term "signal" depending on the circumstances. Vice versa, a term such as "signal" may be changed to the term "potential."

[0095] In addition, timing charts may be used in this specification to explain an operation method of a semiconductor device. The timing charts used in this specification illustrate ideal operation examples, and the periods, magnitudes, and timings of signals (e.g., potentials or currents) described in the timing charts are not limited unless otherwise specified. The magnitudes and timings of signals (e.g., potentials or currents) input to each wiring (including a node) in the timing charts described in this specification may be changed depending on the situation. For example, even if two periods are shown at equal intervals in a timing chart, the lengths of the two periods may be different. For example, even if one period is shown as long and the other as short, the lengths of the two periods may be equal, or one period may be short and the other period may be long. For example, to clearly illustrate the timing charts, two or more overlapping signals may be intentionally shifted.

[0096] In this specification, a metal oxide refers to an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as oxide semiconductors or simply as OSs), and the like. For example, when a metal oxide is contained in a channel formation region of a transistor, the metal oxide may be referred to as an oxide semiconductor. In other words, when a metal oxide can form a channel formation region of a transistor having at least one of an amplifying function, a rectifying function, and a switching function, the metal oxide can be referred to as a metal oxide semiconductor. Furthermore, an OS transistor can be referred to as a transistor including a metal oxide or an oxide semiconductor.

[0097] In this specification, nitrogen-containing metal oxides may also be collectively referred to as metal oxides, and nitrogen-containing metal oxides may also be referred to as metal oxynitrides.

[0098] In this specification, the term "impurities" in a semiconductor refers to, for example, elements other than the main component constituting the semiconductor layer. For example, an element with a concentration of less than 0.1 atomic % is an impurity. The presence of impurities may cause one or more of the following: an increase in the defect level density of the semiconductor, a decrease in carrier mobility, and a decrease in crystallinity. When the semiconductor is an oxide semiconductor, impurities that change the characteristics of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main component, particularly, for example, hydrogen (also contained in water), lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen.

[0099] In this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, it also includes cases where the angle is -5° or more and 5° or less. Furthermore, "substantially parallel" or "roughly parallel" refers to a state in which two straight lines are arranged at an angle of -30° or more and 30° or less. Furthermore, "perpendicular" refers to a state in which two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, it also includes cases where the angle is 85° or more and 95° or less. Furthermore, "substantially perpendicular" or "approximately perpendicular" refers to a state in which two straight lines are arranged at an angle of 60° or more and 120° or less.

[0100] In this specification, unless otherwise specified, the expression "A and B are equal" means that the ratio of one of A and B to the other is 0.9 or more and 1.1 or less. For example, the case where the ratio of B to A is 0.9 or more and 1.1 or less and the ratio of A to B is not 0.9 or more and 1.1 or less is also considered to be "A and B are equal." Furthermore, unless otherwise specified, the expression "A and B are approximately equal" means that the ratio of one of A and B to the other is 0.8 or more and 1.2 or less, is also considered to be "A and B are approximately equal." For example, the case where the ratio of B to A is 0.8 or more and 1.2 or less and the ratio of A to B is not 0.8 or more and 1.2 or less is also considered to be "A and B are approximately equal."

[0101] In this specification, the configurations shown in each embodiment can be combined with the configurations shown in other embodiments as appropriate to form one aspect of the present invention. When multiple configuration examples are shown in one embodiment, the configuration examples can be combined with each other as appropriate.

[0102] In addition, the content described in one embodiment can be applied, combined, or replaced with another content described in that embodiment and at least one of the content described in another embodiment.

[0103] The contents described in the embodiments refer to the contents described in each embodiment using various figures or the contents described using text in the specification.

[0104] Furthermore, a figure described in one embodiment can be combined with another portion of that figure and at least one figure described in one or more other embodiments to form even more figures.

[0105] The embodiments described in this specification are described with reference to the drawings. However, it will be readily understood by those skilled in the art that the embodiments can be implemented in many different ways, and that various changes in form and details can be made without departing from the spirit and scope of the invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments. Note that in the configuration of the invention of the embodiments, the same reference numerals are used in different drawings for the same parts or parts having similar functions, and repeated description thereof may be omitted. Also, in perspective views and the like, the description of some components may be omitted to ensure clarity of the drawings.

[0106] In this specification, when the same reference numeral is used for multiple elements, and particularly when it is necessary to distinguish between them, an identification symbol such as "_1", "[n]", "[m, n]" may be added to the reference numeral. Furthermore, when an identification symbol such as "_1", "[n]", "[m, n]" is added to the reference numeral in the drawings or the like, the identification symbol may not be added if it is not necessary to distinguish between them in this specification.

[0107] In addition, in the drawings of this specification, the size, layer thickness, or region may be exaggerated for clarity. Therefore, the drawings are not necessarily limited to the scale. Note that the drawings are schematic illustrations of ideal examples, and are not limited to the shapes or values ​​shown in the drawings. For example, variations in signals, voltages, or currents due to noise, or variations in signals, voltages, or currents due to timing differences may be included.

[0108] Embodiment 1 In this embodiment, an arithmetic circuit, which is a semiconductor device of one embodiment of the present invention, will be described.

[0109] <Configuration Example 1 of Arithmetic Device> One embodiment of the present invention is an arithmetic circuit capable of multiplying a multiplier of one positive or negative number or 0 by a multiplicand of one positive or negative number or 0. Specifically, for example, when a multiplier of one positive or negative number or 0 is w and a multiplicand of one positive or negative number or 0 is x, the arithmetic circuit can perform x × w multiplication.

[0110] In this specification, the multiplier is referred to as the first data, and the multiplicand is referred to as the second data. Note that the multiplier and the multiplicand can be interchangeable due to the commutative law of products. For example, the multiplier can be referred to as the second data, and the multiplicand can be interchangeable as the first data.

[0111] 2 is a block diagram showing a configuration example of an arithmetic circuit CC, which is a semiconductor device of one embodiment of the present invention. As an example, the arithmetic circuit CC includes an arithmetic cell IMp, an arithmetic cell IMn, and a driver cell IMd. In addition, in order to describe an operation example of the arithmetic circuit CC later, FIG. 2 also shows a driver circuit WCD, a driver circuit XCD, a driver circuit WSD, and a driver circuit ITS for driving the arithmetic circuit CC. Therefore, in this specification and the like, a circuit including the arithmetic circuit CC and the above-listed driver circuits may be referred to as an arithmetic device CDV. In this specification, the arithmetic device CDV may also be referred to as a semiconductor device.

[0112] The computation cells IMp and IMn are connected to the wirings WCLp, WCLn, XCLp, XCLn, and WSL, respectively. The driving cell IMd is connected to the wirings XCLp, XCLn, and WSL. The driving circuit WCD is connected to the wirings WCLp and WCLn. The driving circuit XCD is connected to the wirings XCLp and XCLn. The driving circuit WSD is connected to the wiring WSL. The driving circuit ITS is connected to the wirings WCLp, WCLn, and OL.

[0113] 2 is an arithmetic circuit capable of multiplying one first data item by one second data item. Specifically, when the first data item is w and the second data item is x, the arithmetic circuit CC is capable of performing the operation w×x.

[0114] The first data w is a positive or negative number or 0. In this embodiment, two parameters w ｐ And lol ｎ It is expressed using w ｐ is referred to as the first parameter, the first variable, the first value, etc., and w ｎ is sometimes referred to as a second parameter, a second variable, a second value, etc. Specifically, when w is a positive number, (w ｐ , w ｎ ) = (w, 0), and if w is a negative number, then (w ｐ , w ｎ ) = (0, -w). Also, if w is 0, then (w ｐ , w ｎ ) = (0,0).

[0115] The second data x is a positive or negative number or 0. In this embodiment, similar to the first data w, the two parameters x ｐ and x ｎ It is expressed using x ｐ is referred to as the third parameter, third variable, third value, etc., and x ｎ is sometimes referred to as a fourth parameter, a fourth variable, a fourth value, etc. Specifically, when x is a positive number, (x ｐ, x ｎ ) = (x, 0), and if x is a negative number, then (x ｐ , x ｎ ) = (0, -x). Also, if x is 0, then (x ｐ , x ｎ ) = (0,0).

[0116] In the calculation circuit CC of FIG. 2, the calculation cell IMp has ｐ The calculation cell IMn has a function of holding w ｎ It has the function of retaining the

[0117] In addition, the calculation cell IMp is x ｐ and x ｎ is input into the calculation cell IMp, and w ｐ and x ｐ Multiplication with w ｐ and x ｎ Similarly, the operation cell IMn has the function of simultaneously performing multiplication with x ｐ and x ｎ is input to the calculation cell IMn, ｎ and x ｐ Multiplication with w ｎ and x ｎ It has the function of simultaneously executing multiplication with and.

[0118] Specifically, for example, the operation cell IMp receives a signal W transmitted from the driving circuit WCD, which will be described later. ｐ and the function of holding x transmitted from the drive circuit XCD (described later). ｐ and x ｎ By obtaining each of the ｐ ×x ｐ and w ｐ ×x ｎ It has the function of performing the calculations of and.

[0119] Moreover, the calculation cell IMn receives, as an example, a signal w transmitted from a driving circuit WCD, which will be described later. ｎ and the function of holding x transmitted from the drive circuit XCD (described later). ｐ and x ｎ By obtaining each of the ｎ ×x ｐ and w ｎ ×xｎ It has the function of performing the calculations of and.

[0120] That is, calculation cells IMp and IMn are used to calculate w ｐ ×x ｐ And, lol ｐ ×x ｎ And, lol ｎ ×x ｐ And, lol ｎ ×x ｎ and are executed simultaneously. The results of each calculation are determined by the values ​​of the first data w and the second data x. As mentioned above, when w is a positive number, (w ｐ , w ｎ ) = (w, 0), when w is negative, (w ｐ , w ｎ ) = (0, -w), when w is 0, (w ｐ , w ｎ ) = (0,0), and when x is a positive number, (x ｐ , x ｎ ) = (x, 0), when x is negative, (x ｐ , x ｎ ) = (0, -x), when x is 0, (x ｐ , x ｎ ) = (0,0), so w ｐ ×x ｐ And, lol ｐ ×x ｎ And, lol ｎ ×x ｐ And, lol ｎ ×x ｎ The calculation results of and are as shown in the table below.

[0121]

[0122] In other words, when the result of the operation w × x is a positive number, w ｐ ×x ｐ and w ｎ ×x ｎ One of them is w×x, and w ｐ ×x ｐ and w ｎ ×x ｎ On the other hand, ｐ ×x ｎ And lol ｎ ×x ｐand each of them will be 0. Also, when the calculation result of w × x is a negative number, w ｎ ×x ｐ and w ｐ ×x ｎ One of the two is -w × x, and w ｎ ×x ｐ and w ｐ ×x ｎ On the other hand, ｐ ×x ｐ And lol ｎ ×x ｎ When the calculation result of w × x is 0, w ｐ ×x ｐ , w ｎ ×x ｎ , w ｐ ×x ｎ and w ｎ ×x ｐ Each of these becomes 0.

[0123] The driving cell IMd has, for example, a function of holding reference data transmitted from a driving circuit XCD (described later) and a function of setting the potentials of the wirings XCLp and XCLn to potentials corresponding to the reference data. ｐ and x ｎ By acquiring the potential of the wiring XCLp, the potential of the wiring XCLp is set to the reference data or x ｐ and the potential of the wiring XCLn is set to a potential according to the reference data or x ｎ It has the function of setting the potential according to the

[0124] For example, the wiring WCLp is formed between the driving circuit WCD and the processing cell IMp. ｐ The wiring WCLp functions as a wiring for passing a current of an amount corresponding to the amount of current flowing. As will be described in detail later, the current is generated by the driving circuit WCD. In addition, as an example, the wiring WCLp is provided between the driving circuit ITS and the processing cell IMp, in accordance with the amount of current flowing in the processing cell IMp. ｐ ×x ｐ The wiring WCLp functions as a wiring for passing a current of an amount corresponding to the multiplication result of the multiplication of the driving circuit ITS and the operation cell IMn.ｎ ×x ｎ The wiring functions as a wiring for passing a current of an amount corresponding to the multiplication result.

[0125] For example, the wiring WCLn is formed between the driving circuit WCD and the calculation cell IMn. ｎ The wiring WCLn functions as a wiring for passing a current of an amount corresponding to the amount of current flowing. As will be described in detail later, the current is generated by the driving circuit WCD. In addition, as an example, the wiring WCLn is provided between the driving circuit ITS and the processing cell IMn, ｎ ×x ｐ The wiring WCLn functions as a wiring for passing a current of an amount corresponding to the multiplication result of the multiplication of the driving circuit ITS and the operation cell IMp. ｐ ×x ｎ The wiring functions as a wiring for passing a current of an amount corresponding to the multiplication result.

[0126] The wiring XCLp, for example, functions as a wiring for passing a reference current corresponding to reference data between the drive circuit XCD and the drive cell IMd. Details of the reference data will be described later, and here, as an example, the value of the reference data is set to "1". The wiring XCLp also functions as a wiring for passing a reference current corresponding to reference data between the drive circuit XCD and the drive cell IMd. ｐ It functions as wiring to pass an amount of current according to the

[0127] For example, the wiring XCLn functions as a wiring for passing a reference current corresponding to reference data between the driving circuit XCD and the driving cell IMd. ｎ It functions as wiring for passing a current according to the

[0128] Although the details will be described later, the reference current according to the above-mentioned reference data and x ｐ and a current according to x ｎ The currents corresponding to and are generated by the drive circuit XCD.

[0129] As an example, the wiring WSL is connected to the operation cell IMp. ｐand write w into the calculation cell IMn. ｎ 2, the wiring WSL is a single wiring, and therefore the selection signal transmitted to the wiring WSL is transmitted simultaneously to the processing cells IMp, IMn, and the driving cell IMd. ｐ and writing w to the calculation cell IMn ｎ and the writing of the reference data to the driving cell IMd can be performed simultaneously.

[0130] In addition, as an example, the wiring WSL is connected to the operation cell IMp. ｐ is stored in the calculation cell IMn. ｎ When the reference data is stored in the driving cell IMd, the wiring WSL functions as a wiring for transmitting a non-selection signal to each of the processing cells IMp, IMn, and IMd. ｐ and storing w ｎ and the reference data can be held in the driving cell IMd at the same time.

[0131] The driver circuit WCD is ｐ A function of generating a current according to w ｎ Specifically, for example, the driving circuit WCD receives digital data w ｐ And lol ｎ Get w ｐ And lol ｎ The driver circuit WCD generates an analog current corresponding to each of the ｐ An analog current corresponding to w flows through the wiring WCLp. ｎ For example, in FIG. 2, an analog current corresponding to w is supplied to the driver circuit WCD from the outside via the wiring IWLp. ｐ is given to the driving circuit WCD from the outside via the wiring IWLn. ｎ This shows an example where

[0132] The driver circuit XCD is ｐ a function of generating a current according to x ｎ Specifically, for example, the drive circuit XCD receives digital data x from the outside. ｐ and x ｎ Obtain x ｐ and x ｎ The driver circuit XCD generates analog currents according to the respective ｐ An analog current corresponding to x is passed through the wiring XCLp. ｎ For example, in FIG. 2, an analog current corresponding to x is supplied to the driver circuit XCD via the wiring IXLp from the outside. ｐ is supplied from the outside to the drive circuit XCD via the wiring IXLn. ｎ In this example, the driving circuit XCD has a function of generating a reference current according to the reference data. Specifically, for example, the driving circuit XCD receives digital data x ｐ or x ｎ is treated as reference data, and a reference current according to the reference data can be passed through the wiring XCLp and the wiring XCLn.

[0133] The drive circuit WSD is, for example, ｐ and the calculation cell IMp to which w is written. ｎ When selecting the calculation cell IMp and the calculation cell IMn to be written into, the driving circuit WSD has a function of transmitting a selection signal for turning on the write transistors included in the calculation cells IMp and IMn. ｐ And lol ｎ When the write transistors IMp and IMn are not to be written into the processing cells IMp and IMn, the write transistors IMp and IMn are transmitted with a non-selection signal to turn off the corresponding write transistors.

[0134] Furthermore, since the wiring WSL is also connected to the driving cell IMd, the driving circuit WSD transmits a selection signal or a non-selection signal to the driving cell IMd at the same time as to the processing cells IMp and IMn. In particular, when a selection signal is transmitted to the driving cell IMd, the driving cell IMd holds the reference data.

[0135] As an example, the driving circuit ITS determines the amount of current (I ＳＰ ) and the amount of current flowing through the wiring WCLn (I ＳＮ The drive circuit ITS has a function of calculating the difference between the differential current and the output current z, and generating a differential current. The drive circuit ITS also calculates an activation function F as a function system (for example, a nonlinear function system) using the differential current as an input value, and outputs the output data z=F(I ＳＰ -I ＳＮ ) to the wiring OL. In the calculation device CDV of FIG. 2, the amount of current I ＳＰ is the w ｐ ×x ｐ or the calculation result of w in the calculation cell IMn ｎ ×x ｎ The amount of current flowing through the wiring WCLn is determined by the calculation result of ＳＮ is the w ｐ ×x ｎ or the calculation result of w in the calculation cell IMn ｎ ×x ｐ The amount of current is determined according to the calculation result.

[0136] The activation function F may be a nonlinear function such as a sigmoid function, a tanh function, a softmax function, a ReLU function, or a threshold function. In particular, a configuration example of the driver circuit ITS that performs the calculation of the ReLU function will be described later.

[0137] The output data z output from the driver circuit ITS to the wiring OL may be digital data, an analog current, or an analog potential. When the output data z is digital data, the driver circuit ITS preferably includes an analog current-to-digital potential converter circuit.

[0138] In addition, in the calculation device CDV, when it is not necessary for the drive circuit ITS to calculate the activation function, the drive circuit ITS determines the amount of current I flowing through the wiring WCLp. ＳＰ and the amount of current I flowing through the wiring WCLn. ＳＮThe circuit may be configured to output the difference current between

[0139] Next, a specific example of the configuration of the calculation circuit CC in Fig. 2 will be described. Fig. 1 shows an example of the circuit configuration of each of the calculation cells IMp, IMn, and driver cell IMd included in the calculation circuit CC shown in Fig. 2. Fig. 1 also shows the driver circuits WCD, XCD, WSD, and ITS. Fig. 1 also shows the driver circuits ROD and WROD as new components of the calculation device CDV.

[0140] As explained in the connection configuration in FIG. 2, the drive circuit WCD is connected to the wiring WCLp. The drive circuit XCD is connected to the wiring XCLp and the wiring XCLn. The drive circuit WSD is connected to the wiring WSL. The drive circuit ITS is connected to the wiring WCLp, the wiring WCLn, and the wiring OL. As shown in FIG. 1, the drive circuit WROD is connected to the wiring WROL, and the drive circuit ROD is connected to the wiring ROL.

[0141] 1, the calculation cell IMp includes, for example, transistors M1p, M2p, M3p, M4p, M5p, M6p, and capacitive elements C1p and C2p. The calculation cell IMn includes, for example, transistors M1n, M2n, M3n, M4n, M5n, M6n, and capacitive elements C1n and C2n. The drive cell IMd includes, for example, transistors M1d, M2d, M3d, M4d, M5d, M6d, and capacitive elements C1d and C2d.

[0142] In the operation cell IMp, the transistors M1p and M2p each function as a write transistor (sometimes called a holding transistor or a switching transistor). The transistors M3p and M5p each function as a transistor (sometimes called an amplifying transistor) for outputting the multiplication result of the multiplier and the multiplicand as a current. The transistor M4p also functions as a clamp transistor for preventing a decrease in the threshold voltage of the transistor M3p due to drain-induced barrier lowering (DIBL). The transistor M4p also functions as a switching transistor for switching between a conductive state and a non-conductive state between the wiring WCLp (described later) and the source or drain of the transistor M3p. The transistor M6p also functions as a clamp transistor for preventing a decrease in the threshold voltage of the transistor M5p due to DIBL. The transistor M6p also functions as a switching transistor that switches between a conductive state and a non-conductive state between a wiring WCLn (to be described later) and the source or drain of the transistor M5p.

[0143] In the operation cell IMn, the transistors M1n and M2n function as write transistors, similar to the transistors M1p and M2p described above. The transistors M3n and M5n function as amplifier transistors for outputting the multiplication result of the multiplier and the multiplicand as a current, similar to the transistors M3p and M5p described above. The transistor M4n functions as a clamp transistor for preventing a decrease in the threshold voltage of the transistor M3n due to DIBL, similar to the transistors M4p and M6p described above. The transistor M4n also functions as a switching transistor for switching between a conductive state and a non-conductive state between the wiring WCLn (described later) and the source or drain of the transistor M3n, similar to the transistor M4p. The transistor M6n also functions as a clamp transistor for preventing a decrease in the threshold voltage of the transistor M5n due to DIBL. Similarly to the transistor M6p, the transistor M6n also functions as a switching transistor that switches between a conductive state and a non-conductive state between a wiring WCLp (to be described later) and the source or drain of the transistor M5n.

[0144] In the driver cell IMd, the transistors M1d and M2d each function as a write transistor, similar to the transistors M1p, M2p, M1n, and M2n described above. The transistors M3d and M5d each function as an amplifier transistor for outputting a current corresponding to the data written to the driver cell IMd. The data may be a multiplicand or reference data (described later). The transistor M4d also functions as a clamp transistor for preventing a decrease in the threshold voltage of the transistor M3d due to DIBL, similar to the transistors M4p, M6p, M4n, and M6n described above. The transistor M6d also functions as a clamp transistor for preventing a decrease in the threshold voltage of the transistor M5d due to DIBL.

[0145] In the operational circuit CC in FIG. 1 , the transistors M1p to M6p, the transistors M1n to M6n, and the transistors M1d to M6d are preferably OS transistors, for example. In particular, indium oxide (sometimes referred to as indium oxide) is preferably used as a metal oxide that can be used as an oxide semiconductor included in the channel formation region of an OS transistor. By using indium oxide as the metal oxide in the channel formation region of each of the transistors listed above, the frequency characteristics of the transistor can be improved. Furthermore, the on-state current of the transistor can be increased. Furthermore, the off-state current of the transistor can be reduced. Indium oxide will be described in detail in Embodiment 3.

[0146] Examples of the OS transistor include gallium oxide and zinc oxide, in addition to indium oxide. The metal oxide preferably includes one or more elements selected from the group consisting of indium, an element M, and zinc. The element M is one or more elements selected from aluminum, gallium, silicon, yttrium, tin, copper, vanadium, chromium, manganese, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, calcium, strontium, barium, cobalt, and antimony. The element M is preferably one or more elements selected from the group consisting of aluminum, gallium, yttrium, and tin.

[0147] As the metal oxide used for the semiconductor layer, an oxide containing indium (In), gallium (Ga), and zinc (Zn) (also referred to as IGZO) can be used. Alternatively, an oxide containing indium, tin, and zinc (also referred to as ITZO (registered trademark)) can be used. Alternatively, an oxide containing indium, gallium, tin, and zinc can be used. Alternatively, an oxide containing indium (In), aluminum (Al), and zinc (Zn) (also referred to as IAZO) can be used. Alternatively, an oxide containing indium (In), aluminum (Al), gallium (Ga), and zinc (Zn) (also referred to as IAGZO) can be used. Note that metal oxides will be described in detail in Embodiment 2.

[0148] Furthermore, the metal oxide containing indium and the element M preferably has a stacked structure of multiple oxide layers with different chemical compositions. For example, consider an oxide layer with a two-layer structure consisting of a first layer and a second layer located immediately above the first layer. The atomic ratio of the element M to the main component metal element in the metal oxide used for the first layer is preferably greater than the atomic ratio of the element M to the main component metal element in the metal oxide used for the second layer. Furthermore, the atomic ratio of the element M to In in the metal oxide used for the first layer is preferably greater than the atomic ratio of the element M to In in the metal oxide used for the second layer. This configuration can suppress the diffusion of impurities and oxygen from structures formed below the first layer into the second layer.

[0149] In addition, the atomic ratio of In to the element M in the metal oxide used for the second layer is preferably larger than the atomic ratio of In to the element M in the metal oxide used for the first layer. With this structure, an OS transistor having this structure can have large on-state current and high frequency characteristics.

[0150] Specifically, for example, the metal oxide used in the first layer may have a composition of In:M:Zn = 1:3:2 (atomic ratio) or a composition thereabout, In:M:Zn = 1:3:4 (atomic ratio) or a composition thereabout, or In:M:Zn = 1:1:0.5 (atomic ratio) or a composition thereabout. Furthermore, the metal oxide used in the second layer may have a composition of In:M:Zn = 1:1:1 (atomic ratio) or a composition thereabout, In:M:Zn = 1:1:1.2 (atomic ratio) or a composition thereabout, In:M:Zn = 1:1:2 (atomic ratio) or a composition thereabout, or In:M:Zn = 4:2:3 (atomic ratio) or a composition thereabout. Note that a composition thereabout includes a range of 0.70 to 1.3 times the desired atomic ratio. For example, when the desired atomic ratio is 4, the atomic ratio of the neighboring composition is 2.8 or more and 5.2 or less.

[0151] Incidentally, in order to reduce the off-state current of a transistor, it is preferable to use, for example, an oxide containing indium (In), gallium (Ga), and zinc (Zn) as the metal oxide used in the semiconductor layer of the transistor. When the semiconductor layer of the transistor contains an oxide containing indium (In), gallium (Ga), and zinc (Zn), the amount of current flowing between the source and drain of the transistor when the gate-source voltage is 0 V is 1×10 per 1 μm of channel width at room temperature (e.g., 25° C.). −２０ A or less, 1 x 10 at 85°C −１８ A or less, or 1 x 10 at 125°C −１６ In this specification, the state in which the amount of current flowing between the source and drain when the gate-source voltage of a transistor is 0 V is extremely small is referred to as normally-off.

[0152] As described above, in a transistor in which a semiconductor layer contains an oxide containing indium (In), gallium (Ga), and zinc (Zn), when the gate-source voltage is lower than the threshold voltage, the amount of current flowing per 1 μm of channel width is 1×10 −１６ A or less, preferably 1 x 10 −１８ A or less, more preferably 1×10−２０ A or less. Depending on the situation, the amount of current flowing per 1 μm of channel width may be 1×10 −２０ A or less, more preferably 1×10 −２２ A or less, more preferably 1×10 −２４ In this specification, the operation of the transistor in this region may be referred to as an off state. In this case, the current flowing through the transistor may be referred to as an off-state current.

[0153] In particular, by using transistors including the oxide in semiconductor layers for the transistors M1p, M2p, M1n, M2n, M1d, and M2d, the off-state current of these transistors can be made extremely small. As described above, the transistors M1p and M2p each function as a write transistor in the calculation cell IMp, the transistors M1n and M2n each function as a write transistor in the calculation cell IMn, and the transistors M1d and M2d each function as a write transistor in the driver cell IMd. Therefore, it is preferable to use OS transistors with extremely low off-state current as the write transistors.

[0154] Furthermore, by using transistors including the above oxide in semiconductor layers for the transistors M3p, M5p, M3n, M5n, M3d, and M5d, the subthreshold regions of these transistors can be widened, thereby reducing current consumption.

[0155] By using transistors including the oxide in semiconductor layers for transistors M4p, M6p, M4n, M6n, M4d, and M6d in addition to transistors M1p to M3p, M5p, M1n to M3n, M5n, M1d to M3d, and M6d, the transistors included in the calculation cell IMp, the calculation cell IMn, and the driver cell IMd can be manufactured simultaneously. Therefore, the manufacturing process of the calculation device CDV can be shortened in some cases.

[0156] Furthermore, each of the transistors M1p to M6p, the transistors M1n to M6n, and the transistors M1d to M6d can be a transistor containing silicon in a channel formation region (hereinafter referred to as a Si transistor) other than an OS transistor. Si transistors have a higher on-state current than OS transistors and are therefore suitable for passing a large current.

[0157] Furthermore, each of the transistors M1p to M6p, the transistors M1n to M6n, and the transistors M1d to M6d can be, other than an OS transistor or a Si transistor, a transistor including germanium in a channel formation region, a transistor including a compound semiconductor such as zinc selenide, cadmium sulfide, gallium arsenide, indium phosphide, gallium nitride, or silicon germanium in a channel formation region, a transistor including a carbon nanotube in a channel formation region, or a transistor including an organic semiconductor in a channel formation region.

[0158] In the processing cell IMp, the first terminal of the transistor M1p is connected to the gate of the transistor M3p and the first terminal of the capacitance element C1p, and the second terminal of the transistor M1p is connected to the first terminal of the transistor M2p, the gate of the transistor M5p, and the first terminal of the capacitance element C2p. The first terminal of the transistor M3p is connected to the first terminal of the transistor M4p, and the second terminal of the transistor M3p is connected to the wiring VE1. The first terminal of the transistor M5p is connected to the first terminal of the transistor M6p, and the second terminal of the transistor M5p is connected to the wiring VE1.

[0159] In the calculation cell IMn, the first terminal of the transistor M1n is connected to the gate of the transistor M3n and the first terminal of the capacitance element C1n, and the second terminal of the transistor M1n is connected to the first terminal of the transistor M2n, the gate of the transistor M5n, and the first terminal of the capacitance element C2n. The first terminal of the transistor M3n is connected to the first terminal of the transistor M4n, and the second terminal of the transistor M3n is connected to the wiring VE1. The first terminal of the transistor M5n is connected to the first terminal of the transistor M6n, and the second terminal of the transistor M5n is connected to the wiring VE1.

[0160] In the driving cell IMd, the first terminal of the transistor M1d is connected to the gate of the transistor M3d and the first terminal of the capacitance element C1d, and the second terminal of the transistor M1d is connected to the first terminal of the transistor M2d, the gate of the transistor M5d, and the first terminal of the capacitance element C2d. The first terminal of the transistor M3d is connected to the first terminal of the transistor M4d, and the second terminal of the transistor M3d is connected to the wiring VE1. The first terminal of the transistor M5d is connected to the first terminal of the transistor M6d, and the second terminal of the transistor M5d is connected to the wiring VE1. The gates of the transistors M4d and M6d are each connected to the wiring VE2.

[0161] The second terminal of the transistor M2p and the second terminal of the transistor M4p are connected to the wiring WCLp. The second terminal of the transistor M6p is connected to the wiring WCLn. The second terminal of the transistor M2n and the second terminal of the transistor M4n are connected to the wiring WCLn. The second terminal of the transistor M6n is connected to the wiring WCLp.

[0162] The second terminal of the transistor M2d, the second terminal of the transistor M4d, the second terminal of the capacitance element C1p, the second terminal of the capacitance element C1n, and the second terminal of the capacitance element C1d are connected to the wiring XCLp. The second terminal of the transistor M6d, the second terminal of the capacitance element C2p, the second terminal of the capacitance element C2n, and the second terminal of the capacitance element C2d are connected to the wiring XCLn.

[0163] The gate of the transistor M1p, the gate of the transistor M2p, the gate of the transistor M1n, the gate of the transistor M2n, the gate of the transistor M1d, and the gate of the transistor M2d are each connected to the wiring WSL.

[0164] The gates of the transistors M4p and M4n are connected to the wiring WROL, and the gates of the transistors M6p and M6n are connected to the wiring ROL.

[0165] 1, the connection point between the first terminal of transistor M1p, the gate of transistor M3p, and the first terminal of capacitor C1p is shown as node N1p. The connection point between the second terminal of transistor M1p, the first terminal of transistor M2p, the gate of transistor M5p, and the first terminal of capacitor C2p is shown as node N2p. The connection point between the first terminal of transistor M1n, the gate of transistor M3n, and the first terminal of capacitor C1n is shown as node N1n. The connection point between the second terminal of transistor M1n, the first terminal of transistor M2n, the gate of transistor M5n, and the first terminal of capacitor C2n is shown as node N2n. The connection point between the first terminal of transistor M1d, the gate of transistor M3d, and the first terminal of capacitor C1d is shown as node N1d. The connection point between the second terminal of the transistor M1d, the first terminal of the transistor M2d, the gate of the transistor M5d, and the first terminal of the capacitive element C2d is shown as a node N2d.

[0166] As an example, the wiring WSL functions as a wiring for transmitting a selection signal from the driver circuit WSD as described above. ｐ When writing data, a high-level potential is applied as a selection signal from the driver circuit WSD to the wiring WSL of the processing cell IMp in order to turn on the transistors M1p and M2p. ｎWhen writing reference data to the driving cell IMp, a high level potential is applied to the wiring WSL from the driving circuit WSD as a selection signal to the processing cell IMn in order to turn on the transistors M1n and M2n. When writing reference data to the driving cell IMd, a high level potential is applied to the wiring WSL from the driving circuit WSD as a selection signal to the driving cell IMd in order to turn on the transistors M1d and M2d. As shown in FIG. 1, the wiring WSL is a single wiring, and therefore the selection signal transmitted to the wiring WSL is simultaneously applied to the gates of the transistors M1p, M2p, M1n, M2n, M1d, and M2d. In other words, when writing reference data to the processing cell IMp, a high level potential is applied to the wiring WSL from the driving circuit WSD as a selection signal to the driving cell IMd in order to turn on the transistors M1d and M2d. ｐ and writing w to the calculation cell IMn ｎ The writing of the reference data to the driving cell IMd is performed simultaneously.

[0167] As an example, the wiring WSL is connected to the operation cell IMp as described above. ｐ is stored in the calculation cell IMn. ｎ and when the reference data is held in the driving cell IMd, it also functions as a wiring that transmits a non-selection signal to each of the processing cells IMp, IMn, and IMd. Specifically, for example, in order to turn off the transistors M1p, M2p, M1n, M2n, M1d, and M2d, a low-level potential is applied as a non-selection signal from the driving circuit WSD to the gates of these transistors via the wiring WSL. Also, as described above, the wiring WSL is a single wiring, and therefore the wiring WSL does not transmit a non-selection signal to the processing cell IMp. ｐ and storing w ｎ and the reference data can be held in the driving cell IMd at the same time.

[0168] For example, the wiring WROL is connected to the operation cell IMp in the same manner as the wiring WSL. ｐ When writing, w ｎWhen writing data to the driving cell IMd, and when writing reference data to the driving cell IMd, the wiring WROL functions as a wiring for transmitting a selection signal to each of the processing cells IMp and IMn in order to turn on the transistors M4p and M4n. ｐ ×x ｐ When a current corresponding to the calculation result of the current flows, the wiring WROL functions as a wiring for transmitting a selection signal to the calculation cell IMp in order to turn on the transistor M4p. ｎ ×x ｎ When a current corresponding to the calculation result of is passed through the calculation cell IMn, the calculation cell IMn also functions as a wiring for transmitting a selection signal to the calculation cell IMn in order to turn on the transistor M4n.

[0169] The wiring WROL also functions as a wiring that transmits a non-selection signal to the processing cell IMp when no current flows between the processing cell IMp and the wiring WCLp, and as a wiring that transmits a non-selection signal to the processing cell IMn when no current flows between the processing cell IMn and the wiring WCLn, for example.

[0170] The selection signal and the non-selection signal are generated by the drive circuit WROD.

[0171] For example, the wiring ROL is connected to the operation cell IMp in the same manner as the wiring WSL. ｐ When writing, w ｎ When writing data to the driving cell IMd, and when writing reference data to the driving cell IMd, the wiring WROL functions as a wiring for transmitting a non-selection signal to each of the processing cells IMp and IMn in order to turn off the transistors M6p and M6n. ｐ ×x ｎWhen a current corresponding to the calculation result of the current flow is supplied, the wiring WROL functions as a wiring for transmitting a selection signal to the calculation cell IMp in order to turn on the transistor M6p. ｎ ×x ｐ When a current corresponding to the calculation result of is passed through the calculation cell IMn, the calculation cell IMn also functions as a wiring for transmitting a selection signal to the calculation cell IMn in order to turn on the transistor M6n.

[0172] The selection signal and the non-selection signal are generated by the drive circuit ROD.

[0173] For example, the wiring VE1 functions as a wiring that applies a fixed potential. Specifically, the wiring VE1 functions as a wiring that applies the fixed potential to the second terminals of the transistors M3p, M5p, M3n, M5n, M3d, and M5d. In particular, the fixed potential is a potential in the subthreshold region of each of the transistors M3p, M5p, M3n, M5n, M3d, and M5d. Specifically, the fixed potential is, for example, V ｇｐ (w ｐ = 1), V ｇｎ (w ｎ = 1) and V ｇｍ The fixed potential may be a potential lower than (r=1), a low-level potential, a ground potential, a negative potential, or the like. Alternatively, depending on the situation, the fixed potential may be a high-level potential, a positive potential, or the like. Alternatively, depending on the situation, the wiring VE1 may function as a wiring that applies a variable potential, such as a pulse potential (which may be called a pulse signal) or a clock potential (which may be called a clock signal), for example.

[0174] For example, the wiring VE2 functions as a wiring that applies a fixed potential. Note that the fixed potential can be, for example, a high-level potential or a positive potential. As a result, the transistors M4d and M6d, which are clamp transistors, are turned on. Note that, depending on the situation, the fixed potential applied by the wiring VE2 can be a low-level potential, a ground potential, a negative potential, or the like. For example, the wiring VE2 may also function as a wiring that applies a variable potential instead of a fixed potential.

[0175] Each of the lines OL functions as a line for outputting the result of the multiplication performed in the arithmetic unit CDV as digital data to the outside.

[0176] As described above, the drive circuit WCD is ｐ A function of generating a current according to w ｎ Specifically, for example, the driving circuit WCD receives digital data w ｐ And lol ｎ Get w ｐ Amount I ｗｐ and the function of converting it into an analog current of w ｎ Amount I ｗｎ The driving circuit WCD has a function of converting the analog current into an analog current of w ｐ Amount I according to ｗｐ An analog current of w flows through the wiring WCLp, and ｎ Amount I according to ｗｎ The analog current flows through the wiring WCLn.

[0177] As shown in FIG. 1 , the driver circuit WCD includes, for example, a circuit WCDp, a circuit WCDn, and a circuit SWCA. The circuit SWCA also includes a switch SAp and a switch SAn. The input terminal of the circuit WCDp is connected to a wiring IWLp, and the output terminal of the circuit WCDp is connected to a first terminal of the switch SAp. The second terminal of the switch SAp is connected to a wiring WCLp, and the control terminal of the switch SAp is connected to a wiring SWLA. The input terminal of the circuit WCDn is connected to a wiring IWLn, and the output terminal of the circuit WCDn is connected to a first terminal of the switch SAn. The second terminal of the switch SAn is connected to the wiring WCLn, and the control terminal of the switch SAn is connected to the wiring SWLA.

[0178] The circuit SWCA has a function of bringing the output terminal of the circuit WCDp and the wiring WCLp into a conductive state or a non-conductive state, and a function of bringing the output terminal of the circuit WCDn and the wiring WCLn into a conductive state or a non-conductive state. Therefore, the switch SAp switches the conductive state or the non-conductive state between the output terminal of the circuit WCDp and the wiring WCLp, and the switch SAn switches the conductive state or the non-conductive state between the output terminal of the circuit WCDn and the wiring WCLn.

[0179] For example, electrical switches such as analog switches and transistors can be used for each of the switches SAp and SAn. In particular, the above-described transistors are preferably used as the electrical switches for each of the switches SAp and SAn, and OS transistors are more preferably used. Note that when electrical switches are used for each of the switches SAp and SAn, the electrical switches can be, for example, Si transistors other than OS transistors. Furthermore, for example, mechanical switches may also be used for each of the switches SAp and SAn.

[0180] In this specification, each of the switches SAp and SAn shown in FIG. 1 is assumed to be in an on state when a high-level potential is applied as a signal to its control terminal, and to be in an off state when a low-level potential is applied as a signal to its control terminal.

[0181] For example, the wiring SWLA functions as a wiring for transmitting a signal for controlling switching between the on state and the off state of each of the switches SAp and SAn.

[0182] For example, each of the circuits WCDp and WCDn has a function of converting digital data input to an input terminal into an analog current and outputting the analog current to an output terminal, and therefore each of the circuits WCDp and WCDn preferably has a digital potential-analog current conversion circuit.

[0183] As an example, each of the wirings IWLp and IWLn transmits two parameters w representing the first data w as digital data from the outside of the calculation device CDV to the driving circuit WCD. ｐ And lol ｎ It functions as a wiring for transmitting.

[0184] For example, the circuit WCDp receives digital data from the wiring IWLp and transfers it to the input terminal WCDp. ｐ When this is done, the output terminal ｐ As a current according to ｗｐ =w ｐ I ＵＴ It has the function of flowing. ＵＴ Ha, w ｐ is the amount of current output from the output terminal of the digital potential-analog current conversion circuit when the value of the digital potential-analog current conversion circuit is 1. Similarly, the circuit WCDn converts digital data input from the wiring IWLn to the input terminal of the circuit WCDn. ｎ When this is done, the output terminal ｎ As a current according to ｗｎ =w ｎ I ＵＴ It has the function of flowing water.

[0185] In particular, the quantity I output by the circuit WCDp ｗｐand the analog current output by the circuit WCDn. ｗｎ The analog currents are currents in the subthreshold regions of the transistors M3p, M5p, M3n, and M5n. Specifically, for example, the currents flowing between the source and drain of these transistors are I ｄ and the gate-source voltage of the transistor is V ｇｓ When this is the case, the relationship of the following equation (1.1) is satisfied. ｄ =I ｗｐ or I ｄ =I ｗｎ is exp[V ｇｓ ] shall be proportional to

[0186]

[0187] Calculation cell IMp w ｐ When is written, the transistors M1p, M2p, and M4p are turned on so that the potentials of the gate and the first terminal of the transistor M3p are equal to each other. This causes the transistor M3p to be diode-connected, and the amount I output by the circuit WCDp is applied between the source and drain of the transistor M3p. ｗｐ The analog current V flows, and the gate-source voltage V of the transistor M3p ｇｓ Furthermore, since the potential of the source of the transistor M3p is the potential given from the wiring VE1, the potential of the gate of the transistor M3p is determined by the amount of analog current I ｗｐ , that is, w ｐ At this time, the potential of the gate of the transistor M3p (potential of the node N1p) is determined by V ｇｐ (w ｐ ) Furthermore, since the transistor M1p is in an on state, the potential of the node N2p is also V ｇｐ (w ｐ )

[0188] Similarly, in the calculation cell IMn, ｎWhen is written, the transistors M1n, M2n, and M4n are turned on so that the potentials of the gate and the first terminal of the transistor M3n are equal to each other. This causes the transistor M3n to be diode-connected, and the amount I output by the circuit WCDn is applied between the source and drain of the transistor M3n. ｗｎ When an analog current of V flows, the gate-source voltage V of the transistor M3n increases. ｇｓ Furthermore, since the potential of the source of the transistor M3n is the potential given from the wiring VE1, the potential of the gate of the transistor M3n is determined by the amount of analog current I ｗｎ , that is, w ｎ At this time, the potential of the gate of the transistor M3n (potential of the node N1n) is determined by V ｇｎ (w ｎ ) In addition, since the transistor M1n is in an on state, the potential of the node N2n is also V ｇｎ (w ｎ )

[0189] Furthermore, w ｐ When 0, the circuit WCDp outputs V ｇｐ (w ｐ = 1) and V ｇｍ It is preferable to output a potential lower than (r=1), a ground potential, or a negative potential. Alternatively, a potential equal to the potential applied by the wiring VE1 may be output. ｎ Even if you set it to 0, the above w ｐ As in the case where V is set to 0, the circuit WCDn outputs V ｇｎ (w ｐ = 1) and V ｇｍ It is preferable to output a potential lower than (r=1), a ground potential, or a negative potential. Alternatively, a potential equal to the potential applied by the wiring VE1 may be output. ｐ When is set to 0, the potential output by the circuit WCDp is ｎ may be equal to the potential output by the circuit WCDn when is set to 0.

[0190] Also, w ｐ When 0, the circuit WCDp is ｐ As an approximation of =0, wｐ = 0.001 or less, preferably w ｐ = 0.0001 or less, more preferably w ｐ = 0.00001 or less, more preferably w ｐ = 0.000001 or less, more preferably w ｐ = 0.0000001 or less. ｗｐ A current of w ｎ If w is set to 0, ｐ As in the case where w is set to 0, the circuit WCDn ｎ As an approximation of =0, w ｎ = 0.001 or less, preferably w ｎ = 0.0001 or less, more preferably w ｎ = 0.00001 or less, more preferably w ｎ = 0.000001 or less, more preferably w ｎ = 0.0000001 or less. ｗｎ A current of w ｐ The amount of analog current I output by the circuit WCDp when ｗｐ Ha, w ｎ The amount of analog current I output by the circuit WCDn when ｗｎ may be equal to

[0191] Calculation cell IMp w ｐ When writing, first, the circuit WCDp receives digital data w ｐ Get w ｐ After that, a high-level potential is applied to the wiring SWLA to turn on the switch SAp, and a high-level potential is applied to the wiring WROL to turn on the transistor M4p, whereby the analog current output from the output terminal of the circuit WCDp is expressed as w ｐ In response to ｗｐ flows to the operation cell IMp via the wiring WCLp.

[0192] Similarly, in the calculation cell IMn, ｎ When writing, first, the circuit WCDn receives digital data w ｎ Get w ｎAfter that, a high-level potential is applied to the wiring SWLA to turn on the switch SAn, and a high-level potential is applied to the wiring WROL to turn on the transistor M4n, whereby the analog current output from the output terminal of the circuit WCDn is expressed as w ｎ In response to ｗｎ flows to the operation cell IMn via the wiring WCLn.

[0193] Also, the w ｐ and writing w to the calculation cell IMn ｎ Between writing and writing, a low-level potential is preferably applied to the wiring ROL to turn off the transistors M6p and M6n.

[0194] As will be described in detail later, by applying a high-level potential to the wiring WSL to turn on the transistors M1p, M2p, M1n, and M2n, and by applying a high-level potential to the wiring WROL to turn on the transistors M4p and M4n, the potentials of the nodes N1p and N2p of the processing cell IMp are increased by the amount of analog current I ｗｐ The potential V ｇｐ (w ｐ ), and the potentials of the nodes N1n and N2n of the processing cell IMn are respectively determined by the amount of analog current I ｗｎ The potential V ｇｎ (w ｎ ) to the operation cell IMp. ｐ and writing w to the calculation cell IMn ｎ After that, a low-level potential is applied to the wiring WSL to turn off the transistors M1p, M2p, M1n, and M2n, and a low-level potential is applied to the wiring WROL to turn off the transistors M4p and M4n, thereby writing the data in the processing cell IMp. ｐ and w in the calculation cell IMn ｎ and retention of the data.

[0195] Also, the w ｐand writing w to the calculation cell IMn ｎ After the writing of the data, it is preferable to apply a low-level potential to the wiring SWLA in the driver circuit WCD to turn off the switches SAp and SAn. This increases the impedance of the output terminals of the circuits WCDp and WCDn, and reduces the w ｐ and the transmission of w from the output terminal of the circuit WCDn to the wiring WCLn. ｎ This also makes it possible to reduce the power consumption of each of the circuits WCDp and WCDn.

[0196] The driver circuit XCD supplies the calculation cell IMp with ｐ is written, and w is written to the calculation cell IMn. ｎ When the reference data r is written, the wiring XCLp and the wiring XCLn are supplied with the amount rI ＵＴ It has the function of providing a current of

[0197] As described above, the driving circuit XCD is configured such that the calculation cell IMp is ｐ and x ｐ Multiplication and w ｐ and x ｎ When multiplication is performed, the operation cell IMn is ｎ and x ｐ Multiplication and w ｎ and x ｎ When multiplying and x used ｐ and x ｎ Specifically, for example, the driver circuit XCD receives digital data x ｐ and x ｎ Obtain x ｐ Amount I ｘｐ and the function of converting it into an analog current of x ｎ Amount I ｘｎ The driving circuit XCD has a function of converting the quantity I ｘｐ An analog current of the amount I ｘｎ The analog current flows through the wiring XCLn.

[0198] 1, the driver circuit XCD includes, for example, a circuit XCDp and a circuit XCDn. An input terminal of the circuit XCDp is connected to a wiring IXLp, and an output terminal of the circuit XCDp is connected to a wiring XCLp. An input terminal of the circuit XCDn is connected to a wiring IXLn, and an output terminal of the circuit XCDn is connected to a wiring XCLn.

[0199] For example, each of the circuits XCDp and XCDn has a function of converting digital data input to an input terminal into an analog current, and therefore each of the circuits XCDp and XCDn preferably includes a digital potential-analog current conversion circuit.

[0200] As an example, each of the wirings IXLp and IXLn transmits two parameters x representing the second data x as digital data to the driving circuit XCD from the outside of the calculation device CDV. ｐ and x ｎ It functions as a wiring for transmitting.

[0201] As an example, when digital data input to the input terminal from the wiring IXLp is taken as reference data r, the circuit XCDp outputs a reference current I according to r at the output terminal. ｘｐ = rI ＵＴ It has the function of flowing. ＵＴ is the amount of current output from the output terminal of the digital potential-analog current conversion circuit when r is 1. Similarly, when digital data input to the input terminal from the wiring IXLn is taken as reference data r, the circuit XCDn outputs a current I according to r at the output terminal. ｘｎ = rI ＵＴ It has the function of flowing water.

[0202] For example, the circuit XCDp converts digital data input from the wiring IXLp to the input terminal x ｐ When this is done, the output terminal ｐ As a current according to ｘｐ = x ｐ I ＵＴ Similarly, the circuit XCDn has a function of transmitting digital data input to the input terminal from the wiring IXLn as an example.ｎ When this is done, the output terminal ｎ As a current according to ｘｎ = x ｎ I ＵＴ It has the function of flowing water.

[0203] The amount of current I flowing through each of the circuits XCDp and XCDn is ＵＴ is the amount of current I flowing through each of the circuits WCDp and WCDn. ＵＴ is preferably equal to

[0204] In particular, the quantity I output by the circuit XCDp ｘｐ and the amount I output by the circuit XCDn. ｘｎ The analog current is a current in the subthreshold region of each of the transistors M3d and M5d. Specifically, for example, the amount of current flowing between the source and drain of these transistors is I ｄｍ and the gate-source voltage of the transistor is V ｇｓｍ When this is the case, the relationship of the following equation (1.2) is satisfied. ｄｍ =I ｘｐ or I ｄｍ =I ｘｎ is exp[V ｇｓｍ ] shall be proportional to

[0205]

[0206] When the reference data r is written to the driving cell IMd, the transistors M1d, M2d, and M4d are turned on so that the potentials of the gate and the first terminal of the transistor M3d are equal to each other. This causes the transistor M3d to be diode-connected, and the amount of analog current I output by the circuit XCDp is increased between the source and drain of the transistor M3d. ｘｐ = rI ＵＴ flows, the gate-source voltage V of the transistor M3d ｇｓｍ Furthermore, since the potential of the source of the transistor M3d is the potential given from the wiring VE1, the potential of the gate of the transistor M3d is determined as follows: ｘｐ, that is, it is determined according to the reference data r. At this time, the potential of the gate of the transistor M3d (potential of the node N1d) is V ｇｍ In addition, since the transistor M1d is in the on state, the potential of the node N2d is also V ｇｍ (r). Also, from the above equation (1.2), I ｘｐ = rI ＵＴ or I ｘｎ = rI ＵＴ is V ｇｍ It is proportional to (r).

[0207] In addition, the calculation cell IMp is ｐ and x ｐ Multiplication and w ｐ and x ｎ and the calculation cell IMn is ｎ and x ｐ Multiplication and w ｎ and x ｎ When performing the multiplication of the above, in the driving cell IMd, the transistors M1d and M2d are turned off and the transistors M4d and M6d are turned on. After that, the circuit XCDp connects the x between the source and drain of the transistor M3d of the driving cell IMd via the wiring XCLp. ｐ Amount I according to ｘｐ An analog current of x flows between the source and drain of the transistor M5d of the driving cell IMd via the wiring XCLn. ｎ Amount I according to ｘｎ The gate potential of the transistor M3d changes due to the capacitive coupling of the capacitive element C1d, so that the gate potential of the transistor M3d changes depending on the amount of analog current I ｘｐ , that is, x ｐ At this time, the gate potential of the transistor M3d is V ｇｍ (x ｐ ), then, from the above equation (1.2), I ｘｐ is V ｇｍ (x ｐ Similarly, the gate potential of the transistor M5d changes due to the capacitive coupling of the capacitive element C2d, and therefore the gate potential of the transistor M5d is proportional to the amount of analog current I ｘｎ , that is, x ｎAt this time, the gate potential of the transistor M3d is V ｇｍ (x ｎ ), then, from the above equation (1.2), I ｘｎ is V ｇｍ (x ｎ ) is proportional to

[0208] In addition, x ｐ When 0, the circuit XCDp outputs V ｇｐ (w ｐ = 1), V ｇｎ (w ｎ = 1) and V ｇｍ (x ｐ It is preferable to output a potential lower than x (=1), a ground potential, or a negative potential. Alternatively, a potential equal to the potential applied by the wiring VE1 may be output. ｎ When V is set to 0, the circuit XCDn outputs V from the output terminal in the same manner as above. ｇｐ (w ｐ = 1), V ｇｎ (w ｎ = 1) and V ｇｍ (x ｎ It is preferable that the circuit XCDp outputs a potential lower than x (=1), a ground potential, or a negative potential. Alternatively, it may output a potential equal to the potential applied by the wiring VE1. ｐ = 0, x ｐ = 0.001 or less, preferably x ｐ = 0.0001 or less, more preferably x ｐ = 0.00001 or less, more preferably x ｐ = 0.000001 or less, more preferably x ｐ = 0.0000001 or less. ｘｐ The same applies to the circuit XCDn.

[0209] The drive circuit WSD is, for example, ｐ and the calculation cell IMp to which w is written. ｎWhen selecting the calculation cell IMn to be written to, the wiring WSL has a function of applying a selection signal to the wiring WSL in order to turn on the transistors M1p, M2p, M1n, and M2n, which are write transistors. ｐ And lol ｎ When the values ​​of the selection signal and the non-selection signal are not written to the calculation cells IMp and IMn, the wiring WSL has a function of supplying a non-selection signal to turn off the transistors M1p, M2p, M1n, and M2n. Note that in the circuit configuration of FIG. 1, the selection signal is preferably set to a high potential and the non-selection signal is preferably set to a low potential.

[0210] Furthermore, since the wiring WSL is also connected to the driver cell IMd, the driver circuit WSD transmits a select signal or a non-select signal to the driver cell IMd at the same time as transmitting the select signal to the processor cells IMp and IMn. As a result, when a select signal is transmitted to the wiring WSL, the write transistors M1d and M2d of the driver cell IMd are also turned on. Furthermore, when a non-select signal is transmitted to the wiring WSL, the transistors M1d and M2d are turned off.

[0211] The driver circuit WROD supplies the w ｐ and writing w to the calculation cell IMn ｎ When writing data, the data is written from the operation cell IMp to the wiring WCLp. ｐ ×x ｐ When a current corresponding to the calculation result of is passed from the calculation cell IMn to the wiring WCLn, ｎ ×x ｐ 1, the selection signal is preferably set to a high potential and the non-selection signal is preferably set to a low potential.

[0212] The driver circuit ROD is connected from the processing cell IMp to the wiring WCLn. ｐ ×x ｎ When a current corresponding to the calculation result of is passed from the calculation cell IMn to the wiring WCLp, ｎ ×x ｎ 1, the selection signal is preferably set to a high potential and the non-selection signal is preferably set to a low potential.

[0213] As shown in FIG. 1 , the drive circuit ITS includes, for example, a circuit ITSpn, a switch SBp, and a switch SBn. The circuit ITSpn includes a first input terminal, a second input terminal, and an output terminal. The first terminal of the switch SBp is connected to the wiring WCLp, the second terminal of the switch SBp is connected to the first input terminal of the circuit ITSpn, and the control terminal of the switch SBp is connected to the wiring SWLB. The first terminal of the switch SBn is connected to the wiring WCLn, the second terminal of the switch SBn is connected to the second input terminal of the circuit ITSpn, and the control terminal of the switch SBn is connected to the wiring SWLB. The output terminal of the circuit ITSpn is connected to the wiring OL.

[0214] For example, the switches applicable to the switches SAp and SAn can be used as the switches SBp and SBn, respectively. Therefore, for the switches SBp and SBn, respectively, the description of the switches SAp and SAn can be referred to.

[0215] The wiring SWLB functions as a wiring for transmitting a signal for controlling the on / off switching of the switches SBp and SBn. For example, a high-level potential or a low-level potential is supplied to the wiring SWLB.

[0216] For example, the circuit ITSpn has a function of performing a function system operation using the difference between the amount of current input to the first input terminal and the amount of current input to the second input terminal as an input value, and also has a function of converting the result of the operation into digital data, an analog potential, or an analog current, and outputting the result to the output terminal.

[0217] Next, examples of the configurations of the drive circuits WCD, XCD, and ITS for driving the computation cells IMp, IMn, and drive cells IMd will be described.

[0218] <<Driver Circuit WCD>> The driver circuit WCD shown in Fig. 1 can have, for example, the configuration shown in Fig. 3A. Note that Fig. 3A also illustrates wiring SWLA, wiring IWLp, and wiring WCLp in order to show connection of the driver circuit WCD with peripheral circuits.

[0219] 3A shows the circuit WCDp and the switch SAp selected from the circuits and circuit elements included in the drive circuit WCD. In the following description of the circuit WCDn and the switch SAn, the circuit WCDp is replaced with the circuit WCDn, the wiring WCLp is replaced with the wiring WCLn, the wiring IWLp is replaced with the wiring IWLn, and ｐ Wow ｎ This is the same as replacing it with

[0220] The circuit WCDp receives digital data w from the wiring IWLp. ｐ Get w ｐ 1, the signal is a current. Therefore, the circuit WCDp preferably includes a digital potential-analog current conversion circuit.

[0221] The circuit WCDp shown in FIG. 3A includes a switch SWW, as an example. A first terminal of the switch SWW is connected to a second terminal of the switch SAp, and the second terminal of the switch SWW is connected to a wiring VINI1. The wiring VINI1 functions as a wiring that applies a fixed potential for initialization to the wiring WCLp, and the initialization potential can be a negative potential, a ground potential (GND), a low-level potential, or a high-level potential. Note that the switch SWW is turned on only when a potential for initialization is applied to the wiring WCLp, and is turned off otherwise. The initialization potential can be a negative potential, a ground potential (GND), a low-level potential, or a high-level potential. ｐ The potential given when w is 0, or ｐ When the potential is zero, it can be set to a potential corresponding to the current that flows.

[0222] Note that the wiring VINI1 may have a function as a wiring that applies a variable potential such as a pulse potential or a clock potential instead of a fixed potential.

[0223] For the switch SWW, for example, a switch applicable to the switch SAp can be used.

[0224] 3A includes a plurality of current sources CS. Ｋ value) (K is an integer of 1 or more) ｐ In this case, the circuit WCDp has a function of outputting 2 Ｋ The circuit WCDp has, for example, one current source CS that outputs the value of the 0th bit as a current, two current sources CS that output the value of the 1st bit as a current, and two current sources CS that output the value of the (K-1)th bit as a current. Ｋ−１ There are individual ones.

[0225] 3A, each current source CS has a terminal T1 and a terminal T2. The terminal T1 of each current source CS is connected to a first terminal of a switch SAp included in the circuit SWCA. The terminal T2 of one current source CS is connected to a wiring DW[0], and each of the terminals T2 of two current sources CS is connected to a wiring DW[1]. Ｋ−１Each of the terminals T2 of the current sources CS is connected to a wiring DW[K-1].

[0226] In particular, the wirings DW[0] to DW[K-1] can be the wiring IWLp shown in Fig. 1. That is, the wiring IWLp can be a wiring group including the wirings DW[0] to DW[K-1].

[0227] The multiple current sources CS included in the circuit WCDp each have the same amount I Ｗｕｔ In reality, during the manufacturing stage of the arithmetic unit CDV, errors may occur due to variations in the electrical characteristics of the transistors included in each current source CS. Therefore, the amount I output from each terminal T1 of the multiple current sources CS may be Ｗｕｔ The error of the constant current is preferably within 10%, more preferably within 5%, and even more preferably within 1%. In this embodiment, the amount I output from the terminal T1 of each of the multiple current sources CS included in the circuit WCDp is Ｗｕｔ The explanation will be given assuming that there is no error in the constant current.

[0228] The wiring DW[0] to the wiring DW[K-1] receive the quantity I from the connected current source CS. Ｗｕｔ The wiring DW[0] functions as a wiring that transmits a control signal for outputting a constant current of I. This allows the circuit WCDp to flow a current of an amount corresponding to K-bit data transmitted from the wirings DW[0] to DW[K-1] to the wiring WCLp. Specifically, for example, when a high-level potential is applied to the wiring DW[0], the current source CS connected to the wiring DW[0] outputs a constant current I Ｗｕｔ flows to the first terminal of the switch SAp, and when a low-level potential is applied to the wiring DW[0], the current source CS connected to the wiring DW[0] flows as follows: Ｗｕｔ For example, when a high-level potential is applied to the wiring DW[1], the two current sources CS connected to the wiring DW[1] output a total of 2I Ｗｕｔ When a constant current of 2I flows through the first terminal of the switch SAp and a low-level potential is applied to the wiring DW[1], the current source CS connected to the wiring DW[1] has a total of 2IＷｕｔ For example, when a high-level potential is applied to the wiring DW[K-1], the constant current of the second Ｋ−１ The current sources CS are a total of 2 Ｋ−１ I Ｗｕｔ When a constant current of 2 flows through the second terminal of the switch SW3 and a low-level potential is applied to the wiring DW[K-1], the current source CS connected to the wiring DW[K-1] has a total of 2 Ｋ−１ I Ｗｕｔ It does not output a constant current.

[0229] The current flowing from one current source CS connected to the wiring DW[0] corresponds to the value of the 0th bit, the current flowing from two current sources CS connected to the wiring DW[1] corresponds to the value of the 1st bit, and the amount of current flowing from K current sources CS connected to the wiring DW[K-1] corresponds to the value of the (K-1)th bit. Now, consider the circuit WCDp when K is 2. For example, when the value of the 0th bit is "1" and the value of the 1st bit is "0", a high-level potential is applied to the wiring DW[0] and a low-level potential is applied to the wiring DW[1]. At this time, a constant current I is supplied from the circuit WCDp to the first terminal of the switch SAp of the circuit SWCA. Ｗｕｔ Furthermore, for example, when the value of the 0th bit is "0" and the value of the 1st bit is "1", a low level potential is applied to the wiring DW[0] and a high level potential is applied to the wiring DW[1]. At this time, a constant current of 2I flows from the circuit WCDp to the first terminal of the switch SAp of the circuit SWCA. Ｗｕｔ Furthermore, for example, when the value of the 0th bit is "1" and the value of the 1st bit is "1", a high-level potential is applied to the wiring DW[0] and the wiring DW[1]. At this time, a constant current of 3I flows from the circuit WCDp to the first terminal of the switch SAp of the circuit SWCA. Ｗｕｔ Furthermore, for example, when the value of the 0th bit is "0" and the value of the 1st bit is "0", a low-level potential is applied to the wiring DW[0] and the wiring DW[1]. At this time, no constant current flows from the circuit WCDp to the first terminal of the switch SAp of the circuit SWCA.

[0230] 3A illustrates the circuit WCDp when K is an integer equal to or greater than 3, but when K is 1, it is preferable that the circuit WCDp in FIG. 3A does not include a current source CS connected to the wirings DW[1] to DW[K-1]. When K is 2, it is preferable that the circuit WCDp in FIG. 3A does not include a current source CS connected to the wirings DW[2] to DW[K-1].

[0231] Next, a specific example of the configuration of the current source CS will be described.

[0232] The current source CS1 shown in FIG. 4A is a circuit that can be applied to the current source CS included in the circuit WCDp of FIG. 3A, and the current source CS1 has a transistor Tr1 and a transistor Tr2.

[0233] A first terminal of the transistor Tr1 is connected to the wiring VEH, and a second terminal of the transistor Tr1 is connected to the gate of the transistor Tr1, the back gate of the transistor Tr1, and the first terminal of the transistor Tr2. A second terminal of the transistor Tr2 is connected to the terminal T1, and a gate of the transistor Tr2 is connected to the terminal T2. The terminal T2 is also connected to the wiring DW.

[0234] The wiring DW is any one of the wirings DW[0] to DW[K-1] in FIG. 3A.

[0235] The wiring VEH functions as a wiring that applies a fixed potential. The fixed potential can be, for example, a high-level potential.

[0236] When the fixed potential applied by the wiring VEH is set to a high-level potential, the high-level potential is input to the first terminal of the transistor Tr1. The potential of the second terminal of the transistor Tr1 is set to a potential lower than the high-level potential. In this case, the first terminal of the transistor Tr1 functions as a drain, and the second terminal of the transistor Tr1 functions as a source. Since the gate and the second terminal of the transistor Tr1 are connected to each other, the gate-source voltage of the transistor Tr1 is 0 V. Therefore, when the threshold voltage of the transistor Tr1 is within an appropriate range, a current in the subthreshold region (source-drain current, subthreshold current) flows between the first and second terminals of the transistor Tr1. The amount of the current flowing per 1 μm of channel width is, for example, 1.0×10 when the transistor Tr1 is an OS transistor. −８ A or less, and 1.0 × 10 −１２ A or less is more preferable, and 1.0 × 10 −１５ A or less is more preferable. Furthermore, for example, it is more preferable that the current is within a range in which it increases exponentially with respect to the gate-source voltage. In other words, the transistor Tr1 functions as a current source for supplying a current in the subthreshold region. The current is assumed to be a current in the subthreshold region for the transistors M3p and M5p included in the processing cell IMp, the transistors M3n and M5n included in the processing cell IMn, and the transistors M3d and M5d included in the driving cell IMd. The current is also assumed to be the current in the subthreshold region for the transistors M3p and M5p included in the processing cell IMp, the transistors M3n and M5n included in the processing cell IMn, and the transistors M3d and M5d included in the driving cell IMd. Ｗｕｔ , or I described below Ｘｕｔ It can be said that:

[0237] The transistor Tr2 functions as a switching transistor. When the potential of the first terminal of the transistor Tr2 is higher than the potential of the second terminal of the transistor Tr2, the first terminal of the transistor Tr2 functions as a drain, and the second terminal of the transistor Tr2 functions as a source. The back gate of the transistor Tr2 and the second terminal of the transistor Tr2 are connected to each other, so the back gate-source voltage is 0 V. Therefore, when the threshold voltage of the transistor Tr2 is within an appropriate range, the transistor Tr2 is turned on when a high-level potential is input to the gate of the transistor Tr2, and is turned off when a low-level potential is input to the gate of the transistor Tr2. Specifically, when the transistor Tr2 is on, the current in the subthreshold region described above flows from the second terminal of the transistor Tr1 to the terminal T1. When the transistor Tr2 is off, the current does not flow from the second terminal of the transistor Tr1 to the terminal T1.

[0238] Note that circuits applicable to the current source CS included in the circuit WCDp of FIG. 3A are not limited to the current source CS1 of FIG. 4A. For example, while the current source CS1 has a configuration in which the back gate of transistor Tr2 and the second terminal of transistor Tr2 are connected to each other, the back gate of transistor Tr2 may be connected to a separate wiring. An example of such a configuration is shown in FIG. 4B. The current source CS2 shown in FIG. 4B has a configuration in which the back gate of transistor Tr2 is connected to wiring VTHL. By connecting wiring VTHL to an external circuit or the like, the current source CS2 can apply a predetermined potential to wiring VTHL via the external circuit or the like, thereby applying the predetermined potential to the back gate of transistor Tr2. This allows the threshold voltage of transistor Tr2 to be varied. In particular, increasing the threshold voltage of transistor Tr2 can reduce the off-state current of transistor Tr2.

[0239] For example, the current source CS1 has a configuration in which the back gate of transistor Tr1 and the second terminal of transistor Tr1 are connected to each other, but a configuration in which a capacitive element maintains a voltage between the back gate and the second terminal of transistor Tr1 may be used. An example of such a configuration is shown in FIG. 4C . The current source CS3 shown in FIG. 4C includes, in addition to transistors Tr1 and Tr2, a transistor Tr3 and a capacitive element C6. The current source CS3 differs from the current source CS1 in that the second terminal of transistor Tr1 is connected to the first terminal of capacitive element C6 and the back gate of transistor Tr1 is connected to the second terminal of capacitive element C6. The current source CS3 has a configuration in which the back gate of transistor Tr1 is connected to the first terminal of transistor Tr3, the second terminal of transistor Tr3 is connected to wiring VTL, and the gate of transistor Tr3 is connected to wiring VWL. The current source CS3 can apply a high-level potential to the line VWL to turn on the transistor Tr3, thereby establishing electrical continuity between the line VTL and the back gate of the transistor Tr1. At this time, a predetermined potential can be input from the line VTL to the back gate of the transistor Tr1. Then, by applying a low-level potential to the line VWL to turn off the transistor Tr3, the capacitor C6 can maintain the voltage between the second terminal of the transistor Tr1 and the back gate of the transistor Tr1. In other words, by determining the potential applied to the back gate of the transistor Tr1 by the line VTL, the threshold voltage of the transistor Tr1 can be varied, and the threshold voltage of the transistor Tr1 can be fixed by the transistor Tr3 and the capacitor C6.

[0240] 4D may be used as the current source CS included in the circuit WCDp of FIG. 3A. The current source CS4 is configured such that the back gate of the transistor Tr2 in the current source CS3 of FIG. 4C is connected to the wiring VTHL instead of the second terminal of the transistor Tr2. In other words, the current source CS4, like the current source CS2 of FIG. 4B, can vary the threshold voltage of the transistor Tr2 depending on the potential provided by the wiring VTHL.

[0241] In the current source CS4, when a large current flows between the first and second terminals of the transistor Tr1, it is necessary to increase the on-current of the transistor Tr2 in order to pass the current from the terminal T1 to the outside of the current source CS4. In this case, the current source CS4 applies a high-level potential to the wiring VTHL to lower the threshold voltage of the transistor Tr2 and increase the on-current of the transistor Tr2, thereby allowing the large current flowing between the first and second terminals of the transistor Tr1 to flow from the terminal T1 to the outside of the current source CS4.

[0242] By applying any one of the current sources CS1 to CS4 shown in FIGS. 4A to 4D as the current source CS included in the circuit WCDp of FIG. 3A, the circuit WCDp can generate a K-bit w ｐ The amount of the current can be, for example, the amount of current flowing between the source and drain of the transistor M3p and the transistor M5p included in the operation cell IMp within the range in which they operate in the subthreshold region.

[0243] 3B may be used as the circuit WCDp of Fig. 3A. The circuit WCDp of Fig. 3B has a configuration in which the current source CS of Fig. 4A is connected to each of the wirings DW[0] to DW[K-1]. When the channel width of the transistor Tr1[0] is w[0], the channel width of the transistor Tr1[1] is w[1], and the channel width of the transistor Tr1[K-1] is w[K-1], the ratio of the channel widths is w[0]:w[1]:w[K-1]=1:2:2. Ｋ−１ Since the source-drain current of a transistor in the subthreshold region is proportional to the channel width, the circuit WCDp shown in FIG. 3B is a K-bit w ｐ It is possible to output a current according to the

[0244] Note that the transistors Tr1 (including transistors Tr1[0] to Tr1[K-1]), Tr2 (including transistors Tr2[0] to Tr2[K-1]), and Tr3 can be, for example, transistors that can be used for the transistors M1p, M6p, M1n, M6n, M1d, or M6d. In particular, OS transistors are preferably used for the transistors Tr1 (including transistors Tr1[0] to Tr1[K-1]), Tr2 (including transistors Tr2[0] to Tr2[K-1]), and Tr3.

[0245] In particular, the circuits shown in FIGS. 3A and 3B are sometimes called K-bit current ladder type DACs (Digital to Analog Converters), which are a type of digital potential-analog current conversion circuit.

[0246] 3B may be modified to a CMOS circuit configuration including n-channel transistors and p-channel transistors. For example, the circuit WCDp in FIG. 3A may be modified to a circuit configuration shown in FIG.

[0247] The circuit WCDp shown in Figure 5 has a circuit configuration including n-channel transistors and p-channel transistors, and is an example of a configuration of a K-bit current-type ladder DAC. The circuit WCDp has K current sources CS and a current mirror circuit CRM. The current source CS shown in Figure 5 differs from each of the current sources CS1 to CS4 shown in Figures 4A to 4D in terms of connection configuration.

[0248] Next, each current source CS shown in FIG. 5 will be described.

[0249] A first terminal of the transistor Tr1[0] is connected to the wiring VSSL, a second terminal of the transistor Tr1[0] is connected to the first terminal of the transistor Tr2[0], and a gate of the transistor Tr1[0] is connected to the wiring BIS. Also, a gate of the transistor Tr2[0] is connected to the wiring DW[0].

[0250] Similarly, a first terminal of the transistor Tr1[1] is connected to the wiring VSSL, a second terminal of the transistor Tr1[1] is connected to the first terminal of the transistor Tr2[1], and a gate of the transistor Tr1[1] is connected to the wiring BIS. Also, a gate of the transistor Tr2[1] is connected to the wiring DW[1].

[0251] Similarly, a first terminal of the transistor Tr1[K-1] is connected to the wiring VSSL, a second terminal of the transistor Tr1[K-1] is connected to the first terminal of the transistor Tr2[K-1], and a gate of the transistor Tr1[K-1] is connected to the wiring BIS. Also, a gate of the transistor Tr2[K-1] is connected to the wiring DW[K-1].

[0252] Further, second terminals of the transistors Tr2[0] to Tr2[K-1] are connected to a terminal CTi of a current mirror circuit CRM, which will be described later.

[0253] In FIG. 5, the channel widths of the transistors Tr1[0] to Tr1[K-1] can be determined by referring to the description of the transistors Tr1[0] to Tr1[K-1] in FIG. 3B.

[0254] 5, the transistors Tr2[0] to Tr2[K-1] function as transistors capable of adjusting the amount of current flowing between the source and drain of each of the transistors Tr1[0] to Tr1[K-1]. Therefore, the wiring BIS functions as a wiring that applies a fixed potential. Note that the fixed potential may be a high-level potential, a positive potential, or the like. Depending on the situation, the fixed potential may also be a low-level potential, a ground potential, a negative potential, or the like.

[0255] For example, the wiring VSSL functions as a wiring that applies a fixed potential. The fixed potential can be, for example, a low-level potential, a ground potential, a negative potential, or the like. Depending on the situation, the fixed potential may be a high-level potential. For example, the wiring VSSL may also function as a wiring that applies a variable potential such as a pulse potential or a clock potential instead of a fixed potential.

[0256] Each current source CS shown in FIG. 5 has the above-described connection configuration, and therefore functions as a current sink circuit that causes a current to flow from the terminal T1 of the current source CS to the wiring VSSL via the transistor Tr1 and the transistor Tr2.

[0257] Next, the current mirror circuit CRM will be described.

[0258] The current mirror circuit CRM has a terminal CTi that functions as an input terminal and a terminal CTo that functions as an output terminal. Ideally, the current mirror circuit CRM has a function of outputting a current to the terminal CTo that is equal to the amount of current flowing through the terminal CTi.

[0259] The current mirror circuit CRM includes a transistor Tr5, a transistor Tr5m, a transistor Tr6, and a transistor Tr6m.

[0260] The first terminal of transistor Tr5 is connected to terminal CTi, the gate of transistor Tr6, and the gate of transistor Tr6m. The second terminal of transistor Tr5 is connected to the first terminal of transistor Tr6. The gate of transistor Tr5 is connected to the gate of transistor Tr5m and the wiring CPE. The second terminal of transistor Tr6 is connected to the wiring VEH. The first terminal of transistor Tr5m is connected to terminal CTo. The second terminal of transistor Tr5m is connected to the first terminal of transistor Tr6m. The second terminal of transistor Tr6m is connected to the wiring VEH.

[0261] For the wiring VEH, reference can be made to the description of the wiring VEH shown in FIG. 3A.

[0262] For example, the wiring CPE functions as a wiring that applies a fixed potential. The fixed potential may be a low-level potential, a ground potential, a negative potential, or the like. Depending on the situation, the fixed potential may be a high-level potential, or the like. For example, the wiring CPE may also function as a wiring that applies a variable potential such as a pulse potential or a clock potential instead of a fixed potential.

[0263] In the current mirror circuit CRM, the second terminals of the transistors Tr6 and Tr6m are connected such that a potential is applied from the wiring VDDL, and the gates of the transistors Tr6 and Tr6m are connected such that a potential of the terminal CTi is applied. Ideally, therefore, equal amounts of current flow between the source and drain of the transistors Tr6 and Tr6m.

[0264] Furthermore, transistor Tr5 functions as a transistor cascode-connected to transistor Tr6. Similarly, transistor Tr5m functions as a transistor cascode-connected to transistor Tr6m. This prevents the potential of terminal CTi from being directly input to the first terminal of transistor Tr6. In other words, this prevents the potential of the first terminal of transistor Tr6 from suddenly fluctuating, thereby stabilizing the operation of the current mirror circuit CRM.

[0265] <<Driver Circuit XCD>> The driver circuit XCD shown in Fig. 1 can have, for example, the configuration shown in Fig. 3C. Note that Fig. 3C also illustrates wiring IXLp and wiring XCLp in order to show the connection of the driver circuit XCD with peripheral circuits.

[0266] 3C shows an excerpt of the circuit XCDp from among the circuits included in the drive circuit XCD. In the following description of the circuit XCDn, the circuit XCDp will be replaced with the circuit XCDn, the wiring XCLp with the wiring XCLn, the wiring IXLp with the wiring IXLn, and the x ｐ x ｎ This is the same as replacing it with

[0267] 3C has a function of supplying a signal corresponding to the second data x to the wiring XCL. Note that in the case of the arithmetic unit CDV in FIG. 1, the signal can be a current.

[0268] The circuit XCDp shown in FIG. 3C includes a switch SWX, for example. A first terminal of the switch SWX is connected to the wiring XCLp, and a second terminal of the switch SWX is connected to the wiring VINI2. The wiring VINI2 functions as a wiring that applies an initialization potential to the wiring XCLp, and the initialization potential can be a negative potential, a ground potential (GND), a low-level potential, or a high-level potential. The initialization potential applied by the wiring VINI2 may be approximately equal to the potential applied by the wiring VINI1. Note that the switch SWX is turned on only when an initialization potential is applied to the wiring XCLp, and is turned off otherwise. The initialization potential can be a negative potential, a ground potential (GND), a low-level potential, or a high-level potential. ｐ The potential given when x is 0, or ｐ When the potential is zero, it can be set to a potential corresponding to the current that flows.

[0269] The switch SWX may be, for example, a switch applicable to the switch SAp.

[0270] The circuit configuration of the circuit XCDp in Fig. 3C can be substantially the same as that of the circuit WCDp in Fig. 3A. Specifically, the circuit XCDp has a function of outputting reference data as a current amount and a function of outputting L bits (2 Ｌ value) (L is an integer of 1 or more) ｐ In this case, the circuit XCDp has a function of outputting 2 Ｌ The circuit XCDp has one current source CS that outputs the value of the 0th bit as a current, two current sources CS that output the value of the 1st bit as a current, and two current sources CS that output the value of the (L-1)th bit as a current. Ｌ−１ There are individual ones.

[0271] Incidentally, when the reference data output as a current from the circuit XCDp is set to 1, for example, the value of the 0th bit can be set to "1" and the values ​​of the 1st and subsequent bits can be set to "0".

[0272] In FIG. 3C, the terminal T2 of one current source CS is connected to the wiring DX[0], and each of the terminals T2 of the two current sources CS is connected to the wiring DX[1]. Ｌ−１ Each of the terminals T2 of the current sources CS is connected to the wiring DX[L-1].

[0273] In particular, the wirings DX[0] to DX[L-1] can be the wiring IXLp shown in Fig. 1. That is, the wiring IXLp can be a wiring group including the wirings DX[0] to DX[L-1].

[0274] The multiple current sources CS included in the circuit XCDp each have the same constant current I Ｘｕｔ from the terminal T1. The wirings DX[0] to DX[L-1] are connected to the current source CS and output I Ｘｕｔ This allows the circuit XCDp to pass, to the wiring XCLp, an amount of current corresponding to the L-bit data transmitted from the wirings DX[0] to DX[L-1].

[0275] Specifically, consider the circuit XCDp when L is set to 2. For example, when the value of the 0th bit is "1" and the value of the 1st bit is "0", a high-level potential is applied to the wiring DX[0] and a low-level potential is applied to the wiring DX[1]. At this time, a constant current I is supplied from the circuit XCDp to the wiring XCLp. Ｘｕｔ Furthermore, for example, when the value of the 0th bit is "0" and the value of the 1st bit is "1", a low level potential is applied to the wiring DX[0] and a high level potential is applied to the wiring DX[1]. At this time, a constant current of 2I flows from the circuit XCDp to the wiring XCLp. Ｘｕｔ Furthermore, for example, when the value of the 0th bit is "1" and the value of the 1st bit is "1", a high-level potential is applied to the wiring DX[0] and the wiring DX[1]. At this time, a constant current of 3I flows from the circuit XCDp to the wiring XCLp. Ｘｕｔflows. Also, for example, when the value of the 0th bit is "0" and the value of the 1st bit is "0", a low-level potential is applied to the wiring DX[0] and the wiring DX[1]. At this time, no constant current flows from the circuit XCDp to the wiring XCLp. Note that in this specification, this may be rephrased as a current of zero amount flows from the circuit XCDp to the wiring XCLp. Also, the current of zero amount, I, output from the circuit XCDp Ｘｕｔ , 2I Ｘｕｔ , 3I Ｘｕｔ and the like are x, one of the two parameters expressing the second data x output by the circuit XCDp. ｐ It can be said that:

[0276] In addition, when an error occurs due to variations in the electrical characteristics of the transistors included in each current source CS of the circuit XCDp, the amount I Ｘｕｔ The error of the constant current is preferably within 10%, more preferably within 5%, and even more preferably within 1%. In this embodiment, the amount I output from the terminal T1 of each of the multiple current sources CS included in the circuit XCDp is Ｘｕｔ In this embodiment, the constant current I is output from the terminal T1 of each of the multiple current sources CS included in the circuit XCDp. Ｘｕｔ The explanation will be given assuming that there is no error in the constant current.

[0277] 4A to 4D can be applied as the current source CS of the circuit XCDp, similarly to the current source CS of the circuit WCDp. In this case, by replacing the wiring DW with the wiring DX in the description of the current sources CS1 to CS4 of FIGS. 4A to 4D, the description can be made as a description of the current source CS used in the circuit XCDp. As a result, the circuit XCDp can generate the reference data or the L-bit x data by using any of the current sources CS1 to CS4 of FIGS. 4A to 4D. ｐ As a result, a current in the subthreshold region can be passed through the wiring XCLp.

[0278] 3C can be applied to the circuit XCDp of Fig. 3B . In this case, in the description of the circuit WCDp of Fig. 3B , by replacing the circuit WCDp with the circuit XCDp, the wiring DW[0] with the wiring DX[0], the wiring DW[1] with the wiring DX[1], the wiring DW[K-1] with the wiring DX[L-1], the switch SWW with the switch SWX, and the wiring VINI1 with the wiring VINI2, the description can be interpreted as a description of the circuit XCDp having the same circuit configuration as that of Fig. 3B .

[0279] 3C can have the same circuit configuration as the circuit WCDp shown in Fig. 5. In this case, in the description of the circuit WCDp in Fig. 5, by replacing the circuit WCDp with the circuit XCDp, the wiring DW[0] with the wiring DX[0], the wiring DW[1] with the wiring DX[1], and the wiring DW[K-1] with the wiring DX[L-1], the description can be interpreted as a description of the circuit XCDp having the same circuit configuration as that in Fig. 5.

[0280] <<Driver Circuit WSD>> The driver circuit WSD shown in FIG. ｐ and writing w to the calculation cell IMn ｎand when writing reference data r to the driver cell IMd, the driver circuit WSD supplies a predetermined signal to the wiring WSL to turn on the write transistors included in each of the processor cells IMp, IMn, and driver cell IMd. That is, the driver circuit WSD functions as a write word line driver circuit for the processor cells IMp, IMn, and driver cell IMd. For example, the driver circuit WSD can turn on the transistors M1p and M2p included in the processor cell IMp, the transistors M1n and M2n included in the processor cell IMn, and the transistors M1d and M2d included in the driver cell IMd by supplying a high-level potential as a selection signal to the wiring WSL. Furthermore, by the driver circuit WSD supplying a low-level potential as a non-selection signal to the wiring WSL, the transistors M1p and M2p included in the processing cell IMp, the transistors M1n and M2n included in the processing cell IMn, and the transistors M1d and M2d included in the driving cell IMd can be turned off. As described above, by the driver circuit WSD transmitting a selection signal or a non-selection signal to the wiring WSL, it is possible to select either writing data or retaining data in each of the processing cells IMp, IMn, and driving cell IMd.

[0281] 1 can have, for example, the configuration shown in Fig. 6A . Note that Fig. 6A also illustrates wiring SWLB, wiring WCLp, wiring WCLn, and wiring OL to show connections of the driver circuit ITS with peripheral circuits.

[0282] The circuit SWCB shown in Fig. 6A is an example of a circuit configuration that can be applied to the circuit SWCB shown in Fig. 1. The circuit ITSpn shown in Fig. 6A is an example of a circuit configuration that can be applied to the circuit ITSpn shown in Fig. 1.

[0283] As described above, the circuit ITSpn shown in FIG. 6A has a current flowing through the wiring WCLp. ＳＰ and the amount of current I flowing through the wiring WCLn. ＳＮand a circuit for calculating a difference between the input current and the output current and for calculating a function system (e.g., a nonlinear function system) by substituting the difference as a variable, and an analog-to-digital conversion circuit. In particular, the circuit for calculating the function system preferably has a function for calculating the function system using, as an input value, a value corresponding to the amount of input current, and outputting digital data (e.g., a digital potential) corresponding to the result of the calculation.

[0284] 6A includes, for example, a circuit RL and an analog-to-digital conversion circuit ATDC. The circuit RL includes, for example, a terminal RTip, a terminal RTin, and a terminal RTo.

[0285] A second terminal of the switch SBp is connected to a terminal RTip of the circuit RL via a first input terminal of the circuit ITSpn. A second terminal of the switch SBn is connected to a terminal RTin of the circuit RL via a second input terminal of the circuit ITSpn. A terminal RTo of the circuit RL is connected to an input terminal of the analog-digital conversion circuit ATDC, and an output terminal of the analog-digital conversion circuit ATDC is connected to a wiring OL via an output terminal of the circuit ITSpn.

[0286] The circuit RL preferably includes a circuit that obtains the difference between the amounts of two input currents and a function-based calculation circuit. The function-based calculation circuit may be an activation function used in an artificial neural network model. Examples of the activation function include a nonlinear function such as a sigmoid function, a tanh function, a softmax function, a ReLU function, or a threshold function. The circuit RL may also include a circuit that performs pooling processing instead of the function-based calculation circuit. In the circuit configuration shown in FIG. 6A , the circuit RL preferably outputs a digital potential from the terminal RTo.

[0287] The circuit RL may also include a current-voltage conversion circuit. When the circuit RL includes a current-voltage conversion circuit, the circuit RL may, for example, ＳＰ and the amount of current I flowing through the wiring WCLn. ＳＮIt is preferable to generate an analog potential corresponding to the difference current between and and output it to the terminal RTo of the circuit RL.

[0288] The analog-to-digital converter circuit ATDC preferably converts an analog potential supplied from the terminal RTo of the circuit RL into a digital signal and outputs the digital signal to the wiring OL.

[0289] 6B shows an example of the configuration of the drive circuit ITS when the circuit RL includes a current-voltage conversion circuit. The circuit RL shown in FIG. 6B includes, as an example, loads LEp1, LEp2, LEn1, LEn2, and a differential amplifier circuit OP.

[0290] The differential amplifier circuit OP is an amplifier circuit having an inverting input terminal, a non-inverting input terminal, and an output terminal. For example, an operational amplifier can be used as the differential amplifier circuit OP.

[0291] The non-inverting input terminal of the differential amplifier circuit OP is connected to the first terminal of the load LEp1 and the first terminal of the load LEp2. The inverting input terminal of the differential amplifier circuit OP is connected to the first terminal of the load LEn1 and the first terminal of the load LEn2. The output terminal of the differential amplifier circuit OP is connected to the second terminal of the load LEn2 and the terminal RTo. The second terminal of the load LEp1 is connected to the second terminal of the switch SBp, the second terminal of the load LEp2 is connected to the wiring VRL, and the second terminal of the load LEn1 is connected to the second terminal of the switch SBn.

[0292] The wiring VRL functions as a wiring that applies a fixed potential, which may be, for example, a ground potential (GND) or a low-level potential.

[0293] In particular, since the differential amplifier circuit OP is configured as a negative feedback circuit (the output terminal of the differential amplifier circuit OP is connected to the inverting input terminal of the differential amplifier circuit OP via the load LEn2), the inverting input terminal and the non-inverting input terminal of the differential amplifier circuit OP are virtually short-circuited to each other.

[0294] When the resistance values ​​of the loads LEp1, LEp2, LEn1, and LEn2 are equal to each other, the potential of the non-inverting input terminal is V ＋ and the inverting input terminal V − The potential of V − and the potential of the output terminal is V ｏｕｔ By doing so, V ｏｕｔ =V ＋ -V − Also, when the resistance value is R, V ｏｕｔ =V ＋ -V − = R(I ＳＰ -I ＳＮ That is, the amount of current I flowing through the wiring WCLp due to the circuit RL can be expressed as ＳＰ and the amount of current I flowing through the wiring WCLn. ＳＮ The difference current between these two can be converted into an analog potential according to the amount.

[0295] 6B, the driver circuit ITS can output to the terminal RTo an analog potential corresponding to the difference between the currents flowing through the wirings WCLp and WCLn. The analog potential can be converted into a digital signal by the analog-to-digital converter ATDC and output to the wiring OL.

[0296] Note that, when the driver circuit ITS outputs an analog current rather than a digital signal to the wiring OL, the circuit ITSpn does not need to include an analog-digital conversion circuit ATDC, as in the driver circuit ITS shown in FIG. 6C . Also, in FIG. 6C , the circuit RL preferably performs a function calculation in which the difference between the amount of current flowing through the terminal RTip and the amount of current flowing through the terminal RTin is assigned as a variable, and outputs the result of the calculation as an analog current to the terminal RTo. Furthermore, by passing the analog current resulting from the calculation output from the terminal RTo, for example, through the wiring XCLp or XCLn of another calculation unit CDV, another calculation can be performed using the result of the calculation. This corresponds to sending the calculation result to the next fully connected layer in a multilayer perceptron, a type of artificial neural network. By directly using the analog current resulting from the calculation in the next calculation, analog-to-digital conversion and digital-to-analog current conversion are unnecessary, and these conversion circuits can be omitted. This makes it possible to reduce the circuit area of ​​the arithmetic unit CDV and also to reduce the power consumption required for the conversion circuit.

[0297] Next, a specific example of the configuration of the circuit RL included in the circuit ITSpn in FIG. 6A or FIG. 6C will be described.

[0298] FIG. 7 is a circuit diagram showing, as an example, a specific configuration of the circuit RL included in the circuit ITSpn of FIG. 6A or 6C, and the circuit RL of FIG. 7 has a function of performing the calculation of the ReLU function.

[0299] The circuit RL shown in FIG. 7 includes, as an example, transistors MP1i, MP1o, MP2i, MP2o, MP3i, MP3o, MP4i, MP4o, MN1i, MN1o, MN2i, and MN2o.

[0300] 7, a first current mirror circuit is formed by p-channel transistors MP1i, MP2i, MP1o, and MP2o, a second current mirror circuit is formed by n-channel transistors MN1i, MN2i, MN1o, and MN2o, and a third current mirror circuit is formed by p-channel transistors MP3i, MP4i, MP3o, and MP4o.

[0301] Furthermore, since the circuit RL includes a first current mirror circuit to a third current mirror circuit, the circuit RL is sometimes called a three-stage current mirror circuit.

[0302] The drain of the transistor MP1i is connected to the terminal RTip, the drain of the transistor MP1o is connected to the terminal RTin and the drain of the transistor MN2i, and the drain of the transistor MN2o is connected to the drain of the transistor MP3i, and the transistor MP3o is connected to the terminal RTo.

[0303] The first current mirror circuit ideally has the function of passing a current between the source and drain of transistor MP2o that is equal to the source-drain current corresponding to the gate-source voltage of transistor MP2i. Similarly, the second current mirror circuit ideally has the function of passing a current between the source and drain of transistor MN1o that is equal to the source-drain current corresponding to the gate-source voltage of transistor MN1i. Similarly, the third current mirror circuit ideally has the function of passing a current between the source and drain of transistor NP4o that is equal to the source-drain current corresponding to the gate-source voltage of transistor MP4i.

[0304] In the first current mirror circuit, transistor MP1i functions as a clamp transistor to prevent a decrease in the threshold voltage of transistor MP2i due to DIBL. Similarly, transistor MP1o also functions as a clamp transistor to prevent a decrease in the threshold voltage of transistor MP2o due to DIBL. Therefore, wiring RSWL1 that applies a desired bias potential is connected to the gates of transistor MP1i and transistor MP1o.

[0305] In the second and third current mirror circuits, the transistors MN2i, MN2o, MP3i, and MP3o also function as clamp transistors to prevent a decrease in the threshold voltage of the transistors connected in series by DIBL. In this case, the wirings RSWL2 and RSWL3 each function as wirings that apply a desired bias potential.

[0306] Note that the bias potentials applied by the wirings RSWL1 to RSWL3 can be made equal to each other. Therefore, the wirings RSWL1 to RSWL3 can be the same wiring. The ratio of the bias potential applied by one selected from the wirings RSWL1 to RSWL3 to the bias potential applied by the remaining two is preferably 0.9 to 1.1, more preferably 0.95 to 1.05, and even more preferably 0.99 to 1.01.

[0307] Each of the transistors MP1i and MP1o can function as a switching transistor. In this case, the wiring RSWL1 preferably functions as a wiring for controlling the switching between the on state and the off state of each of the transistors MP1i and MP1o. Furthermore, by turning off the transistors MP1i and MP1o, the first current mirror circuit can be stopped, thereby reducing power consumption in the circuit RL.

[0308] Similarly, since the transistors MN2i and MN2o each function as a switching transistor, the second current mirror circuit can be stopped at a desired timing. In this case, it is preferable that the wiring RSWL2 function as a wiring for controlling the switching between the on state and the off state of the transistors MN2i and MN2o. Similarly, since the transistors MP3i and MP3o each function as a switching transistor, the third current mirror circuit can be stopped at a desired timing. In this case, it is preferable that the wiring RSWL3 function as a wiring for controlling the switching between the on state and the off state of the transistors MP3i and MP3o.

[0309] Note that the transistors MP1i and MP1o, and the transistors MP3i and MP3o can be simultaneously turned on or off. Therefore, the wiring RSWL1 and the wiring RSWL3 can be the same wiring.

[0310] In the first current mirror circuit, the source of the transistor MP2i and the source of the transistor MP2o are each connected to the wiring VDDL. The first current mirror circuit is configured with p-channel transistors, and therefore also functions as a current source circuit. Therefore, the wiring VDDL functions as a wiring that provides a high-level potential as a high power supply potential for the first current mirror circuit. Similarly, the third current mirror also functions as a current source circuit, and therefore, the high-level potential provided by the wiring VDDL also functions as a high power supply potential for the third current mirror circuit.

[0311] In the second current mirror circuit, the source of the transistor MN1i and the source of the transistor MN1o are connected to a wiring VSSL. The second current mirror circuit is configured with n-channel transistors, and therefore also functions as a current sink circuit. Therefore, the wiring VSSL functions as a wiring that applies a low-level potential as a low power supply potential of the second current mirror circuit.

[0312] When a high-level potential is applied to the wiring SWLB, the high-level potential is applied to the control terminals of the switches SBp and SBn, turning the switches SBp and SBn on. At this time, the wiring WCLp is supplied with a quantity I ＳＰ A current of a quantity I ＳＮ A current of flows.

[0313] Therefore, a quantity I is supplied from the wiring VDDL to the wiring WCLp via the transistor MP2i, the transistor MP1i, the terminal RTip, and the switch SBp. ＳＰ Therefore, the amount of the source-drain current of the transistor MP2o is also I ＳＰ This becomes:

[0314] At the connection point between the transistor MP1o and the terminal RTin, a source-drain current of the transistor MP2o flows in, and a quantity I ＳＮ and the source-drain current of the transistor MN1i in the second current mirror circuit. Therefore, according to Kirchhoff's current law, ＳＰ =I ＳＮ +I Ｓ is established. Note that I Ｓ is the amount of current flowing between the source and drain of the transistor MN1i. Therefore, the amount of source-drain current of the transistor MN1o is also I Ｓ This becomes:

[0315] In addition, the amount of source-drain current of the transistor MN1o is I Ｓ Therefore, the amount of source-drain current of the transistor MP4i is also I Ｓ Therefore, the amount of source-drain current of the transistor MP4o is also I Ｓ and the terminal RTo is charged with the quantity I ＳA current of flows.

[0316] The circuit RL is I ＳＰ Ga I ＳＮ If it is greater than , the difference is the amount I Ｓ A current of I flows through the terminal RTo. ＳＰ Ga I ＳＮ When the current flowing between the source and drain of the transistor MP2o increases, the current flowing between the source and drain of the transistor MP2o decreases to I ＳＮ This is equivalent to I Ｓ = 0. In this case, no current flows from the terminal RTo of the circuit RL. In other words, the circuit RL shown in FIG. 7 can perform the calculation of the ReLU function.

[0317] Next, an example of the configuration of a circuit that is different from the circuit ITSpn of FIG. 7 and that can be applied to the circuit ITSpn of the arithmetic unit CDV of FIG. 1 will be described.

[0318] 8 has a function of obtaining a difference between the currents flowing through the wirings WCLp and WCLn and outputting a value corresponding to the difference as digital data. The circuit ITSpn shown in FIG. 8 is also sometimes called a successive approximation register (SAR) type ADC (analog to digital converter).

[0319] As an example, the circuit ITSpn shown in FIG. 8 includes transistors MP5i, MP6i, MP5o, and MP6o included in a fourth current mirror circuit, and transistors MP7i, MP8i, MP7o, and MP8o included in a fifth current mirror circuit.

[0320] 8 includes a first digital potential-analog current converter circuit and a second digital potential-analog current converter circuit. The first digital potential-analog current converter circuit includes transistors Tp1[0] to Tp1[M-1] (M is an integer greater than or equal to 1) and transistors Mp2[0] to Tp2[M-1]. The second digital potential-analog current converter circuit includes transistors Tn1[0] to Tn1[M-1] and transistors Mn2[1] to Tn2[M-1].

[0321] Note that the transistors Tp1[s] (here, s is an integer greater than or equal to 0 and less than or equal to M-1) and the transistor Tp2[s] each have the same function as the transistors Tr1 and Tr2 included in the current source CS shown in FIG. 5 . The transistors Tn1[s] and Tn2[s] also have the same function as the transistors Tr1 and Tr2 included in the current source CS shown in FIG. 5 . For example, the transistors Tp1[0] to Tp1[M-1] and the transistors Tn1[0] to Tn1[M-1] each function as a transistor that passes a constant current according to the channel width. For example, the transistors Tp2[0] to Tp2[M-1] and the transistors Tn2[0] to Tn2[M-1] each function as a switching transistor.

[0322] Here, when the channel width of the transistors Tp1[0] and Tn1[0] is w[0], the channel width of the transistors Tp1[1] and Tn1[1] is w[1], and the channel width of the transistors Tp1[M-1] and Tn1[M-1] is w[M-1], the ratio of the respective channel widths is w[0]:w[1]:w[M-1]=1:2:2. Ｍ−１ Let's say.

[0323] 8 includes a comparator CPR and a logic circuit LGC. The logic circuit LGC includes a terminal LTi, a terminal LFTp, a terminal LFTn, and a terminal LTo.

[0324] A first terminal of the transistor MP5i is connected to the terminal RTip, the gate of the transistor MP6i, the gate of the transistor MP6o, and the first terminals of the transistors Tp2[0] to Tp2[M-1]. A second terminal of the transistor MP5i is connected to the first terminal of the transistor MP6i, and a gate of the transistor MP5i is connected to the gate of the transistor MP5o and the wiring RSWLp.

[0325] A first terminal of the transistor MP7i is connected to the terminal RTin, the gate of the transistor MP8i, the gate of the transistor MP8o, and the first terminals of the transistors Tn2[0] to Tn2[M-1]. A second terminal of the transistor MP7i is connected to the first terminal of the transistor MP8i, and a gate of the transistor MP7i is connected to the gate of the transistor MP7o and the wiring RSWLn.

[0326] For the wirings RSWLp and RSWLn, the description of the wirings RSWL1 to RSWL3 shown in FIG. 7 can be referred to.

[0327] A first terminal of the transistor MP5o is connected to a first terminal of the comparator CPR, a second terminal of the transistor MP5o is connected to a first terminal of the transistor MP6o, a first terminal of the transistor MP7o is connected to a second terminal of the comparator CPR, and a second terminal of the transistor MP7o is connected to a first terminal of the transistor MP8o. In addition, second terminals of the transistors MP6i, MP6o, MP8i, and MP8o are connected to the wiring VDDL.

[0328] For the wiring VDDL, the description of the wiring VDDL shown in FIG. 7 can be referred to.

[0329] The second terminal of the transistor Tp2[s] is connected to the first terminal of the transistor Tp1[s]. The gates of the transistors Tp2[0] to Tp2[M-1] are connected to the terminal LFTp of the logic circuit LGC. The second terminals of the transistors Tp1[0] to Tp1[M-1] are connected to the wiring VSSL. The gates of the transistors Tp1[0] to Tp1[M-1] are connected to the wiring VFE.

[0330] The second terminal of the transistor Tn2[s] is connected to the first terminal of the transistor Tn1[s]. The gates of the transistors Tn2[0] to Tn2[M-1] are connected to the terminal LFTn of the logic circuit LGC. The second terminals of the transistors Tn1[0] to Tn1[M-1] are connected to the wiring VSSL. The gates of the transistors Tn1[0] to Tn1[M-1] are connected to the wiring VFE.

[0331] For the wiring VSSL, the description of the wiring VSSL shown in Fig. 7 can be referred to. For the wiring VFE, the description of the wiring BIS shown in Fig. 5 can be referred to.

[0332] The output terminal of the comparator CPR is connected to the terminal LTi of the logic circuit LGC, and the terminal LTo of the logic circuit LGC is connected to the terminal RTo. ＦＳｐ The amount of current I input to the second input terminal is ＦＳｎ When is small, the amount of current I input to the first input terminal ＦＳｐ and the amount of current I input to the second input terminal ＦＳｎ When the values ​​of I and I are equal, a high level potential is output to the output terminal, or the amount of current I input to the first input terminal is ＦＳｐ The amount of current I input to the second input terminal is ＦＳｎ When the voltage Vcc is large, the output terminal has a function of outputting a low level potential.

[0333] The logic circuit LGC has the function of obtaining the comparison result of the comparator CPR from the terminal LTi, and outputting a digital signal Q to each of the terminals LFTp and LFTn according to the comparison result, and the function of outputting digital data to the terminal LTo according to the comparison result.

[0334] Next, an example of the operation of the circuit ITSpn in FIG. 8 will be described, including the detailed operation of the logic circuit LGC.

[0335] 9 is a timing chart showing an example of the operation of the circuit ITSpn in FIG. 8. The timing chart in FIG. 9 shows the current I ＳＰ is the current I input to the terminal RTin ＳＮ This is an example of operation when the current amount I is larger than ＦＳｐ and current I ＦＳｎ , the fluctuation of the potential input to the terminal LTi in the logic circuit LGC, and the fluctuation of the logic of the signal Q output from the terminal LFTp. ＦＳｐ is the amount of current input to the first input terminal of the comparator CPR, and the current amount I ＦＳｎ is the amount of current input to the second input terminal of the comparator CPR.

[0336] In the timing chart of Fig. 9, the ordinal number M described in the circuit ITSpn of Fig. 8 is 8. In this case, the resolution of each of the first digital potential-analog current conversion circuit and the second digital potential-analog current conversion circuit is 8 bits. Furthermore, the amount of current output by each of the first digital potential-analog current conversion circuit and the second digital potential-analog current conversion circuit is, for example, in the range from 0 nA to 255 nA in increments of 1 nA.

[0337] Furthermore, the logic of the b-th bit (b is an integer between 0 and 7) of the digital signal Q output from the logic circuit LGC to each of the terminals LFTp and LFTn is defined as Q[b].

[0338] During the period T0, the logic circuit LGC outputs (00000000) as 8-bit digital signals Qp and Qn to the terminals LFTp and LFTn, respectively. ２ As a result, a low-level potential is input to the gates of the transistors Tp2[0] to Tp2[7] of the first digital potential-analog current converter circuit, turning the transistors Tp2[0] to Tp2[7] off. Similarly, a low-level potential is input to the gates of the transistors Tn2[0] to Tn2[7] of the second digital potential-analog current converter circuit, turning the transistors Tn2[0] to Tn2[7] off.

[0339] At this time, the terminal RTip receives the amount I from the cell array CA. ＳＰ A current of I flows from the cell array CA to the terminal RTin. ＳＮ Here, a current of I ＳＰ = 203 nA, and I ＳＮ At this time, the first input terminal of the comparator CPR is supplied with a quantity I ＳＰ A current of the magnitude I flows through the second input terminal of the comparator CPR. ＳＮ At this time, a current of I ＦＳｐ I ＦＳｎ Therefore, the comparator CPR outputs a high-level potential to the output terminal, and the high-level potential is input to the terminal LTi of the logic circuit LGC.

[0340] During the period T1, the logic circuit LGC outputs (10000000) as an 8-bit digital signal Qp to the terminal LFTp. ２ In other words, the logic of the seventh bit of the digital signal Qp changes from "0" to "1". As a result, a high level potential is input only to the gate of the transistor Tp2[7] of the first digital potential-analog current conversion circuit, and a current of 128 nA flows from the first terminal of the transistor MP5i to the wiring VSSL through the source-drain of the transistor Tp1[7] and the transistor Tp2[7]. As a result, I ＦＳｐ = 203 - 128 = 75 nA, and IＦＳｎ = 150 nA. Therefore, the output terminal of the comparator CPR outputs a low-level potential, which is input to the terminal LTi of the logic circuit LGC.

[0341] If the potential of the terminal LTi changes from the initial state potential during the period T1, the logic of the seventh bit Q[7] of the digital signal Qp is set to "0" after the period T1. Also, if the potential of the terminal LTi does not change from the initial state potential, the logic of the seventh bit Q[7] of the digital signal Qp is set to "1" after the period T1. In this operation example, the logic of Q[7] is "0" after the period T1.

[0342] During the period T2, the logic circuit LGC outputs (01000000) as an 8-bit digital signal Qp to the terminal LFTp. ２ That is, in the digital signal Qp, the logic of the seventh bit changes from "1" to "0", and the logic of the sixth bit changes from "0" to "1". As a result, a high-level potential is input only to the gate of the transistor Tp2[6] of the first digital potential-analog current conversion circuit, and a current of 64 nA flows from the first terminal of the transistor MP5i to the wiring VSSL through the source-drain of the transistor Tp1[6] and the transistor Tp2[6]. As a result, I ＦＳｐ = 203 - 64 = 139 nA, and I ＦＳｎ = 150 nA, the output terminal of the comparator CPR outputs a low level potential, which is input to the terminal LTi of the logic circuit LGC.

[0343] If the potential of the terminal LTi changes from the initial state potential during the period T2, the logic of the sixth bit Q[6] of the digital signal Qp is set to "0" after the period T2. Also, if the potential of the terminal LTi does not change from the initial state potential, the logic of the sixth bit Q[6] of the digital signal Qp is set to "1" after the period T2. In this operation example, the logic of Q[6] is "0" after the period T2.

[0344] During the period T3, the logic circuit LGC outputs (00100000) to the terminal LFTp as an 8-bit digital signal Qp. ２That is, in the digital signal Qp, the logic of the sixth bit changes from "1" to "0", and the logic of the fifth bit changes from "0" to "1". As a result, a high-level potential is input only to the gate of the transistor Tp2[6] of the first digital potential-analog current conversion circuit, and a current of 32 nA flows from the first terminal of the transistor MP5i to the wiring VSSL through the source-drain of the transistor Tp1[6] and the transistor Tp2[6]. As a result, I ＦＳｐ = 203 - 32 = 171 nA, and I ＦＳｎ =150 nA, the output terminal of the comparator CPR outputs a high-level potential, which is input to the terminal LTi of the logic circuit LGC.

[0345] In the period T3, if the potential of the terminal LTi changes from the potential in the initial state, after the period T3, the digital signal Q ｐ In addition, if the potential of the terminal LTi does not change from the potential in the initial state, after the period T3, the logic of the fifth bit Q[5] of the digital signal Q ｐ The logic of the fifth bit Q[5] is set to "1." In this operation example, the logic of Q[5] is "1" after the period T3.

[0346] During the period T4, the logic circuit LGC outputs (00110000) to the terminal LFTp as an 8-bit digital signal Qp. ２ That is, in the digital signal Qp, the logic of the fourth bit changes from "0" to "1". As a result, a high level potential is input only to the gates of the transistors Tp2[5] and Tp2[4] of the first digital potential-analog current conversion circuit, and a current of 32+16=48 nA flows from the first terminal of the transistor MP5i to the wiring VSSL. As a result, I ＦＳｐ = 203 - 48 = 155 nA, and I ＦＳｎ =150 nA, the output terminal of the comparator CPR outputs a high-level potential, which is input to the terminal LTi of the logic circuit LGC.

[0347] In the period T4, if the potential of the terminal LTi changes from the potential in the initial state, after the period T4, the digital signal Q ｐ The logic of the fourth bit Q[4] of the digital signal Q is set to "0". Also, if the potential of the terminal LTi has not changed from the potential in the initial state, the logic of the fourth bit Q[4] of the digital signal Q is set to "1" after the period T4. In this operation example, the logic of Q[4] is "1" after the period T4.

[0348] During the period T5, the logic circuit LGC outputs (00111000) to the terminal LFTp as an 8-bit digital signal Qp. ２ That is, in the digital signal Qp, the logic of the third bit changes from "0" to "1". As a result, a high-level potential is input only to the gates of the transistors Tp2[3] to Tp2[5] of the first digital potential-analog current conversion circuit, and a current of 32+16+8=56 nA flows from the first terminal of the transistor MP5i to the wiring VSSL. As a result, I ＦＳｐ = 203 - 56 = 147 nA, and I ＦＳｎ = 150 nA, the output terminal of the comparator CPR outputs a low level potential, which is input to the terminal LTi of the logic circuit LGC.

[0349] In the period T5, if the potential of the terminal LTi changes from the potential in the initial state, after the period T5, the digital signal Q ｐ The logic of the third bit Q[3] of the digital signal Q is set to "0". Furthermore, if the potential of the terminal LTi has not changed from the potential in the initial state, the logic of the third bit Q[3] of the digital signal Q is set to "1" after the period T5. In this operation example, the logic of Q[3] is "0" after the period T5.

[0350] During the period T6, the logic circuit LGC outputs (00110100) to the terminal LFTp as an 8-bit digital signal Qp. ２That is, in the digital signal Qp, the logic of the third bit changes from "1" to "0", and the logic of the second bit changes from "0" to "1". As a result, a high-level potential is input only to the gates of the transistors Tp2[5], Tp2[4], and Tp2[2] of the first digital potential-analog current conversion circuit, and a current of 32+16+4=52 nA flows from the first terminal of the transistor MP5i to the wiring VSSL. As a result, I ＦＳｐ = 203 - 52 = 151 nA, and I ＦＳｎ =150 nA, the output terminal of the comparator CPR outputs a high-level potential, which is input to the terminal LTi of the logic circuit LGC.

[0351] In the period T6, if the potential of the terminal LTi changes from the potential in the initial state, after the period T6, the digital signal Q ｐ The logic of the second bit Q[2] of the digital signal Q is set to "0". Furthermore, if the potential of the terminal LTi has not changed from the potential in the initial state, the logic of the second bit Q[2] of the digital signal Q is set to "1" after the period T6. In this operation example, the logic of Q[2] is "1" after the period T6.

[0352] During the period T7, the logic circuit LGC outputs (00110110) to the terminal LFTp as an 8-bit digital signal Qp. ２ That is, in the digital signal Qp, the logic of the first bit changes from "0" to "1". As a result, a high level potential is input only to the gates of the transistors Tp2[5], Tp2[4], Tp2[2], and Tp2[1] of the first digital potential-analog current conversion circuit, and a current of 32+16+4+2=54 nA flows from the first terminal of the transistor MP5i to the wiring VSSL. As a result, I ＦＳｐ = 203 - 54 = 149 nA, and I ＦＳｎ =150 nA, the output terminal of the comparator CPR outputs a low level potential, which is input to the terminal LTi of the logic circuit LGC.

[0353] In the period T7, if the potential of the terminal LTi changes from the potential in the initial state, after the period T7, the digital signal Q ｐ The logic of the first bit Q[1] of the digital signal Q is set to "0". Also, if the potential of the terminal LTi has not changed from the potential in the initial state, the logic of the first bit Q[1] of the digital signal Q is set to "1" after the period T7. In this operation example, the logic of Q[1] is "0" after the period T7.

[0354] During the period T8, the logic circuit LGC outputs (00110101) to the terminal LFTp as an 8-bit digital signal Qp. ２ That is, in the digital signal Qp, the logic of the 1st bit changes from "1" to "0", and the logic of the 0th bit changes from "0" to "1". As a result, a high-level potential is input only to the gates of the transistors Tp2[5], Tp2[4], Tp2[2], and Tp2[0] of the first digital potential-analog current conversion circuit, and a current of 32+16+4+1=53 nA flows from the first terminal of the transistor MP5i to the wiring VSSL. As a result, I ＦＳｐ = 203 - 53 = 150 nA, and I ＦＳｎ =150 nA, the output terminal of the comparator CPR outputs a high-level potential, which is then input to the terminal LTi of the logic circuit LGC.

[0355] In the period T8, if the potential of the terminal LTi changes from the potential in the initial state, after the period T8, the digital signal Q ｐ The logic of the 0th bit Q[0] of the digital signal Q is set to "0". Furthermore, if the potential of the terminal LTi has not changed from the potential in the initial state, the logic of the 0th bit Q[0] of the digital signal Q is set to "1" after the period T8. In this operation example, the logic of Q[0] is "1" after the period T8.

[0356] During the period T9, the logic circuit LGC outputs (00000000) to the terminal LFTp as an 8-bit digital signal Qp. ２ As a result, the current supply from the first digital potential-analog current conversion circuit is stopped, and I ＦＳｐ = 203 nA. Therefore, IＦＳｎ = 150 nA, the output terminal of the comparator CPR outputs a high level potential.

[0357] During the period T9, the terminal LTo of the logic circuit LGC outputs the digital signal Qp (00110101). ２ This outputs I ＳＰ = 203 nA and I ＳＮ The differential current of 53 nA, which is 150 nA, is converted into digital data.

[0358] As described above, by operating the circuit ITSpn of FIG. ＳＰ and I ＳＮ The differential current can be output as digital data.

[0359] The above is I ＳＰ Ga I ＳＮ This is an example of operation assuming that I is larger than ＳＮ Ga I ＳＰ If the value is larger than , it can be understood by changing the terms appropriately.

[0360] <Example of Operation Method of Calculation Device> Next, an example of operation of the calculation device CDV shown in FIG. 1 will be described.

[0361] 10 to 15 are timing charts showing an example of an operation method of the arithmetic device CDV. The timing charts show fluctuations in potentials of the wirings SWLA, SWLB, WSL, WROL, ROL, XCLp, XCLn, the nodes N1p, N2p, N1n, N2n, N1d, and N2d during and around periods T11 to T18. The timing charts also ... Ｍ３ｐ and the amount of source-drain current I flowing through the transistor M5p. Ｍ５ｐ and the amount of source-drain current I flowing through the transistor M3n. Ｍ３ｎ and the amount of source-drain current I flowing through the transistor M5n. Ｍ５ｎ and the amount of source-drain current I flowing through the transistor M3d. Ｍ３ｄand the amount of source-drain current I flowing through the transistor M5d. Ｍ５ｄ The respective variations of and are also shown.

[0362] 10 to 15, the types of wiring, nodes, etc. are shown on the left side, and the potential levels are shown on the right side. In particular, "High" in the timing charts means a high-level potential in the wiring, and "Low" means a low-level potential in the wiring or node.

[0363] The timing chart of Fig. 10 shows an example of operation when the first data w is a positive number and the second data x is a positive number. The timing chart of Fig. 11 shows an example of operation when the first data w is a positive number and the second data x is a negative number. The timing chart of Fig. 12 shows an example of operation when the first data w is a negative number and the second data x is a positive number. The timing chart of Fig. 13 shows an example of operation when the first data w is a negative number and the second data x is a negative number.

[0364] The timing chart of Fig. 14 shows a case where the first data w is 0. In the timing chart of Fig. 14, the second data x is a positive number, for example. The timing chart of Fig. 15 shows a case where the second data x is 0. In this case, the first data w is a positive number, for example.

[0365] In this operation example, the drive circuit WCD included in the calculation device CDV of FIG. 1 will be described as being applied with the drive circuit WCD of FIG. 3A, and the circuit XCDp and circuit XCDn included in the calculation device CDV of FIG. 1 will be described as being applied with the circuit XCDp of FIG. 3C.

[0366] Also, I generated by the circuit XCDp in FIG. Ｘｕｔ is the I generated by the circuit WCDp of FIG. Ｗｕｔ It is preferable that the value is equal to I. Ｘｕｔ and I ＷｕｔThe ratio of one of the two to the other is preferably 0.9 or more and 1.1 or less, more preferably 0.95 or more and 1.05 or less, and even more preferably 0.99 or more and 1.01 or less. Ｘｕｔ and I Ｗｕｔ Each of these is I ＵＴ It will be explained as follows.

[0367] The potentials applied by the wirings VE1, VE2, VINI1, and VINI2 are V Ｎ In addition, V Ｎ is V ｇｐ (w ｐ = 1), V ｇｎ (w ｎ = 1) and V ｇｍ It can be a potential lower than (r=1), ground potential (GND), or a negative potential.

[0368] Furthermore, a fixed potential is applied to the wiring VE2 so that the transistors M4d and M6d are turned on. As described above, the transistors M4d and M6d each function as a clamp transistor for suppressing the DIBL of the transistors M3d and M5d, respectively.

[0369] A high-level potential is supplied to the wiring WROL as a selection signal for turning on the transistors M4p and M4n, or a low-level potential is supplied as a non-selection signal for turning off the transistors M4d and M4n. As described above, the transistors M4p and M4n each function as a clamp transistor for suppressing the DIBL of the transistors M3p and M3n, respectively. Therefore, the high-level potential is preferably a fixed potential provided by the wiring VE2.

[0370] A high-level potential is supplied to the wiring ROL as a selection signal for turning on the transistors M6p and M6n, or a low-level potential is supplied to the wiring ROL as a non-selection signal for turning off the transistors M6d and M6n. As described above, the transistors M6p and M6n each function as a clamp transistor for suppressing the DIBL of the transistors M5p and M5n, respectively. Therefore, the high-level potential is preferably a fixed potential provided by the wiring VE2.

[0371] 10 to 15, before the period T11, a low-level potential is applied to the wirings SWLA, SWLB, WSL, WROL, and ROL. The potentials of the nodes N1p and N2p of the processing cell IMp, the nodes N1n and N2n of the processing cell IMn, and the nodes N1d and N2d of the driving cell IMd are initially set to V Ｎ It is assumed that I Ｍ３ｐ , I Ｍ５ｐ , I Ｍ３ｎ , I Ｍ５ｎ , I Ｍ３ｄ and I Ｍ５ｄ Each of these is initially set to 0.

[0372] Since a low-level potential is applied to each of the wirings SWLA and SWLB, a low-level potential is applied to the control terminals of the switches SAp, SAn, SBp, and SBn, respectively, which turns off the switches SAp, SAn, SBp, and SBn.

[0373] Since the wiring WSL is supplied with a low-level potential, the gates of the transistors M1p, M2p, M1n, M2n, M1d, and M2d are supplied with a low-level potential, turning these transistors off.

[0374] Since a low-level potential is applied to each of the wirings WROL and ROL, a low-level potential is applied to the gates of the transistors M4p, M6p, M4n, and M6n, turning these transistors off.

[0375] Also, before the period T11, the two parameters x representing the second data x are still input to the drive circuit XCD from the outside. ｐ and x ｎ Therefore, the amount of current generated in the circuits XCDp and XCDn of the driver circuit XCD is set to 0. Specifically, in each of the circuits XCDp and XCDn, the switch SWX is in an on state, and the potential V from the wiring VINI2 is applied to each of the wirings XCLp and XCLn via the switch SWX. Ｎ is assumed to be given.

[0376] Furthermore, from the above, between the first terminal and the second terminal of each of the capacitance elements C1p, C2p, C1n, C2n, C1d, and C2d, V Ｎ -V Ｎ The voltage is maintained at 0.

[0377] 10 to 15, a high-level potential is applied to the wiring SWLA in the period T11. Therefore, the high-level potential is applied to the control terminals of the switches SAp and SAn, and the switches SAp and SAn are turned on.

[0378] Also, during the period T11, the two parameters w representing the first data w are still input to the drive circuit WCD from the outside. ｐ And lol ｎ Therefore, in the driving circuit WCD, the amount of current I generated in the circuit WCDp is ｗｐ becomes 0, and the amount of current generated by the circuit WCDn, I ｗｎ Specifically, the switch SWW is in an on state, and the potential VＮ Similarly, the potential V Ｎ is assumed to be given.

[0379] 10 to 15, in the period T12, a high-level potential is applied to the wiring WSL. Therefore, a high-level potential is applied to the gates of the transistors M1p, M2p, M1n, M2n, M1d, and M2d, turning these transistors on.

[0380] In addition, in the period T12, a high-level potential is applied to the wiring WROL, and therefore a high-level potential is applied to the gates of the transistors M4p and M4n, turning these transistors on.

[0381] In the processing cell IMp, the transistors M1p and M2p are turned on, and the potential V Ｎ is supplied to the gate of the transistor M3p, the first terminal of the capacitor C1p (node ​​N1p), and the gate of the transistor M5p, and the first terminal of the capacitor C2p (node ​​N2p) via the wiring WCLp.

[0382] At this time, the potential V output from the circuit WCDp Ｎ is also applied to a first terminal of the transistor M3p via the wiring WCLp and the transistor M4p. Ｎ is given, no current flows between the source and drain of the transistor M3p (I Ｍ３ｐ = 0).

[0383] Similarly, in the calculation cell IMn, when the transistor M1n and the transistor M2n are turned on, the potential V Ｎ is supplied to the gate of the transistor M3n, the first terminal of the capacitor C1n (node ​​N1n), and the gate of the transistor M5n, and the first terminal of the capacitor C2n (node ​​N2n) via the wiring WCLn.

[0384] At this time, the potential V output from the circuit WCDn Ｎ is also applied to the first terminal of the transistor M3n through the wiring WCLn and the transistor M4n. Ｎ is given, no current flows between the source and drain of the transistor M3n (I Ｍ３ｐ = 0).

[0385] In addition, in the driving cell IMd, the transistors M1d and M2d are turned on, and the potential V Ｎ is applied to the gate of the transistor M3d and the first terminal of the capacitance element C1d (node ​​N1d), and to the gate of the transistor M5d and the first terminal of the capacitance element C2d (node ​​N2d).

[0386] At this time, the potential V output from the circuit XCDp Ｎ is also applied to the first terminal of the transistor M3d through the wiring XCLp and the transistor M4d. Ｎ is given, no current flows between the source and drain of the transistor M3d (I Ｍ３ｄ = 0).

[0387] Similarly, the potential V output from the circuit XCDn Ｎ is also applied to the first terminal of the transistor M5d through the wiring XCLn and the transistor M6d. Ｎ is given, no current flows between the source and drain of the transistor M5d (I Ｍ５ｄ = 0).

[0388] 10 to 15, in the period T13, reference data r, which is digital data, is provided from each of the wirings IXLp and IXLn. Therefore, in the driver circuit XCD, the amount of analog current generated by each of the circuits XCDp and XCDn is determined according to r. Here, the amount of analog current is defined as rI. ＵＴ In addition, I ＵＴ is the amount of current that flows when r = 1. Also, the switch SWX is in the OFF state, and the amount rI generated by the circuit XCDp ＵＴ Similarly, the current generated by the circuit XCDn flows through the wiring XCLp. ＵＴ The current flows through the wiring XCLn.

[0389] Also, in the driving cell IMd, the quantity rI from the circuit XCDp ＵＴ The current I flows through the wiring VE1 via the wiring XCLp and the source-drain paths of the transistors M4d and M3d. Ｍ３ｄ = rI ＵＴ At this time, since the transistors M1d and M2d are in the on state, the potentials of the gate of the transistor M3d and the first terminal of the capacitance element C1d (node ​​N1d), and the potentials of the gate of the transistor M5d and the first terminal of the capacitance element C2d (node ​​N2d) are each equal to or greater than rI ＵＴ At this time, the potential is V ｇｍ Let (r).

[0390] During the period T13, the potentials of the gates of the transistors M3d and M5d are V ｇｍ Since the two terminals of the transistors M3d and M5d are connected to the wiring VE1, the gate-source voltages of the transistors M3d and M5d are equal to each other. Therefore, the amount of current flowing between the source and drain of the transistor M5d is equal to the amount of current rI flowing between the source and drain of the transistor M3d. ＵＴ That is, I Ｍ５ｄ = rI ＵＴThis is because, during the period T13, the conduction state of each of the circuit elements included in the driving cell IMd becomes equivalent to the configuration of a current mirror circuit.

[0391] Also, the driving cell IMd receives the quantity rI from the circuit XCDn. ＵＴ The current generated by the transistor M5d is also rI. ＵＴ Therefore, the amount of current flowing in and out of the connection point between the second terminal of the transistor M6d and the line XCLn is zero.

[0392] Furthermore, the amount of current generated by each of the circuits XCDp and XCDn is rI ＵＴ is the current in the subthreshold region of each of the transistors M3d and M5d, and when the gate-source voltage of each of the transistors M3d and M5d is V ｇｍ (r)-V Ｎ Therefore, rI ＵＴ can be expressed as the following equation (1.3).

[0393]

[0394] In addition, V ｔｈ is the threshold voltage of the transistor M3d or the transistor M5d, and J is a correction coefficient determined by temperature, device structure, etc. ａ is the gate-source voltage of the transistor M3d or the transistor M5d is V ｔｈ is the amount of current that flows when

[0395] At this time, the potentials of the wirings XCLp and XCLn are V ｇｍ (r), and the potentials of the nodes N1d and N2d are also V ｇｍ Since (r), the voltage between the first terminal and the second terminal of each of the capacitance elements C1d and C2d is V ｇｍ (r)-V ｇｍ (r)=0.

[0396] In addition, in a period T13, the calculation device CDV is externally supplied with first data w. Specifically, in the drive circuit WCD of the calculation device CDV, digital data w is supplied from the wiring IWLp to the circuit WCDp. ｐ is given to the circuit WCDn from the wiring IWLn, and digital data w ｎ Also, as defined above, w ｐ and w ｎ The values ​​of each of the first data w differ depending on whether the first data w is a positive number, a negative number, or 0. Therefore, each case will be described below.

[0397] [When the first data w is a positive number] When the first data w is a positive number, refer to the timing charts shown in FIGS. 10, 11, and 15. ｐ Amount I according to ｗｐ =w ｐ I ＵＴ The analog current is then passed through the switch SAp and the wiring WCLp to the processing cell IMp.

[0398] In the calculation cell IMp, the quantity w ｐ I ＵＴ The current flows through the wiring VE1 via the source-drain paths of the transistors M4p and M3p. At this time, since the transistors M1p and M2p are in the on state, the potentials of the gate of the transistor M3p and the first terminal of the capacitor C1p (node ​​N1p), and the gate of the transistor M5p and the first terminal of the capacitor C2p (node ​​N2p) are each equal to the potential of the amount w ｐ I ＵＴ At this time, the potential is V ｇｐ (w ｐ )

[0399] At this time, since the wiring VE1 is connected to the second terminals of the transistors M3p and M5p, the gate-source voltages of the transistors M3p and M5p are equal to each other. However, since the transistor M6p is in the off state, a quantity w ｐ I ＵＴ However, no current flows between the source and drain of the transistor M5p. Ｍ３ｐ =w ｐ I ＵＴ And I Ｍ５ｐ =0.

[0400] Also, the amount of current generated in the circuit WCDp is ｐ I ＵＴ is the current in the subthreshold region of each of the transistors M3p and M5p, and when the gate-source voltage of each of the transistors M3p and M5p is V ｇｐ (w ｐ ) -V Ｎ Therefore, w ｐ I ＵＴ can be expressed as the following equation (1.4a):

[0401]

[0402] For the sake of simplicity, V ｔｈ is the V in each of the transistors M3d and M5d described above. ｔｈ and V in each of the transistors M3n and M5n, which will be described later. ｔｈ In addition, J in these transistors is also equal to each other, and I in these transistors is also equal to each other. ａ are also considered to be equal to each other.

[0403] Here, I ＵＴ can be expressed as the following equation (1.5).

[0404]

[0405] Therefore, by using equations (1.4a) and (1.5), w ｐ can be expressed as the following equation (1.6a):

[0406]

[0407] Furthermore, if the first data w is a positive number, w ｎ =0, as defined above, the circuit WCDn has the same potential V Ｎ As a result, the potential V Ｎ At this time, since the transistors M1n and M2n are in the on state, the potential V output from the circuit WCDn is also applied to the gate of the transistor M3n and the first terminal of the capacitance element C1n (node ​​N1n), and to the gate of the transistor M5n and the first terminal of the capacitance element C2n (node ​​N2n). Ｎ is given.

[0408] The wiring VE1 supplies a potential V Ｎ Therefore, the source-drain voltage of the transistor M3n is V Ｎ -V Ｎ = 0V. Therefore, the amount of current I flowing between the source and drain of the transistor M3n Ｍ３ｎ becomes 0 (I Ｍ３ｎ =0).

[0409] At this time, the potentials of the wirings XCLp and XCLn are V ｇｍ (r), and the potentials of the nodes N1p and N2p are V ｇｐ (w ｐ ), the voltage between the first terminal and the second terminal of each of the capacitance elements C1p and C2p is V ｇｐ (w ｐ ) -V ｇｍ (r). The potentials of the nodes N1n and N2n are V Ｎ Therefore, the voltage between the first terminal and the second terminal of each of the capacitance elements C1n and C2n is V Ｎ -Vｇｍ (r).

[0410] [When the first data w is a negative number] When the first data w is a negative number, refer to the timing charts shown in FIGS. 12 and 13. ｐ =0, as defined above, the circuit WCDp has a potential V Ｎ As a result, the potential V Ｎ At this time, since the transistors M1p and M2p are in the on state, the potential V output from the circuit WCDp is also applied to the gate of the transistor M3p and the first terminal of the capacitance element C1p (node ​​N1p), and to the gate of the transistor M5p and the first terminal of the capacitance element C2p (node ​​N2p). Ｎ is given.

[0411] The wiring VE1 supplies a potential V Ｎ Therefore, the source-drain voltage of the transistor M3p is 0 V. Therefore, the amount of current I Ｍ３ｐ becomes 0 (I Ｍ３ｐ =0).

[0412] Furthermore, when the first data w is a negative number, the circuit WCDn ｎ Amount I according to ｗｎ =w ｎ I ＵＴ The analog current is generated and flows through the operation cell IMn via the switch SAn and the wiring WCLn.

[0413] In the calculation cell IMn, the quantity w ｎ I ＵＴ The current flows through the wiring VE1 via the source-drain paths of the transistors M4n and M3n. At this time, since the transistors M1n and M2n are on, the potentials of the gate of the transistor M3n and the first terminal of the capacitor C1n (node ​​N1n), and the potentials of the gate of the transistor M5n and the first terminal of the capacitor C2n (node ​​N2n) are equal to or greater than the potential of the transistors M1n and M2n.ｎ I ＵＴ At this time, the potential is V ｇｎ (w ｎ )

[0414] At this time, since the wiring VE1 is connected to the second terminals of the transistors M3n and M5n, the gate-source voltages of the transistors M3n and M5n are equal to each other. However, since the transistor M6n is in the off state, a quantity w ｎ I ＵＴ However, no current flows between the source and drain of the transistor M5n. Ｍ３ｎ =w ｎ I ＵＴ And I Ｍ５ｎ =0.

[0415] Also, the amount of current generated in the circuit WCDn is ｎ I ＵＴ is the current in the subthreshold region of each of the transistors M3n and M5n, and when the gate-source voltage of each of the transistors M3n and M5n is V ｇｎ (w ｎ ) -V Ｎ Therefore, w ｎ I ＵＴ can be expressed as the following equation (1.4b):

[0416]

[0417] Therefore, by using equations (1.4b) and (1.5), w ｎ can be expressed as the following equation (1.6b):

[0418]

[0419] At this time, the potentials of the wirings XCLp and XCLn are V ｇｍ (r), and the potentials of the nodes N1p and N2p are V Ｎ Therefore, the voltage between the first terminal and the second terminal of each of the capacitance elements C1p and C2p is VＮ -V ｇｍ (r). The potentials of the nodes N1n and N2n are V ｇｎ (w ｎ ), the voltage between the first terminal and the second terminal of each of the capacitance elements C1n and C2n is V ｇｎ (w ｎ ) -V ｇｍ (r).

[0420] [When the first data w is 0] When the first data w is 0, refer to the timing chart of FIG. 14. When the first data w is 0, ｐ =w ｎ =0, as defined above, the circuit WCDp has a potential V Ｎ Similarly, the circuit WCDn outputs a potential V Ｎ The output shall be:

[0421] Therefore, the potential V output by the circuit WCDp Ｎ At this time, since the transistors M1p and M2p are in the on state, the potential V output from the circuit WCDp is also applied to the gate of the transistor M3p and the first terminal of the capacitance element C1p (node ​​N1p), and to the gate of the transistor M5p and the first terminal of the capacitance element C2p (node ​​N2p). Ｎ is given.

[0422] The wiring VE1 supplies a potential V Ｎ Therefore, the source-drain voltage of the transistor M3p is 0 V. Therefore, the amount of current I Ｍ３ｐ becomes 0 (I Ｍ３ｐ =0).

[0423] Similarly, the potential V output by the circuit WCDn ＮAt this time, since the transistors M1n and M2n are in the on state, the potential V output from the circuit WCDn is also applied to the gate of the transistor M3n and the first terminal of the capacitance element C1n (node ​​N1n), and to the gate of the transistor M5n and the first terminal of the capacitance element C2n (node ​​N2n). Ｎ is given.

[0424] The wiring VE1 supplies a potential V Ｎ Therefore, the source-drain voltage of the transistor M3n is 0 V. Therefore, the amount of current I Ｍ３ｎ becomes 0 (I Ｍ３ｎ =0).

[0425] At this time, the potentials of the wirings XCLp and XCLn are V ｇｍ (r), and the potentials of the nodes N1p, N2p, N1n, and N2n are V Ｎ Therefore, the voltage between the first terminal and the second terminal of each of the capacitance elements C1p, C2p, C1n, and C2n is V Ｎ -V ｇｍ (r).

[0426] 10 to 15, during the period T14, a low-level potential is applied to the wiring WSL. Therefore, a low-level potential is applied to the gates of the transistors M1p, M2p, M1n, M2n, M1d, and M2d, and these transistors are turned off.

[0427] During the period T14, a low-level potential is applied to the wiring WROL, and therefore a low-level potential is applied to the gates of the transistors M4p and M4n, turning off the transistors M4p and M4n.

[0428] In the driving cell IMd, the transistors M1d and M2d are turned off, so that the potential Vｇｍ (r) is held by the capacitance element C1d, and the potential V ｇｍ In other words, V is held between the first terminal and the second terminal of each of the capacitive elements C1d and C2d. ｇｍ (r)-V ｇｍ A voltage of (r)=0 is maintained. As a result, the nodes N1d and N2d are also in a floating state. Furthermore, by maintaining the potentials of the nodes N1d and N2d, the gate-source voltages of the transistors M3n and M5n are fixed. As a result, the quantity rI continues to flow between the source and drain of each of the transistors M3d and M5d. ＵＴ A current of flows.

[0429] Furthermore, in the computation cell IMp, when the transistors M1p and M2p are turned off, the potential of the node N1p is held by the capacitive element C1p, and the potential of the node N2p is held by the capacitive element C2p. In other words, the voltages between the first terminal and the second terminal of the capacitive elements C1p and C2p are held. As a result, the nodes N1p and N2p are each in a floating state. Furthermore, by holding the potentials of the nodes N1p and N2p, the gate-source voltages of the transistors M3p and M5p are fixed.

[0430] Similarly, in the computation cell IMn, when the transistors M1n and M2n are turned off, the potential of the node N1n is held by the capacitive element C1n, and the potential of the node N2n is held by the capacitive element C2n. In other words, the voltages between the first terminal and the second terminal of the capacitive elements C1n and C2n are held. As a result, the nodes N1n and N2n are each placed in a floating state. Furthermore, by holding the potentials of the nodes N1n and N2n, the gate-source voltages of the transistors M3n and M5n are fixed.

[0431] [When the First Data w is a Positive Number] When the first data w is a positive number, as shown in FIGS. 10, 11, and 15, the nodes N1p and N2p of the processing cell IMp are supplied with a potential V ｇｐ (w ｐ Specifically, V is held between the first terminal and the second terminal of each of the capacitance elements C1p and C2p. ｇｐ (w ｐ ) -V ｇｍ As a result, the gate-source voltages of the transistors M3p and M5p are maintained at V ｇｐ (w ｐ ) -V Ｎ Furthermore, since the transistors M4p and M6p are in the off state, the amount of current I Ｍ３ｐ Ha, w ｐ I ＵＴ 0, and the amount of current I flowing between the source and drain of the transistor M5p Ｍ５ｐ continues to remain 0 (I Ｍ３ｐ = 0, I Ｍ５ｐ =0).

[0432] In addition, the node N1n and the node N2n of the calculation cell IMn are supplied with a potential V Ｎ Specifically, V is held between the first terminal and the second terminal of each of the capacitance elements C1n and C2n. Ｎ -V ｇｍ As a result, the gate-source voltages of the transistors M3n and M5n are maintained at V Ｎ -V Ｎ In addition, since the transistors M4n and M6n are in the off state, the amount of current I Ｍ３ｎ continues to remain 0, and the amount of current I flowing between the source and drain of the transistor M5n Ｍ５ｎ continues to remain 0 (I Ｍ３ｎ = 0, I Ｍ５ｎ =0).

[0433] [When the First Data w is a Negative Number] When the first data w is a negative number, as shown in FIGS. 12 and 13, the node N1p and the node N2p of the processing cell IMp are supplied with a potential V Ｎ Specifically, V is held between the first terminal and the second terminal of each of the capacitance elements C1p and C2p. Ｎ -V ｇｍ As a result, the gate-source voltages of the transistors M3p and M5p are maintained at V Ｎ -V Ｎ In addition, since the transistors M4p and M6p are in the off state, the amount of current I Ｍ３ｐ continues to remain 0, and the amount of current I flowing between the source and drain of the transistor M5p Ｍ５ｐ continues to remain 0 (I Ｍ３ｐ = 0, I Ｍ５ｐ =0).

[0434] In addition, the node N1n and the node N2n of the calculation cell IMn are supplied with a potential V ｇｎ (w ｎ Specifically, V is held between the first terminal and the second terminal of each of the capacitance elements C1n and C2n. ｇｎ (w ｎ ) -V ｇｍ As a result, the gate-source voltages of the transistors M3n and M5n are maintained at V ｇｎ (w ｎ ) -V Ｎ Furthermore, since the transistors M4n and M6n are in the off state, the amount of current I flowing between the source and drain of the transistor M3n is fixed at Ｍ３ｎ Ha, w ｎ I ＵＴ 0, and the amount of current I flowing between the source and drain of the transistor M5n Ｍ５ｎ continues to remain 0 (I Ｍ３ｎ = 0, I Ｍ５ｎ =0).

[0435] [When the First Data w is 0] When the first data w is 0, as shown in FIG. 14, the node N1p and the node N2p of the processing cell IMp are supplied with the potential V Ｎ Specifically, V is held between the first terminal and the second terminal of each of the capacitance elements C1p and C2p. Ｎ -V ｇｍ As a result, the gate-source voltages of the transistors M3p and M5p are maintained at V Ｎ -V Ｎ In addition, since the transistors M4p and M6p are in the off state, the amount of current I Ｍ３ｐ continues to remain 0, and the amount of current I flowing between the source and drain of the transistor M5p Ｍ５ｐ continues to remain 0 (I Ｍ３ｐ = 0, I Ｍ５ｐ =0).

[0436] In addition, the node N1n and the node N2n of the calculation cell IMn are supplied with a potential V Ｎ Specifically, V is held between the first terminal and the second terminal of each of the capacitance elements C1n and C2n. Ｎ -V ｇｍ As a result, the gate-source voltages of the transistors M3n and M5n are maintained at V Ｎ -V Ｎ In addition, since the transistors M4n and M6n are in the off state, the amount of current I Ｍ３ｎ continues to remain 0, and the amount of current I flowing between the source and drain of the transistor M5n Ｍ５ｎ continues to remain 0 (I Ｍ３ｎ = 0, I Ｍ５ｎ =0).

[0437] As with the above-described transistors M3p, M5p, 3n, 3p, M3d, and M5d, by causing a current of amount I to flow between the source and drain and holding a potential corresponding to that current at the gate, it is possible to continue to cause a current of amount I to flow between the source and drain thereafter. In this specification, this type of operation is referred to as "setting (programming) the amount of current flowing between the source and drain of a transistor to I."

[0438] <<Period T15>> In the period T15, the circuits XCDp and XCDn of the driver circuit XCD are stopped, and the amount of current generated by each of the circuits XCDp and XCDn is 0. In the circuit XCDp, the switch SWX is turned on, and the potential V Ｎ In the circuit XCDn, the switch SWX is turned on, and the potential V Ｎ is applied via switch SWX.

[0439] The potential V Ｎ Consider the case where the potential V from the circuit XCDp is given. Ｎ is supplied to the first terminal of the transistor M3d of the driving cell IMd via the wiring XCLp and the transistor M4d. Furthermore, since the node N1d is in a floating state, the potential of the node N1d fluctuates in accordance with the change in the potential of the wiring XCLp due to the capacitive coupling in the capacitive element C1d. For example, the potential of the wiring XCLp is V ｇｍ (r) to V Ｎ The changed voltage is V ｇｍ (r)-V Ｎ In addition, from now on, V ｇｍ (r)-V Ｎ = ΔV ｇｍ Furthermore, when the capacitive coupling coefficient of the capacitive element C1d is k, the change in the potential of the node N1d is kΔV ｇｍ (r) = k(V ｇｍ (r)-V Ｎ) Therefore, the potential of the node N1d during the period T15 is V ｇｍ (r) -kΔV ｇｍ (r).

[0440] At this time, the gate-source voltage of the transistor M3d is V ｇｍ (r) -kΔV ｇｍ (r)-V Ｎ In addition, the source-drain voltage of the transistor M3d is V Ｎ -V Ｎ In this example of operation, the amount of current I flowing between the source and drain of the transistor M3d under the bias conditions given to the transistor M3d as described above is Ｍ３ｄ is set to 0 (I Ｍ３ｄ =0).

[0441] In addition, the potential V output from the circuit XCDp Ｎ is also applied to the second terminal of the capacitance element C1p of the processing cell IMp and the second terminal of the capacitance element C1n of the processing cell IMn via the wiring XCLp. Furthermore, since the nodes N1p and N1n are also in a floating state, the potential of the node N1p also fluctuates in response to a change in the potential of the wiring XCLp due to capacitive coupling in the capacitance element C1p. Similarly, the potential of the node N1n also fluctuates in response to a change in the potential of the wiring XCLp due to capacitive coupling in the capacitance element C1n. Furthermore, the amount of change in the potential of the wiring XCLp is, as described above, ΔV ｇｍ (r), and when the capacitive coupling coefficients of the capacitive elements C1p and C1n are k, which is the same as that of the capacitive elements C1d and C2d, the amount of change in the potential of each of the nodes N1p and N1n is kΔV ｇｍ (r) = k(V ｇｍ (r)-V Ｎ )

[0442] Similarly, the potential V Ｎ Consider the case where the potential V from the circuit XCDn is given. Ｎis supplied to the first terminal of the transistor M5d of the driving cell IMd via the wiring XCLn and the transistor M6d. Furthermore, since the node N2d is in a floating state, the potential of the node N2d fluctuates in accordance with the change in the potential of the wiring XCLn due to the capacitive coupling of the capacitive element C2d. For example, the potential of the wiring XCLn is V ｇｍ (r) to V Ｎ The changed voltage is V ｇｍ (r)-V Ｎ In addition, from now on, V ｇｍ (r)-V Ｎ = ΔV ｇｍ In addition, when the capacitive coupling coefficient of the capacitive element C2d is also k, which is the same as that of the capacitive element C1d, the change in the potential of the node N2d is kΔV ｇｍ (r) = k(V ｇｍ (r)-V Ｎ ) during the period T15. Therefore, the potential of the node N2d during the period T15 is V ｇｍ (r) -kΔV ｇｍ (r).

[0443] At this time, the gate-source voltage of the transistor M5d is V ｇｍ (r) -kΔV ｇｍ (r)-V Ｎ Similarly to the transistor M3d, the source-drain voltage of the transistor M5d is V Ｎ -V Ｎ In this example of operation, the amount of current I flowing between the source and drain of the transistor M5d under the bias conditions given to the transistor M5d as described above is Ｍ５ｄ is set to 0 (I Ｍ５ｄ =0).

[0444] In addition, the potential V output from the circuit XCDn Ｎis also applied to the second terminal of the capacitance element C2p of the arithmetic cell IMp and the second terminal of the capacitance element C2n of the arithmetic cell IMn via the wiring XCLn. Furthermore, since the nodes N2p and N2n are also in a floating state, the potential of the node N2p also fluctuates in response to a change in the potential of the wiring XCLn due to capacitive coupling in the capacitance element C2p. Similarly, the potential of the node N2n also fluctuates in response to a change in the potential of the wiring XCLn due to capacitive coupling in the capacitance element C2n. Furthermore, the amount of change in the potential of the wiring XCLn is, as described above, ΔV ｇｍ (r), and when the capacitive coupling coefficients of the capacitive elements C2p and C2n are k, which is the same as the capacitive elements C1d and C2d, the amount of change in the potential of each of the nodes N2p and N2n is kΔV ｇｍ (r) = k(V ｇｍ (r)-V Ｎ )

[0445] [When the First Data w is a Positive Number] When the first data w is a positive number, refer to the timing charts shown in FIGS. 10, 11, and 15. Ｎ is output from the circuit XCDn to the wiring XCLn, and the potential V Ｎ is output, the potentials of the nodes N1p and N2p in the processing cell IMp are V ｇｐ (w ｐ ) to V ｇｐ (w ｐ ) -kΔV ｇｍ In the calculation cell IMn, the potentials of the nodes N1n and N2n change to V Ｎ From V Ｎ −kΔV ｇｍ It changes to (r).

[0446] Furthermore, in the calculation cell IMp, from the above, the gate-source voltages of the transistors M3p and M5p are V ｇｐ (w ｐ ) -V Ｎ From V ｇｐ (w ｐ ) -kΔV ｇｍ (r)-V ＮIn the calculation cell IMn, the gate-source voltages of the transistors M3n and M5n are changed to V Ｎ to -kΔV ｇｍ Since the transistors M4p, M6p, M4n, and M6n are in the off state, the amount of current I flowing between the source and drain of each of the transistors M3p, M5p, M3n, and M5n is Ｍ３ｐ , I Ｍ５ｐ , I Ｍ３ｎ and I Ｍ５ｎ becomes 0 (I Ｍ３ｐ = 0, I Ｍ５ｐ = 0, I Ｍ３ｎ = 0, I Ｍ５ｎ =0).

[0447] [When the First Data w is a Negative Number] When the first data w is a negative number, refer to the timing charts shown in FIGS. 12 and 13. Ｎ is output from the circuit XCDn to the wiring XCLn, and the potential V Ｎ is output, the potentials of the nodes N1p and N2p in the processing cell IMp are V Ｎ From V Ｎ −kΔV ｇｍ In the calculation cell IMn, the potentials of the nodes N1n and N2n change to V ｇｎ (w ｎ ) to V ｇｎ (w ｎ ) -kΔV ｇｍ It changes to (r).

[0448] Furthermore, in the calculation cell IMp, from the above, the gate-source voltages of the transistors M3p and M5p are V Ｎ to -kΔV ｇｍ In the calculation cell IMn, the gate-source voltages of the transistors M3n and M5n are V ｇｎ (w ｎ ) -V Ｎ From V ｇｎ (wｎ ) -kΔV ｇｍ (r)-V Ｎ Since the transistors M4p, M6p, M4n, and M6n are in the off state, the amount of current I flowing between the source and drain of each of the transistors M3p, M5p, M3n, and M5n is Ｍ３ｐ , I Ｍ５ｐ , I Ｍ３ｎ and I Ｍ５ｎ becomes 0 (I Ｍ３ｐ = 0, I Ｍ５ｐ = 0, I Ｍ３ｎ = 0, I Ｍ５ｎ =0).

[0449] [When the First Data w is 0] When the first data w is 0, the timing chart shown in FIG. 14 is referred to. Ｎ is output from the circuit XCDn to the wiring XCLn, and the potential V Ｎ is output, the potentials of the nodes N1p and N2p in the processing cell IMp are V Ｎ From V Ｎ −kΔV ｇｍ In the calculation cell IMn, the potentials of the nodes N1n and N2n change to V Ｎ From V Ｎ −kΔV ｇｍ It changes to (r).

[0450] Furthermore, in the calculation cell IMp, from the above, the gate-source voltages of the transistors M3p and M5p are V Ｎ to -kΔV ｇｍ In the calculation cell IMn, the gate-source voltages of the transistors M3n and M5n are V Ｎ to -kΔV ｇｍ Since the transistors M4p, M6p, M4n, and M6n are in the off state, the amount of current I flowing between the source and drain of each of the transistors M3p, M5p, M3n, and M5n isＭ３ｐ , I Ｍ５ｐ , I Ｍ３ｎ and I Ｍ５ｎ becomes 0 (I Ｍ３ｐ = 0, I Ｍ５ｐ = 0, I Ｍ３ｎ = 0, I Ｍ５ｎ =0).

[0451] In this operation example, even if the transistors M4p and M6p are in the on state, the amount of current I flowing between the source and drain of the transistor M3p under the bias conditions given to the transistor M3p as described above is Ｍ３ｐ is set to 0, and the amount of current I flowing between the source and drain of the transistor M5p under the bias conditions given to the transistor M5p as described above is Ｍ５ｐ Also, it is assumed that I Ｍ３ｐ = 0, I Ｍ５ｐ Similarly, in this operation example, even if the transistors M4n and M6n are in the on state, the amount of current I flowing between the source and drain of the transistor M3n under the bias conditions given to the transistor M3n as described above is Ｍ３ｎ is set to 0, and the amount of current I flowing between the source and drain of the transistor M5n under the bias conditions given to the transistor M5n as described above is Ｍ５ｎ Also, it is assumed that I Ｍ３ｎ = 0, I Ｍ５ｎ =0).

[0452] 10 to 15, in the period T16, a low-level potential is applied to the wiring SWLA. Therefore, the low-level potential is applied to the control terminals of the switches SAp and SAn, and the switches SAp and SAn are turned off.

[0453] During period T16, the circuits WCDp and WCDn of the drive circuit WCD are stopped, and the amount of current generated by each of the circuits WCDp and WCDn is zero. The switch SWW may be turned on or off. In either case, because the switch SAp is turned off, the terminal connected to the wiring WCLp of the drive circuit WCD has high impedance, and no current or potential is applied from the drive circuit WCD to the wiring WCLp. Similarly, because the switch SAn is turned off, the terminal connected to the wiring WCLn of the drive circuit WCD has high impedance, and no current or potential is applied from the drive circuit WCD to the wiring WCLn.

[0454] 10 to 15, in the period T17, a high-level potential is applied to the wiring SWLB. Therefore, a high-level potential is applied to each of the control terminals of the switches SBp and SBn, and the switches SBp and SBn are turned on.

[0455] 10 to 15, in the period T17, a high-level potential is applied to each of the wirings WROL and ROL, and therefore a high-level potential is applied to each of the gates of the transistors M4p, M6p, M4n, and M6n, thereby turning on each of the transistors M4p, M6p, M4n, and M6n.

[0456] At this time, the first input terminal of circuit ITSpn is in a conductive state with the first terminal of transistor M3p of calculation cell IMp and the first terminal of transistor M5n of calculation cell IMn. Similarly, the second input terminal of circuit ITSpn is in a conductive state with the first terminal of transistor M5p of calculation cell IMp and the first terminal of transistor M3n of calculation cell IMn.

[0457] In this case, the circuit ITSpn may output a predetermined bias potential from its first input terminal to the first terminal of the transistor M3p of the arithmetic cell IMp and the first terminal of the transistor M5n of the arithmetic cell IMn. Similarly, the circuit ITSpn may output a predetermined bias potential from its second input terminal to the first terminal of the transistor M5p of the arithmetic cell IMp and the first terminal of the transistor M3n of the arithmetic cell IMn. Note that these bias potentials are preferably higher than the potential provided by the wiring VE1, for example, and are potentials at which the transistors M3p, M5p, M3n, and M5n each operate in the subthreshold region. Furthermore, these bias potentials may be generated from the potential provided by the wiring VDDL in FIG. 7 or FIG. 8 .

[0458] <<Period T18>> During the period T18, the calculation device CDV is externally supplied with second data x. Specifically, in the drive circuit XCD of the calculation device CDV, digital data x is supplied from the wiring IXLp to the circuit XCDp. ｐ is given to the circuit WCDn from the wiring IXLn, and digital data x ｎ Also, as defined above, x ｐ and x ｎ The values ​​of each of the above differ depending on whether the second data x is a positive number, a negative number, or 0. Therefore, each case will be described below.

[0459] [When the second data x is a positive number] When the second data x is a positive number, refer to the timing charts shown in Fig. 10 and Fig. 12. ｐ Amount I according to ｘｐ = x ｐ I ＵＴ and passes the analog current through the wiring XCLp to the driving cell IMd. ｎ =0, as defined above, the circuit XCDn has a potential V Ｎ The output shall be:

[0460] In the driving cell IMd, the amount x flowing through the wiring XCLp ｐ I ＵＴ The current flows through the source-drain paths of the transistors M4d and M3d to the wiring VE1. At this time, the potential of the wiring XCLp is V Ｎ From V ｇｍ (x ｐ At this time, since the node N1d is in a floating state, the potential of the node N1d fluctuates in accordance with the change in the potential of the wiring XCLp due to capacitive coupling in the capacitor C1d. For example, the potential of the wiring XCLp is V Ｎ From V ｇｍ (x ｐ ) so the changed voltage is V ｇｍ (x ｐ ) -V Ｎ In addition, from now on, V ｇｍ (x ｐ ) -V Ｎ = ΔV ｇｍ (x ｐ ) Furthermore, since the capacitive coupling coefficient of the capacitive element C1d is k, the change in potential of the node N1d is kΔV ｇｍ (x ｐ ) = k(V ｇｍ (x ｐ ) -V Ｎ ) Therefore, the potential of the node N1d during the period T18 is V ｇｍ (r) -kΔV ｇｍ (r) + kΔV ｇｍ (x ｐ ) = V ｇｍ (r) + k(ΔV ｇｍ (x ｐ ) -ΔV ｇｍ This corresponds to the potential change indicated by the solid line in the period T18 labeled "node N1d, node N2d" in each of FIGS.

[0461] At this time, the gate-source voltage of the transistor M3d is V ｇｍ (r) + k(ΔV ｇｍ (x ｐ ) -ΔV ｇｍ (r))-V ＮAs a result, the amount of current I flowing between the source and drain of the transistor M3d Ｍ３ｄ = x ｐ I ＵＴ is expressed as the following equation (1.7).

[0462]

[0463] In addition, in the driving cell IMd, the line XCLn is connected to a potential V Ｎ , the potential V Ｎ At this time, the potential of the wiring XCLn is V Ｎ At this time, the node N2d is in a floating state, but as described above, the potential of the wiring XCLn has not changed, so the potential of the node N2d also remains at V Ｎ This corresponds to the potential change indicated by the dotted line in the period T18 labeled "node N1d, node N2d" in each of FIGS.

[0464] At this time, the gate-source voltage of the transistor M5d is V ｇｍ (r) -kΔV ｇｍ (r)-V Ｎ The source-drain voltage of the transistor M5d is V Ｎ -V Ｎ =0. In addition, the bias conditions of the transistor M5d are the same as the bias conditions of the transistor M5d in the period T12, so no current flows between the source and drain of the transistor M5d (I Ｍ５ｄ = 0).

[0465] [When the second data x is a negative number] When the second data x is a negative number, refer to the timing charts shown in FIGS. 11 and 13. In this case, x ｐ =0, as defined above, the circuit XCDp has a potential V Ｎ The circuit XCDp outputs x ｎ Amount I according to ｘｎ = x ｎI ＵＴ The analog current is generated and flows through the driving cell IMd via the wiring XCLn.

[0466] In the driving cell IMd, the line XCLp is connected to a potential V Ｎ , the potential V Ｎ At this time, the potential of the wiring XCLp is V Ｎ At this time, the node N1d is in a floating state, but as described above, the potential of the wiring XCLp has not changed, and therefore the potential of the node N1d also remains at V Ｎ This corresponds to the potential change indicated by the solid line in the period T18 labeled "node N1d, node N2d" in each of FIGS.

[0467] At this time, the gate-source voltage of the transistor M3d is V ｇｍ (r) -kΔV ｇｍ (r)-V Ｎ In addition, the source-drain voltage of the transistor M3d is V Ｎ -V Ｎ = 0. In addition, the bias conditions of the transistor M3d are the same as the bias conditions of the transistor M3d in the period T12, so no current flows between the source and drain of the transistor M3d (I Ｍ３ｄ = 0).

[0468] In addition, in the driving cell IMd, the amount x flowing through the wiring XCLn ｎ I ＵＴ The current flows through the wiring VE1 via the source-drain paths of the transistors M6d and M5d. At this time, the potential of the wiring XCLn is V Ｎ From V ｇｍ (x ｎ At this time, since the node N2d is in a floating state, the potential of the node N2d fluctuates in accordance with the change in the potential of the wiring XCLn due to capacitive coupling in the capacitor C2d. For example, the potential of the wiring XCLn is V ＮFrom V ｇｍ (x ｎ ) so the changed voltage is V ｇｍ (x ｎ ) -V Ｎ In addition, from now on, V ｇｍ (x ｎ ) -V Ｎ = ΔV ｇｍ (x ｎ ) Furthermore, since the capacitive coupling coefficient of the capacitive element C2d is k, the change in potential of the node N2d is kΔV ｇｍ (x ｎ ) = k(V ｇｍ (x ｎ ) -V Ｎ ) Therefore, the potential of the node N2d during the period T18 is V ｇｍ (r) -kΔV ｇｍ (r) + kΔV ｇｍ (x ｎ ) = V ｇｍ (r) + k(ΔV ｇｍ (x ｎ ) -ΔV ｇｍ This corresponds to the potential change indicated by the dotted line in the period T18 labeled "node N1d, node N2d" in each of FIGS.

[0469] At this time, the gate-source voltage of the transistor M5d is V ｇｍ (r) + k(ΔV ｇｍ (x ｎ ) -ΔV ｇｍ (r))-V Ｎ As a result, the amount of current I flowing between the source and drain of the transistor M5d Ｍ５ｄ = x ｎ I ＵＴ is expressed as the following equation (1.8).

[0470]

[0471] [When the second data x is 0] When the second data x is 0, refer to the timing chart shown in FIG. 15. When the second data x is 0, x ｐ = x ｎ =0, as defined above, the circuit XCDp has a potential VＮ Similarly, the circuit XCDn outputs a potential V Ｎ The output shall be:

[0472] In the driving cell IMd, the line XCLp is connected to a potential V Ｎ , the potential V Ｎ At this time, the potential of the wiring XCLp is V Ｎ At this time, the node N1d is in a floating state, but as described above, the potential of the wiring XCLp has not changed, and therefore the potential of the node N1d also remains at V Ｎ It has remained unchanged.

[0473] In addition, in the driving cell IMd, the line XCLn is connected to a potential V Ｎ , the potential V Ｎ At this time, the potential of the wiring XCLn is V Ｎ At this time, the node N2d is in a floating state, but as described above, the potential of the wiring XCLn has not changed, so the potential of the node N2d also remains at V Ｎ It has remained unchanged.

[0474] The potential changes at the nodes N1d and N2d correspond to the potential changes indicated by the solid lines in the period T18 labeled "node N1d, node N2d" in Fig. 15. As shown in Fig. 15, when the second data x is 0, the potential changes at the nodes N1d and N2d overlap each other.

[0475] [Calculation when the first data w is a positive number and the second data x is a positive number] Here, the calculation operation of the calculation device CDV in the period T18 when the first data w is a positive number and the second data x is a positive number will be described. Note that the explanation will refer to the timing chart of FIG. 10.

[0476] Since the second data x is a positive number, I is applied between the source and drain of the transistor M3d of the driving cell IMd via the wiring XCLp from the circuit XCDp. Ｍ３ｄ = x ｐ I ＵＴ Compared to the period T17, the potential of the wiring XCLp is V Ｎ From V ｇｍ (x ｐ ) from the circuit XCDn to the wiring XCLn, which has been in the period T15. Ｎ is given.

[0477] In the processing cell IMp, the node N1p is in a floating state, and therefore the potential of the node N1p fluctuates in accordance with the change in the potential of the wiring XCLp due to capacitive coupling in the capacitance element C1p. For example, the amount of change in the potential of the wiring XCLp is ΔV ｇｍ (x ｐ ) = V ｇｍ (x ｐ ) -V Ｎ Since the capacitance coupling coefficient of the capacitance element C1p is k, the change in the potential of the node N1p is kΔV ｇｍ (x ｐ ) = k(V ｇｍ (x ｐ ) -V Ｎ ) Therefore, the potential of the node N1p during the period T18 is V ｇｐ (w ｐ ) -kΔV ｇｍ (r) + kΔV ｇｍ (x ｐ ) = V ｇｐ (w ｐ ) + k(ΔV ｇｍ (x ｐ ) -ΔV ｇｍ This corresponds to the portion of potential change indicated by the solid line in the period T18 labeled "node N1p, node N2p" in FIG.

[0478] From the above, the gate-source voltage of the transistor M3p is V ｇｐ (w ｐ ) + k(ΔV ｇｍ (x ｐ ) -ΔV ｇｍ (r))-V ＮTherefore, the amount of current I flowing between the source and drain of the transistor M3p Ｍ３ｐ is expressed as the following equation (1.9).

[0479]

[0480] where r and x ｐ are defined as in equation (1.10) and equation (1.11a), respectively.

[0481]

[0482] By using equations (1.5), (1.6a), (1.10) and (1.11a), equation (1.9) becomes the following equation (1.12).

[0483]

[0484] During the period T18, the transistor M4p is turned on, and therefore the quantity I Ｍ３ｐ A current (a current flowing between the source and drain of the transistor M3p) flows.

[0485] In the processing cell IMp, the node N2p is in a floating state. However, as described above, the potential of the wiring XCLn has not changed, and therefore the potential of the node N2p is also V Ｎ This corresponds to the potential change indicated by the dotted line in the period T18 labeled "node N1p, node N2p" in FIG.

[0486] From the above, the gate-source voltage of the transistor M5p is V ｇｐ (w ｐ ) -kΔV ｇｍ (r)-V Ｎ In this operation example, it is assumed that no current flows between the source and drain of the transistor M5p at this gate-source voltage (I Ｍ５ｐ = 0).

[0487] During the period T18, the transistor M6p is turned on. As described above, the amount of current I between the source and drain of the transistor M5p is Ｍ５ｐis 0, so no current flows between the processing cell IMp and the wire WCLn.

[0488] In the processing cell IMn, the node N1n is in a floating state, and therefore the potential of the node N1n fluctuates in accordance with the change in the potential of the line XCLp due to capacitive coupling in the capacitive element C1n. For example, the amount of change in the potential of the line XCLp is ΔV ｇｍ (x ｐ ) = V ｇｍ (x ｐ ) -V Ｎ Since the capacitance coupling coefficient of the capacitance element C1n is k, the change in the potential of the node N1n is kΔV ｇｍ (x ｐ ) = k(V ｇｍ (x ｐ ) -V Ｎ ) Therefore, the potential of the node N1n during the period T18 is V Ｎ −kΔV ｇｍ (r) + kΔV ｇｍ (x ｐ ) = V Ｎ + k (ΔV ｇｍ (x ｐ ) -ΔV ｇｍ This corresponds to the potential change indicated by the solid line in the period T18 labeled "node N1n, node N2n" in FIG.

[0489] From the above, the gate-source voltage of the transistor M3n is V Ｎ + k (ΔV ｇｍ (x ｐ ) -ΔV ｇｍ (r))-V Ｎ = k (ΔV ｇｍ (x ｐ ) -ΔV ｇｍ (r)) = k(V ｇｍ (x ｐ ) -V ｇｍ In this example of operation, it is assumed that no current flows between the source and drain of the transistor M3n at this gate-source voltage (I Ｍ３ｎ = 0).

[0490] In addition, during the period T18, the transistor M4n is turned on, but as described above, the amount of current I between the source and drain of the transistor M3n is Ｍ３ｎ is 0, so no current flows between the operation cell IMn and the wire WCLn.

[0491] In addition, in the processing cell IMn, the node N2n is also in a floating state. However, as described above, since the potential of the wiring XCLn has not changed, the potential of the node N2n is also V Ｎ This corresponds to the potential change indicated by the dotted line in the period T18 labeled "node N1n, node N2n" in FIG.

[0492] The gate-source voltage of the transistor M5n is V Ｎ −kΔV ｇｍ (r)-V Ｎ = -kΔV ｇｍ In this example of operation, it is assumed that no current flows between the source and drain of the transistor M5n at this gate-source voltage (I Ｍ５ｎ = 0).

[0493] In addition, during the period T18, the transistor M6n is turned on, but as described above, the amount of current I between the source and drain of the transistor M5n is Ｍ５ｎ is 0, so no current flows between the operation cell IMn and the wire WCLp.

[0494] To summarize the above, when the first data w is a positive number and the second data x is a positive number, there is a difference I between the operation cell IMp and the wiring WCLp. Ｍ３ｐ =I ＵＴ ×w ｐ x ｐ A current of an amount equal to / r flows. Furthermore, no current flows between the processing cell IMp and the wiring WCLn, between the processing cell IMn and the wiring WCLp, or between the processing cell IMn and the wiring WCLn. Thus, when w×x is a positive number, a current flows from the processing circuit CC to the wiring WCLp.

[0495] [Calculation when the first data w is a positive number and the second data x is a negative number] Here, the calculation operation of the calculation unit CDV in the period T18 when the first data w is a positive number and the second data x is a negative number will be described. Note that the explanation will refer to the timing chart of FIG. 11.

[0496] Since the second data x is a negative number, the potential V Ｎ Further, I is applied between the source and drain of the transistor M3d of the driving cell IMd via the wiring XCLn from the circuit XCDn. Ｍ３ｄ = x ｎ I ＵＴ Compared to the period T17, the potential of the wiring XCLn is V Ｎ From V ｇｍ (x ｎ ) has changed.

[0497] In the processing cell IMp, the node N1p is in a floating state, but as described above, the potential of the wiring XCLp has not changed, and therefore the potential of the node N1p is also V Ｎ This corresponds to the potential change indicated by the solid line in the period T18 labeled "node N1p, node N2p" in FIG.

[0498] From the above, the gate-source voltage of the transistor M3p is V ｇｐ (w ｐ ) -kΔV ｇｍ (r)-V Ｎ In this example of operation, it is assumed that no current flows between the source and drain of the transistor M3p at this gate-source voltage (I Ｍ３ｐ = 0).

[0499] During the period T18, the transistor M4p is turned on. As described above, the amount of current I between the source and drain of the transistor M3p is Ｍ３ｐ is 0, so no current flows between the processing cell IMp and the wire WCLp.

[0500] In the processing cell IMp, the node N2p is in a floating state, and therefore the potential of the node N2p fluctuates in accordance with the change in the potential of the wiring XCLn due to capacitive coupling in the capacitance element C2p. For example, the amount of change in the potential of the wiring XCLn is ΔV ｇｍ (x ｎ ) = V ｇｍ (x ｎ ) -V Ｎ Since the capacitance coupling coefficient of the capacitance element C2p is k, the change in the potential of the node N2p is kΔV ｇｍ (x ｎ ) = k(V ｇｍ (x ｎ ) -V Ｎ ) Therefore, the potential of the node N2p during the period T18 is V ｇｐ (w ｐ ) -kΔV ｇｍ (r) + kΔV ｇｍ (x ｎ ) = V ｇｐ (w ｐ ) + k(ΔV ｇｍ (x ｎ ) -ΔV ｇｍ This corresponds to the portion of potential change indicated by the dotted line in the period T18 labeled "node N1p, node N2p" in FIG.

[0501] From the above, the gate-source voltage of the transistor M5p is V ｇｐ (w ｐ ) + k(ΔV ｇｍ (x ｎ ) -ΔV ｇｍ (r))-V Ｎ Therefore, the amount of current I flowing between the source and drain of the transistor M3p Ｍ５ｐ is expressed as the following equation (1.13).

[0502]

[0503] Here, x ｎ is defined as in equation (1.11b) below.

[0504]

[0505] By using equations (1.5), (1.6a), (1.10) and (1.11b), equation (1.13) becomes the following equation (1.14).

[0506]

[0507] During the period T18, the transistor M6p is turned on, and therefore the quantity I Ｍ５ｐ A current (current flowing between the source and drain of the transistor M5p) flows.

[0508] In the processing cell IMn, the node N1n is in a floating state, but as described above, the potential of the line XCLp has not changed, and therefore the potential of the node N1n is also V Ｎ This corresponds to the potential change indicated by the solid line in the period T18 labeled "node N1n, node N2n" in FIG.

[0509] The gate-source voltage of the transistor M3n is V Ｎ −kΔV ｇｍ (r)-V Ｎ = -kΔV ｇｍ In this example of operation, it is assumed that no current flows between the source and drain of the transistor M3n at this gate-source voltage (I Ｍ３ｎ = 0).

[0510] In addition, during the period T18, the transistor M4n is turned on, but as described above, the amount of current I between the source and drain of the transistor M3n is Ｍ３ｎ is 0, so no current flows between the operation cell IMn and the wire WCLn.

[0511] In addition, in the processing cell IMn, the node N2n is in a floating state, and therefore the potential of the node N2n fluctuates in accordance with the change in the potential of the line XCLn due to the capacitive coupling of the capacitive element C2n. For example, the amount of change in the potential of the line XCLn is ΔV ｇｍ (x ｎ ) = V ｇｍ (x ｎ ) -V ＮSince the capacitance coupling coefficient of the capacitance element C2n is k, the change in the potential of the node N2n is kΔV ｇｍ (x ｎ ) = k(V ｇｍ (x ｎ ) -V Ｎ ) Therefore, the potential of the node N2n during the period T18 is V Ｎ −kΔV ｇｍ (r) + kΔV ｇｍ (x ｎ ) = V Ｎ + k (ΔV ｇｍ (x ｎ ) -ΔV ｇｍ This corresponds to the portion of potential change indicated by the dotted line in the period T18 labeled "node N1n, node N2n" in FIG.

[0512] From the above, the gate-source voltage of the transistor M5n is V Ｎ + k (ΔV ｇｍ (x ｎ ) -ΔV ｇｍ (r))-V Ｎ = k (ΔV ｇｍ (x ｎ ) -ΔV ｇｍ (r)) = k(V ｇｍ (x ｎ ) -V ｇｍ In this example of operation, it is assumed that no current flows between the source and drain of the transistor M5n at this gate-source voltage (I Ｍ５ｎ = 0).

[0513] In addition, during the period T18, the transistor M6n is turned on, but as described above, the amount of current I between the source and drain of the transistor M5n is Ｍ５ｎ is 0, so no current flows between the operation cell IMn and the wire WCLp.

[0514] To summarize the above, when the first data w is a positive number and the second data x is a negative number, there is a difference I between the operation cell IMp and the wiring WCLn. Ｍ５ｐ =I ＵＴ ×w ｐ x ｎA current of an amount equal to / r flows. Furthermore, no current flows between the processing cell IMp and the wiring WCLp, between the processing cell IMn and the wiring WCLp, or between the processing cell IMn and the wiring WCLn. Thus, when w×x is a negative number, a current flows from the processing circuit CC to the wiring WCLn.

[0515] [Calculation when the first data w is a negative number and the second data x is a positive number] Here, the calculation operation of the calculation unit CDV in the period T18 when the first data w is a negative number and the second data x is a positive number will be described. Note that the explanation will refer to the timing chart of FIG. 12.

[0516] Since the second data x is a positive number, I is applied between the source and drain of the transistor M3d of the driving cell IMd via the wiring XCLp from the circuit XCDp. Ｍ３ｄ = x ｐ I ＵＴ Compared to the period T17, the potential of the wiring XCLp is V Ｎ From V ｇｍ (x ｐ ) from the circuit XCDn to the wiring XCLn, which has been in the period T15. Ｎ is given.

[0517] In the calculation cell IMp, during the period T17, the voltage between the first terminal and the second terminal of the capacitance element C1p is V Ｎ -V ｇｍ (r), and the voltage between the first terminal and the second terminal of the capacitance element C2p is V Ｎ -V ｇｍ In the period T18, the potential of the wiring XCLp is V Ｎ From V ｇｍ (x ｐ ), and the potential V Ｎ is given, this operation can be explained by appropriately referring to the operation of the operation cell IMn in the period T18 in FIG.

[0518] During the period T18 in FIG. 12, the potential of the node N1p is V Ｎ + k (ΔV ｇｍ (x ｐ) -ΔV ｇｍ This corresponds to the potential change indicated by the solid line in the period T18 labeled "node N1p, node N2p" in FIG. 12. The potential of node N2p continues to be V Ｎ −kΔV ｇｍ This corresponds to the portion of the potential change indicated by the dotted line labeled "node N1p, node N2p" during period T18 in FIG. 12, which remains as is (r).

[0519] Therefore, the gate-source voltage of the transistor M3p is k(V ｇｍ (x ｐ ) -V ｇｍ (r)), and the amount of current flowing between the source and drain is I Ｍ３ｐ becomes 0. The gate-source voltage of the transistor M5p is −kΔV ｇｍ (r), and the amount of current flowing between the source and drain is I Ｍ５ｐ will be 0.

[0520] In addition, during the period T18 in FIG. 12, the transistors M4p and M6p are turned on, but as described above, the amount of current I between the source and drain of the transistor M3p Ｍ３ｐ and the amount of current I between the source and drain of transistor M5p. Ｍ５ｐ Since each of and is 0, no current flows between the processing cell IMp and the wire WCLp, and no current flows between the processing cell IMp and the wire WCLn.

[0521] In addition, in the calculation cell IMn, the voltage between the first terminal and the second terminal of the capacitance element C1n during the period T17 is V ｇｎ (w ｎ ) -V ｇｍ (r), and the voltage between the first terminal and the second terminal of the capacitance element C2n is V ｇｎ (w ｎ ) -V ｇｍ In the period T18, the potential of the wiring XCLp is V Ｎ From V ｇｍ (x ｐ ), and the potential of the wiring XCLn continues to V Ｎis given, this operation can be explained by appropriately referring to the operation of the operation cell IMp in the period T18 in FIG.

[0522] During the period T18 in FIG. 12, the potential of the node N1n is V ｇｎ (w ｎ ) + k(ΔV ｇｍ (x ｐ ) -ΔV ｇｍ This corresponds to the potential change indicated by the solid line in the period T18 labeled "node N1n, node N2n" in FIG. 12. The potential of node N2n continues to be V ｇｎ (w ｎ ) -kΔV ｇｍ This corresponds to the portion of potential change indicated by the dotted line labeled "node N1n, node N2n" during period T18 in FIG. 12, which remains as is (r).

[0523] Therefore, the gate-source voltage of the transistor M3n is V ｇｎ (w ｎ ) + k(V ｇｍ (x ｐ ) -V ｇｍ (r))-V Ｎ and the amount of current flowing between the source and drain is I Ｍ３ｐ is expressed as the following equation (1.15).

[0524]

[0525] Note that equation (1.15) is obtained by adding V ｇｐ (w ｐ ) to V ｇｎ (w ｎ ) is the formula in which

[0526] The gate-source voltage of the transistor M5n is V ｇｎ (w ｎ ) -kΔV ｇｍ (r)-V Ｎ and the amount of current flowing between the source and drain is I Ｍ５ｎ will be 0.

[0527] During the period T18, the transistor M4n is in the on state, and therefore, a quantity I Ｍ３ｎ During the period T18, the transistor M6n is in the ON state, but the amount of current I between the source and drain of the transistor M5n flows. Ｍ５ｎ is 0, so no current flows between the operation cell IMn and the wire WCLp.

[0528] To summarize the above, when the first data w is a negative number and the second data x is a positive number, there is a difference I between the operation cell IMn and the wiring WCLn. Ｍ３ｎ =I ＵＴ ×w ｎ x ｐ A current of an amount equal to / r flows. Furthermore, no current flows between the processing cell IMp and the wiring WCLp, between the processing cell IMp and the wiring WCLn, or between the processing cell IMn and the wiring WCLp. Thus, when w×x is a negative number, a current flows from the processing circuit CC to the wiring WCLn.

[0529] [Calculation when the first data w is a negative number and the second data x is a negative number] Here, the calculation operation of the calculation unit CDV in the period T18 when the first data w is a negative number and the second data x is a negative number will be described. Note that the explanation will refer to the timing chart of FIG. 13.

[0530] Since the second data x is a negative number, the potential V Ｎ Further, I is applied between the source and drain of the transistor M5d of the driving cell IMd from the circuit XCDn via the wiring XCLn. Ｍ５ｄ = x ｎ I ＵＴ Compared to the period T17, the potential of the wiring XCLn is V Ｎ From V ｇｍ (x ｎ ) has changed.

[0531] In the calculation cell IMp, during the period T17, the voltage between the first terminal and the second terminal of the capacitance element C1p is V Ｎ-V ｇｍ (r), and the voltage between the first terminal and the second terminal of the capacitance element C2p is V Ｎ -V ｇｍ In the period T18, the potential V Ｎ is given, and the potential of the wiring XCLn is V Ｎ From V ｇｍ (x ｎ ), this operation can be explained by appropriately referring to the operation of the operation cell IMn in period T18 in FIG. 11 described above.

[0532] During the period T18 in FIG. 13, the potential of the node N1p continues to be V Ｎ −kΔV ｇｍ The potential change at node N2p is V Ｎ + k (ΔV ｇｍ (x ｎ ) -ΔV ｇｍ This corresponds to the portion of potential change indicated by the dotted line in the period T18 labeled "node N1p, node N2p" in FIG.

[0533] Therefore, the gate-source voltage of the transistor M3p is −kΔV ｇｍ (r), and the amount of current flowing between the source and drain is I Ｍ３ｐ becomes 0. The gate-source voltage of the transistor M5p is k(V ｇｍ (x ｎ ) -V ｇｍ (r)), and the amount of current flowing between the source and drain is I Ｍ５ｐ will be 0.

[0534] In addition, during the period T18 in FIG. 13, the transistors M4p and M6p are turned on, but as described above, the amount of current I between the source and drain of the transistor M3p Ｍ３ｐ and the amount of current I between the source and drain of transistor M5p. Ｍ５ｐSince each of and is 0, no current flows between the processing cell IMp and the wire WCLp, and no current flows between the processing cell IMp and the wire WCLn.

[0535] In addition, in the calculation cell IMn, the voltage between the first terminal and the second terminal of the capacitance element C1n during the period T17 is V ｇｎ (w ｎ ) -V ｇｍ (r), and the voltage between the first terminal and the second terminal of the capacitance element C2n is V ｇｎ (w ｎ ) -V ｇｍ In the period T18, the potential V Ｎ is given, and the potential of the wiring XCLn is V Ｎ From V ｇｍ (x ｎ ), this operation can be explained by appropriately referring to the operation of the operation cell IMp in the period T18 in FIG. 11 described above.

[0536] During the period T18 in FIG. 13, the potential of the node N1n continues to be V ｇｎ (w ｎ ) -kΔV ｇｍ The potential at node N2n remains unchanged (r), and corresponds to the potential change indicated by the solid line in the period T18 labeled "node N1n, node N2n" in FIG. 13. ｇｎ (w ｎ ) + k(ΔV ｇｍ (x ｎ ) -ΔV ｇｍ This corresponds to the portion of potential change indicated by the dotted line in the period T18 labeled "node N1n, node N2n" in FIG.

[0537] Therefore, the gate-source voltage of the transistor M3n is V ｇｎ (w ｎ ) -kΔV ｇｍ (r)-V Ｎ and the amount of current flowing between the source and drain is I Ｍ３ｎ will be 0.

[0538] The gate-source voltage of the transistor M5n is Vｇｎ (w ｎ ) + k(V ｇｍ (x ｎ ) -V ｇｍ (r))-V Ｎ and the amount of current flowing between the source and drain is I Ｍ５ｎ is expressed as the following equation (1.16).

[0539]

[0540] Note that equation (1.16) is obtained by adding V ｇｐ (w ｐ ) to V ｇｎ (w ｎ ) is the formula in which

[0541] In addition, during the period T18, the transistor M4n is in the ON state, but the amount of current I between the source and drain of the transistor M3n Ｍ３ｎ Since the value of I is 0, no current flows between the processing cell IMn and the wiring WCLn. In addition, since the transistor M6n is in the on state during the period T18, the quantity I Ｍ５ｎ A current (current flowing between the source and drain of the transistor M5n) flows.

[0542] To summarize the above, when the first data w is a negative number and the second data x is a negative number, there is a difference I between the operation cell IMn and the wiring WCLp. Ｍ５ｎ =I ＵＴ ×w ｎ x ｎ A current of an amount equal to / r flows. Furthermore, no current flows between the processing cell IMp and the wiring WCLp, between the processing cell IMp and the wiring WCLn, or between the processing cell IMn and the wiring WCLn. Thus, when w×x is a positive number, a current flows from the processing circuit CC to the wiring WCLp.

[0543] [When the first data w is 0] Here, a description will be given of the arithmetic operation of the arithmetic unit CDV in the period T18 when the first data w is 0. Note that the description will refer to the timing chart of FIG. 14 when the second data x is a positive number.

[0544] Since the first data w is 0, before the period T17, the potentials of the nodes N1p and N2p of the processing cell IMp are V Ｎ −kΔV ｇｍ (r), and the potentials of the nodes N1n and N2n of the processing cell IMn are V Ｎ −kΔV ｇｍ (r).

[0545] Since the second data x is a positive number, during the period T18, I flows between the source and drain of the transistor M3d of the driving cell IMd from the circuit XCDp via the wiring XCLp. Ｍ３ｄ = x ｐ I ＵＴ Compared to the period T17, the potential of the wiring XCLp is V Ｎ From V ｇｍ (x ｐ ) from the circuit XCDn to the wiring XCLn, which has been in the period T15. Ｎ is given.

[0546] During the period T18, the potential of the node N1p of the processing cell IMp changes to V Ｎ −kΔV ｇｍ (r) to V Ｎ + k (ΔV ｇｍ (x ｐ ) -ΔV ｇｍ During the period T18, the potential of the node N2p of the processing cell IMp is V Ｎ −kΔV ｇｍ The above potential change is the same as that of the nodes N1p and N2p of the calculation cell IMp during the period T18 in the timing chart of FIG. 12. Therefore, referring to the description of the operations of the calculation cells IMp and IMn during the period T18 in the timing chart of FIG. 12, the amount of current I flowing between the source and drain of the transistor M3p is Ｍ３ｐ becomes 0, and the amount of current I Ｍ５ｐ becomes 0 (I Ｍ３ｐ = 0, I Ｍ５ｐ =0).

[0547] Similarly, during the period T18, the potential of the node N1n of the processing cell IMn changes to V Ｎ −kΔV ｇｍ (r) to V Ｎ + k (ΔV ｇｍ (x ｐ ) -ΔV ｇｍ During the period T18, the potential of the node N2n of the processing cell IMn is V Ｎ −kΔV ｇｍ The above potential change is the same as the potential change at nodes N1n and N2n of the calculation cell IMn during period T18 in the timing chart of FIG. 10. Therefore, referring to the explanation of the operation of calculation cells IMp and IMn during period T18 in the timing chart of FIG. 10, the amount of current I flowing between the source and drain of transistor M3n is Ｍ３ｎ becomes 0, and the amount of current I Ｍ５ｎ becomes 0 (I Ｍ３ｎ = 0, I Ｍ５ｎ =0).

[0548] From the above, when the first data w is 0 and the second data x is a positive number, no current flows between the computation cell IMp and the wiring WCLp, between the computation cell IMp and the wiring WCLn, between the computation cell IMn and the wiring WCLp, or between the computation cell IMn and the wiring WCLn. Note that this also applies when the first data w is 0 and the second data x is a negative number or 0. In this way, when w×x is 0, no current flows from the computation circuit CC to the wiring WCLp and the wiring WCLn.

[0549] [When the first data w is a positive or negative number or 0, and the second data x is 0] Here, a description will be given of the arithmetic operation of the arithmetic unit CDV in the period T18 when the second data x is 0. Note that the description will refer to the timing chart of FIG. 15 when the first data w is a positive number.

[0550] Since the first data w is a positive number, before the period T17, the potentials of the nodes N1p and N2p of the processing cell IMp are Vｇｐ (w ｐ ) -kΔV ｇｍ (r), and the potentials of the nodes N1n and N2n of the processing cell IMn are V Ｎ −kΔV ｇｍ (r).

[0551] Since the second data x is 0, during the period T18, V continues to be applied from the circuit XCDp to the wiring XCLp as in the period T15. Ｎ The potential V Ｎ is given.

[0552] During the period T18, the potential of the node N1p of the processing cell IMp is V ｇｐ (w ｐ ) -kΔV ｇｍ Furthermore, during the period T18, the potential of the node N2p of the processing cell IMp also remains at V Ｎ −kΔV ｇｍ It remains as (r).

[0553] The node N1p is the same as the node N1p of the processing cell IMp in the period T18 in the timing chart of FIG. 11. Therefore, referring to this, the amount of current I flowing between the source and drain of the transistor M3p is Ｍ３ｐ becomes 0 (I Ｍ３ｐ 10. In addition, the node N2p is the same as the node N2p of the processing cell IMp in the period T18 in the timing chart of FIG. 10. Therefore, referring to this, the amount of current I Ｍ５ｐ becomes 0 (I Ｍ５ｐ =0).

[0554] During the period T18, the potential of the node N1n of the processing cell IMn is V Ｎ −kΔV ｇｍ Furthermore, during the period T18, the potential of the node N2n of the processing cell IMn remains at V Ｎ −kΔV ｇｍIt remains as (r).

[0555] The node N1n is the same as the node N1n of the processing cell IMn in the period T18 in the timing chart of FIG. 11. Therefore, referring to this, the amount of current I flowing between the source and drain of the transistor M3n is Ｍ３ｎ becomes 0 (I Ｍ３ｎ 10. In addition, the node N2n is the same as the node N2n of the processing cell IMn in the period T18 in the timing chart of FIG. 10. Therefore, referring to this, the amount of current I Ｍ５ｎ becomes 0 (I Ｍ５ｎ =0).

[0556] From the above, when the first data w is a positive number and the second data x is 0, no current flows between the computation cell IMp and the wiring WCLp, between the computation cell IMp and the wiring WCLn, between the computation cell IMn and the wiring WCLp, or between the computation cell IMn and the wiring WCLn. Note that this also applies when the first data w is a negative number or 0 and the second data x is 0. In this way, when w×x is 0, no current flows from the computation circuit CC to the wiring WCLp and the wiring WCLn.

[0557] This concludes the explanation of the operation examples shown in the timing charts of Figures 10 to 15. The calculations performed in the above operation examples will be summarized below.

[0558] As shown in equation (1.12), the amount of current I flowing between the source and drain of the transistor M3p Ｍ３ｐ Ha, w ｐ ×x ｐ (= w × x). Also, as shown in equation (1.14), the amount of current I flowing between the source and drain of the transistor M5p is Ｍ５ｐ Ha, w ｐ ×x ｎ (= w × (-x) = - w × x). Also, as shown in equation (1.15), the amount of current I flowing between the source and drain of transistor M3n is Ｍ３ｎ Ha, w ｎ ×x ｐ(=(-w) x = -w x x). Also, as shown in equation (1.16), the amount of current I flowing between the source and drain of the transistor M5n is Ｍ５ｎ Ha, w ｎ ×x ｎ It is proportional to (=(-w) x (-x) = w x x).

[0559] Also, the quantity I is proportional to w x x. Ｍ３ｐ Current or quantity I Ｍ５ｎ The current flows through the wiring WCLp and is proportional to -w x x, Ｍ５ｐ Current or quantity I Ｍ３ｎ A current of w×x flows through the wiring WCLn. Furthermore, when w×x is 0, no current flows from the arithmetic circuit CC to the wiring WCLp and the wiring WCLn. As a result, when the first data w is a positive or negative number or 0 and the second data x is a positive or negative number or 0, the calculation of w×x can be performed using the arithmetic device CDV shown in FIG.

[0560] In particular, when multiplying the first data by the second data, it is preferable to set the reference data r to 1. That is, in the above example of operation, in the periods T13 and T14, the amount of current that the circuit XCDp passes through the wiring XCLp is set to I ＵＴ and the amount of current that the circuit XCDn passes through the wiring XCLn is I ＵＴ It is preferable to set the following.

[0561] Furthermore, from the above explanation, in the arithmetic unit CDV of FIG. 1, by setting the reference data r to a positive number other than 1, it is possible to perform division using r as the divisor and w x x as the dividend. In other words, it is possible to perform the multiplication of w and x / r. This allows the arithmetic unit CDV to increase the resolution of values ​​that can be input as second data. Furthermore, when considering the multiplication of w / r and x, it can also be said that the arithmetic unit CDV can increase the resolution of values ​​that can be input as first data.

[0562] Furthermore, it is preferable that the capacitive coupling coefficient k of each of the capacitive elements C1p, C2p, C1n, C2n, C1d, and C2d is as close to 1 as possible. Specifically, for example, k is preferably set to 0.8 or more and 1 or less, more preferably 0.9 or more and 1 or less, even more preferably 0.95 or more and 1 or less, and even more preferably 0.99 or more and 1 or less. For example, by setting k to 1, in the periods T13, T14, and T18, in the capacitive coupling among the nodes N1p, N1n, and N1d due to a change in the potential of the wiring XCLp, the amount of change in the potential of the nodes N1p, N1n, and N1d can be made equal to the amount of change in the potential of the wiring XCLp. Similarly, in the capacitive coupling of the nodes N2p, N2n, and N2d caused by a change in the potential of the wiring XCLn, the amount of change in the potential of the wiring XCLn can be made equal to the amount of change in the potential of the nodes N2p, N2n, and N2d. Conversely, the smaller k is than 1, the smaller the amount of change in the potential of the nodes N1p, N2p, N1n, N2n, N1d, and N2d caused by the capacitive coupling. Therefore, the two parameters x expressing the second data x that can be provided to the processing cells IMp and IMn can be set to ｐ , x ｎ Therefore, it is preferable that k is as close to 1 as possible.

[0563] During the period T18, the switches SAp and SAn are in the OFF state, and the switches SBp and SBn are in the ON state. Therefore, the quantity I Ｍ３ｐ or the quantity I from the calculation cell IMn Ｍ５ｎ The current I flows through the wiring WCLp to the first input terminal of the circuit ITSpn of the drive circuit ITS. Ｍ５ｐ or the quantity I from the calculation cell IMn Ｍ３ｎ The current flows to the second input terminal of the circuit ITSpn of the drive circuit ITS via the wiring WCLn. ＳｐThe amount of current flowing through the wiring WCLn is I Ｓｎ Let's say.

[0564] In the circuit ITSpn, the quantity I flowing to the first input terminal Ｓｐ and the amount I flowing into the second input terminal Ｓｎ By obtaining the current and the quantity I Ｓｐ -I Ｓｎ The circuit ITSpn calculates a function in which a value according to I is substituted as a variable, and outputs a voltage or current according to the calculation result from the output terminal. Ｓｐ -I Ｓｎ The function with the input value is F(I Ｓｐ -I Ｓｎ ) and the result of the operation is z １ When this is the case, z １ can be shown as the following equation (1.17).

[0565]

[0566] 1, when the first data w is a positive or negative number or 0 and the second data x is a positive or negative number or 0, it is possible to perform an operation of w×x and to calculate a function in which the operation result is substituted as a variable. In addition, it is possible to output the result of the calculation to the wiring OL.

[0567] In the calculation device CDV shown in FIG. 1, if the calculation circuit CC is only for one row, Ｓｐ and I Ｓｎ One of the two is 0. The case where there are a plurality of rows of arithmetic circuits CC will be described in detail in <Configuration Example 2 of the Arithmetic Device>.

[0568] In this operation method, as an example, the potential of the gate of the transistor M3p is V Ｎ , V Ｎ + k (ΔV ｇｍ (x ｐ ) -ΔV ｇｍ (r)), V ｇｐ (w ｐ ) -kΔV ｇｍ (r), V Ｎ −kΔVｇｍ When either (r) or (r), the gate-source voltage of the transistor M3p is 0, k(ΔV ｇｍ (x ｐ ) -ΔV ｇｍ (r)), V ｇｐ (w ｐ ) -kΔV ｇｍ (r)-V Ｎ , −kΔV ｇｍ (r)), the amount of current flowing between the source and drain of the transistor M3p is set to 0. Therefore, the potential V Ｎ is preferably set so as to satisfy the above. In some cases, it is also preferable that the threshold voltage of the transistor M3p is set so as to satisfy the above.

[0569] Also, the maximum value of r is ＭＡＸ As a result, the potential of the gate of the transistor M3p becomes V ｇｐ (w ｐ = 1) + k(ΔV ｇｍ (x ｐ = 1) - ΔV ｇｍ (r ＭＡＸ )), it is preferable that a non-zero minimum source-drain current flows between the source and drain of the transistor M3p. Ｎ , V Ｎ + k (ΔV ｇｍ (x ｐ ) -ΔV ｇｍ (r)), V ｇｐ (w ｐ ) -kΔV ｇｍ (r), V Ｎ −kΔV ｇｍ (r) is V ｇｐ (w ｐ = 1) + k(ΔV ｇｍ (x ｐ = 1) - ΔV ｇｍ (r ＭＡＸ )) is preferably a potential less than .

[0570] Also, w ｐ The maximum value of w ｐＭＡＸ As a result, the potential of the gate of the transistor M3p becomes Vｇｐ (w ｐＭＡＸ ) -kΔV ｇｍ (r=1)), the amount of current flowing between the source and drain of the transistor M3p is I Ｍ３ｐ It is preferable that V = 0, and ｇｐ (w ｐＭＡＸ ) -kΔV ｇｍ (r=1)) is V ｇｐ (w ｐ = 1) + k(ΔV ｇｍ (x ｐ = 1) - ΔV ｇｍ (r ＭＡＸ It is more preferable that the potential is less than .

[0571] Also, x ｐ The maximum value of x ｐＭＡＸ As a result, the potential of the gate of the transistor M3p becomes V Ｎ + k (ΔV ｇｍ (x ｐＭＡＸ ) -ΔV ｇｍ (r=1)), the amount of current flowing between the source and drain of the transistor M3p is I Ｍ３ｐ It is preferable that V = 0, and Ｎ + k (ΔV ｇｍ (x ｐＭＡＸ ) -ΔV ｇｍ (r=1)) is V ｇｐ (w ｐ = 1) + k(ΔV ｇｍ (x ｐ = 1) - ΔV ｇｍ (r ＭＡＸ It is more preferable that the potential is less than .

[0572] Although the above description has been given with respect to the gate of the transistor M3p, it is preferable that the same description be given with respect to the transistors M5p, M3n, and M5n.

[0573] <Modification 1 of Arithmetic Circuit> Next, a modification of the arithmetic circuit CC included in the arithmetic device CDV shown in FIG. 1 will be described.

[0574] The arithmetic device CDV shown in FIG. 16 has a modified configuration in the drive cell IMd shown in FIG. 1, and differs from the drive cell IMd of FIG. 1 in that the second terminal of the capacitance element C1d is connected to the wiring XCLn instead of the wiring XCLp, the second terminal of the capacitance element C2d is connected to the wiring XCLp instead of the wiring XCLn, the second terminal of the transistor M2d and the second terminal of the transistor M4d are each connected to the wiring XCLn instead of the wiring XCLp, and the second terminal of the transistor M6d is connected to the wiring XCLp instead of the wiring XCLn.

[0575] 16, the reference data r to be written to the driving cell IMd is input from the circuit XCDn via the wiring XCLn, not from the circuit XCDp. The reference data r transmitted from the wiring XCLn is written to the nodes N1d and N2d when the transistors M1d and M2d are in the on state.

[0576] The arithmetic unit CDV of Fig. 16 can be said to differ from the arithmetic unit CDV of Fig. 1 in that the source of the reference data r is the circuit XCDn. Furthermore, even if the configuration of the arithmetic unit CDV of Fig. 1 is changed to that of the arithmetic unit CDV shown in Fig. 16, by appropriately referring to the operation examples of the respective timing charts shown in Figs. 10 to 15 described above, the arithmetic unit CDV of Fig. 16 can multiply the first data w by the second data x, just like the arithmetic unit CDV of Fig. 1.

[0577] The arithmetic unit CDV shown in Fig. 1 may be changed to the circuit configuration of the arithmetic unit CDV shown in Fig. 17. The arithmetic unit CDV shown in Fig. 17 differs from the arithmetic unit CDV of Fig. 1 in the configurations of the arithmetic cells IMp, IMn, and driver cells IMd.

[0578] Specifically, in the calculation cell IMp of the calculation device CDV shown in FIG. 17, the gate of the transistor M3p is connected to the second terminal of the transistor M1p, the first terminal of the transistor M2p, and the first terminal of the capacitance element C2p, rather than to the first terminal of the transistor M1p and the first terminal of the capacitance element C1p; the gate of the transistor M5p is connected to the first terminal of the transistor M1p and the first terminal of the capacitance element C1p, rather than to the second terminal of the transistor M1p, the first terminal of the transistor M2p, and the first terminal of the capacitance element C2p; the second terminal of the capacitance element C1p is connected to the wiring XCLn, rather than to the wiring XCLp; and the second terminal of the capacitance element C2p is connected to the wiring XCLp, rather than to the wiring XCLn.

[0579] In addition, the calculation cell IMn of the calculation device CDV shown in FIG. 17 is configured such that the gate of the transistor M3n is connected to the second terminal of the transistor M1n, the first terminal of the transistor M2n, and the first terminal of the capacitance element C2n, rather than to the first terminal of the transistor M1n and the first terminal of the capacitance element C1n, the gate of the transistor M5n is connected to the first terminal of the transistor M1n and the first terminal of the capacitance element C1n, rather than to the second terminal of the transistor M1n, the first terminal of the transistor M2n, and the first terminal of the capacitance element C2n, the second terminal of the capacitance element C1n is connected to the wiring XCLn, rather than to the wiring XCLp, and the second terminal of the capacitance element C2n is connected to the wiring XCLp, rather than to the wiring XCLn.

[0580] Furthermore, the driving cell IMd of the calculation device CDV shown in FIG. 17 is configured such that the gate of the transistor M3d is connected to the second terminal of the transistor M1d, the first terminal of the transistor M2d, and the first terminal of the capacitance element C2d, rather than to the first terminal of the transistor M1d and the first terminal of the capacitance element C1d; the gate of the transistor M5d is connected to the first terminal of the transistor M1d and the first terminal of the capacitance element C1d, rather than to the second terminal of the transistor M1d, the first terminal of the transistor M2d, and the first terminal of the capacitance element C2d; the second terminal of the capacitance element C1d is connected to the wiring XCLn, rather than to the wiring XCLp; and the second terminal of the capacitance element C2d is connected to the wiring XCLp, rather than to the wiring XCLn.

[0581] With the above configuration, in the arithmetic unit CDV of FIG. 17, in the arithmetic cell IMp, ｐ ×x ｐ The calculation is performed by the potential change of the node N2p, and w ｐ ×x ｎ The calculation is performed by the potential change of the node N1p. ｎ ×x ｐ The calculation is performed by the potential change of the node N2n, and w ｎ ×x ｎ The calculation is performed based on the potential change at node N1n.

[0582] Even if the configuration of the arithmetic unit CDV of Fig. 1 is changed to that of the arithmetic unit CDV shown in Fig. 17, by appropriately referring to the operation examples of the respective timing charts shown in Fig. 10 to 15 described above, the arithmetic unit CDV of Fig. 16 can multiply the first data w by the second data x, similarly to the arithmetic unit CDV of Fig. 1. Specifically, in the operation examples of the respective timing charts of Fig. 10 to 15 and their explanations, the operation example of the arithmetic unit CDV shown in Fig. 17 can be explained by replacing the nodes N1p and N2p with each other, the nodes N1n and N2n with each other, and the nodes N1d and N2d with each other.

[0583] Furthermore, the arithmetic unit CDV shown in Fig. 17 may be changed to the circuit configuration of the arithmetic unit CDV shown in Fig. 18. The arithmetic unit CDV shown in Fig. 18 differs from the arithmetic unit CDV in Fig. 17 in the connection configuration between the driving cell IMd and the peripheral wiring.

[0584] Specifically, the driving cell IMd of the calculation device CDV shown in FIG. 18 is configured such that the second terminals of the transistors M2d and M4d are connected to the wiring XCLn instead of the wiring XCLp, the second terminal of the transistor M6d is connected to the wiring XCLp instead of the wiring XCLn, the second terminal of the capacitance element C1d is connected to the wiring XCLp instead of the wiring XCLn, and the second terminal of the capacitance element C2d is connected to the wiring XCLn instead of the wiring XCLp.

[0585] 16, the calculation device CDV of Fig. 18 is configured such that the reference data r to be written to the driver cell IMd is input from the circuit XCDn via the wiring XCLn, not from the circuit XCDp. Furthermore, the reference data r transmitted from the wiring XCLn is written to the nodes N1d and N2d when the transistors M1d and M2d are in the on state.

[0586] The arithmetic unit CDV of Fig. 18 can be said to differ from the arithmetic unit CDV of Fig. 17 in that the source of the reference data r is the circuit XCDn. Furthermore, even if the configuration of the arithmetic unit CDV of Fig. 17 is changed to that of the arithmetic unit CDV shown in Fig. 18, the arithmetic unit CDV of Fig. 18 can multiply the first data w and the second data x by appropriately referring to the operation examples of the respective timing charts shown in Figs. 10 to 15 described above.

[0587] 1, the driving cell IMd shown in FIG. 16, the driving cell IMd of the arithmetic unit CDV shown in FIG. 17, and the driving cell IMd of the arithmetic unit CDV shown in FIG. 18 are different from one another in terms of their circuit configurations or connection configurations with peripheral wiring, but they all hold the reference data r and have x ｐ and x ｎ In terms of function, they can be said to be equivalent to each other in that they pass currents according to the respective values. Therefore, the driver cell IMd of the arithmetic unit CDV shown in FIG. 1 can be appropriately replaced with the driver cell IMd shown in each of FIGS. 16, 17, and 18. Furthermore, the driver cell IMd of the arithmetic unit CDV shown in FIG. 16 can be appropriately replaced with the driver cell IMd shown in each of FIGS. 1, 17, and 18. Furthermore, the driver cell IMd of the arithmetic unit CDV shown in FIG. 17 can be appropriately replaced with the driver cell IMd shown in each of FIGS. 1, 16, and 18. Furthermore, the driver cell IMd of the arithmetic unit CDV shown in FIG. 18 can be appropriately replaced with the driver cell IMd shown in each of FIGS. 1, 16, and 17.

[0588] <Modification 2 of the arithmetic circuit> The arithmetic circuit CC shown in Figure 19 is a modification of the arithmetic circuit CC shown in Figure 1, and has a circuit configuration in which wiring WROL is connected to the gates of transistors M4d and M6d in the driving cell IMd shown in Figure 1, rather than wiring VE2.

[0589] Therefore, the transistors M4d and M6d can be turned on or off by a selection signal or a non-selection signal transmitted from the wiring WROL.

[0590] The driver cell IMd of the arithmetic circuit CC shown in Fig. 19 can turn off the transistors M4d and M6d, unlike the driver cell IMd of the arithmetic circuit CC shown in Fig. 1. In other words, in the operation examples of the timing charts shown in Fig. 10 to Fig. 15, the transistors M4d and M6d are turned off simultaneously with the transistors M4p, M6p, M4n, and M6n during the periods T11 and T14 to T16.

[0591] As described above, by turning off the transistors M4d and M6d in the period T11 and the periods T14 to T16, no current flows between the source and drain of the transistors M4d and M6d in these periods, thereby reducing power consumption. That is, the arithmetic circuit CC shown in FIG. 19 can reduce power consumption compared to the arithmetic circuit CC shown in FIG.

[0592] <Modification Example 3 of Arithmetic Circuit> The arithmetic circuit CC shown in FIG. 20 is a modification of the arithmetic circuit CC shown in FIG. 1, and has a circuit configuration in which the gates of the transistors M4p and M4n are connected to the wiring VE2 instead of the wiring WROL, and the gates of the transistors M6p and M6n are connected to the wiring VE2 instead of the wiring WROL.

[0593] The transistor M4d functions as a clamp transistor provided to suppress DIBL in the transistor M3d, and the transistor M6d functions as a clamp transistor provided to suppress DIBL in the transistor M5d. Therefore, a predetermined fixed potential is applied to the gates of the transistors M4d and M6d from the wiring VE2.

[0594] Referring to the above, by connecting the wiring VE2 to the gates of the transistors M4p, M6p, M4n, and M6n, the above-mentioned transistors function not as switching transistors but as clamp transistors that suppress DIBL of the corresponding transistors. Specifically, the transistor M4p functions as a clamp transistor that suppresses DIBL of the transistor M3p, the transistor M6p functions as a clamp transistor that suppresses DIBL of the transistor M5p, the transistor M4n functions as a clamp transistor that suppresses DIBL of the transistor M3n, and the transistor M6n functions as a clamp transistor that suppresses DIBL of the transistor M5n.

[0595] Furthermore, the operation examples of the timing charts shown in Figures 10 to 15 can also be performed in the arithmetic device CDV shown in Figure 20. In the timing charts of Figures 10 to 15, in the arithmetic device CDV of Figure 1, the transistors M4p and M4n are turned on only in periods T12 and T13, respectively, and the transistors M6p and M6n are turned on only in periods T12, T13, T17, and T18, respectively. On the other hand, in the arithmetic device CDV of Figure 20, the transistors are turned on in periods T11 to T18.

[0596] 20, consider a case where the transistors M4p, M6p, M4n, and M6n are in an on state during the periods T11, T15, and T16. At this time, the nodes N1p, N2p, N1n, and N2n are in a floating state, and the wirings XCLp and XCLn are connected to the potential V Ｎ is given. In this case, V Ｎ are at appropriate potentials, the potentials of nodes N1p, N2p, N1n, and N2n will drop due to capacitive coupling by the corresponding capacitive elements, and transistors M3p, M5p, M3n, and M5n will be turned off, so no current will flow from calculation cell IMp to wiring WCLp or wiring WCLn, and similarly, no current will flow from calculation cell IMn to wiring WCLp or wiring WCLn.

[0597] 20, consider a case where the transistors M4p, M6p, M4n, and M6n are each in an on state during a period T14. At this time, the nodes N1p, N2p, N1n, and N2n are each in a floating state, and a reference current corresponding to the reference data r flows through each of the wirings XCLp and XCLn. The potentials of the wirings XCLp and XCLn are V ｇｍ It is written as (r).

[0598] Furthermore, when w is a positive number, specifically, the potentials of the nodes N1p and N2p of the processing cell IMp are V ｇｐ (w ｐ ) and the potentials of the nodes N1n and N2n of the calculation cell IMn are V Ｎ When ｇｐ (w ｐ ) -V Ｎ The gate-source voltages of the transistors M3n and M5n are V Ｎ -V Ｎ =0.

[0599] At this time, a potential is applied from the wiring WCLp to the first terminal of the transistor M3p via the transistor M4p, so that a voltage of a quantity w ｐ I ＵＴ A current of (I Ｍ３ｐ =w ｐ I ＵＴ ). A potential is also applied to the first terminal of the transistor M5n from the wiring WCLp via the transistor M6n, but the gate-source voltage of the transistor M5n is V Ｎ -V Ｎ = 0, if the threshold voltage of the transistor M5n is appropriate, no current flows between the source and drain of the transistor M5n (I Ｍ５ｎ =0).

[0600] In addition, a potential V Ｎ is given, the source-drain voltage of the transistor M5p is V Ｎ -V Ｎ =0, and no current flows between the source and drain of the transistor M5p (I Ｍ５ｐ =0). The potential V Ｎ is given, and the gate-source voltage of the transistor M3n is V Ｎ -V Ｎ = 0, the source-drain voltage is V Ｎ -V Ｎ = 0, if the threshold voltage of the transistor M3n is appropriate, no current will flow between the source and drain of the transistor M3n (I Ｍ３ｎ =0).

[0601] Even if w is a negative number, taking the above into consideration, during the period T14, the amount w ｎ I ＵＴ A current of (I Ｍ３ｎ =w ｎ I ＵＴ), no current flows through the transistors M3p, M5p, and M5n (I Ｍ３ｐ = 0, I Ｍ５ｐ = 0, I Ｍ５ｎ =0).

[0602] As described above, the arithmetic unit CDV shown in FIG. 20 can also perform the same operations as those shown in the timing charts of FIGS.

[0603] 20, by connecting the gates of the transistors M4p, M6p, M4n, and M6n to the wiring VE2, the wiring WROL and the wiring ROL are no longer necessary. Also, the driver circuit WROD that transmits a signal to the wiring WROL and the driver circuit ROD that transmits a signal to the wiring ROL are no longer necessary. This allows the circuit area of ​​the arithmetic unit CDV to be reduced.

[0604] <Modification 4 of Arithmetic Circuit> The arithmetic device CDV shown in Fig. 21 has a circuit configuration obtained by modifying the arithmetic circuit CC shown in Fig. 1. Specifically, the arithmetic cells IMp, IMn, and driving cell IMd included in the arithmetic circuit CC1 in Fig. 21 are modifications of the arithmetic cells IMp, IMn, and driving cell IMd included in the arithmetic circuit CC in Fig. 1, respectively.

[0605] 21 shows only the drive circuits WCD, XCD, WSD, WROD, and ROD in order to illustrate the connection configuration of the arithmetic circuit CC1. Although the drive circuit ITS is not shown in FIG. 21, it is assumed that the arithmetic device CDV in FIG. 21 includes the drive circuit ITS described above.

[0606] 21 , the calculation cell IMp includes a transistor M11p, a transistor M12p, a transistor M3p, a transistor M4p, a transistor M5p, a transistor M6p, a capacitance element C1p, and a capacitance element C2p. The calculation cell IMn includes a transistor M11n, a transistor M12n, a transistor M3n, a transistor M4n, a transistor M5n, a transistor M6n, a capacitance element C1n, and a capacitance element C2n. The driver cell IMd includes a transistor M11d, a transistor M12d, a transistor M3d, a transistor M4d, a transistor M5d, a transistor M6d, a capacitance element C1d, and a capacitance element C2d.

[0607] In the processing cell IMp, for the transistors M3p to M6p and the capacitor C1p and C2p, respectively, the description of the transistors M3p to M6p and the capacitor C1p and C2p included in the processing cell IMp of the processing device CDV in Fig. 1 can be referred to. Similarly, in the processing cell IMn, for the transistors M3n to M6n and the capacitor C1n and C2n, respectively, the description of the transistors M3n to M6n and the capacitor C1n and C2n included in the processing cell IMn of the processing device CDV in Fig. 1 can be referred to. Similarly, in the driver cell IMd, for the transistors M3d to M6d and the capacitor C1d and C2d, respectively, the description of the transistors M3d to M6d and the capacitor C1d and C2d included in the driver cell IMd of the processing device CDV in Fig. 1 can be referred to.

[0608] In the calculation cell IMp, the transistors M11p and M12p have the same functions as the transistors M1p and M2p of the calculation cell IMp in Fig. 1 and function as write transistors, respectively. Therefore, the transistors M11p and M12p can be transistors that can be used as the transistors M1p and M2p.

[0609] Similarly, in the calculation cell IMn, the transistors M11n and M12n have the same functions as the transistors M1n and M2n of the calculation cell IMn in FIG. 1, respectively, and each function as a write transistor. Therefore, transistors applicable to the transistors M1n and M2n can be used for the transistors M11n and M12n. Similarly, in the driver cell IMd, the transistors M11d and M12d have the same functions as the transistors M1d and M2d of the driver cell IMd in FIG. 1, respectively, and each function as a write transistor. Therefore, transistors applicable to the transistors M1d and M2d can be used for the transistors M11d and M12d.

[0610] In the processing cell IMp, the first terminal of the transistor M11p is connected to the first terminal of the capacitance element C1p and the gate of the transistor M3p, and the first terminal of the transistor M12p is connected to the first terminal of the capacitance element C2p and the gate of the transistor M5p. The second terminals of the transistors M11p, M12p, and M4p are connected to the wiring WCLp. The gates of the transistors M11p and M12p are each connected to the wiring WSL.

[0611] 21, the connection point between the first terminal of the transistor M11p, the first terminal of the capacitance element C1p, and the gate of the transistor M3p is shown as a holding node, which is designated as a node N1p, and the connection point between the first t...

Claims

a first cell, a second cell, a third cell, a first drive circuit, and a second drive circuit; The first drive circuit A first value w ｐ The function of passing a current according to the A second value w ｎ and a function of passing a current in an amount corresponding to the The second drive circuit is The third cell is connected to the third wiring via a third wiring. ｐ The function of passing a current according to the The reference data r or the fourth value x is transmitted to the third cell via a fourth wiring. ｎ and a function of passing a current in an amount corresponding to the The first cell is The first value w ｐ and the ability to retain The amount of current flowing through the third wiring is reduced from the amount according to the reference data r to the third value x ｐ When the potential of the third wiring changes to an amount corresponding to w ｐ ×x ｐ / r to generate a first current in an amount corresponding to the first wiring; The amount of current flowing through the fourth wiring is changed from the amount according to the reference data r to the fourth value x ｎ When the potential of the fourth wiring changes to an amount corresponding to w ｐ ×x ｎ / r and causing a second current to flow through the second wiring; The second cell is The second value w ｎ and the ability to retain The amount of current flowing through the third wiring is reduced from the amount according to the reference data r to the third value x ｐ When the potential of the third wiring changes to an amount corresponding to w ｎ ×x ｐ / r to generate a third current in an amount corresponding to the second wiring; The amount of current flowing through the fourth wiring is changed from the amount according to the reference data r to the fourth value x ｎ When the potential of the fourth wiring changes to an amount corresponding to w ｎ ×x ｎ and a function of generating a fourth current in an amount corresponding to / r and flowing the fourth current through the first wiring, The third cell is a function of storing the reference data r; The amount of current flowing through the third wiring is reduced from the amount according to the reference data r to the third value x ｐ When the potential of the third wiring changes by an amount corresponding to x ｐ generating a fifth current in an amount according to The amount of current flowing through the fourth wiring is changed from the amount according to the reference data r to the fourth value x ｎ When the potential of the fourth wiring changes by an amount corresponding to x ｎ and generating a sixth current in an amount corresponding to Semiconductor device. 　 In claim 1, the first cell includes a first transistor and a second transistor; the second cell includes a third transistor and a fourth transistor; the third cell includes a fifth transistor and a sixth transistor; the first transistor has a function of passing the first current in a subthreshold region; the second transistor has a function of passing the second current in a subthreshold region; the third transistor has a function of passing the third current in a subthreshold region; the fourth transistor has a function of passing the fourth current in a subthreshold region; the fifth transistor has a function of passing the fifth current in a subthreshold region; the sixth transistor has a function of passing the sixth current in a subthreshold region. Semiconductor device. 　 In claim 2, a third drive circuit; each of the first cell, the second cell, and the third cell includes a seventh transistor; The third driving circuit drives the first cell with a first value w ｐ is written to the second cell, and a second value w ｎ is written to the first cell, the second cell, and the third cell via a fifth wiring when reference data r is written to the third cell; the seventh transistor has a function of being turned on when the selection signal is applied to a gate thereof; Semiconductor device. 　 In claim 3, each of the first to seventh transistors includes an oxide semiconductor in a channel formation region; the oxide semiconductor contains indium; Semiconductor device. 　 In claim 4, a fourth drive circuit; the fourth drive circuit has a function of generating a seventh current that is the difference between the amount of current flowing through the first wiring and the amount of current flowing through the second wiring; Semiconductor device. 　 A first cell, a second cell, and a third cell, the first cell includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a first capacitance element, and a second capacitance element; the second cell includes a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a third capacitive element, and a fourth capacitive element; the third cell includes a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, a sixteenth transistor, a seventeenth transistor, an eighteenth transistor, a fifth capacitive element, and a sixth capacitive element; one of the source and the drain of the first transistor is electrically connected to the gate of the third transistor and the first terminal of the first capacitive element; the other of the source and the drain of the first transistor is electrically connected to the one of the source and the drain of the second transistor, to the gate of the fifth transistor, and to a first terminal of the second capacitive element; one of the source and the drain of the third transistor is electrically connected to one of the source and the drain of the fourth transistor; one of the source and the drain of the fifth transistor is electrically connected to one of the source and the drain of the sixth transistor; one of the source and the drain of the seventh transistor is electrically connected to the gate of the ninth transistor and the first terminal of the third capacitive element; the other of the source and the drain of the seventh transistor is electrically connected to one of the source and the drain of the eighth transistor, the gate of the eleventh transistor, and a first terminal of the fourth capacitive element; one of the source and the drain of the ninth transistor is electrically connected to one of the source and the drain of the tenth transistor; one of the source and the drain of the eleventh transistor is electrically connected to one of the source and the drain of the twelfth transistor; one of the source and the drain of the thirteenth transistor is electrically connected to the gate of the fifteenth transistor and the first terminal of the fifth capacitive element; the other of the source and the drain of the thirteenth transistor is electrically connected to one of the source and the drain of the fourteenth transistor, to the gate of the seventeenth transistor, and to a first terminal of the sixth capacitive element; one of a source or a drain of the fifteenth transistor is electrically connected to one of a source or a drain of the sixteenth transistor; one of the source and the drain of the seventeenth transistor is electrically connected to one of the source and the drain of the eighteenth transistor; the other of the source or the drain of the second transistor, the other of the source or the drain of the fourth transistor, and the other of the source or the drain of the twelfth transistor are electrically connected to a first wiring, the other of the source or the drain of the sixth transistor, the other of the source or the drain of the eighth transistor, and the other of the source or the drain of the tenth transistor are electrically connected to a second wiring, the other of the source or the drain of the fourteenth transistor, the other of the source or the drain of the sixteenth transistor, the second terminal of the first capacitance element, the second terminal of the third capacitance element, and the second terminal of the fifth capacitance element are each electrically connected to a third wiring; the other of the source or the drain of the eighteenth transistor, the second terminal of the second capacitance element, the second terminal of the fourth capacitance element, and the second terminal of the sixth capacitance element are each electrically connected to a fourth wiring; a gate of the first transistor, a gate of the second transistor, a gate of the seventh transistor, a gate of the eighth transistor, a gate of the thirteenth transistor, and a gate of the fourteenth transistor are electrically connected to a fifth wiring; Semiconductor device. 　 In claim 6, a gate of the fourth transistor and a gate of the tenth transistor are electrically connected to a sixth wiring; a gate of the sixth transistor and a gate of the twelfth transistor are electrically connected to a seventh wiring; Semiconductor device. 　 In claim 7, a channel length of one or more selected from the first transistor, the second transistor, the seventh transistor, the eighth transistor, the thirteenth transistor, and the fourteenth transistor is longer than a channel length of each of the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the ninth transistor, the tenth transistor, the eleventh transistor, the twelfth transistor, the fifteenth transistor, the sixteenth transistor, the seventeenth transistor, and the eighteenth transistor; a channel width of one or more selected from the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the ninth transistor, the tenth transistor, the eleventh transistor, the twelfth transistor, the fifteenth transistor, the sixteenth transistor, the seventeenth transistor, and the eighteenth transistor is longer than a channel width of each of the first transistor, the second transistor, the seventh transistor, the eighth transistor, the thirteenth transistor, and the fourteenth transistor; Semiconductor device. 　 In any one of claims 6 to 8, each of the transistors included in the first cell, the second cell, and the third cell has an oxide semiconductor in a channel formation region; the oxide semiconductor contains indium; Semiconductor device. 　 In claim 9, a first drive circuit, a second drive circuit, a third drive circuit, and a fourth drive circuit; The first drive circuit A first value w is transmitted to the first cell via the first wiring. ｐ a function of providing a first current according to A second value w is transmitted to the second cell via the second wiring. ｎ and a function of providing a second current according to the The second drive circuit A third value x is transmitted to the third cell via the third wiring. ｐ a function of supplying a third current according to the reference data r or a reference current according to the reference data r; A fourth value x is transmitted to the third cell via the fourth wiring. ｎ and a function of flowing a fourth current corresponding to the reference current or the fourth current corresponding to the reference current; The third driving circuit supplies the first cell with the first value w ｐ and write the second value w ｎ and a function of transmitting a selection signal to the fifth wiring in order to write the reference data r to the third cell, The fourth driving circuit is A current flowing between the source or drain of the third transistor and the first wiring, ｐ ×x ｐ / r, and a fifth current flowing between one of the source or drain of the eleventh transistor and the first wiring, w ｎ ×x ｎ / r, and a function of acquiring a first sum current of A current flowing between the source or drain of the fifth transistor and the second wiring, ｐ ×x ｎ a seventh current corresponding to / r, and a current flowing between one of the source and drain of the ninth transistor and the second wiring; ｎ ×x ｐ / r, and a function of acquiring a second sum current of the eighth current according to a function of generating a difference current between the first summed current and the second summed current, the amounts of the first current, the second current, the third current, the fourth current, the fifth current, the sixth current, the seventh current, the eighth current, and the reference current are the amounts of current in subthreshold regions of the third transistor, the fifth transistor, the ninth transistor, the eleventh transistor, the fifteenth transistor, and the seventeenth transistor, respectively; Semiconductor device.

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