Display apparatus and electronic device

Abstract

Provided is a display apparatus with high light outcoupling efficiency and a wide viewing angle. This display apparatus has a first structure on a light-emitting element, a second structure covering a lateral surface of the first structure, and a plano-convex lens on the first structure. The first structure acts as a light guide for light emitted by the light-emitting element, and the second structure acts as a reflective surface. By using such a configuration, light emitted by the light-emitting element can be emitted efficiently in a frontal direction, thereby increasing light outcoupling efficiency in the display apparatus. Also, since the configuration is such that light does not intrude into adjacent pixels, the viewing angle can be enhanced and the visibility of the display can be improved.

Description

Display devices and electronic devices

[0001] One embodiment of the present invention relates to a display device and an electronic device.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. The technical field of one embodiment of the invention disclosed in this specification and the like relates to an object, a method, or a manufacturing method. Alternatively, one embodiment of the present invention relates to a process, a machine, manufacture, or a composition of matter. Therefore, more specifically, examples of the technical field of one embodiment of the present invention disclosed in this specification include a semiconductor device, a display device, a liquid crystal display device, a light-emitting device, a lighting device, a power storage device, a memory device, an imaging device, and an operation method thereof or a manufacturing method thereof.

[0003] Note that in this specification and the like, a semiconductor device refers to any device that can function by utilizing semiconductor characteristics. A transistor and a semiconductor circuit are examples of a semiconductor device. In addition, a memory device, a display device, an imaging device, and an electronic device may include a semiconductor device.

[0004] Goggle-type devices and eyeglass-type devices have been developed as electronic devices for XR (a collective term for virtual reality (VR), augmented reality (AR), mixed reality (MR), etc.).

[0005] Representative display panels used in these electronic devices include display devices equipped with liquid crystal elements, and display devices equipped with organic EL (Electro Luminescence) elements or light-emitting diodes (LEDs: Light Emitting Diodes).

[0006] A display device equipped with an organic EL element does not require a backlight, which is necessary in a liquid crystal display device, and therefore can realize a thin, lightweight, high-contrast, and low-power display device. For example, an example of a display device using an organic EL element is described in Patent Document 1.

[0007] Furthermore, in order to improve light extraction efficiency, display devices also employ a structure in which light emitted from a light-emitting device is extracted through a microlens. Patent Document 2 discloses a method for forming a microlens using a radiation-sensitive resin composition.

[0008] JP 2018-107444 A JP 2020-101659 A

[0009] Takashi Koida, "High Mobility Transparent Conductive Film," National Institute of Advanced Industrial Science and Technology, AIST Photovoltaic Power Generation Research Results Report 2019, Internet <URL: https: / / unit.aist.go.jp / rpd-envene / PV / ja / results / 2019 / oral / T13.pdf>

[0010] Catadioptric systems used in VR devices and the like utilize selective reflection of polarized light, resulting in insufficient light utilization efficiency. Furthermore, AR devices require high display visibility even in strong external light. Therefore, XR devices require increased display brightness. Increasing the brightness of display devices increases power consumption and reduces the reliability of display devices. Therefore, a display device with high light extraction efficiency is desired.

[0011] A portion of the light emitted from the light-emitting element is emitted in an oblique direction and may not be able to be extracted to the outside due to total reflection at interfaces within the display panel and reflection or absorption by structures in the light path. By providing a plano-convex lens on the light-emitting element, the light emitted in an oblique direction from the light-emitting element can be refracted toward the upper surface of the display panel, thereby increasing the front brightness.

[0012] However, depending on the positional relationship between the focal point of the plano-convex lens and the light-emitting area, the effect of improving the front luminance may not be sufficient. Also, if light penetrates into adjacent pixels, the viewing angle may decrease even if the front luminance is improved.

[0013] Therefore, an object of one embodiment of the present invention is to provide a display device with high front luminance and a wide viewing angle. Another object is to provide a display device with high light extraction efficiency. Another object is to provide a display device with high color-emitting performance. Another object is to provide a display device with low power consumption. Another object is to provide a display device with high visibility. Another object is to provide an electronic device including the display device. Another object is to provide a novel electronic device.

[0014] Note that the description of these problems does not preclude the existence of other problems. Note that one embodiment of the present invention does not necessarily solve all of these problems. Note that problems other than these will become clear from the description of the specification, drawings, claims, etc., and it is possible to extract other problems from the description of the specification, drawings, claims, etc.

[0015] One embodiment of the present invention relates to a display device having high light extraction efficiency and a wide viewing angle.

[0016] One embodiment of the present invention is a display device including a light-emitting element, a first structure, a second structure, and a plano-convex lens. The first structure is provided between a top surface of the light-emitting element and a bottom surface of the plano-convex lens. The first structure has a first surface on the light-emitting element side, a second surface on the plano-convex lens side, and a third surface between the first surface and the second surface. The third surface has a curved surface. The second structure is provided to cover the third surface. The plano-convex lens and the first structure transmit light emitted by the light-emitting element. A region of the second structure in contact with the third surface is reflective to light emitted by the light-emitting element.

[0017] The region of the second structure that contacts the third surface preferably contains a metal material, or may contain a material that has a smaller refractive index for light emitted from the light-emitting element than the first structure.

[0018] The first and second surfaces and the bottom surface of the plano-convex lens are each circular when viewed from above and are arranged concentrically, the diameter of the first surface being equal to or greater than the diameter of the circumscribing circle of the light-emitting element, the diameter of the second surface being greater than the diameter of the first surface, and the diameter of the bottom surface of the plano-convex lens being equal to or greater than the diameter of the second surface.

[0019] Alternatively, the first and second surfaces and the bottom surface of the plano-convex lens can each be elliptical when viewed from above and arranged so that their centers are at the same position, and the major and minor axes of the first surface can each be equal to or greater than the major and minor axes of an ellipse circumscribing the light-emitting element, the major and minor axes of the second surface can each be greater than the major and minor axes of the first surface, and the major and minor axes of the bottom surface of the plano-convex lens can each be equal to or greater than the major and minor axes of the second surface.

[0020] The curved surface of the third surface preferably has a region in which the curvature continuously increases from the first surface to the second surface in a cross section in the height direction including the center of the first structure, or the curved surface of the third surface may have a region in which the curvature continuously decreases from the first surface to the second surface in a cross section in the height direction including the center of the first structure.

[0021] The first structure and the plano-convex lens may be made of the same material.

[0022] The light-emitting element is preferably connected to a transistor having a metal oxide in a channel formation region, and the metal oxide is preferably indium oxide.

[0023] An electronic device using the above-described display device as a light source and having a catadioptric system provided on the display surface side of the display device is also one aspect of the present invention.

[0024] According to one embodiment of the present invention, a display device with high front luminance and a wide viewing angle can be provided. Alternatively, a display device with high light extraction efficiency can be provided. Alternatively, a display device with high color-emitting performance can be provided. Alternatively, a display device with low power consumption can be provided. Alternatively, a display device with high visibility can be provided. Alternatively, an electronic device including the display device can be provided. Alternatively, a novel electronic device can be provided.

[0025] Note that the description of these effects does not preclude the existence of other effects. One embodiment of the present invention does not necessarily have all of these effects. Effects other than these can be extracted from the description in the specification, drawings, and claims.

[0026] FIG. 1 is a perspective cross-sectional view illustrating a pixel of a display device. FIG. 2 is a diagram illustrating a pixel of the display device. FIG. 3 is a diagram illustrating a pixel of the display device. FIG. 4 is a diagram illustrating a pixel of the display device. FIG. 5 is a diagram illustrating a pixel of the display device. FIGS. 6A and 6B are diagrams illustrating a simulation model. FIGS. 7A and 7B are diagrams illustrating simulation results. FIGS. 8A and 8B are diagrams illustrating simulation results. FIGS. 9A to 9C are diagrams illustrating simulation results. FIGS. 10A and 10B are diagrams illustrating a display device. FIGS. 11A to 11E are diagrams illustrating a method for manufacturing a lens. FIG. 12A is a diagram illustrating a display device. FIGS. 12B to 12E are diagrams illustrating a method for manufacturing a display device. FIG. 13A is a diagram illustrating a display device. FIGS. 13B to 13E are diagrams illustrating a method for manufacturing a display device. FIG. 14A is a diagram illustrating a display device. FIGS. 14B to 14E are diagrams illustrating a method for manufacturing a display device. FIGS. 15A to 15E are diagrams illustrating a display panel. Fig. 16A to Fig. 16C are diagrams illustrating a glasses-type device. Fig. 17A and Fig. 17B are diagrams illustrating an example of the configuration of a display panel. Fig. 18 is a diagram illustrating an example of the configuration of a display panel. Fig. 19 is a diagram illustrating an example of the configuration of a display panel. Fig. 20 is a diagram illustrating an example of the configuration of a display panel. Fig. 21 is a diagram illustrating an example of the configuration of a display panel. Fig. 22 is a diagram illustrating an example of the configuration of a display panel. Fig. 23 is a diagram illustrating an example of the configuration of a display panel. Figs. 24A and 24B are diagrams illustrating a transistor. Figs. 25A and 25B are diagrams illustrating the carrier concentration dependence of Hall mobility. Fig. 25C is a cross-sectional view illustrating an indium oxide film.

[0027] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and those skilled in the art will readily understand that various modifications in form and detail may be made without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments shown below. In the configuration of the invention described below, the same parts or parts having similar functions will be designated by the same reference numerals in different drawings, and repeated description thereof may be omitted. Hatching of the same elements constituting the drawings may be omitted or changed as appropriate in different drawings.

[0028] Furthermore, even if a circuit diagram shows a single element, that element may be configured as multiple elements as long as there is no functional problem. For example, multiple transistors operating as switches may be connected in series or parallel. Also, a capacitor may be divided and placed in multiple locations.

[0029] Furthermore, one conductor may have multiple functions, such as wiring, electrode, and terminal, and in this specification, multiple names may be used for the same element. Also, even when elements are shown as being directly connected to each other on a circuit diagram, in reality, the elements may be connected via one or more conductors, and in this specification, such a configuration is also included in the category of direct connection.

[0030] In this specification, "connection" includes, as an example, "electrical connection." Note that the term "electrical connection" is sometimes used to define the connection relationship between circuit elements as a physical entity. Furthermore, "electrical connection" includes "direct connection" and "indirect connection." "A and B are directly connected" means that A and B are connected without the intervention of a circuit element (e.g., a transistor, a switch, etc.; wiring is not considered a circuit element). On the other hand, "A and B are indirectly connected" means that A and B are connected via one or more circuit elements.

[0031] For example, assuming that a circuit including A and B is operating, if there is a time during the operation of the circuit when an electrical signal is exchanged or an interaction of electrical potential occurs between A and B, then it can be defined that "A and B are indirectly connected" as objects. Note that even if there is a time during the operation of the circuit when no electrical signal is exchanged or an interaction of electrical potential occurs between A and B, it can still be defined that "A and B are indirectly connected" as long as there is a time during the operation of the circuit when an electrical signal is exchanged or an interaction of electrical potential occurs between A and B.

[0032] An example of a case where "A and B are indirectly connected" is when A and B are connected via the source and drain of one or more transistors. On the other hand, an example of a case where it cannot be said that "A and B are indirectly connected" is when an insulator is present in the path from A to B. Specifically, there are cases where a capacitive element is connected between A and B, and cases where a gate insulating film of a transistor is present between A and B. Therefore, it cannot be said that "the gate (A) of a transistor and the source or drain (B) of the transistor are indirectly connected."

[0033] Another example of a case where it cannot be said that "A and B are indirectly connected" is when multiple transistors are connected via their sources and drains to the path from A to B, and a constant potential V is supplied to a node between one transistor and another transistor from a power supply, GND, etc.

[0034] Embodiment 1 In this embodiment, a display device and an electronic device according to one embodiment of the present invention will be described.

[0035] One embodiment of the present invention is a display device having high light extraction efficiency and a wide viewing angle. The display device includes a light-emitting element (also referred to as a light-emitting device) as a display element, a first structure over the light-emitting element, a second structure covering a side surface of the first structure, and a plano-convex lens over the first structure.

[0036] Placing a convex lens over the light-emitting element is an effective way to improve the light extraction efficiency of a display device. By providing a convex lens, light emitted obliquely from the light-emitting element can be refracted toward the upper surface of the display panel, thereby increasing the front brightness.

[0037] When the distance from the light-emitting element to the bottom surface of the convex lens is relatively short, the light emitted by the light-emitting element easily enters the convex lens directly above the light-emitting element, and the viewing angle is likely to improve. On the other hand, when the light-emitting element is located closer to the convex lens than the focal point of the convex lens, the amount of light refracted in the front direction decreases, and the front brightness may not improve. Conversely, when the distance from the light-emitting element to the bottom surface of the convex lens is increased, the position of the light-emitting element is closer to the focal point of the convex lens, and more light is refracted in the front direction, and the front brightness improves. On the other hand, some of the light traveling in an oblique direction may enter the convex lens of an adjacent pixel rather than the convex lens directly above the light-emitting area, and the viewing angle may decrease.

[0038] Therefore, in one aspect of the present invention, a first structure is provided between the light-emitting element and the plano-convex lens, and a second structure is provided to cover the side surface of the first structure. The first structure acts as a light guide path for light emitted by the light-emitting element, and the second structure acts as a reflecting surface.

[0039] By using such a configuration, light emitted by the light-emitting element can be efficiently emitted in the forward direction, thereby increasing the light extraction efficiency of the display device. Therefore, it is possible to reduce the voltage applied to the light-emitting element, thereby improving the reliability of the light-emitting element and reducing the power consumption of the light-emitting element. Furthermore, since the configuration prevents light from penetrating into adjacent pixels, the viewing angle can be improved, thereby improving the visibility of the display. The viewing angle can be defined as the range in which the brightness and color tone of the display do not change significantly and can be viewed normally.

[0040] 1 is an example of a perspective cross-sectional view of a pixel and its vicinity included in a display device of one embodiment of the present invention, and illustrates pixels (subpixels 105R, 105G, and 105B) included in a stack 100, structures 103 (structures 103R, 103G, and 103B) and a structure 104 on the stack 100, and lenses 102 (lenses 102R, 102G, and 102B) on the structures 103 and 104. Note that FIG. 1 illustrates, as an example, cross sections of three subpixels included in a pixel with an S-stripe arrangement.

[0041] The structure 103R is provided on the subpixel 105R, the structure 103G is provided on the subpixel 105G, and the structure 103B is provided on the subpixel 105B. Furthermore, the lens 102R is provided on the structure 103R, the lens 102G is provided on the structure 103G, and the lens 102B is provided on the structure 103B.

[0042] The stack 100 can have elements that constitute a pixel. Here, a region where a light-emitting element is provided will be described as a pixel (sub-pixel). Therefore, in the drawings shown in this embodiment, a region shown as a sub-pixel can also be referred to as a region of a light-emitting element. In addition, elements such as structures 103 and 104 and a lens 102 on a light-emitting element may also be expressed as a pixel (sub-pixel).

[0043] The pixel has sub-pixel 105R having a light-emitting element that emits red light (for example, wavelength 625 nm to 780 nm), sub-pixel 105G having a light-emitting element that emits green light (for example, wavelength 500 nm to 565 nm), and sub-pixel 105B having a light-emitting element that emits blue light (for example, wavelength 450 nm to 485 nm). By configuring a pixel with multiple sub-pixels that emit different colors of light, full-color display is possible.

[0044] The lens 102 is a plano-convex lens and has a configuration in which the sub-pixels are separated from each other. Therefore, the plano-convex lens has a structure that is easily applicable even when the sub-pixels of a pixel have different shapes. Note that in this embodiment, an example using pixels with an S-stripe arrangement will be described as a representative example of sub-pixels with different shapes, but the present invention can also be applied to any arrangement of sub-pixels, regardless of their shape, such as a stripe arrangement, a delta arrangement, a zigzag arrangement, a pentile arrangement, or a diamond arrangement.

[0045] A pixel in the S-stripe arrangement has first to third subpixels that emit light of different colors. The first and second subpixels are arranged adjacent to each other in a first direction. The third subpixel is arranged adjacent to both the first and second subpixels in a second direction that is perpendicular to the first direction.

[0046] The S-stripe arrangement allows for a smaller area between sub-pixels than the stripe arrangement, making it easier to increase the aperture ratio, and is therefore advantageous in terms of increasing the brightness of the display panel, reducing power consumption, and improving the reliability of the light-emitting elements.

[0047] Next, the configurations of the structure 103, the structure 104, and the lens 102 will be described with reference to Fig. 2 to Fig. 5. In Fig. 2 to Fig. 5, the upper side is a top view showing a part of adjacent pixels, and the lower side corresponds to a cross-sectional view taken along the line A1-A2 shown in the top view.

[0048] A structural body 103 is provided on the subpixel 105 provided in the stacked body 100. The structural body 103 can be provided so as to encompass the upper surface (opening surface) of the light-emitting element of the subpixel 105.

[0049] Furthermore, the structures 104 are provided so as to cover the side surfaces of the structures 103. In other words, the structures 104 are provided so as to fill the spaces between the adjacent structures 103.

[0050] A lens 102 is provided on the structures 103 and 104. The lens 102 can be provided on the structures 103 and 104 so as to encompass the upper surface of the structure 103.

[0051] The structure 103 acts as a light guide path provided between the subpixel 105 and the lens 102 and can be formed from an insulator that is translucent to light emitted from the light-emitting element. The structure 104 can be formed from a metal, resin, or insulator that is reflective or absorbing to light emitted from the light-emitting element.

[0052] In either case where the structure 104 has light reflectivity or light absorption properties, it acts as a barrier that prevents light emitted from the light-emitting element in an oblique direction from penetrating into an adjacent subpixel. Therefore, only light traveling in the front direction of the display panel can be effectively utilized, which makes it difficult for changes in color tone to occur and improves the viewing angle.

[0053] Furthermore, when the structure 104 has light reflectivity, it can reflect light emitted from the light-emitting element in an oblique direction, making it easier to extract the light in the front direction of the display panel. Therefore, in addition to improving the viewing angle, it can also increase the front brightness.

[0054] The lens 102 is a plano-convex lens, and is also called a microlens because it has a minute size corresponding to the size of the pixel. Furthermore, a configuration in which the plano-convex lenses are regularly arranged on a surface is also called an MLA (microlens array).

[0055] To increase the front brightness of the display panel, it is ideal to use a plano-convex lens with a large curvature, such as a hemispherical lens, which can provide a large refraction. A lens with a large curvature has a strong ability to refract light emitted from the light-emitting element in an oblique direction toward the front, making it easier to increase the front brightness. Note that an aspherical lens can also be used as lens 102.

[0056] It is preferable that the bottom surface of the structure 103, the top surface of the structure 103, and the lens 102 are each circular in top view and arranged concentrically. This is to make the contribution of the structures 103 and 104 to the emission direction of light emitted from the light-emitting element uniform. Furthermore, even if the top surface shape of the subpixel is not circular, the light emitted from the light-emitting element can be efficiently incident on the lens 102. Furthermore, by making the shape of the structure 103 circular in top view, it can be efficiently enclosed by the circular lens 102.

[0057] Note that the surface on which the structures 103 and 104 are provided may not be flat due to the influence of the unevenness of the structures that constitute the subpixel 105. Therefore, the bottom surface of each of the structures 103 and 104 may have multiple flat or curved surfaces.

[0058] The top surface shape of the subpixel 105 is not particularly limited, but may be, for example, a quadrilateral or approximately quadrilateral shape used in a stripe array or an S-stripe array, depending on the relationship between aperture ratio and display quality. An approximately quadrilateral shape refers to one or a combination of two or more of the following shapes: a quadrilateral shape in which the corners of the quadrilateral are deformed to have curvature, or a quadrilateral shape in which one or more sides of the quadrilateral are deformed to have curvature. Examples of approximately quadrilateral shapes include an approximately square shape and an approximately rectangular shape. The top surface shape of the subpixel 105 may also be circular or approximately circular. An approximately circular shape refers to a circular shape with two or more curvatures. The top surface shape of the subpixel 105 can be rephrased as the top surface shape of the light-emitting element or the shape of the aperture.

[0059] In this way, even if the sub-pixels 105 and the lenses 102 have different shapes, the provision of the structures 103 allows the light emitted from the sub-pixels 105 to be efficiently incident on the lenses 102 .

[0060] As shown in FIG. 2, the diameter D103L of the bottom surface of the structure 103 is preferably equal to or larger than the diameter D105 of the circumscribing circle of the subpixel 105 (D103L≧D105).

[0061] Furthermore, it is preferable that the diameter D103H of the top surface of the structure 103 is larger than the diameter D103L of the bottom surface of the structure 103 (D103H>D103L).

[0062] Furthermore, it is preferable that the diameter D102 of the bottom surface of the lens 102 is equal to or larger than the diameter D103H of the top surface of the structure 103 (D102≧D103H).

[0063] One of the purposes of satisfying D103L≧D105 and D102≧D103H is to improve the viewing angle. To improve the viewing angle, it is preferable that light emitted by the light-emitting element is efficiently incident on the lens 102 directly above. Therefore, it is preferable that the bottom surface of the structure 103 includes the light-emitting element and that the occupancy rate of the light-emitting element is high. In other words, it is preferable that the diameter D103 of the bottom surface of the structure 103 is equal to or greater than the diameter D105 of the circumscribing circle of the light-emitting element.

[0064] Furthermore, it is preferable that the lens 102 be as large as possible within the limits of the layout, and that the lens 102 be configured to allow light to easily enter the lens 102. Therefore, in order to allow a large amount of light to easily enter the bottom surface of the lens 102, it is preferable that the diameter D103 of the bottom surface of the structure 103 be equal to or larger than the diameter D105 of the circumscribing circle of the light-emitting element.

[0065] With this configuration, light emitted from the sub-pixel 105 is efficiently taken in by the structure 103, and the structure 103 acts as a light guide path to be guided to the lens 102 directly above, thereby improving the viewing angle and light utilization efficiency.

[0066] One of the purposes of making D103H>D103L is to improve the front brightness. If D103H<D103L, the sidewall of the structure 103 will have a tapered shape, and the optical path from the light-emitting element to the lens 102 will be tapered, which is undesirable. By making D103H>D103L, the sidewall of the structure 103 will have an inverse tapered shape, and if the surface of the structure 104 that contacts the structure 103 has light reflectivity, it will be easier to reflect light upward.

[0067] Furthermore, it is preferable that the sidewalls of the structure 103 have an inverse tapered shape (D103H>D103L) rather than a vertical shape (D103H=D103L). By having the sidewalls of the structure 103 have an inverse tapered shape, oblique light emitted from the light-emitting element can reach the lens 102 with fewer reflections, thereby reducing loss of light due to absorption by the wall surface. Therefore, light can be efficiently incident on the lens 102, and front brightness can be improved.

[0068] Note that when the surface of the structure 104 in contact with the structure 103 has light absorption properties, the structure 104 has the effect of absorbing and blocking light that penetrates into an adjacent pixel. Therefore, although the light absorbed by the wall surface is lost, the viewing angle can be improved in some cases.

[0069] In the structure 103, when D103H > D103L, the side surface preferably has a curved, inversely tapered shape. For example, the curved surface may have a region in which the curvature continuously increases from the bottom surface to the top surface of the structure 103 in a cross section in the height direction including the center of the structure 103 (see FIG. 2). Alternatively, the curved surface may have a region in which the curvature continuously decreases from the bottom surface to the top surface of the structure 103 (see FIG. 3). Alternatively, the side surface of the structure 103 may not have a curved surface, but may have a surface with a constant absolute value of inclination from the bottom surface to the top surface of the structure 103 (see FIG. 4). These effects will be described later, along with simulation results.

[0070] The sidewall of the structure 103 may not be entirely reverse tapered, but may be partially reverse tapered. For example, the sidewall of the structure 103 may have a region having a reverse tapered shape and a region having a shape perpendicular to the bottom surface of the structure 103.

[0071] 2 to 4 have been described as an example in which the top surface shape of the subpixel 105 is substantially square, but it may also be substantially rectangular. In this case, as shown in Fig. 5, the bottom surface of the structure 103, the top surface of the structure 103, and the bottom surface of the lens 102 can each be an ellipse whose center is located at the same position when viewed from above. Note that Fig. 5 illustrates a cross section of the ellipse in the major axis direction.

[0072] In this case, it is preferable that the major axis and minor axis of the bottom surface of the structure 103 are equal to or greater than the major axis and minor axis of the ellipse circumscribing the light-emitting element, respectively. That is, when the top surface shape of the subpixel 105 is substantially rectangular, it is preferable that the major axis H103L of the bottom surface of the structure 103 is equal to or greater than the major axis H105 of the ellipse circumscribing the subpixel 105 (H103L≧H105).

[0073] Furthermore, it is preferable that the major axis and minor axis of the top surface of the structure 103 are larger than the major axis and minor axis of the bottom surface of the structure 103. That is, it is preferable that the major axis H103H of the top surface of the structure 103 is larger than the major axis H103L of the bottom surface of the structure 103 (H103H>H103L).

[0074] Furthermore, it is preferable that the major axis and minor axis of the bottom surface of the lens 102 are equal to or greater than the major axis and minor axis of the top surface of the structure 103. That is, it is preferable that the major axis H102 of the bottom surface of the lens 102 is equal to or greater than the major axis H103H of the top surface of the structure 103 (H102≧H103H).

[0075] The cross section of the ellipse in the minor axis direction can be, for example, the same as the cross section shown in Fig. 2. For an explanation of the size relationship of the faces in each element, please refer to the explanation of Fig. 2.

[0076] Next, a description will be given of simulation results regarding the front luminance and viewing angle of a display panel in which the structures 103, 104, and the lens 102 are provided on the subpixels.

[0077] The simulation assumed pixels in an S-stripe arrangement having subpixels 105R, 105G, and 105B in a display panel P, as shown in the top view of Fig. 6A. The outer shapes of lenses 102R and 102G in a top view were set to a size inscribed in a square that divides a square pixel into four equal parts, and the outer shape of lens 102B in a top view was set to a size inscribed in a rectangle that divides a square pixel into two equal parts. The radius of curvature of the region of lens 102B that has curvature was set to be the same as the radius of curvature of lenses 102R and 102G.

[0078] The resolution of the display panel P was 5009 ppi, the pixel size was 5.07 μm square, and the size of the sub-pixel serving as the light source was 1.2675 μm square. The angle dependence of luminance was simulated for the case where only the sub-pixel 105G was illuminated. Note that the front luminance is defined as the luminance when the light-receiving surface is positioned at an angle (0°) perpendicular to the display surface of the display panel. The front luminance is defined as 1, and the angle at which the luminance becomes 0.5 by moving the light-receiving surface is defined as the viewing angle.

[0079] 6B shows the positional relationship of each element of the model used in the calculation, and the refractive index n of each element. The models were model MD1 with the configuration shown in FIG. 2, model MD2 with the configuration shown in FIG. 3, and model MD3 with the configuration shown in FIG. 4, and the height h of the structure 103 was varied from 1 μm to 4 μm. For comparison, calculations were also performed for model MD0, which did not include structures 103 and 104.

[0080] As a common basic configuration of the models, the lens 102 is located on a structure 103 provided on the light-emitting surface LS of the light-emitting element of the subpixel, and a structure 104 is arranged so as to cover the side surface of the structure 103. A light-transmitting insulating layer 107 is arranged on the lens 102 and the structure 104. A film FLM is also arranged on the insulating layer 107. The light-receiving surface LR is also arranged on the film FLM, with air assumed to be present between them.

[0081] The refractive index n of the structure 103 and the lens 102 was 1.58, the refractive index n of the insulating layer 107 was 1.41, the refractive index n of the film FLM was 1.5, and the refractive index n of air was 1. The distance between the upper surface of the film FLM and the light receiving surface LR was 350 mm. The structure 104 was assumed to be made of a highly reflective material such as metal, and the reflectance at the interface between the structure 104 and the structure 103 was set to 100%. Note that in model MD0, the structures 103 and 104 were not provided, and a layer having the same refractive index n as the structure 103 was provided.

[0082] The calculation was performed using a lighting analysis simulator, LightTools, manufactured by Synopsys, Inc. Furthermore, assuming that the light source of each subpixel is the light emission of an organic EL element, an organic EL device simulator, Setofos, manufactured by Fluxim, was used to calculate and use the emission spectrum and orientation pattern of an actual element configuration.

[0083] 7A is a diagram showing the angle dependence of brightness of a display panel P using the reference model MD0. The vertical axis represents normalized brightness, which is a relative value when the front brightness (0°) is set to 1. Each piece of data is symmetrical with respect to the angle of 0°, and it can be said that the wider the width at the position of normalized brightness 0.5, the wider the viewing angle. As mentioned above, the shorter the distance between the light source and the lens, the more easily light can enter the lens, and the simulation results also show that the viewing angle improves as the height h of the structure 103 becomes shorter.

[0084] Furthermore, when the height h of the structure 103 is relatively large, the luminance that has once decreased tends to increase again at high angles. This is due to the light emitted by the light-emitting element penetrating into adjacent pixels, causing a change in the color tone of the display. This phenomenon is also a factor in reducing the viewing angle, and it is preferable to suppress this. In particular, it is preferable to suppress this when h = 2 μm or more, at which point the luminance that has once decreased tends to increase again.

[0085] 7B is a diagram showing the angular dependence of brightness of a display panel P using model MD1 shown in FIG. 2. FIG. 8A is a diagram showing the angular dependence of brightness of a display panel P using model MD2. FIG. 8B is a diagram showing the angular dependence of brightness of a display panel P using model MD3. In both cases, it can be seen that when h = 2 μm or more, the tendency for brightness to increase again after temporarily decreasing on the high-angle side is suppressed. It can also be seen that the width at the position where the normalized brightness is 0.5 is wider for models MD1 to MD3 than for model MD0.

[0086] Figure 9A is a diagram comparing the front radiance of each model obtained from the results shown in Figures 7A to 8B. While luminance is a photometric value, radiance is the amount of radiated energy, and the two are proportional. In other words, the higher the radiance, the higher the luminance.

[0087] As mentioned above, when the light-emitting element is positioned closer to the convex lens, the amount of light refracted in the front direction decreases, resulting in a decrease in front brightness. Furthermore, when the light-emitting element is positioned closer to the convex lens, the amount of light refracted in the front direction increases, resulting in an increase in front brightness. As shown in Figure 9A, the above effects are reflected in the simulation results, including those for model MD0.

[0088] 9B is a diagram comparing the improvement rates of front luminance (relative values ​​when the value of model MD0 is set to 1). As a result, the difference between models MD1 to MD3 and model MD0 becomes smaller (approaching 1) when the height h of the structure 103 is high, and it can be seen that at least models MD1 to MD3 do not have factors that reduce the front luminance.

[0089] Furthermore, when the height h of the structure 103 is low, the difference between the models MD1 to MD3 and model MD0 is large (greater than 1). This means that more light travels in the front direction than model MD0. In other words, the effect of reflection by the structure 104 is apparent.

[0090] 9C is a diagram comparing the viewing angle improvement rate (relative value when the value of model MD0 is set to 1) of each model. In FIG. 9C, all values ​​are greater than 1, which indicates that the viewing angle improvement effect can be obtained in all of models MD1 to MD3.

[0091] Furthermore, the greater the height h of the structure 103, the greater the rate of improvement in the viewing angle. Generally, the longer the distance between the lens 102 and the light-emitting element, the lower the viewing angle, so it can be said that the effect of reflection by the structure 104 is apparent. The model with the highest effect in improving the viewing angle is model MD1, followed by model MD3 and model MD2.

[0092] Therefore, in comparing models MD1 to MD3, model MD1, which has a curved surface whose curvature continuously increases from the bottom surface to the top surface of structure 103, is most preferable, followed by model MD2, which has a surface whose absolute value of inclination is constant from the bottom surface to the top surface of structure 103, and then model MD2, which has a curved surface whose curvature continuously decreases from the bottom surface to the top surface of structure 103. It can be said that models MD1 to MD3 have equal or higher front luminance than model MD0, which is the reference. It can also be said that models MD1 to MD3 have a better viewing angle than model MD0.

[0093] The above simulation results demonstrate the effects of the structures 103 and 104 provided between the light emitting element and the lens.

[0094] Next, the structure of a pixel including a light-emitting element will be described. A light-emitting element that can be used in one embodiment of the present invention preferably has an MML (metal maskless) structure in which a light-emitting layer is separately formed using a lithography process without using a FMM (fine metal mask). A light-emitting element with an MML structure can have a higher aperture ratio than a light-emitting element manufactured using an FMM, and can emit light with high luminance or low power consumption. One embodiment of the present invention has a structure in which a light-emitting element with an MML structure is combined with a convex lens to further increase light extraction efficiency.

[0095] 10A is a cross-sectional view corresponding to the cross section B1-B2 shown in the top view of the pixel in the S-stripe arrangement shown in FIG. 10B. The pixel has subpixels 105R, 105G, and 105B. However, the description of subpixel 105R will be omitted here, and only subpixels 105G and 105B will be described. Regarding subpixel 105R, the description of subpixels 105G and 105B can be referred to.

[0096] The light emitting element 110G of the sub-pixel 105G and the light emitting element 110B of the sub-pixel 105B are provided on a substrate 161. The substrate 161 includes a support, as well as elements of a pixel circuit.

[0097] It is preferable to use, for example, an OLED (organic light-emitting diode) or a QLED (quantum-dot light-emitting diode) as the light-emitting element 110G and the light-emitting element 110B. As the light-emitting substance contained in the EL element, not only an organic compound but also an inorganic compound (such as a quantum dot material) can be used.

[0098] The light-emitting element 110G has a pixel electrode 111G, an organic layer 112G, a common layer 114, and a common electrode 113. The light-emitting element 110B has a pixel electrode 111B, an organic layer 112B, a common layer 114, and a common electrode 113. The common layer 114 and the common electrode 113 are provided in common to the light-emitting element 110G and the light-emitting element 110B.

[0099] The organic layer 112G of the light-emitting element 110G contains a light-emitting organic compound that emits at least green light. The organic layer 112B of the light-emitting element 110B contains a light-emitting organic compound that emits at least blue light. The organic layer 112G and the organic layer 112B can also be called EL layers, and each include at least a layer containing a light-emitting substance (light-emitting layer).

[0100] Hereinafter, when describing matters common to light emitting element 110G and light emitting element 110B, they may be referred to as light emitting element 110. Similarly, when describing matters common to components distinguished by alphabets, such as organic layer 112G and organic layer 112B, they may be described using symbols without the alphabets.

[0101] The organic layer 112 and the common layer 114 can each independently have one or more of an electron injection layer, an electron transport layer, a hole injection layer, and a hole transport layer. For example, the organic layer 112 can have a stacked structure of a hole injection layer, a hole transport layer, a light-emitting layer, and an electron transport layer from the pixel electrode 111 side, and the common layer 114 can have an electron injection layer.

[0102] The pixel electrode 111G and the pixel electrode 111B are provided for each light-emitting element. The common electrode 113 and the common layer 114 are provided as a continuous layer common to each light-emitting element. A conductive film that is translucent to visible light is used for either the pixel electrode or the common electrode 113, and a conductive film that is reflective is used for the other. By making each pixel electrode translucent and the common electrode 113 reflective, a bottom-emission display device can be obtained. Conversely, by making each pixel electrode reflective and the common electrode 113 translucent, a top-emission display device can be obtained. Incidentally, by making both the pixel electrodes and the common electrode 113 translucent, a dual-emission display device can also be obtained.

[0103] A protective layer 121 is provided on the common electrode 113 to cover the light emitting elements 110G and 110B. The protective layer 121 has a function of preventing impurities such as water from diffusing from above into each light emitting element.

[0104] The edge of the pixel electrode 111 preferably has a tapered shape. When the edge of the pixel electrode 111 has a tapered shape, the organic layer 112 provided along the edge of the pixel electrode 111 can also have an inclined portion. By tapering the edge of the pixel electrode 111, the coverage of the organic layer 112 provided over the edge of the pixel electrode 111 can be improved. Furthermore, by tapering the side surface of the pixel electrode 111, foreign matter (for example, also referred to as dust or particles) during the manufacturing process can be easily removed by a process such as cleaning, which is preferable.

[0105] In this specification and the like, the term "tapered shape" refers to a shape in which at least a part of a side surface of a structure is inclined with respect to a substrate surface. For example, it is preferable that the structure has a region in which the angle between the inclined side surface and the substrate surface (also referred to as the taper angle) is less than 90°.

[0106] The organic layer 112 is processed into an island shape using, for example, a resist mask formed by lithography. As a result, the organic layer 112 has a shape in which the angle between the top surface and the side surface is close to 90 degrees at its edge. On the other hand, an organic film formed using FMM (Fine Metal Mask) or the like tends to be gradually thinner toward the edge, and the top surface is formed in a sloped shape over a range of, for example, 1 μm to 10 μm, making it difficult to distinguish between the top surface and the side surface.

[0107] Between two adjacent light emitting elements, an insulating layer 124, an insulating layer 125 and a resin layer 126 are provided.

[0108] Between two adjacent light-emitting elements, the side surfaces of the organic layers 112 face each other with the resin layer 126 sandwiched therebetween. The resin layer 126 is located between the two adjacent light-emitting elements and is provided so as to fill the ends of each organic layer 112 and the region between the two organic layers 112. The resin layer 126 has a smooth, convex upper surface, and a common layer 114 and a common electrode 113 are provided to cover the upper surface of the resin layer 126.

[0109] The resin layer 126 functions as a planarizing film that fills in the step between two adjacent light-emitting elements. By providing the resin layer 126, it is possible to prevent the common electrode 113 from being separated by the step at the end of the organic layer 112 (also called step disconnection), which would otherwise occur and result in insulation of the common electrode on the organic layer 112.

[0110] Furthermore, the resin layer 126 insulates the organic layers 112 of adjacent light-emitting elements 110 from each other. This reduces leakage current between adjacent light-emitting elements via the organic layers 112, thereby suppressing unnecessary light emission due to crosstalk. This improves the color-developing performance of the display device.

[0111] An insulating layer containing an organic material can be suitably used as the resin layer 126. For example, acrylic resin, polyimide resin, epoxy resin, imide resin, polyamide resin, polyimideamide resin, silicone resin, siloxane resin, benzocyclobutene resin, phenolic resin, precursors of these resins, etc. can be used as the resin layer 126. Alternatively, organic materials such as polyvinyl alcohol (PVA), polyvinyl butyral, polyvinylpyrrolidone, polyethylene glycol, polyglycerin, pullulan, water-soluble cellulose, or alcohol-soluble polyamide resin can be used as the resin layer 126.

[0112] Furthermore, a photosensitive resin can be used as the resin layer 126. A photoresist can be used as the photosensitive resin. The photosensitive resin can be a positive-type material or a negative-type material.

[0113] The resin layer 126 may contain a material that absorbs visible light. For example, the resin layer 126 itself may be made of a material that absorbs visible light, or the resin layer 126 may contain a pigment that absorbs visible light. For example, the resin layer 126 may be a resin that can be used as a color filter that transmits red, blue, or green light and absorbs other light, or a resin that contains carbon black as a pigment and functions as a black matrix.

[0114] The resin layer 126 absorbs light emitted from the light emitting element in an oblique direction, thereby suppressing leakage of light (stray light) from the light emitting element to an adjacent light emitting element via the resin layer 126. This improves the display quality of the display device.

[0115] The insulating layer 125 is provided in contact with the side surface of the organic layer 112. The insulating layer 125 is also provided to cover the upper end portion of the organic layer 112. A portion of the insulating layer 125 is provided in contact with the upper surface of the substrate 161.

[0116] The insulating layer 125 is located between the resin layer 126 and the organic layer 112, and functions as a protective film to prevent the resin layer 126 from contacting the organic layer 112. If the organic layer 112 and the resin layer 126 come into contact with each other, the organic layer 112 may be dissolved by an organic solvent or the like used when forming the resin layer 126. Therefore, by providing the insulating layer 125 between the organic layer 112 and the resin layer 126, it is possible to protect the side surfaces of the organic layer 112.

[0117] The insulating layer 125 can be an insulating layer containing an inorganic material. For example, an inorganic insulating film such as an insulating oxide film, a nitride insulating film, an oxynitride insulating film, or a nitride oxide insulating film can be used for the insulating layer 125. The insulating layer 125 may have a single-layer structure or a stacked-layer structure. Examples of oxide insulating films include a silicon oxide film, an aluminum oxide film, a magnesium oxide film, an indium gallium zinc oxide film, a gallium oxide film, a germanium oxide film, an yttrium oxide film, a zirconium oxide film, a lanthanum oxide film, a neodymium oxide film, a hafnium oxide film, and a tantalum oxide film. Examples of nitride insulating films include a silicon nitride film and an aluminum nitride film. Examples of oxynitride insulating films include a silicon oxynitride film and an aluminum oxynitride film. Examples of nitride oxide insulating films include a silicon nitride oxide film and an aluminum nitride oxide film. In particular, by using a metal oxide film such as an aluminum oxide film or a hafnium oxide film formed by an ALD method, or an inorganic insulating film such as a silicon nitride film or a silicon oxide film, as the insulating layer 125, an insulating layer 125 with few pinholes and excellent protection of the EL layer can be formed.

[0118] In this specification and elsewhere, an oxynitride refers to a material whose composition contains more oxygen than nitrogen, and a nitride oxide refers to a material whose composition contains more nitrogen than oxygen. For example, silicon oxynitride refers to a material whose composition contains more oxygen than nitrogen, and silicon nitride oxide refers to a material whose composition contains more nitrogen than oxygen.

[0119] The insulating layer 125 can be formed by a sputtering method, a CVD method, a PLD method, an ALD method, or the like. The insulating layer 125 is preferably formed by an ALD method because it has good coverage.

[0120] Furthermore, a reflective film (e.g., a metal film containing one or more selected from silver, palladium, copper, titanium, aluminum, etc.) may be provided between the insulating layer 125 and the resin layer 126, so that the light emitted from the light-emitting layer is reflected by the reflective film, thereby improving the light extraction efficiency.

[0121] The insulating layer 124 is a portion of a protective layer (also referred to as a mask layer or a sacrificial layer) that protects the organic layer 112 when the organic layer 112 is etched. The insulating layer 124 can be made of the same material as can be used for the insulating layer 125. In particular, it is preferable to use the same material for the insulating layer 124 and the insulating layer 125 because this allows the use of common processing equipment and the like.

[0122] In particular, metal oxide films such as aluminum oxide films and hafnium oxide films, or inorganic insulating films such as silicon nitride films and silicon oxide films formed by the ALD method have few pinholes and are therefore excellent in the function of protecting the EL layer, and can be suitably used for the insulating layer 125 and the insulating layer 124.

[0123] The protective layer 121 can have, for example, a single-layer structure or a stacked structure including at least an inorganic insulating film. Examples of the inorganic insulating film include oxide films or nitride films such as a silicon oxide film, a silicon oxynitride film, a silicon nitride oxide film, a silicon nitride film, an aluminum oxide film, an aluminum oxynitride film, and a hafnium oxide film. Alternatively, a semiconductor material or a conductive material such as indium gallium oxide, indium zinc oxide, indium tin oxide, or indium gallium zinc oxide may be used as the protective layer 121. The structure from the substrate 161 to the protective layer 121 corresponds to the stacked body 100 shown in FIG. 1 .

[0124] The structures 103 (structures 103G and 103B) and the structure 104 are provided on the protective layer 121. Details of the structures 103 and 104 will be described later. As described above, the bottom surface of the structure 103 may have multiple flat or curved surfaces due to the influence of the unevenness of the structures that make up the pixel. In such cases, as shown in FIG. 10A , the diameter D103L of the bottom surface of the structure 103 can be the diameter of the bottom when viewed from above.

[0125] Lenses 102 (lenses 102G and 102B), which are plano-convex lenses, are provided on structures 103 and 104 so as to overlap light-emitting element 110. In addition, an insulating layer 107 is provided on lens 102. Lenses 102 are provided in pairs with light-emitting element 110. In other words, one lens 102 is provided for each sub-pixel.

[0126] The lens 102 is provided above the light-emitting element 110 (in the direction in which light is emitted). The lens 102 has a convex lens shape, and therefore can act in a direction to converge light. In other words, the lens 102 can suppress divergence of light emitted by the light-emitting element, thereby improving the light extraction efficiency of the display device. The lens 102 can be manufactured using the same material and process as the resin layer 126.

[0127] 11A to 11E are diagrams illustrating an example of a manufacturing process for the lens 102. FIG.

[0128] First, a photosensitive resin is applied onto the insulating layer and pre-baked to form a resin layer 102a (see FIG. 11A). The photosensitive resin may be, for example, the material used to form the resin layer 126 described above. Although an example using a positive photosensitive resin is described here, a negative photosensitive resin may also be used.

[0129] Next, a photomask 145 is used to shield the regions where the lenses 102 are to be formed from light, and the resin layer 102a is exposed to light (see FIG. 11B). When a negative photosensitive resin is used, a photomask is used that shields the regions where the lenses 102 are not to be formed from light. The arrows in the figure indicate the light used for exposure.

[0130] Next, a development step is performed to remove unnecessary regions of the resin layer 102a, forming a resin layer 102b (see FIG. 11C). Here, since the resin layer 102b is unexposed, unreacted components remain and the resin layer 102b may be colored. Since the lens 102 to be formed preferably has high transmittance to visible light, if the resin layer 102b is colored, the resin layer 102b is exposed to light to promote the reaction.

[0131] By promoting the reaction, a resin layer 102c with improved transmittance can be formed (see FIG. 11D). Furthermore, by performing such exposure after the development step, the post-baking temperature of the resin layer 102c in a subsequent step can be reduced in some cases. Note that if the resin layer 102b is not colored, exposure after the development step may not be necessary.

[0132] Then, post-baking is performed to reflow and harden the resin layer 102c, thereby forming the lens 102 (FIG. 11E).

[0133] The insulating layer 107 provided on the lens 102 is an adhesive layer provided between the lens 102 and the substrate 163, and is preferably made of an organic material. For example, an optical adhesive having a refractive index close to that of the glass or film that can be used as the substrate 163 can be used.

[0134] Although the provision of the lens can improve the efficiency of light extraction from the display panel, it is also effective to use a light-emitting element with higher luminous efficiency in order to improve the front brightness of the display panel. In principle, the brightness of tandem organic EL elements improves depending on the number of layers they are stacked in if the current density is the same, and a two-layer tandem organic EL element can achieve twice the brightness of a single-layer light-emitting element.

[0135] Furthermore, because the lifespan of an organic EL element depends on the current density, even if the brightness of a tandem organic EL element is doubled, the lifespan will be equivalent to that of a single organic EL element if the current density is the same. In other words, tandem organic EL elements are an effective technology for increasing the brightness and reliability of organic EL elements.

[0136] The above is a description of an example of the configuration of the light-emitting element and its vicinity. Next, the structure 103 and the structure 104 will be described in detail.

[0137] 12A is a diagram illustrating a specific example of the structure 103 (structures 103G and 103B) and the structure 104. In the configuration shown in Fig. 12A, the structure 104 has a layer 104A and a layer 104B. The layer 104A is provided between the structure 103 and the layer 104B.

[0138] The layer 104A is a reflective layer having high reflectivity for light emitted from the light-emitting element, and can be made of, for example, a metal film such as Ag, Al, or APC (an alloy of Ag, Pd, and Cu). Alternatively, an insulating layer having a refractive index for light emitted from the light-emitting element that is smaller than that of the structure 103 can be used so that total reflection can occur easily. Typical examples of the insulating layer include a silicon oxide film, an aluminum oxide film, a silicon nitride film, an aluminum nitride film, a silicon oxynitride film, and an aluminum oxynitride film.

[0139] Layer 104B is a layer that fills the spaces between adjacent structures 103, and can be made of a resin layer, a metal layer, an inorganic insulating layer, etc. Note that when layer 104A is an insulating layer having a smaller refractive index than structures 103 and a light-transmitting resin layer or inorganic insulating layer is used, it is preferable to use a material that has a smaller refractive index for light emitted from the light-emitting element than layer 104A so that total reflection occurs more easily.

[0140] Next, an outline of a manufacturing method of the structure of one embodiment of the present invention shown in Fig. 12A will be described. In this manufacturing method, the structure 103 is formed, and then the structure 104 is formed. Therefore, a step of opening a shield over the light-emitting element is not required.

[0141] First, as shown in Fig. 12B , structure 103, which will serve as a light guide path, is formed on protective layer 121. For simplicity, protective layer 121 is shown in a planar form. The material for forming structure 103 can be, for example, the same material as that for resin layer 126 described above. To give the sidewall of structure 103 an inverse tapered shape as shown in Fig. 12B , there are methods such as using a negative photosensitive resin or using an easily peelable structure having the same shape as structure 104 as a mold.

[0142] Next, a layer 104a, which is a reflective film, is formed on the wall surface of the structure 103 (see FIG. 12C ). The layer 104a can be formed by evaporation, sputtering, CVD, or the like. In particular, it is preferable to use ALD (Atomic Layer Deposition), which can easily form a uniform film even on an inverted tapered surface.

[0143] Next, a laminate is formed by providing layer 104b on structure 103 and layer 104a (see FIG. 12D), and the upper part of the laminate is polished with a grinder GD to expose the upper surface of structure 103 (see FIG. 12E). By forming structures 103 and 104 (layers 104A and 104B) using this method and providing lens 102 on structures 103 and 104, the structure shown in FIG. 12A can be formed.

[0144] 13A is a diagram illustrating a structure of one embodiment of the present invention that is different from that of FIG. 12A . In the structure shown in FIG. 13A , the structure 104 is formed, and then the structure 103 is formed. The side surface of the structure 104 can be tapered relatively easily. Since the structure 103 is formed in an opening surrounded by the structure 104, it is also easy to form the side surface of the structure 103 into an inverse tapered shape.

[0145] 13B, a layer 104B is formed on the protective layer 121. To form the sidewall of the structure 104 into a tapered shape, there are a method using a positive photosensitive resin, a method of forming a thick film to be the layer 104B and then opening it using an isotropic etching method, and the like.

[0146] Next, a layer 104a is formed on the wall surfaces of the layer 104B and on the exposed upper surface of the protective layer 121 (see FIG. 13C), and the layer 104a on the protective layer 121 is removed to form a layer 104A (see FIG. 13D).

[0147] Then, the structure 103 is formed so as to cover the exposed upper surface of the protective layer 121 and the sidewall of the layer 104A, and the lens 102 is formed on the structure 103 and the structure 104 (see FIG. 13E). Note that when the structure 103 and the lens 102 are formed of the same material, the structure 103 and the lens 102 can also be formed using the same process.

[0148] Fig. 14A is a diagram illustrating a configuration different from Fig. 12A and Fig. 13A. The configuration shown in Fig. 14A is similar to Fig. 13A in that structure 104 is formed followed by structure 103, but differs in that structure 104 is formed as a single layer of layer 104A. Therefore, the configuration shown in Fig. 14A can be formed in fewer steps than the configuration shown in Fig. 13A.

[0149] 14B, a layer 104a is formed on the protective layer 121. The layer 104a is a thick film such as the above-mentioned metal film or an insulating film having a refractive index smaller than that of the material used for the structure 103.

[0150] Next, a resist mask 108 is formed on the layer 104a, and dry etching is performed in an anisotropic etching mode to a depth L1 (see FIG. 14C). Next, the mode is switched to isotropic etching, and dry etching is performed to the remaining load depth L2 (see FIG. 14D). In this way, by processing the layer 104a using a combination of anisotropic etching and isotropic etching, the layer 104a can be formed with tapered sidewalls.

[0151] The depths L1 and L2 vary depending on the material used, and can be appropriately determined so that the sidewalls have a desired tapered shape. In the above, the abnormal etching and the isotropic etching are performed once each, but they may be performed one or more times alternately.

[0152] Next, after removing the resist mask 108, the structure 103 is formed so as to cover the exposed upper surface of the protective layer 121 and the sidewall of the layer 104A, and the lens 102 is formed on the structure 103 and the structure 104 (see FIG. 14E ). Note that when the structure 103 and the lens 102 are formed of the same material, the structure 103 and the lens 102 can also be formed using the same process.

[0153] When the structure 104 is used as a light absorbing layer, a colored resin such as black resin can be provided instead of the layer 104a and processed in the same manner. Alternatively, if a photosensitive resin is used as the colored resin, the layer 104A having tapered sidewalls can be formed only by a lithography process.

[0154] 15A is a block diagram illustrating a display device according to one embodiment of the present invention. The display device 20 includes a pixel array 74, a circuit 75, and a circuit 76. The pixel array 74 includes pixels 40 arranged in a column direction and a row direction.

[0155] The pixel 40 can have a plurality of sub-pixels 71. The sub-pixels 71 have the function of emitting light for display. By assigning colors such as R (red), G (green), and B (blue) to the light emitted by the sub-pixels 71, a full-color display can be achieved.

[0156] The subpixel 71 has a light-emitting device that emits unpolarized visible light. As the light-emitting device, it is preferable to use an EL element such as an OLED (organic light-emitting diode) or a QLED (quantum-dot light-emitting diode). Examples of light-emitting materials that the EL element has include fluorescent materials, phosphorescent materials, thermally activated delayed fluorescence (TADF) materials, and inorganic compounds (quantum dot materials). Alternatively, an LED such as a micro LED can be used as the light-emitting device.

[0157] The circuit 75 and the circuit 76 are driver circuits for driving the sub-pixel 71. The circuit 75 can function as a source driver circuit, and the circuit 76 can function as a gate driver circuit. The circuits 75 and 76 can be, for example, shift register circuits.

[0158] The display device 20 may be divided into a plurality of regions vertically and horizontally, and pixels may be driven for each divided region.

[0159] 15B , the circuit 75 and the circuit 76 can be separately arranged below the pixel array 74. In this case, the display device 20 has a laminated structure of a layer 77 and a layer 78, and a plurality of the circuits 75 and a plurality of the circuits 76 are provided on the layer 77, and the pixel array 74 is provided on the layer 78 so as to overlap the circuits 75 and the circuits 76.

[0160] By dividing the circuit 75 and the circuit 76, the pixel array 74 can be driven for each divided area. For example, the pixel array 74 can be operated at different frame rates in parts. The pixel array 74 can be displayed at different resolutions in parts, and can also be made compatible with foveated rendering.

[0161] Furthermore, by providing the driver circuit below the pixel array 74, the wiring length can be shortened and the wiring capacitance can be reduced. This allows the display device 20 to operate at high speed and with low power consumption. Furthermore, the display device 20 can have a narrow frame.

[0162] 15B is an example and can be changed as appropriate. Part of the circuit 75 and the circuit 76 can be formed in the same layer as the pixel array 74. The layer 77 may also include circuits such as a memory circuit, an arithmetic circuit, and a communication circuit.

[0163] In this structure, for example, the layer 77 is provided on a single crystal silicon substrate, the circuits 75 and 76 are formed using transistors having silicon in their channel formation regions (hereinafter referred to as Si transistors), and the pixel circuits included in the pixel array 74 provided in the layer 78 are formed using transistors having metal oxide in their channel formation regions (hereinafter referred to as OS transistors). The OS transistor can be formed using a thin film and can be stacked on the Si transistor.

[0164] 15C , a structure may be adopted in which a layer 79 including an OS transistor is provided between the layer 77 and the layer 78. The layer 79 may include an OS transistor that forms part of a pixel circuit included in the pixel array 74. Alternatively, the layer 79 may include an OS transistor that forms part of the circuit 75 and the circuit 76. Alternatively, the layer 77 may include an OS transistor that forms part of a circuit such as a memory circuit, an arithmetic circuit, or a communication circuit.

[0165] Furthermore, the shape of the display device 20 when viewed from above is not limited to a rectangle, but may be a circle as shown in Fig. 15D, or a polygon such as an octagon as shown in Fig. 15E.

[0166] 16A is a diagram showing an example of an eyeglass-type device having a display device and an optical device according to one embodiment of the present invention. Here, a combination of a display device 20 and an optical device 21 is shown by a dashed line as a display unit 60. FIG. 16C is a diagram illustrating elements of the display unit 60.

[0167] The user can view the image displayed on the display device 20 by bringing their eyes close to the optical device 21 provided on the display surface side of the display device 20. The user can view the image with the viewing angle widened by the optical device 21, which gives the user a sense of immersion and realism.

[0168] A linear polarizer 62 and a retardation film 63 can be attached to the display surface of the display device 20. The optical device 21 can have a configuration including, for example, a half mirror 64, a lens 65, a retardation film 66, a reflective polarizer 67, and a lens 68.

[0169] The optical device 21 converts the light emitted by the display device 20 into linearly polarized light or circularly polarized light and utilizes it to selectively reflect or transmit light at elements arranged on the optical path. This allows the optical path length to be secured within a limited space, and the focal length of the optical device to be shortened. This type of optical system is called a catadioptric system. It is also sometimes called a pancake lens due to its thin shape.

[0170] The two display units 60 are incorporated into the housing 30 so that the surfaces of the lenses 68 are exposed on the inside. One display unit 60 is for the right eye, and the other display unit 60 is for the left eye, and by displaying images corresponding to the parallax on each display unit 60, the user can feel the three-dimensionality of the image.

[0171] Furthermore, the housing 30 or the holder 35 may be provided with an input terminal and an output terminal. The input terminal can be connected to a cable that supplies a video signal from a video output device or the like, power for charging the battery, etc. The output terminal, for example, functions as an audio output terminal, and can be connected to earphones, headphones, etc. Note that if the device is configured to be able to output audio data via wireless communication, or if audio is output from an external video output device, the audio output terminal need not be provided.

[0172] Furthermore, a wireless communication module and a storage module may be provided inside the housing 30 or the holder 35. The wireless communication module performs wireless communication, and the content to be viewed can be downloaded and stored in the storage module. This allows the user to view the downloaded content offline.

[0173] 16B , a line-of-sight detection sensor 41 may be provided within the housing 30. The line-of-sight detection sensor 41 detects the position of the gaze by detecting changes in the reflected light due to iris movement using light emitted from a light source 42 provided within the housing 30. The light emitted by the light source 42 is preferably near-infrared light, which has extremely low visibility. For example, operation buttons such as power on, power off, sleep, volume adjustment, channel change, menu display, selection, decision, and back, as well as operation buttons such as video play, stop, pause, fast forward, and fast rewind, may be displayed, and the respective operations can be performed by visually recognizing the operation buttons. Furthermore, the user's level of fatigue may be detected based on the number of blinks, and an alert may be displayed.

[0174] By using the display device of one embodiment of the present invention for a glasses-type device, the electronic device can have low power consumption and high reliability.

[0175] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0176] Embodiment 2 In this embodiment, a structural example of a display panel that can be used as a display device according to one embodiment of the present invention will be described.

[0177] The display panel of this embodiment is a high-definition display panel, and is particularly suitable for use as the display section of VR devices such as head-mounted displays, and wearable devices that can be worn on the head, such as eyeglass-type AR devices.

[0178] 17A shows a perspective view of a display module 280. The display module 280 has a display panel 200A and an FPC 290. Note that the display panel included in the display module 280 is not limited to the display panel 200A, and may be any of display panels 200B to 200F described below.

[0179] The display module 280 has a substrate 291 and a substrate 292. The display module 280 has a display unit 281. The display unit 281 is an area for displaying an image.

[0180] 17B is a perspective view schematically illustrating the configuration on the substrate 291 side. A circuit portion 282, a pixel circuit portion 283 on the circuit portion 282, and a pixel portion 284 on the pixel circuit portion 283 are stacked on the substrate 291. A terminal portion 285 for connecting to the FPC 290 is provided in a portion of the substrate 291 that does not overlap with the pixel portion 284. The terminal portion 285 and the circuit portion 282 are connected via a wiring portion 286 composed of a plurality of wirings.

[0181] The pixel section 284 has a plurality of periodically arranged pixels 284a. An enlarged view of one pixel 284a is shown on the right side of Fig. 17B. The pixel 284a has a light-emitting element 110R that emits red light, a light-emitting element 110G that emits green light, and a light-emitting element 110B that emits blue light.

[0182] The pixel circuit portion 283 has a plurality of pixel circuits 283a arranged periodically. Each pixel circuit 283a is a circuit that controls the light emission of three light-emitting devices included in one pixel 284a. One pixel circuit 283a may be configured to have three circuits that control the light emission of one light-emitting device. For example, the pixel circuit 283a may be configured to have at least one selection transistor, one current control transistor (drive transistor), and a capacitor for each light-emitting device. In this case, a gate signal is input to the gate of the selection transistor, and a source signal is input to the source. This realizes an active matrix display panel.

[0183] The circuit portion 282 includes a circuit for driving each pixel circuit 283a in the pixel circuit portion 283. For example, it is preferable that the circuit portion 282 includes one or both of a gate line driver circuit and a source line driver circuit. In addition, the circuit portion 282 may include at least one of an arithmetic circuit, a memory circuit, a power supply circuit, and the like. Furthermore, a transistor provided in the circuit portion 282 may constitute a part of the pixel circuit 283a. That is, the pixel circuit 283a may be composed of a transistor included in the pixel circuit portion 283 and a transistor included in the circuit portion 282.

[0184] The FPC 290 functions as wiring for supplying a video signal, a power supply potential, etc. from the outside to the circuit portion 282. An IC may be mounted on the FPC 290.

[0185] The display module 280 can be configured such that one or both of the pixel circuit unit 283 and the circuit unit 282 are provided overlapping below the pixel unit 284, thereby enabling the aperture ratio (effective display area ratio) of the display unit 281 to be extremely high. For example, the aperture ratio of the display unit 281 can be set to 40% or more and less than 100%, preferably 50% or more and 95% or less, and more preferably 60% or more and 95% or less. Furthermore, the pixels 284a can be arranged at an extremely high density, enabling the pixel density of the display unit 281 to be extremely high. For example, it is preferable that the pixels 284a be arranged in the display unit 281 at a pixel density of 2000 ppi or more, preferably 3000 ppi or more, more preferably 5000 ppi or more, and even more preferably 6000 ppi or more, and 20,000 ppi or less, or 30,000 ppi or less.

[0186] Because such a display module 280 has extremely high resolution, it can be suitably used in VR devices such as head-mounted displays, or eyeglass-type AR devices. For example, even in a configuration in which the display unit of the display module 280 is viewed through lenses, the display module 280 has an extremely high-resolution display unit 281, so even if the display unit is enlarged with the lenses, the pixels are not visible, allowing for a highly immersive display. Furthermore, the display module 280 is not limited to this, and can be suitably used in electronic devices with relatively small display units. For example, it can be suitably used in the display unit of a wearable electronic device such as a wristwatch.

[0187] [Display Panel 200A] The display panel 200A shown in FIG. 18 includes a substrate 301, light-emitting elements 110R, 110G, and 110B, a capacitor 240, and a transistor 310.

[0188] Substrate 301 corresponds to substrate 291 in FIGS. 17A and 17B.

[0189] The transistor 310 has a channel formation region in a substrate 301. The substrate 301 can be, for example, a semiconductor substrate such as a single crystal silicon substrate. The transistor 310 includes a part of the substrate 301, a conductive layer 311, a low-resistance region 312, an insulating layer 313, and an insulating layer 314. The conductive layer 311 functions as a gate electrode. The insulating layer 313 is located between the substrate 301 and the conductive layer 311 and functions as a gate insulating layer. The low-resistance region 312 is a region in which the substrate 301 is doped with impurities and functions as one of a source and a drain. The insulating layer 314 is provided to cover a side surface of the conductive layer 311.

[0190] An element isolation layer 315 is provided between two adjacent transistors 310 so as to be embedded in the substrate 301 .

[0191] In addition, an insulating layer 261 is provided to cover the transistor 310 , and a capacitor 240 is provided over the insulating layer 261 .

[0192] The capacitor 240 has a conductive layer 241, a conductive layer 245, and an insulating layer 243 located therebetween. The conductive layer 241 functions as one electrode of the capacitor 240, the conductive layer 245 functions as the other electrode of the capacitor 240, and the insulating layer 243 functions as a dielectric of the capacitor 240.

[0193] The conductive layer 241 is provided over the insulating layer 261 and is buried in the insulating layer 254. The conductive layer 241 is connected to one of the source and drain of the transistor 310 by a plug 271 buried in the insulating layer 261. The insulating layer 243 is provided to cover the conductive layer 241. The conductive layer 245 is provided in a region overlapping with the conductive layer 241 with the insulating layer 243 interposed therebetween.

[0194] An insulating layer 255a is provided to cover the capacitor 240, an insulating layer 255b is provided over the insulating layer 255a, and an insulating layer 255c is provided over the insulating layer 255b.

[0195] An inorganic insulating film can be preferably used for each of the insulating layers 255a, 255b, and 255c. For example, it is preferable to use a silicon oxide film for the insulating layer 255a and the insulating layer 255c, and a silicon nitride film for the insulating layer 255b. This allows the insulating layer 255b to function as an etching protection film. In this embodiment, an example is shown in which part of the insulating layer 255c is etched to form a recess, but the insulating layer 255c does not necessarily have to have a recess.

[0196] The light-emitting elements 110G and 110B are provided over the insulating layer 255c. Embodiment 1 can be referred to for the structures of the light-emitting elements 110G and 110B.

[0197] In the display panel 200A, a separate light-emitting device is fabricated for each emitted color, resulting in minimal change in chromaticity between light emitted at low and high luminance. Furthermore, because the organic layers 112G and 112B are spaced apart from each other, crosstalk between adjacent subpixels can be suppressed even in a high-resolution display panel. This makes it possible to realize a high-resolution display panel with high display quality.

[0198] An insulating layer 125 and a resin layer 126 are provided in the region between adjacent light emitting elements.

[0199] The pixel electrode 111G and the pixel electrode 111B of the light-emitting element are connected to one of the source and drain of the transistor 310 via a plug 256 embedded in the insulating layers 255a, 255b, 255c, and 243, a conductive layer 241 embedded in the insulating layer 254, and a plug 271 embedded in the insulating layer 261. The height of the top surface of the insulating layer 255c and the height of the top surface of the plug 256 are the same or approximately the same. Various conductive materials can be used for the plug.

[0200] In addition, a protective layer 121 is provided on light-emitting elements 110G and 110B. Structures 103 (structures 103G and 103B), structure 104, and lens 102 (lenses 102G and 102B) are provided on protective layer 121. Substrate 163 is bonded to lens 102 with insulating layer 107 functioning as an adhesive layer.

[0201] There is no insulating layer covering the upper end of each pixel electrode 111 between two adjacent pixel electrodes 111. This allows the distance between adjacent light-emitting elements to be extremely narrow, resulting in a high-definition or high-resolution display panel.

[0202] 19 has a configuration in which a transistor 310A and a transistor 310B, each having a channel formed in a semiconductor substrate, are stacked. Note that in the following description of the display panel, descriptions of parts that are the same as those of the display panel described above may be omitted.

[0203] The display panel 200B has a structure in which a substrate 301B provided with a transistor 310B, a capacitor 240, and a light-emitting device and a substrate 301A provided with a transistor 310A are bonded together.

[0204] Here, an insulating layer 345 is provided on the lower surface of the substrate 301B, and an insulating layer 346 is provided on the insulating layer 261 provided on the substrate 301A. The insulating layers 345 and 346 function as protective layers and can suppress the diffusion of impurities into the substrates 301B and 301A. The insulating layers 345 and 346 can be made of an inorganic insulating film that can be used for the protective layer 121.

[0205] The substrate 301B is provided with a plug 343 that penetrates the substrate 301B and an insulating layer 345. Here, it is preferable to provide an insulating layer 344 that covers the side surface of the plug 343 and functions as a protective layer.

[0206] Furthermore, in the substrate 301B, a conductive layer 342 is provided below the insulating layer 345. The conductive layer 342 is embedded in the insulating layer 335, and the lower surfaces of the conductive layer 342 and the insulating layer 335 are flattened. The conductive layer 342 is connected to a plug 343.

[0207] On the other hand, in the substrate 301A, a conductive layer 341 is provided on an insulating layer 346. The conductive layer 341 is embedded in the insulating layer 336, and the upper surfaces of the conductive layer 341 and the insulating layer 336 are flattened.

[0208] It is preferable to use the same conductive material for the conductive layers 341 and 342. For example, a metal film containing an element selected from Al, Cr, Cu, Ta, Ti, Mo, and W, or a metal nitride film containing the above elements (titanium nitride film, molybdenum nitride film, tungsten nitride film), etc., can be used. In particular, it is preferable to use copper for the conductive layers 341 and 342. This allows for the application of Cu-Cu (copper-copper) direct bonding technology (technology that achieves electrical conductivity by connecting Cu (copper) pads together).

[0209] [Display Panel 200C] A display panel 200C shown in FIG. 20 has a configuration in which a conductive layer 341 and a conductive layer 342 are bonded via a bump 347.

[0210] 20 , by providing a bump 347 between the conductive layer 341 and the conductive layer 342, the conductive layer 341 and the conductive layer 342 can be electrically connected. The bump 347 can be formed using a conductive material containing, for example, gold (Au), nickel (Ni), indium (In), tin (Sn), or the like. Alternatively, for example, solder may be used as the bump 347. An adhesive layer 348 may be provided between the insulating layer 345 and the insulating layer 346. When the bump 347 is provided, the insulating layer 335 and the insulating layer 336 may not be provided.

[0211] [Display Panel 200D] The display panel 200D shown in FIG. 21 differs from the display panel 200A mainly in the configuration of the transistors.

[0212] The transistor 320 is a transistor (OS transistor) in which a metal oxide (also referred to as an oxide semiconductor) is used for a semiconductor layer in which a channel is formed.

[0213] The transistor 320 includes a semiconductor layer 321 , an insulating layer 323 , a conductive layer 324 , a pair of conductive layers 325 , an insulating layer 326 , and a conductive layer 327 .

[0214] Substrate 331 corresponds to substrate 291 in FIGS. 17A and 17B.

[0215] An insulating layer 332 is provided over a substrate 331. The insulating layer 332 functions as a barrier layer that prevents impurities such as water or hydrogen from diffusing from the substrate 331 to the transistor 320 and prevents oxygen from being released from the semiconductor layer 321 toward the insulating layer 332. The insulating layer 332 can be, for example, a film through which hydrogen or oxygen is less likely to diffuse than a silicon oxide film, such as an aluminum oxide film, a hafnium oxide film, or a silicon nitride film.

[0216] A conductive layer 327 is provided over the insulating layer 332, and an insulating layer 326 is provided to cover the conductive layer 327. The conductive layer 327 functions as a first gate electrode of the transistor 320, and part of the insulating layer 326 functions as a first gate insulating layer. An oxide insulating film such as a silicon oxide film is preferably used for at least a portion of the insulating layer 326 that is in contact with the semiconductor layer 321. The top surface of the insulating layer 326 is preferably planarized.

[0217] The semiconductor layer 321 is provided over the insulating layer 326. The semiconductor layer 321 preferably includes a metal oxide (also referred to as an oxide semiconductor) film exhibiting semiconductor characteristics. A pair of conductive layers 325 is provided on and in contact with the semiconductor layer 321 and functions as a source electrode and a drain electrode.

[0218] An insulating layer 328 is provided to cover top surfaces and side surfaces of the pair of conductive layers 325 and side surfaces of the semiconductor layer 321, and an insulating layer 264 is provided over the insulating layer 328. The insulating layer 328 functions as a barrier layer that prevents impurities such as water or hydrogen from diffusing from the insulating layer 264 or the like into the semiconductor layer 321 and prevents oxygen from being released from the semiconductor layer 321. The insulating layer 328 can be an insulating film similar to the insulating layer 332.

[0219] An opening reaching the semiconductor layer 321 is provided in the insulating layer 328 and the insulating layer 264. An insulating layer 323 in contact with the top surface of the semiconductor layer 321 and a conductive layer 324 are buried in the opening. The conductive layer 324 functions as a second gate electrode, and the insulating layer 323 functions as a second gate insulating layer.

[0220] The upper surfaces of the conductive layer 324, the insulating layer 323, and the insulating layer 264 are planarized so that their heights are the same or approximately the same, and insulating layers 329 and 265 are provided to cover them.

[0221] The insulating layer 264 and the insulating layer 265 function as interlayer insulating layers. The insulating layer 329 functions as a barrier layer that prevents impurities such as water or hydrogen from diffusing from the insulating layer 265 or the like to the transistor 320. The insulating layer 329 can be formed using an insulating film similar to the insulating layer 328 and the insulating layer 332.

[0222] The plug 274 connected to one of the pair of conductive layers 325 is provided so as to be embedded in the insulating layer 265, the insulating layer 329, and the insulating layer 264. Here, the plug 274 preferably has a conductive layer 274a covering the side surfaces of the openings of the insulating layer 265, the insulating layer 329, the insulating layer 264, and the insulating layer 328 and part of the top surface of the conductive layer 325, and a conductive layer 274b in contact with the top surface of the conductive layer 274a. In this case, it is preferable to use a conductive material through which hydrogen and oxygen do not easily diffuse as the conductive layer 274a.

[0223] Note that the structure of the transistor included in the display panel of this embodiment is not particularly limited. For example, a planar transistor, a staggered transistor, an inverted staggered transistor, or the like can be used. Furthermore, either a top-gate transistor or a bottom-gate transistor structure may be used. Alternatively, gates may be provided above and below a semiconductor layer in which a channel is formed.

[0224] The transistor 320 has a structure in which a semiconductor layer in which a channel is formed is sandwiched between two gates. The two gates may be connected and the transistor may be driven by supplying the same signal to them. Alternatively, the threshold voltage of the transistor may be controlled by applying a potential for controlling the threshold voltage to one of the two gates and a potential for driving to the other.

[0225] The crystallinity of a semiconductor material used for a semiconductor layer of a transistor is not particularly limited, and any of an amorphous semiconductor, a single-crystal semiconductor, and a semiconductor having crystallinity other than single crystal (a microcrystalline semiconductor, a polycrystalline semiconductor, or a semiconductor having a crystalline region in part) may be used. The use of a single-crystal semiconductor or a crystalline semiconductor is preferable because it can suppress deterioration of transistor characteristics.

[0226] The band gap of the metal oxide used for the semiconductor layer of the transistor is preferably 2 eV or more, more preferably 2.5 eV or more. Use of a metal oxide with a wide band gap can reduce the off-state current of the OS transistor.

[0227] The semiconductor layer provided in the OS transistor preferably contains indium, or preferably contains indium, M (M is one or more selected from gallium, aluminum, silicon, boron, yttrium, tin, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium), and zinc. In particular, M is preferably one or more selected from aluminum, gallium, yttrium, and tin.

[0228] For example, for a semiconductor layer of an OS transistor, an oxide containing indium (InOx) is preferably used. Alternatively, an oxide containing indium and gallium (also referred to as IGO) is preferably used. Alternatively, an oxide containing indium, gallium, and zinc (also referred to as IGZO) is preferably used. Alternatively, an oxide containing indium, tin, and zinc is preferably used. Alternatively, an oxide containing indium, gallium, tin, and zinc is preferably used.

[0229] Note that an oxide semiconductor used for a semiconductor layer of an OS transistor is preferably formed by a sputtering method or an ALD method. When an oxide semiconductor is formed by a sputtering method, productivity and film density can be increased. When an oxide semiconductor is formed by an ALD method, film coverage can be improved.

[0230] An OS transistor has a wider band gap and a lower carrier concentration than silicon transistors, and can have an extremely small off-state current, which enables charge stored in a capacitor connected in series with the transistor to be held for a long period of time.

[0231] An OS transistor has significantly higher field-effect mobility than a transistor using amorphous silicon. Furthermore, an OS transistor has significantly lower source-drain leakage current (also referred to as off-state current) in an off state, and can hold charge accumulated in a capacitor connected in series with the transistor for a long period of time. Furthermore, the use of an OS transistor can reduce the power consumption of a display panel.

[0232] Furthermore, to increase the emission luminance of a light-emitting device included in a pixel circuit, it is necessary to increase the amount of current flowing through the light-emitting device. To achieve this, it is necessary to increase the source-drain voltage of a driving transistor included in the pixel circuit. Since an OS transistor has a higher source-drain withstand voltage than a Si transistor, a high voltage can be applied between the source and drain of the OS transistor. Therefore, by using an OS transistor as the driving transistor included in a pixel circuit, it is possible to increase the amount of current flowing through the light-emitting device and increase the emission luminance of the light-emitting device.

[0233] Furthermore, when the transistor operates in the saturation region, the change in source-drain current of an OS transistor is smaller than that of a Si transistor in response to a change in gate-source voltage. Therefore, by using an OS transistor as a driving transistor included in a pixel circuit, the current flowing between the source and drain can be precisely controlled by changing the gate-source voltage, thereby controlling the amount of current flowing through the light-emitting device. This allows for a larger number of gray levels to be displayed in the pixel circuit.

[0234] Furthermore, in terms of the saturation characteristics of the current that flows when a transistor operates in the saturation region, an OS transistor can pass a more stable current (saturation current) than a Si transistor, even when the source-drain voltage gradually increases. Therefore, by using an OS transistor as a driving transistor, a stable current can be passed through a light-emitting device, even when the current-voltage characteristics of an EL device vary. In other words, when an OS transistor operates in the saturation region, the source-drain current of the OS transistor remains almost unchanged even when the source-drain voltage increases, thereby stabilizing the light-emitting luminance of the light-emitting device.

[0235] As described above, by using an OS transistor for a driving transistor included in a pixel circuit, it is possible to achieve "reduced power consumption," "increased light emission luminance," "multiple gray levels," "suppressed variations in light-emitting devices," and the like.

[0236] [Display Panel 200F] A display panel 200F shown in FIG. 22 has a stacked structure of a transistor 310 in which a channel is formed in a substrate 301 and a transistor 320 in which a channel is formed and a semiconductor layer containing metal oxide is formed.

[0237] An insulating layer 261 is provided to cover the transistor 310, and a conductive layer 251 is provided over the insulating layer 261. An insulating layer 262 is provided to cover the conductive layer 251, and a conductive layer 252 is provided over the insulating layer 262. The conductive layers 251 and 252 each function as wirings. An insulating layer 263 and an insulating layer 332 are provided to cover the conductive layer 252, and the transistor 320 is provided over the insulating layer 332. An insulating layer 265 is provided to cover the transistor 320, and a capacitor 240 is provided over the insulating layer 265. The capacitor 240 and the transistor 320 are electrically connected by a plug 274.

[0238] The transistor 320 can be used as a transistor that forms a pixel circuit. The transistor 310 can be used as a transistor that forms a pixel circuit or a driver circuit (gate line driver circuit, source line driver circuit) that drives the pixel circuit. The transistors 310 and 320 can be used as transistors that form various circuits such as an arithmetic circuit or a memory circuit.

[0239] With this configuration, not only pixel circuits but also driving circuits etc. can be formed directly below the light-emitting device, which makes it possible to make the display panel smaller than when driving circuits are provided around the periphery of the display area.

[0240] [Display Panel 200G] The display panel 200G shown in Fig. 23 has a configuration in which the transistor 320 of the display panel 200F shown in Fig. 22 is replaced with a transistor 320A (vertical transistor). Note that the configuration in which the transistor 320 is replaced with the transistor 320A can also be applied to the display panel 200D shown in Fig. 21.

[0241] 24A shows a cross-sectional view of the transistor 320A in the XZ plane, and FIG. 24B shows a cross-sectional view of the transistor 320A in the XY plane including the wiring 440.

[0242] The transistor 320A includes an oxide semiconductor 470, an insulator 430, and a conductor 420. The oxide semiconductor 470 functions as a semiconductor layer, the insulator 430 functions as a gate insulator, and the conductor 420 functions as a gate electrode. The wiring 450 has a region that functions as one of a source electrode and a drain electrode of the transistor 320A. The wiring 440 has a region that functions as the other of the source electrode and the drain electrode of the transistor 320A.

[0243] An opening 490 is provided through the wiring 440 and the insulator 480, reaching the wiring 450. The opening 490 has a columnar shape with a substantially circular upper surface. This structure allows for miniaturization or high integration of memory cells. Note that the side surface of the opening 490 is preferably perpendicular to the upper surface of the wiring 450.

[0244] At least a part of the oxide semiconductor 470 is disposed in the opening 490. Note that the oxide semiconductor 470 has a region in contact with the top surface of the wiring 450, a region in contact with the side surface of the wiring 440, and a region in contact with the side surface of the insulator 480 in the opening 490.

[0245] The insulator 430 is disposed so that at least a portion thereof covers the opening 490. The conductor 420 is disposed so that at least a portion thereof is located in the opening 490. Note that the conductor 420 is preferably provided so as to fill the opening 490, and preferably has a substantially circular shape in top view in order to increase the degree of integration.

[0246] As illustrated in FIG. 24A, the oxide semiconductor 470 includes a region 470i and regions 470na and 470nb that sandwich the region 470i.

[0247] The region 470na is a region of the oxide semiconductor 470 that is in contact with the wiring 450. At least a portion of the region 470na functions as one of the source region and the drain region of the transistor 320A. The region 470nb is a region of the oxide semiconductor 470 that is in contact with the wiring 440. At least a portion of the region 470nb functions as the other of the source region and the drain region of the transistor 320A. As shown in FIG. 24B , the wiring 440 is in contact with the entire periphery of the oxide semiconductor 470. Therefore, the other of the source region and the drain region of the transistor 320A can be formed along the entire periphery of a portion of the oxide semiconductor 470 that is formed in the same layer as the wiring 440.

[0248] The region 470i is a region sandwiched between the regions 470na and 470nb in the oxide semiconductor 470. At least part of the region 470i functions as a channel formation region of the transistor 320A. That is, the channel formation region of the transistor 320A is formed in a part of the oxide semiconductor 470 located between the wiring 450 and the wiring 440. It can also be said that the channel formation region of the transistor 320A is located in a region of the oxide semiconductor 470 that is in contact with the insulator 480 or in a region in the vicinity of the insulator 480.

[0249] The channel length of the transistor 320A is the distance between the source region and the drain region. In other words, the channel length of the transistor 320A can be determined by the thickness of the insulator 480 on the wiring 450. In FIG. 24A , the channel length L of the transistor 320A is indicated by a dashed double-headed arrow. The channel length L is the distance between the end of the region where the oxide semiconductor 470 and the wiring 450 contact each other and the end of the region where the oxide semiconductor 470 and the wiring 440 contact each other in a cross-sectional view. In other words, the channel length L corresponds to the length of the side surface of the insulator 480 on the opening 490 side in a cross-sectional view.

[0250] In a planar transistor, the channel length is limited by the exposure limit of photolithography, making further miniaturization difficult. However, in one embodiment of the present invention, the channel length can be set by the film thickness of the insulator 480. Therefore, the channel length of the transistor 320A can be made into an extremely fine structure that is equal to or less than the exposure limit of photolithography (for example, 60 nm or less, 50 nm or less, 40 nm or less, 30 nm or less, 20 nm or less, or 10 nm or less, and 1 nm or more, or 5 nm or more). This allows the on-state current of the transistor 320A to be increased.

[0251] Furthermore, as described above, the channel formation region, the source region, and the drain region can be formed in the opening 490. This allows the area occupied by the transistor 320A to be reduced compared to a conventional transistor in which the channel formation region, the source region, and the drain region are provided separately on the XY plane, thereby increasing the pixel density.

[0252] A transistor having a channel formation region along the side surface of the insulator 480 in the opening 490 is also called a vertical transistor.

[0253] 24B , the oxide semiconductor 470, the insulator 430, and the conductor 420 are arranged concentrically in the XY plane including the channel formation region of the oxide semiconductor 470. Therefore, the side surface of the conductor 420 located at the center faces the side surface of the oxide semiconductor 470 with the insulator 430 interposed therebetween. In other words, the entire periphery of the oxide semiconductor 470 forms the channel formation region in a top view. In this case, for example, the channel width of the transistor 320A is determined by the perimeter of the oxide semiconductor 470. In other words, the channel width of the transistor 320A can be determined by the maximum width of the opening 490 (the maximum diameter when the opening 490 is circular in a top view). In FIGS. 24A and 24B , the maximum width D of the opening 490 is indicated by a double-headed, dashed arrow. In FIG. 24B , the channel width W of the transistor 320A is indicated by a double-headed, dashed arrow. By increasing the maximum width D of the opening 490, the channel width per unit area can be increased, and the on-current can be increased.

[0254] When the opening 490 is formed by photolithography, the maximum width D of the opening 490 is limited by the exposure limit of photolithography. The maximum width D of the opening 490 is set depending on the film thicknesses of the oxide semiconductor 470, the insulator 430, and the conductor 420 provided in the opening 490. The maximum width D of the opening 490 is, for example, 5 nm or more, 10 nm or more, or 20 nm or more, and preferably 100 nm or less, 60 nm or less, 50 nm or less, 40 nm or less, or 30 nm or less. When the opening 490 has a circular shape in top view, the maximum width D of the opening 490 corresponds to the diameter of the opening 490, and the channel width W can be calculated as "D × π".

[0255] In the memory device of one embodiment of the present invention, the channel length L of the transistor 320A is preferably at least shorter than the channel width W of the transistor 320A. The channel length L of the transistor 320A of one embodiment of the present invention is 0.1 to 0.99 times, preferably 0.5 to 0.8 times, the channel width W of the transistor 320A. With such a structure, a transistor with favorable electrical characteristics and high reliability can be realized.

[0256] Furthermore, by forming the opening 490 to have a substantially circular shape in top view, the oxide semiconductor 470, the insulator 430, and the conductor 420 are arranged concentrically. This makes the distance between the conductor 420 and the oxide semiconductor 470 substantially uniform, allowing a gate electric field to be applied to the oxide semiconductor 470 substantially uniformly.

[0257] The channel formation region of a transistor using an oxide semiconductor for a semiconductor layer preferably has fewer oxygen vacancies or a lower concentration of impurities such as hydrogen, nitrogen, or metal elements than the source and drain regions. For example, the aluminum concentration in the channel formation region of the oxide semiconductor is preferably 1×10 ２２ atoms / cm ３ Preferably, 1×10 ２１ atoms / cm ３ More preferably, 1×10 ２０ atoms / cm ３ Less than 5 x 10 is more preferable. １９ atoms / cm ３ More preferably, 1×10 １９ atoms / cm ３ Less than 5 x 10 is more preferable. １８ atoms / cm ３ More preferably, 1×10 １８ atoms / cm ３ The following is even more preferred:

[0258] In addition, hydrogen atoms near the oxygen vacancies are converted into defects where hydrogen atoms have entered the oxygen vacancies (hereinafter referred to as V Ｏ H) and generate electrons that become carriers. Therefore, in the channel formation region, V Ｏ It is preferable that H is also reduced. In this way, the channel formation region of the transistor is a high-resistance region with a low carrier concentration. Therefore, the channel formation region of the transistor can be said to be i-type (intrinsic) or substantially i-type.

[0259] In addition, the source and drain regions of a transistor using an oxide semiconductor for a semiconductor layer have more oxygen vacancies than the channel formation region. ＯThe source and drain regions of a transistor are n-type regions with a high carrier concentration and low resistance compared to the channel formation region, due to a high concentration of H or a high concentration of impurities such as hydrogen, nitrogen, and metal elements.

[0260] 24A and other drawings, the opening 490 is provided so that the side surface of the opening 490 is perpendicular to the upper surface of the wiring 450, but the present invention is not limited to this. For example, the side surface of the opening 490 may be tapered.

[0261] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes and examples described in this specification.

[0262] Embodiment 3 In this embodiment, an indium oxide film that can be used for a semiconductor layer of a transistor included in a display device of one embodiment of the present invention will be described.

[0263] In this specification and the like, indium oxide having at least a crystalline portion or a crystalline region in a film is referred to as crystalline indium oxide (crystal IO) or crystalline indium oxide (crystalline IO). Examples of crystalline IO or crystalline IO include single-crystalline indium oxide, polycrystalline indium oxide, and microcrystalline indium oxide.

[0264] Indium oxide is a semiconductor material having physical properties that are completely different from those of oxide semiconductors such as In—Ga—Zn oxide (hereinafter also referred to as IGZO) and zinc oxide.

[0265] The carrier concentration dependence of the Hall mobility of indium oxide, silicon, and IGZO will be explained. Figure 25A shows the carrier concentration dependence of the Hall mobility of silicon (Si) and indium oxide (InO Ｘ ) and FIG. 25B is a schematic diagram showing the carrier concentration dependence of the hole mobility for IGZO.

[0266] First, IGZO tends to exhibit higher hole mobility as the carrier concentration increases, as shown by the arrows in Figure 25B. On the other hand, indium oxide tends to exhibit higher hole mobility as the carrier concentration decreases, as shown by the arrows in Figure 25A (see Non-Patent Document 1). This trend is similar to that of silicon; the lower the dopant (impurity) concentration in the material, the less impurity scattering there is and the higher the hole mobility. In other words, the higher the purity and intrinsic indium oxide, the higher the hole mobility. From these results, it can be said that indium oxide, unlike IGZO, is a material with physical properties similar to those of silicon. Note that the characteristics of indium oxide shown in Figure 25A are assumed to be single crystal. Therefore, when indium oxide is non-single crystal (e.g., polycrystalline), the characteristics may differ from those shown in Figure 25A.

[0267] 25A, the range R1 of low carrier concentration has extremely high hole mobility, and therefore can be said to be a range of carrier concentration suitable for, for example, a channel formation region of a transistor. For example, in the case of indium oxide, the range R1 is a range where the carrier concentration value is 1×10 １５ cm −３ The range includes, for example, 1×10 １４ cm −３ That's it, 1 x 10 １８ cm −３ By sufficiently reducing the carrier concentration, the Hall mobility value can be increased to 270 cm ２ It is expected that the resistance can be increased to about / (V·s).

[0268] In addition, in indium oxide, the region where the carrier concentration is in the range R1 may contain an element that lowers the carrier concentration. Examples of elements that lower the carrier concentration include magnesium, calcium, zinc, cadmium, and copper. By substituting these elements for indium, the carrier concentration can be lowered. Examples of elements that lower the carrier concentration include nitrogen, phosphorus, arsenic, and antimony. For example, by substituting nitrogen, phosphorus, arsenic, or antimony for oxygen, the carrier concentration can be lowered.

[0269] On the other hand, the range R2 with a high carrier concentration has a low electrical resistance, and can be said to be a range of carrier concentrations suitable for, for example, the source and drain regions of a transistor, a resistor, or a transparent conductive film. ２０ cm −３ The range includes, for example, 1×10 １９ cm −３ That's it, 1 x 10 ２２ cm −３ By increasing the carrier concentration sufficiently, the resistivity can be reduced to 1×10 −４ It is expected that the resistivity can be reduced to Ω·cm or less.

[0270] In the indium oxide, the region having a carrier concentration in the range R2 may contain an element that increases the carrier concentration. For example, it is preferable that the indium oxide contains an element that is common to the source electrode and the drain electrode of the transistor. Examples of elements that increase the carrier concentration include titanium, zirconium, hafnium, tantalum, tungsten, molybdenum, tin, silicon, and boron. In particular, it is more preferable to use an element whose oxide has conductive or semiconductive properties.

[0271] In this way, indium oxide uses a region with a low carrier concentration as the channel formation region of a transistor, and a region with a high carrier concentration as the source and drain regions of the transistor. In other words, indium oxide can be said to be an oxide capable of valence electron control. Note that IGZO may experience strain in the source and drain regions due to stress from electrodes in contact with the IGZO, resulting in the formation of n-type regions. On the other hand, unlike IGZO, indium oxide is capable of valence electron control, and therefore does not require strain to be formed in the film as with IGZO. Less strain in the film is expected to improve reliability. For example, by separately creating a region with a carrier concentration in the range R1 shown in FIG. 25A and a region with a carrier concentration in the range R2 in the indium oxide film, a so-called n-i-n junction (a junction between an n-type region, an i-type region, and an n-type region) can be created. Note that valence electron control in transistors using silicon is generally known. On the other hand, valence electron control in transistors using indium oxide is a novel technical concept that would not normally be conceived.

[0272] By using the above technical concept, the transistor having indium oxide in this specification and the like has two or more, preferably three or more, more preferably four or more, and most preferably five of the following characteristics (1) to (5): (1) high on-current (in other words, high mobility); (2) low off-current; (3) normally-off operation; (4) high reliability; and (5) high cutoff frequency (fT). For example, the transistor having indium oxide in this specification and the like has high mobility, low off-current, and is normally-off operation. The transistor has high mobility and is different from a normally-on transistor.

[0273] Next, an indium oxide film applied to a transistor will be described. The indium oxide film preferably has crystallinity (i.e., has crystal grains). Examples of films having crystal grains include single-crystal films, polycrystalline films, and amorphous films containing crystal grains (also called microcrystalline films). In particular, the indium oxide film is preferably a polycrystalline film, and more preferably a single-crystal film. A single-crystal film does not have grain boundaries. Impurities (typically, insulating impurities, insulating oxides, etc.) that hinder carrier flow tend to segregate at grain boundaries. The use of a single-crystal film can suppress carrier scattering at grain boundaries, thereby realizing a transistor exhibiting high field-effect mobility. Furthermore, the use of a single-crystal film has the excellent effect of suppressing variations in transistor characteristics due to the grain boundaries.

[0274] Furthermore, polycrystalline films are preferable because they can reduce carrier scattering and exhibit high field-effect mobility compared to microcrystalline or amorphous films. When using a polycrystalline film, it is preferable to use a film with as large a crystal grain size as possible and with few crystal grain boundaries. Note that in a transistor using an indium oxide polycrystalline film, if there is no crystal grain boundary in the channel formation region or no crystal grain boundary is observed, the channel formation region is located within a single crystal region included in the polycrystalline film, and therefore the transistor can be considered to be using single-crystal indium oxide.

[0275] The crystallinity of indium oxide can be analyzed by, for example, X-ray diffraction (XRD), transmission electron microscope (TEM), or electron diffraction (ED). Alternatively, a combination of these methods may be used for analysis.

[0276] In this specification and the like, a semiconductor layer in which no crystal grain boundary is observed in the channel formation region, a semiconductor layer in which the channel formation region is included in one crystal grain, or a semiconductor layer in which the crystal axis direction is the same in at least two regions in the channel formation region can be called a single crystal film. Also, a semiconductor layer in which, in the channel formation region, within one crystal grain, the direction of another crystal axis continuously changes around a certain crystal axis or a certain crystal orientation as the axis of rotation can be called a single crystal film.

[0277] The channel formation region refers to a region of the semiconductor layer that overlaps (or faces) the gate electrode via the gate insulating layer, and is located between the region in contact with the source electrode and the region in contact with the drain electrode. The current path in the channel formation region is the shortest distance between the source electrode and the drain electrode. Therefore, the crystal grains, crystal grain boundaries, crystal axes, crystal orientation, etc. in the channel formation region can be confirmed by observing a cross section including the semiconductor layer, the source electrode, and the drain electrode.

[0278] The indium oxide film in the channel formation region preferably has a lower impurity concentration. Impurities in the indium oxide film in the channel formation region can be a scattering source of carriers, which can lead to a decrease in field-effect mobility. These impurities can also hinder the crystal growth of the indium oxide film. Examples of impurities in the indium oxide film include boron and silicon. The indium oxide film preferably contains these impurities at concentrations of 0.1% or less, and more preferably 0.01% (100 ppm) or less. Carbon, hydrogen, and other elements may be contained in the film-forming gas or precursor during film formation, and may remain in the indium oxide film in greater amounts than the above-mentioned impurities.

[0279] The indium oxide film in the channel formation region may contain an element that can become the same trivalent cation as indium, as long as the crystal maintains a cubic crystal structure (bixbyite type). Examples of such an element include Group 13 elements of the periodic table, such as gallium and aluminum, and Group 3 elements of the periodic table. These elements exist mainly as trivalent cations in oxides, and therefore the carrier concentration of indium oxide can be maintained low.

[0280] By using such an indium oxide film in a transistor, the field effect mobility of the transistor can be increased to 50 cm ２ / (V·s) or more, preferably 100 cm ２ / (V·s) or more, more preferably 150 cm ２ / (V·s) or more, more preferably 200 cm ２ / (V·s) or more, more preferably 250 cm ２ / (V·s) or more.

[0281] One of the features of an indium oxide film is that it has higher oxygen permeability (diffusibility) than an IGZO film. As shown in FIG. 25C, an indium oxide film (InO Ｘ Oxygen (O) diffusing into the indium oxide film passes through the indium oxide film and becomes oxygen molecules (O ２ ) and is released as water molecules (H ２ O) may be released in the film. Ｏ In the case where an indium oxide film is present, oxygen atoms diffuse to compensate for the oxygen vacancies. Since oxygen diffuses easily in the indium oxide film, it can be said that oxygen vacancies are more easily compensated for in the indium oxide film than in the IGZO film.

[0282] As described above, an indium oxide film can more easily reduce oxygen vacancies in the film than an IGZO film. Therefore, by using such an indium oxide film in a transistor, a transistor with extremely high reliability can be realized.

[0283] Furthermore, as shown in FIG. 25C, the indium oxide film diffuses hydrogen. Hydrogen that diffuses into the indium oxide film from the outside passes through the indium oxide film and becomes hydrogen molecules (H ２ ) or reacts with oxygen contained in the membrane and is released as water molecules.

[0284] A transistor using an indium oxide film is an accumulation-type transistor that uses electrons as majority carriers. Assuming that the carrier relaxation time is constant, the smaller the effective mass of the electrons (carriers), the higher the electron mobility. In other words, by using indium oxide, which has a small effective mass of electrons, for a transistor, the on-state current or field-effect mobility of the transistor can be increased.

[0285] Table 1 shows the results of single crystal indium oxide (here, In ２ O ３ ) and single-crystal silicon (Si). As shown in Table 1, indium oxide is characterized by a small effective mass of electrons and a large effective mass of holes. Indium oxide also has the characteristic that the effective mass of electrons is almost independent of the crystal orientation. Therefore, by using crystalline indium oxide in a transistor, a transistor with high field-effect mobility and high frequency characteristics (also called f characteristics) can be realized. Furthermore, since the effective mass of holes is large, a transistor with extremely small off-current can be realized. For example, by applying an indium oxide film to a vertical transistor, the off-current per 1 μm of channel width can be reduced to 1 fA (1×10) in an environment of 125° C. −１５ A) or less, or 1aA (1 x 10 −１８ A) or less, and under room temperature (25°C) conditions, −１８ A) or less, or 1zA (1 x 10 −２１ Furthermore, as shown in Table 1, indium oxide has a smaller effective mass of electrons and a larger effective mass of holes than silicon, and therefore may be able to realize a transistor with higher field-effect mobility and lower off-state current than a Si transistor.

[0286]

[0287] It is preferable to provide a seed layer so as to be in contact with at least a portion of the crystalline indium oxide film. The seed layer is preferably made of a material containing crystals with a small difference in lattice constant (also called lattice mismatch) with indium oxide. This can improve the crystallinity of the indium oxide film. Note that a substrate (e.g., a single-crystal substrate) may be used as one of the layers in contact with at least a portion of the crystalline indium oxide film.

[0288] One method for evaluating the degree of lattice mismatch is to use the value of the lattice mismatch shown below. The lattice mismatch Δa [%] of the crystals of the formed film (here, the indium oxide film) with respect to the crystals of the seed layer is expressed as Δa = ((L １ -L ２ ) / L ２ ) × 100, where L １ is the length or lattice constant of the unit lattice vector of the crystal of the formed film, and L ２ is the length of the unit cell vector or the lattice constant of the crystal of the seed layer.

[0289] The smaller the absolute value of the lattice mismatch Δa between the seed layer and the indium oxide film, the more preferable, and it is most preferably 0. For example, Δa can be set to −5% or more and 5% or less, preferably −4% or more and 4% or less, more preferably −3% or more and 3% or less, and even more preferably −2% or more and 2% or less.

[0290] Here, the indium oxide crystal has a cubic crystal structure (bixbyite type). For example, the crystal of yttria-stabilized zirconia (YSZ) can have a cubic crystal structure (fluorite type). The lattice mismatch of the indium oxide crystal with the cubic YSZ crystal is in the range of −2% to 2%, and a single crystal film of indium oxide can be epitaxially grown on the YSZ substrate.

[0291] It should be noted that the crystal structure of the seed layer and the crystal structure of the indium oxide film may not necessarily have the same crystal system or crystal orientation. For example, a film having crystals of a hexagonal or trigonal structure may be used under an indium oxide film having crystals of a cubic structure. For example, by setting the crystal orientation of the surface of the seed layer to

[001] and the crystal orientation of the underside of the indium oxide film to

[111] , the requirements related to the crystal orientation necessary for epitaxial growth can be satisfied. Examples of hexagonal or trigonal crystals include wurtzite structure, YbFe ２ O ４ Type structure, Yb ２ Fe ３ O ７ YbFeFe alloys have the following structures: ２ O ４ Type structure or Yb ２ Fe ３ O ７ An example of a crystal having a ZnO-type structure is IGZO.

[0292] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0293] FLM: film, GD: grinder, LR: light receiving surface, LS: light emitting surface, 20: display device, 21: optical device, 30: housing, 35: holder, 40: pixel, 41: line of sight detection sensor, 42: light source, 60: display unit, 62: linear polarizer, 63: retardation plate, 64: half mirror, 65: lens, 66: retardation plate, 67: reflective polarizer, 68: lens, 71: subpixel, 74: pixel array, 75: circuit, 76: circuit, 77: layer, 78: layer, 79: layer, 100: laminate, 102: lens, 102a: resin layer, 102B: lens, 102b: resin layer, 102c: resin layer, 102G: lens, 102R: lens, 103: structure, 103B: structure, 103G: structure, 103R: structure, 104: structure, 104A: layer, 104a: layer, 104B: layer, 104b: layer, 105: sub-pixel, 105B: sub-pixel, 105G: sub-pixel, 105R: sub-pixel, 107: insulating layer, 108: resist mask, 110: light-emitting element, 110B: light-emitting element, 110G: light-emitting element, 110R: light-emitting element, 111: pixel electrode, 111B: pixel electrode, 111G: pixel electrode, 112: organic layer, 112B: organic layer, 112G: organic layer, 113: common electrode, 11 4: common layer, 121: protective layer, 124: insulating layer, 125: insulating layer, 126: resin layer, 145: photomask, 161: substrate, 163: substrate, 200A: display panel, 200B: display panel, 200C: display panel, 200D: display panel, 200F: display panel, 200G: display panel, 240: capacitor, 241: conductive layer, 243: insulating layer, 245: conductive layer, 251: conductive layer, 252: conductive layer, 254: insulating layer, 255a: insulating layer, 255b: insulating layer, 255c: insulating layer, 256: plug, 261: insulating layer, 262: insulating layer, 263: insulating layer, 264: insulating layer Edge layer, 265: insulating layer, 271: plug, 274: plug, 274a: conductive layer, 274b: conductive layer, 280: display module, 281: display section, 282: circuit section, 283: pixel circuit section, 283a: pixel circuit, 284: pixel section, 284a: pixel, 285: terminal section, 286: wiring section, 290: FPC, 291: substrate, 292: substrate, 301: substrate, 301A: substrate, 301B: substrate, 310: transistor, 310A: transistor, 310B: transistor, 311: conductive layer, 312: low resistance region, 313: insulating layer, 314: insulating layer, 315: element isolation layer,320: transistor, 320A: transistor, 321: semiconductor layer, 323: insulating layer, 324: conductive layer, 325: conductive layer, 326: insulating layer, 327: conductive layer, 328: insulating layer, 329: insulating layer, 331: substrate, 332: insulating layer, 335: insulating layer, 336: insulating layer, 341: conductive layer, 342: conductive layer, 343: plug, 344: insulating layer, 345: insulating layer, 346: insulating layer, 347: bump, 348: adhesive layer, 420: conductor, 430: insulator, 440: wiring, 450: wiring, 470: oxide semiconductor, 470i: region, 470na: region, 470nb: region, 480: insulator, 490: opening,

Claims

a light-emitting element, a first structure, a second structure, and a plano-convex lens; the first structure is provided between an upper surface of the light-emitting element and a bottom surface of the plano-convex lens, the first structure has a first surface on the light-emitting element side, a second surface on the plano-convex lens side, and a third surface located between the first surface and the second surface, the third surface has a curved surface, the second structure is provided to cover the third surface, the plano-convex lens and the first structure are translucent to light emitted by the light-emitting element, A display device, wherein a region of the second structure that contacts the third surface is reflective to light emitted by the light-emitting element. 　 In claim 1, The region comprises a metallic material. 　 In claim 1, The region includes a material having a refractive index smaller than that of the first structure with respect to light emitted by the light-emitting element. 　 In claim 1, the first surface, the second surface, and the bottom surface of the plano-convex lens are each circular in top view and are arranged concentrically; a diameter of the first surface is equal to or greater than a diameter of a circumscribing circle of the light-emitting element; The diameter of the second surface is greater than the diameter of the first surface; A display device in which the diameter of the bottom surface of the plano-convex lens is equal to or greater than the diameter of the second surface. 　 In claim 1, the first and second surfaces and the bottom surface of the plano-convex lens are each elliptical in top view and are arranged so that their centers are at the same position; the major axis and the minor axis of the first surface are equal to or greater than the major axis and the minor axis of an ellipse circumscribing the light-emitting element, a major axis and a minor axis of the second surface are larger than a major axis and a minor axis of the first surface, respectively; A display device in which the major axis and the minor axis of the bottom surface of the plano-convex lens are equal to or greater than the major axis and the minor axis of the second surface, respectively. 　 In claim 1, A display device wherein the curved surface has a region in which the curvature continuously increases from the first surface to the second surface in a cross section in the height direction including the center of the first structure. 　 In claim 1, A display device wherein the curved surface has a region in which the curvature changes so as to continuously decrease from the first surface to the second surface in a cross section in the height direction including the center of the first structure. 　 In claim 1, A display device in which the first structure and the plano-convex lens are formed of the same material. 　 In claim 1, The display device wherein the light-emitting element is connected to a transistor having a metal oxide in a channel formation region. 　 In claim 9, The display device, wherein the metal oxide is indium oxide.

11. An electronic device using the display device according to claim 1 as a light source, and having a catadioptric system provided on the display surface side of the display device.

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