Image sensor and control method for image sensor

Abstract

According to the present invention, the circuit scale of an image sensor that compares voltages is reduced.　A comparator compares the voltages of each of a pair of vertical signal lines and outputs a comparison result. A holding unit holds the comparison result and outputs the comparison result as a pre-gain control comparison result. A control unit controls a charge-voltage conversion efficiency of a pixel connected to one of the pair of vertical signal lines to a value different from that of a pixel connected to the other of the pair of vertical signal lines, on the basis of the pre-gain control comparison result. An edge determining circuit determines the presence or absence of an edge on the basis of the pre-gain control comparison result and a post-gain control comparison result, which is the comparison result obtained when the charge-voltage conversion efficiency is controlled.

Description

Image sensor and method for controlling image sensor

[0001] The present technology relates to an image sensor, and more particularly to an image sensor that determines the presence or absence of an edge, and a method for controlling the image sensor.

[0002] Conventionally, image sensors have performed various signal processing such as pixel addition and CDS (Correlated Double Sampling) processing. For example, an image sensor has been proposed in which a comparator is provided for each vertical signal line and edges are detected from the comparison results of each of the pair of comparators (see, for example, Patent Document 1). In this image sensor, a gain circuit increases or decreases the voltage of one of the pair of vertical signal lines using a relative gain, and these voltages are compared using one of the pair of comparators. Also, a gain circuit increases or decreases the voltage of the other of the pair of vertical signal lines using a relative gain, and these voltages are compared using the other of the pair of comparators.

[0003] International Publication No. 2021 / 090538

[0004] The above-mentioned conventional technology aims to detect the presence or absence of an edge without depending on ambient light by increasing or decreasing the voltage of a pair of vertical signal lines using a gain and comparing the results. However, the above-mentioned conventional technology requires a gain circuit and a comparator for each vertical signal line, which increases the circuit size of the image sensor.

[0005] This technology was developed in light of these circumstances, and aims to reduce the circuit scale in image sensors that compare voltages.

[0006] The present technology has been made to solve the above-mentioned problems, and a first aspect thereof is an image sensor and a control method thereof including: a comparator that compares the voltages of a pair of vertical signal lines and outputs a comparison result; a holding unit that holds the comparison result and outputs it as a pre-gain control comparison result; a control unit that controls a charge-voltage conversion efficiency of a pixel connected to one of the pair of vertical signal lines to a value different from that of a pixel connected to the other vertical signal line based on the pre-gain control comparison result; and an edge determination circuit that determines the presence or absence of an edge based on the pre-gain control comparison result and a post-gain control comparison result that is the comparison result when the charge-voltage conversion efficiency is controlled, thereby providing an effect of reducing the circuit size.

[0007] In addition, in the first aspect, the image sensor may further include an offset control unit that applies an offset voltage to one of the pair of vertical signal lines, and the control unit may select one of the pair of vertical signal lines based on the pre-gain control comparison result and cause the offset control unit to apply the offset voltage. This brings about an effect of suppressing inversion of the comparison result due to noise.

[0008] In addition, in this first aspect, the pixel may further include a vertical scanning circuit that supplies a transfer signal, a reset signal, and a control signal, and each of the pixels may include a transfer transistor that transfers charge from the photoelectric conversion element to the floating diffusion layer in accordance with the transfer signal, a reset transistor that initializes the floating diffusion layer in accordance with the reset signal, and a gain control transistor that controls the charge-voltage conversion efficiency in accordance with the control signal, thereby providing the effect of controlling the charge-voltage conversion efficiency for each pixel.

[0009] In addition, in this first aspect, the circuit may further include a timing control circuit that outputs a latch enable signal to the holding unit after the charge is transferred, and the holding unit may acquire and hold the comparison result in accordance with the latch enable signal, thereby achieving the effect of comparing voltages during charge transfer.

[0010] In this first aspect, the timing control circuit may transmit an auto-zero signal to the comparator after transmitting the latch enable signal, the comparator may control the voltages of the pair of vertical signal lines to the same value in accordance with the auto-zero signal, and the vertical scanning circuit may transmit the reset signal after transmitting the auto-zero signal, thereby providing an effect of comparing voltages at the time of initialization.

[0011] In this first aspect, the reset transistor and the gain control transistor may be connected in series between a power supply voltage and the floating diffusion layer, thereby providing an effect that the floating diffusion layer is initialized when the reset transistor and the gain control transistor are in an on state.

[0012] In this first aspect, the reset transistor and the gain control transistor may be connected in parallel to the floating diffusion layer, thereby providing an effect that the floating diffusion layer is initialized when the reset transistor is on, regardless of whether the gain control transistor is on or off.

[0013] In the first aspect, the pixel may include a first pixel and a second pixel, and the first pixel and the second pixel may share the floating diffusion layer, thereby reducing the circuit size per pixel.

[0014] In this first aspect, the pixel may include first and second pixels, the gain control transistor may include a first gain control transistor in the first pixel and a second gain control transistor in the second pixel, the floating diffusion layer may include a first floating diffusion layer in the first pixel and a second floating diffusion layer in the second pixel, and the first and second gain control transistors may open and close a path between the first floating diffusion layer and the second floating diffusion layer in accordance with the control signal, thereby eliminating the need for a capacitance.

[0015] In this first aspect, the pixel may further include an enable switch that opens and closes a path between a vertical control line that transmits the control signal and the gate of the gain control transistor, thereby reducing a wiring load on the vertical control line.

[0016] In this first aspect, the pixel may further include an analog memory that stores the control signal, thereby providing an effect that charge-voltage conversion efficiency is controlled by the control signal of the previous frame.

[0017] In this first aspect, the pixel may further include a charge drain transistor that initializes the photoelectric conversion element in accordance with a signal that is a logical product of the control signal stored in the analog memory and a charge drain signal from the vertical scanning circuit, thereby providing an effect of controlling a charge accumulation period.

[0018] In addition, in this first aspect, a pair of selectors may be further provided for selecting either the comparator or the control unit and connecting the selected one to the pair of vertical signal lines, thereby providing an effect of reducing the number of vertical control lines.

[0019] In addition, in this first aspect, the pixel may further include a signal processing unit that processes a determination result of the edge determination circuit, and the pixels, the comparator, the holding unit, the control unit, and the edge determination circuit may be arranged on a pixel chip, and the signal processing unit may be arranged on a circuit chip. This brings about the effect of facilitating miniaturization of pixels.

[0020] In this first aspect, the pixels may be arranged on a pixel chip, and the signal processing unit, the comparator, the holding unit, the control unit, and the edge determination circuit may be arranged on a circuit chip, thereby making it easier to miniaturize the pixels.

[0021] In the first aspect, the image sensor may be a back-illuminated image sensor, thereby improving the sensitivity of the pixels.

[0022] In the first aspect, the image sensor may be a front-illuminated image sensor, which provides an effect of reducing the circuit scale in the front-illuminated type.

[0023] According to a second aspect of the present technology, there is provided an image sensor including: a comparator that compares the voltages of a pair of vertical signal lines and outputs a comparison result; a holding unit that holds the comparison result and outputs it as a comparison result before accumulation period control; a control unit that controls a charge accumulation period of a pixel connected to one of the pair of vertical signal lines to a value different from that of a pixel connected to the other vertical signal line based on the comparison result before accumulation period control; and an edge determination circuit that determines the presence or absence of an edge based on the comparison result before accumulation period control and a comparison result after accumulation period control that is the comparison result when the charge accumulation period is controlled. This provides an effect of reducing the circuit size.

[0024] 1 is a block diagram showing an example of a configuration of an imaging device according to a first embodiment of the present technology. FIG. 2 is a block diagram showing an example of a configuration of an image sensor according to the first embodiment of the present technology. FIG. 3 is a block diagram showing an example of a configuration of a column signal processing circuit according to the first embodiment of the present technology. FIG. 4 is a circuit diagram showing an example of a configuration of a pixel according to the first embodiment of the present technology. FIG. 5 is an example of a cross-sectional view of a back-illuminated image sensor according to the first embodiment of the present technology. FIG. 6 is an example of a cross-sectional view of a front-illuminated image sensor according to the first embodiment of the present technology. FIG. 7 is a block diagram showing an example of a configuration of an edge detection unit according to the first embodiment of the present technology. FIG. 8 is a diagram showing an example of an operation of a control unit according to the first embodiment of the present technology. FIG. 9 is a diagram showing an example of an operation of an edge determination circuit according to the first embodiment of the present technology. FIG. 10 is a flowchart showing an example of an operation of an image sensor according to the first embodiment of the present technology. FIG. 11 is a block diagram showing an example of a configuration of an edge detection unit according to a second embodiment of the present technology. FIG. 12 is a diagram showing an example of an operation of a control unit according to the second embodiment of the present technology. FIG. 13 is a diagram showing an example of an operation of an offset control unit according to the second embodiment of the present technology. FIG. 14 is a timing chart showing an example of a readout operation of an image sensor according to a third embodiment of the present technology. FIG. 10 is a diagram showing an example of operation of an edge determination circuit in a third embodiment of the present technology. FIG. 11 is a circuit diagram showing an example of a configuration of a pixel in a fourth embodiment of the present technology. FIG. 12 is a timing chart showing an example of a readout operation of an image sensor in the fourth embodiment of the present technology. FIG. 13 is a block diagram showing an example of a configuration of a column signal processing circuit in a fifth embodiment of the present technology. FIG. 14 is a block diagram showing an example of a configuration of an edge detection unit in the fifth embodiment of the present technology. FIG. 15 is a circuit diagram showing an example of a configuration of a pixel in the fifth embodiment of the present technology. FIG. 16 is a timing chart showing an example of a readout operation of an image sensor in the fifth embodiment of the present technology. FIG. 17 is a diagram showing an example of operation of an edge determination circuit in the fifth embodiment of the present technology. FIG. 18 is a circuit diagram showing an example of a configuration of a pixel in a sixth embodiment of the present technology.10 is a block diagram showing an example of a configuration of an edge detection unit in a sixth embodiment of the present technology. FIG. 11 is a timing chart showing an example of a readout operation of an image sensor in the sixth embodiment of the present technology. FIG. 12 is a block diagram showing an example of a configuration of an edge detection unit in a seventh embodiment of the present technology. FIG. 13 is a circuit diagram showing an example of a configuration of a pixel in the seventh embodiment of the present technology. FIG. 14 is a diagram showing an example of an operation of a control unit in the seventh embodiment of the present technology. FIG. 15 is a timing chart showing an example of an operation of an image sensor in the seventh embodiment of the present technology. FIG. 16 is a timing chart showing an example of a readout operation of an image sensor in the seventh embodiment of the present technology. FIG. 17 is a diagram showing an example of an operation of an edge determination circuit in the seventh embodiment of the present technology. FIG. 18 is a circuit diagram showing an example of a configuration of a pixel in an eighth embodiment of the present technology. FIG. 19 is a circuit diagram showing an example of a configuration of an FD sharing block in the eighth embodiment of the present technology. FIG. 19 is a circuit diagram showing an example of a configuration of an FD link block in the eighth embodiment of the present technology. FIG. 20 is a diagram showing an example of a stacked structure of an image sensor in a ninth embodiment of the present technology. FIG. 21 is a diagram showing another example of a stacked structure of an image sensor in the ninth embodiment of the present technology. FIG. 22 is a block diagram showing an example of a schematic configuration of a vehicle control system. FIG. 23 is an explanatory diagram showing an example of installation positions of an outside vehicle information detection unit and an imaging unit.

[0025] Hereinafter, modes for implementing the present technology (hereinafter referred to as embodiments) will be described. The description will be made in the following order. 1. First embodiment (an example in which an edge is determined based on a comparison result from a holding unit and a comparator) 2. Second embodiment (an example in which an offset voltage is applied and an edge is determined based on a comparison result from a holding unit and a comparator) 3. Third embodiment (an example in which initialization is performed during gain control and an edge is determined based on a comparison result from a holding unit and a comparator) 4. Fourth embodiment (an example in which only a selected row is connected to a vertical control line and an edge is determined based on a comparison result from a holding unit and a comparator) 5. Fifth embodiment (an example in which initialization is performed during gain control while only a selected row is connected to a vertical control line and an edge is determined based on a comparison result from a holding unit and a comparator) 6. Sixth embodiment (an example in which a connection destination of a vertical signal line is switched and an edge is determined based on a comparison result from a holding unit and a comparator) 7. Seventh embodiment (an example in which a charge accumulation period is controlled and an edge is determined based on a comparison result from a holding unit and a comparator) 8. 8. Eighth embodiment (an example in which the circuit configuration of a pixel is changed and an edge is determined based on a comparison result from a holding unit and a comparator) 9. Ninth embodiment (an example in which an edge is determined based on a comparison result from a holding unit and a comparator in a stacked structure) 10. Application to a moving body

[0026] 1 is a block diagram showing an example of the configuration of an imaging device 100 according to a first embodiment of the present technology. The imaging device 100 is a device for capturing image data, and includes an optical unit 110, an image sensor 200, and a DSP (Digital Signal Processing) circuit 120. The imaging device 100 further includes a display unit 130, an operation unit 140, a bus 150, a frame memory 160, a storage unit 170, and a power supply unit 180. Examples of the imaging device 100 include digital cameras such as digital still cameras, as well as smartphones, personal computers, and in-vehicle cameras that have an imaging function.

[0027] The optical unit 110 collects light from a subject and guides it to the image sensor 200. The image sensor 200 generates image data by photoelectric conversion in synchronization with a vertical synchronization signal. The vertical synchronization signal is a periodic signal with a predetermined frequency that indicates the timing of imaging. The image sensor 200 supplies the generated image data to the DSP circuit 120 via a signal line 209.

[0028] The DSP circuit 120 performs predetermined signal processing on the image data from the image sensor 200. The DSP circuit 120 outputs the processed image data to a frame memory 160 or the like via a bus 150.

[0029] The display unit 130 displays image data. For example, a liquid crystal panel or an organic EL (Electro Luminescence) panel is assumed as the display unit 130. The operation unit 140 generates an operation signal in accordance with a user's operation.

[0030] The bus 150 is a common path for the optical unit 110, image sensor 200, DSP circuit 120, display unit 130, operation unit 140, frame memory 160, storage unit 170, and power supply unit 180 to exchange data with one another.

[0031] The frame memory 160 holds image data. The storage unit 170 stores various data such as image data. The power supply unit 180 supplies power to the image sensor 200, the DSP circuit 120, the display unit 130, and the like.

[0032] 2 is a block diagram showing a configuration example of an image sensor 200 according to the first embodiment of the present technology. The image sensor 200 includes a vertical scanning circuit 210, a DAC 220, a timing control circuit 230, a pixel array unit 240, a column signal processing circuit 300, a horizontal scanning circuit 280, a signal processing unit 290, and a memory 295. These circuits are arranged on a single semiconductor chip, for example.

[0033] Furthermore, a plurality of pixels 250 are arranged in a two-dimensional lattice pattern in the pixel array unit 240. Hereinafter, a set of pixels 250 arranged in a predetermined horizontal direction will be referred to as a "row," and a set of pixels 250 arranged in a direction perpendicular to the horizontal direction will be referred to as a "column."

[0034] The timing control circuit 230 controls the operation timing of the vertical scanning circuit 210, the column signal processing circuit 300, etc. in synchronization with the vertical synchronization signal.

[0035] The timing control circuit 230 also receives a mode signal MODE that indicates the operation mode of the image sensor 200. The operation modes include an edge detection mode that detects the presence or absence of edges, and an imaging mode that only captures image data without detecting the presence or absence of edges. The timing control circuit 230 controls each circuit based on the operation mode. Note that the image sensor 200 can also capture image data while detecting the presence or absence of edges.

[0036] The vertical scanning circuit 210 sequentially selects and drives rows to output analog pixel signals. The DAC 220 generates a reference signal by DA (Digital to Analog) conversion and supplies it to the column signal processing circuit 300. For example, a sawtooth ramp signal is used as the reference signal. The pixels 250 generate pixel signals by photoelectric conversion under the control of the vertical scanning circuit 210. Each pixel 250 outputs a pixel signal to the column signal processing circuit 300.

[0037] The column signal processing circuit 300 performs signal processing such as CDS (Correlated Double Sampling) processing and AD (Analog to Digital) conversion processing on pixel signals for each column. The column signal processing circuit 300 supplies image data consisting of digital signals after signal processing to the signal processing unit 290 under the control of the horizontal scanning circuit 280.

[0038] The horizontal scanning circuit 280 selects columns in order and causes the column signal processing circuit 300 to output digital signals in order.

[0039] The signal processing unit 290 performs various image processing operations on image data as necessary. In imaging mode, the signal processing unit 290 performs image processing such as defect correction and supplies the processed image data to the DSP circuit 120. In edge detection mode, the signal processing unit 290 acquires and stores edge determination results for each pixel at the timing indicated by the latch enable signal LAT from the timing control circuit 230, and performs processing such as feature extraction. Furthermore, the signal processing unit 290 can also perform object detection and recognition, such as person detection, face detection, and face recognition, based on the extracted features. The signal processing unit 290 then supplies the processed data to the DSP circuit 120.

[0040] The memory 295 is used by the signal processing unit 290 to temporarily store data.

[0041] [Configuration Example of Column Signal Processing Circuit] Fig. 3 is a block diagram showing a configuration example of a column signal processing circuit 300 according to the first embodiment of the present technology. The column signal processing circuit 300 includes a plurality of ADCs 320 and a plurality of edge detection units 330. The ADCs 320 are arranged for each column, and when the number of columns is N (N is an integer), N ADCs 320 are arranged. Furthermore, the edge detection unit 330 is arranged for each pixel pair in a row for which an edge is to be detected. For example, when detecting an edge between the 0th column and the 1st column and between the 1st column and the 2nd column, two edge detection units 330 are arranged for the 0th column to the 3rd column.

[0042] The ADC 320 converts the analog pixel signals of the corresponding columns into digital signals under the control of the timing control circuit 230. The ADC 320 supplies the digital signals to the DSP circuit 120 under the control of the horizontal scanning circuit 280. For example, a single-slope ADC including a comparator and a counter is used as the ADC 320. Note that a successive approximation ADC including a comparator, a successive approximation logic circuit, and a register can also be used.

[0043] The edge detection unit 330 detects whether or not there is an edge between a corresponding pair of pixels. The vertical signal lines of the corresponding columns are connected to the edge detection unit 330. For example, the vertical signal line VSL0 of the 0th column and the vertical signal line VSL1 of the 1st column are connected to the edge detection unit 330 corresponding to the 0th and 1st columns. The edge detection unit 330 detects (in other words, determines) the presence or absence of an edge under the control of the timing control circuit 230, and supplies the result to the DSP circuit 120.

[0044] In the edge detection mode, the timing control circuit 230 enables the edge detection unit 330 to detect the presence or absence of an edge, and disables the ADC 320. On the other hand, in the imaging mode, the timing control circuit 230 enables the ADC 320 to perform AD conversion, and disables the edge detection unit 330.

[0045] 4 is a circuit diagram showing an example of the configuration of a pixel 250 according to the first embodiment of the present technology. The pixel 250 includes a photoelectric conversion element 251, a transfer transistor 252, a reset transistor 253, a capacitor 254, a gain control transistor 255, a floating diffusion layer 256, an amplification transistor 257, and a selection transistor 258. As various transistors in the pixel 250, such as the transfer transistor 252, for example, nMOS (n-channel metal oxide semiconductor) transistors are used.

[0046] The photoelectric conversion element 251 generates electric charges by photoelectric conversion. The transfer transistor 252 transfers the electric charges from the photoelectric conversion element 251 to the floating diffusion layer 256 in accordance with a transfer signal TRG from the vertical scanning circuit 210.

[0047] The reset transistor 253 extracts electric charges from at least one of the photoelectric conversion element 251 and the floating diffusion layer 256 in accordance with a reset signal RST from the vertical scanning circuit 210 to initialize the same.

[0048] The reset transistor 253 and the gain control transistor 255 are connected in series between the power supply voltage and the floating diffusion layer 256. The capacitor 254 is inserted between the connection node of the reset transistor 253 and the gain control transistor 255 and the ground terminal.

[0049] Furthermore, a vertical control line VCL and a vertical signal line VSL are wired for each column within the pixel array section 240. The vertical control line VCL and the vertical signal line VSL are connected to each of the pixels 250 in the corresponding column. The vertical control line VCL transmits a control signal EG from the column signal processing circuit 300 to the pixels 250, and the vertical signal line VSL transmits a pixel signal from the pixels 250 to the column signal processing circuit 300. The vertical control line VCL, vertical signal line VSL, and control signal EG of the nth column (n is an integer from 0 to N-1) will be referred to below as VCLn, VSLn, and EGn. The same figure shows the circuit of the pixel 250 in the 0th column.

[0050] The gain control transistor 255 controls the charge-to-voltage conversion efficiency (in other words, the gain) of the pixel 250 in accordance with a control signal EG from the column signal processing circuit 300. When the gain control transistor 255 is in the on state, the floating diffusion layer 256 and the capacitor 254 are connected, and therefore the combined capacitance is larger than when the gain control transistor 255 is in the off state. As a result, when the gain control transistor 255 is in the on state, the charge-to-voltage conversion efficiency is lower than when the gain control transistor 255 is in the off state.

[0051] The floating diffusion layer 256 accumulates electric charges and converts the amount of electric charges into a voltage. The amplification transistor 257 forms a source follower circuit and outputs a voltage corresponding to the voltage of the floating diffusion layer 256 to the selection transistor 258. The selection transistor 258 supplies a pixel signal of a voltage from the amplification transistor 257 to a vertical signal line VSL in accordance with a selection signal SEL from the vertical scanning circuit 210.

[0052] 5 is an example of a cross-sectional view of the image sensor 200 according to the first embodiment of the present technology. The image sensor 200 includes a substrate 430 and a wiring layer 420. An on-chip lens 411, a color filter 412, and a photoelectric conversion element 251 are arranged for each pixel. With the light incident side facing up, the color filter 412 is arranged below the on-chip lens 411, and the photoelectric conversion element 251 is arranged below the color filter 412.

[0053] Furthermore, a wiring layer 420 is formed on the upper surface of the substrate 430, and transistors such as the transfer transistor 252 described above are formed in the wiring layer 420. A photoelectric conversion element 251 of each pixel is disposed on top of the wiring layer 420. The structure illustrated in the figure is called a back-illuminated type.

[0054] 6, a front-side illumination type may be used instead of the back-side illumination type. In this front-side illumination type, a wiring layer 420 is formed below the color filter 412, and a photoelectric conversion element 251 is disposed below that.

[0055] 7 is a block diagram showing an example of the configuration of the edge detection unit 330 according to the first embodiment of the present technology. The edge detection unit 330 includes a comparator 331, a holding unit 332, a control unit 333, and an edge determination circuit 340.

[0056] The comparator 331 compares the voltages of the pair of vertical signal lines. For example, the vertical signal line VSL0 is connected to the non-inverting input terminal (−) of the comparator 331, and the vertical signal line VSL1 is connected to the inverting input terminal (+) of the comparator 331. The comparator 331 supplies a comparison result VCO to the holding unit 332 and the edge determination circuit 340.

[0057] The holding unit 332 takes in and holds the comparison result VCO in accordance with the latch enable signal LTEN from the timing control circuit 230, and outputs it as the comparison result VCOφ1 to the control unit 333 and the edge determination circuit 340. For example, a 1-bit latch circuit is used as the holding unit 332. The holding unit 332 updates the held value using the comparison result VCO when the latch enable signal LTEN is at a high level, and latches the held value when the latch enable signal LTEN is at a low level.

[0058] The control unit 333 controls the charge-voltage conversion efficiency of the pixel connected to one of the vertical signal lines VSL0 and VSL1 to a value different from that of the pixel connected to the other vertical signal line, based on the comparison result VCOφ1 from the holding unit 332. The control unit 333 receives the comparison result VCOφ1, as well as the reset signal EGRST and edge enable signal EGEN from the timing control circuit 230. Based on these signals, the control unit 333 generates control signals EG0 and EG1 and supplies them to a pair of pixels via vertical control lines VCL0 and VCL1.

[0059] The edge determination circuit 340 determines whether or not an edge exists. Here, the comparison result VCO when the charge-voltage conversion efficiency of one of a pair of pixels is controlled by the control unit 333 is set to VCOφ2. The edge determination circuit 340 determines whether or not an edge exists based on the comparison result VCOφ1 from the holding unit 332 and the comparison result VCOφ2 from the comparator 331, and outputs the determination result OUT to the signal processing unit 290.

[0060] The comparison result VCOφ1 is an example of a comparison result before gain control as set forth in the claims, and the comparison result VCOφ2 is an example of a comparison result after gain control as set forth in the claims.

[0061] As illustrated in the figure, the edge determination circuit 340 determines the presence or absence of an edge based on the comparison result VCOφ1 from the holding unit 332 and the comparison result VCOφ2 from the comparator 331 after gain control, so only one comparator 331 is required for each pair of vertical signal lines. This makes it possible to reduce the number of comparators compared to patent documents that require a comparator for each vertical signal line. This allows the circuit scale of the column signal processing circuit 300 to be reduced.

[0062] 8 is a diagram illustrating an example of an operation of the control unit 333 according to the first embodiment of the present technology. When the reset signal EGRST is at a high level, the control unit 333 outputs high-level control signals EG0 and EG1.

[0063] Furthermore, when both the reset signal EGRST and the edge enable signal EGEN are at a low level, the control unit 333 outputs low-level control signals EG0 and EG1. This edge enable signal EGEN is a signal that indicates whether or not to enable the function of controlling the charge-voltage conversion efficiency, and is set to a high level when enabled and a low level when disabled.

[0064] Here, the voltage of the vertical signal line VSL when the comparison result VCOφ1 is held is at a level corresponding to the amount of accumulated charge, and this level is called the signal level or D phase. On the other hand, the voltage of the vertical signal line VSL when the pixel is initialized is called the reset level or P phase. ΔVSL, which is the difference between these P phase and D phase, indicates the level of the net pixel signal. When the comparison result VCOφ1 is at a low level, ΔVSL1 is greater than ΔVSL0, and when the comparison result VCOφ1 is at a high level, ΔVSL0 is greater than ΔVSL1.

[0065] When the edge enable signal EGEN is high (i.e., enabled) and the comparison result VCOφ1 is low, the control unit 333 sets the control signal EG0 to low and the control signal EG1 to high, thereby controlling the charge-voltage conversion efficiency (i.e., gain) of the pixel on the VSL1 side, where ΔVSL is larger, to a value lower than that on the VSL0 side.

[0066] When the edge enable signal EGEN is at a high level and the comparison result VCOφ1 is at a high level, the control unit 333 sets the control signal EG0 to a high level and the control signal EG1 to a low level, thereby controlling the gain of the pixel on the VSL0 side, which has the larger ΔVSL, to a value lower than that on the VSL1 side.

[0067] As illustrated in the figure, the control unit 333 controls the charge-voltage conversion efficiency of each of the pair of pixels using control signals EG0 and EG1 based on the comparison result VCOφ1.

[0068] [Example of Operation of Edge Determination Circuit] Fig. 9 is a diagram showing an example of operation of the edge determination circuit 340 according to the first embodiment of the present technology. As described above, when a comparison result VCOφ1 indicating that ΔVSL1 is greater than ΔVSL0 is output, the gain on the VSL1 side is controlled to a value lower than that on the VSL0 side. If the relative gain based on the larger gain is G (G is a real number less than 1), after gain control, ΔVSL1 × G and ΔVSL0 are compared, and a comparison result VCOφ2 is output.

[0069] If ΔVSL1×G is greater than ΔVSL0, in other words, if ΔVSL1 is much greater than ΔVSL0, the comparison results VCOφ1 and VCOφ2 are both at low level. Based on these comparison results, the edge determination circuit 340 outputs a high-level determination result OUT indicating the presence of an edge.

[0070] If ΔVSL1×G is less than ΔVSL0, the difference between ΔVSL0 and ΔVSL1 is such that the comparison result is reversed by gain control. In this case, the comparison result VCOφ1 is low and VCOφ2 is high. Based on these comparison results, the edge determination circuit 340 outputs a low-level determination result OUT indicating that there is no edge.

[0071] Furthermore, when a comparison result VCOφ1 indicating that ΔVSL0 is greater than ΔVSL1 is output, the gain on the VSL0 side is controlled to a value lower than that on the VSL1 side. After gain control, ΔVSL1 and ΔVSL0×G are compared, and a comparison result VCOφ2 is output.

[0072] If ΔVSL0×G is less than ΔVSL1, the difference between ΔVSL0 and ΔVSL1 is such that the comparison result is reversed by gain control. In this case, the comparison result VCOφ1 is high and VCOφ2 is low. Based on these comparison results, the edge determination circuit 340 outputs a low-level determination result OUT indicating that there is no edge.

[0073] If ΔVSL0×G is greater than ΔVSL1, in other words, if ΔVSL0 is much greater than ΔVSL1, the comparison results VCOφ1 and VCOφ2 are both at high level. Based on these comparison results, the edge determination circuit 340 outputs a high-level determination result OUT indicating the presence of an edge.

[0074] As can be seen from the figure, the edge determination circuit 340 can be realized by an NXOR (exclusive negative OR) gate.

[0075] The comparator 331 compares the pixel signal ΔVSL0 (or ΔVSL1) increased or decreased by the relative gain G with the pixel signal ΔVSL1 (or ΔVSL0), and the comparison result is a value indicating whether the ratio of ΔVSL0 to ΔVSL1 is equal to or greater than a certain value. Because this ratio is a parameter that does not depend on the amount of ambient light, the edge determination circuit 340 can detect the presence or absence of an edge based on the comparison result, regardless of the amount of ambient light. This can improve the accuracy of edge detection.

[0076] [Example of Image Sensor Operation] Fig. 10 is a timing chart showing an example of a readout operation of the image sensor 200 according to the first embodiment of the present technology. In edge detection mode, the vertical scanning circuit 210 performs exposure using a rolling shutter method, sequentially selects rows during readout, and sets the selection signal SEL for that row to a high level over a pulse period. When all rows have been selected, the downstream signal processing unit 290 acquires data that lists the edge determination results for all pixels. The diagram shows a readout operation during a period in which a certain row is selected.

[0077] The vertical scanning circuit 210 sets the selection signal SEL to high level over the period from timing T0 to T5. Also, the vertical scanning circuit 210 supplies a high-level reset signal RST to the selected row at timing T0 over the pulse period. As a result, the levels of the vertical signal lines VSL0 and VSL1 become P phase.

[0078] Furthermore, at timing T0, the timing control circuit 230 supplies the auto-zero signal AZ and the reset signal EGRST over the pulse period to the comparator 331 and the control unit 333. This causes the auto-zero operation to be performed, and the control signals EG0 and EG1 are controlled to a high level over the pulse period.

[0079] Then, at timing T1, the vertical scanning circuit 210 supplies a high-level transfer signal TRG to the selected row for the pulse period. This transfers charge within the pixel, and the voltages of the vertical signal lines VSL0 and VSL1 drop to the D phase according to the amount of accumulated charge. In the figure, the thin curve indicates the trajectory of the voltage of the vertical signal line VSL0, and the thick curve indicates the trajectory of the voltage of the vertical signal line VSL1.

[0080] In the figure, ΔVSL1, which is the difference between the P phase and D phase on the VSL1 side, is assumed to be greater than ΔVSL0. At this time, the comparator 331 outputs a low-level comparison result VCO. Note that in the figure, the gray portions indicate periods during which the value of the comparison result VCO is not considered.

[0081] Then, during the period from timing T2 to timing T3, the timing control circuit 230 supplies a high-level latch enable signal LTEN to the holding unit 332. As a result, the holding unit 332 captures and holds the low-level comparison result VCO, and outputs it as the comparison result VCOφ1.

[0082] Then, the timing control circuit 230 supplies a high-level edge enable signal EGEN during the period from timing T3 to T5. In response to this signal, the control unit 333 controls the charge-to-voltage conversion efficiency using control signals EG0 and EG1 in accordance with the comparison result VCOφ1. In the figure, since the comparison result VCOφ1 is low, the control unit 333 supplies a low-level control signal EG0 and a high-level control signal EG1.

[0083] Then, the comparator 331 outputs the high-level comparison result VCO as VCOφ2 at timing T4. The edge determination circuit 340 determines whether or not an edge exists based on the comparison result VCOφ1 from the holding unit 332 and the comparison result VCOφ2 after gain control.

[0084] At timing T4, the timing control circuit 230 supplies a high-level latch enable signal LAT over the pulse period to the downstream signal processing unit 290. In accordance with this signal, the signal processing unit 290 captures and holds the edge determination result at timing T4.

[0085] 11 is a flowchart showing an example of the operation of the image sensor 200 according to the first embodiment of the present technology. This operation is started, for example, when the image sensor 200 is powered on.

[0086] The image sensor 200 determines whether the operation mode is set to the edge detection mode (step S901). If the operation mode is set to the edge detection mode (step S901: Yes), the vertical scanning circuit 210 in the image sensor 200 selects and drives any one of the rows (step S902).

[0087] The holding unit 332 in the image sensor 200 holds the comparison result VCO and outputs it as the comparison result VCOφ1 (step S903). Based on the comparison result VCOφ1, the control unit 333 controls the charge-to-voltage conversion efficiency (gain) of one of the pair of pixels to a value different from that of the other (step S904).

[0088] The comparator 331 outputs the comparison result during gain control as VCOφ2 (step S905), and the edge determination circuit 340 determines whether or not an edge exists based on the comparison results VCOφ1 and VCOφ2 (step S906).

[0089] The vertical scanning circuit 210 determines whether all rows have been selected (step S907). If all rows have been selected (step S907: Yes), the image sensor 200 repeats step S901 and subsequent steps. If all rows have not been selected (step S907: No), the image sensor 200 repeats step S902 and subsequent steps.

[0090] If the edge detection mode is not set (step S901: No), the image sensor 200 captures image data (step S908) and repeatedly executes step S901 and subsequent steps.

[0091] As described above, according to the first embodiment of the present technology, the edge determination circuit 340 determines the presence or absence of an edge based on the comparison result VCOφ1 from the holding unit 332 and the comparison result VCOφ2 from the gain-controlled comparator 331. Therefore, only one comparator 331 is required for each pair of vertical signal lines, and the circuit scale of the column signal processing circuit 300 can be reduced compared to patent documents that require a comparator for each vertical signal line.

[0092] 2. Second Embodiment In the first embodiment described above, the control unit 333 controls the charge-voltage conversion efficiency of one of a pair of pixels based on the comparison result VCOφ1. However, when the pixel signals ΔVSL0 and ΔVSL1 are at a low level, such as during low illuminance, noise may cause the comparison result VCOφ2 after gain control to be inverted to a value different from the comparison result VCOφ1. The image sensor 200 in this second embodiment differs from the first embodiment in that an offset voltage is applied to one of a pair of vertical signal lines based on the comparison result VCOφ1.

[0093] 12 is a block diagram showing an example configuration of the edge detection unit 330 according to the second embodiment of the present technology. The edge detection unit 330 according to the second embodiment differs from the first embodiment in that it further includes an offset control unit 334.

[0094] Furthermore, the control unit 333 in the second embodiment further generates a control signal ofs and supplies it to the offset control unit 334. This control signal ofs is a signal that indicates to which of a pair of vertical signal lines the offset voltage should be applied.

[0095] The offset control unit 334 applies an offset voltage to either of the pair of vertical signal lines. The offset control unit 334 receives a control signal OFS from the control unit 333 and an offset enable signal OFSEN from the timing control circuit 230. The offset enable signal OFSEN indicates whether or not to enable the function of applying the offset voltage, and is set to a high level when enabled and a low level when disabled.

[0096] The offset control unit 334 applies an offset voltage to one of the vertical signal lines VSL0 and VSL1 in accordance with these signals, and supplies each applied voltage to the comparator 331.

[0097] 13 is a diagram illustrating an example of the operation of the control unit 333 according to the second embodiment of the present technology. The control unit 333 further outputs a low-level control signal OFS when the edge enable signal EGEN is at a high level (enabled) and the comparison result VCOφ1 is at a low level.

[0098] Furthermore, the control section 333 further outputs a high-level control signal OFS when the edge enable signal EGEN is at a high level (enabled) and the comparison result VCOφ1 is at a high level.

[0099] 14 is a diagram illustrating an example of the operation of the offset control unit 334 according to the second embodiment of the present technology. When the offset enable signal OFSEN is at a low level (i.e., disabled), the offset control unit 334 does not apply offset voltages to both the vertical signal lines VSL0 and VSL1, and supplies these voltages to the comparator 331 as they are.

[0100] When the offset enable signal OFSEN is high (i.e., enabled) and the control signal OFS is low, the offset control unit 334 applies a predetermined offset voltage only to the vertical signal line VSL0. The offset control unit 334 then supplies the voltages of the vertical signal lines VSL0 and VSL1 after the application to the comparator 331.

[0101] When the offset enable signal OFSEN is high (enabled) and the control signal OFS is high, the offset control unit 334 applies a predetermined offset voltage only to the vertical signal line VSL1. The offset control unit 334 then supplies the voltages of the vertical signal lines VSL0 and VSL1 after the application to the comparator 331.

[0102] 13 and 14, when ΔVSL0 is larger than ΔVSL1, the offset control unit 334 applies an offset voltage to the smaller VSL1 during gain control. If the offset voltage is C, the comparator 331 compares ΔVSL0×G with ΔVSL1+C, and outputs the comparison result VCOφ2.

[0103] Furthermore, if ΔVSL1 is larger than ΔVSL0, the offset control section 334 applies an offset voltage to the smaller VSL0 during gain control. ΔVSL1×G and ΔVSL0+C are compared by the comparator 331, and the comparison result VCOφ2 is output.

[0104] The table of the operation of the edge determination circuit 340 in the second embodiment is similar to that in the first embodiment shown in FIG.

[0105] 15 is a timing chart showing an example of a readout operation of the image sensor 200 according to the second embodiment of the present technology. The timing control circuit 230 supplies a high-level offset enable signal OFSEN during a period from timing T3 to T5. The control unit 333 controls the offset control unit 334 based on the comparison result VCOφ1 to apply an offset voltage to one of the vertical signal lines VSL0 and VSL1. Application of this offset voltage can suppress inversion of the comparison result VCOφ2 due to noise when the pixel signals ΔVSL0 and ΔVSL1 are at a low level.

[0106] As described above, according to the second embodiment of the present technology, the control unit 333 controls the offset control unit 334 to apply an offset voltage to one of the vertical signal lines VSL0 and VSL1 based on the comparison result VCOφ1. This makes it possible to suppress inversion of the comparison result VCOφ2 caused by noise when ΔVSL0 and ΔVSL1 are at low levels.

[0107] 3. Third Embodiment In the first embodiment described above, the comparator 331 compares the D phase after charge transfer. However, in this control, gain control causes a difference in the combined capacitance between the VSL0 side and the VSL1 side, which may result in a difference in the noise component due to resetting of the floating diffusion layer 256 and a decrease in detection accuracy. The image sensor 200 in this third embodiment differs from the first embodiment in that it is re-initialized during gain control and compares the P phase of each of a pair of vertical signal lines.

[0108] FIG. 16 is a timing chart showing an example of a readout operation of the image sensor 200 according to the third embodiment of the present technology.

[0109] In the third embodiment, the control up to timing T2 when the pulse of the latch enable signal LTEN is supplied is the same as in the first embodiment.

[0110] The timing control circuit 230 sets the edge enable signal EGEN to a high level at timing T3, and supplies a high-level auto-zero signal AZ to the comparator 331 over the pulse period. In accordance with the auto-zero signal AZ, the comparator 331 controls the voltages of the vertical signal lines VSL0 and VSL1 to the same value.

[0111] Then, at timing T4, the vertical scanning circuit 210 supplies a high-level reset signal RST to the selected row for the pulse period, and the timing control circuit 230 supplies a high-level reset signal EGRST to the control unit 333 for the pulse period, thereby initializing the floating diffusion layer 256 and causing the voltages of the vertical signal lines VSL0 and VSL1 to become P-phase.

[0112] Due to the immediately preceding auto-zero operation, the voltages (i.e., P phases) of the vertical signal lines VSL0 and VSL1 rise in accordance with the amount of accumulated charge. In the figure, the P phase of the vertical signal line VSL1 is higher than that of the vertical signal line VSL0. Then, at timing T5, the P phases after gain control are compared, and a high-level comparison result VCOφ2 is output.

[0113] As shown in the figure, the timing control circuit 230 transmits the auto-zero signal AZ after gain control, and the vertical scanning circuit 210 transmits the reset signal RST after transmitting the auto-zero signal AZ. As a result, even if a difference occurs in the combined capacitance of a pair of pixels due to gain control, the floating diffusion layer 256 is reset again to equalize the noise components caused by the reset. The difference between the P-phase voltage during comparison and the voltage during auto-zero is a value from which the noise components caused by the reset have been removed, based on the same principle as analog CDS, improving edge detection accuracy compared to the first embodiment.

[0114] FIG. 17 is a diagram showing an example of the operation of the edge determination circuit 340 according to the third embodiment of the present technology.

[0115] In the third embodiment, the P phase is compared with the comparison result VCOφ2, so the logic is reversed compared to the first embodiment. In this case, the edge determination circuit 340 can be realized by an XOR (exclusive OR) gate.

[0116] The second embodiment can be applied to the third embodiment.

[0117] As described above, according to the third embodiment of the present technology, after gain control, the timing control circuit 230 transmits the auto-zero signal AZ, and after that, the vertical scanning circuit 210 transmits the reset signal RST. This makes it possible to improve the edge detection accuracy based on the same principle as analog CDS.

[0118] 4. Fourth Embodiment In the first embodiment described above, the control unit 333 supplies the control signal EG to all pixels in a column via the vertical control line VCL, but it is preferable to reduce the wiring load of the vertical control line VCL. The image sensor 200 in this fourth embodiment differs from the first embodiment in that it adds an FDG enable switch that opens and closes the path between the vertical control line VCL and the gate of the gain control transistor 255.

[0119] 18 is a circuit diagram showing a configuration example of a pixel 250 according to a fourth embodiment of the present technology. The pixel 250 according to the fourth embodiment differs from the pixel 250 according to the first embodiment in that it further includes an FDG enable switch 259 and an analog memory 260. For example, an nMOS transistor is used as the FDG enable switch 259. A capacitor is used as the analog memory 260.

[0120] The FDG enable switch 259 opens and closes the path between the vertical control line VCL 0 and the gate of the gain control transistor 255 in accordance with the FDG enable signal FDGEN from the vertical scanning circuit 210 .

[0121] The analog memory 260 is inserted between the gate of the gain control transistor 255 and the ground terminal.

[0122] FIG. 19 is a timing chart showing an example of a readout operation of the image sensor 200 according to the fourth embodiment of the present technology.

[0123] The vertical scanning circuit 210 supplies a high-level FDG enable signal to the selected row over a pulse period at timing T0. The vertical scanning circuit 210 also supplies a high-level FDG enable signal to the selected row during the period from timing T3 to T5. On the other hand, the FDG enable signal FDGEN of the unselected rows is controlled to a low level.

[0124] In the fourth embodiment, the control of signals other than the FDG enable signal is the same as in the first embodiment.

[0125] The vertical scanning circuit 210 supplies a high-level FDG enable signal FDGEN only to the selected row and sets the FDG enable signal FDGEN of the unselected rows to a low level. As a result, the gates of the gain control transistors 255 of only the selected row are connected to the vertical signal line VCL, and the gates of the gain control transistors 255 of the unselected rows are disconnected from the vertical signal line VCL. As a result, the wiring load of the vertical control line VCL can be reduced compared to the first embodiment in which all rows are connected to the vertical control line VCL.

[0126] The table of the operation of the edge determination circuit 340 in the fourth embodiment is the same as that in the first embodiment shown in FIG.

[0127] Moreover, the second embodiment can be applied to the fourth embodiment.

[0128] As described above, according to the fourth embodiment of the present technology, the FDG enable switch 259 opens and closes the path between the vertical control line VCL0 and the gate of the gain control transistor 255, so that only the selected row can be connected to the vertical control line VCL. This makes it possible to reduce the wiring load of the vertical control line VCL compared to the first embodiment.

[0129] 5. Fifth Embodiment In the above-described fourth embodiment, the comparator 331 compares the D phase after charge transfer. However, in this control, gain control causes a difference in the combined capacitance between the VSL0 side and the VSL1 side, which may result in a difference in the noise component due to resetting of the floating diffusion layer 256, resulting in a decrease in detection accuracy. The image sensor 200 in this fifth embodiment differs from the fourth embodiment in that it is re-initialized during gain control and compares the P phase of each of a pair of vertical signal lines.

[0130] 20 is a block diagram showing an example of a configuration of a column signal processing circuit 300 according to the fifth embodiment of the present technology. This column signal processing circuit 300 differs from the first embodiment in that it further includes a frame memory 350.

[0131] The frame memory 350 stores data in which the comparison results for all pixels are arranged as a frame.

[0132] FIG. 21 is a block diagram showing an example configuration of the edge detection unit 330 according to the fifth embodiment of the present technology.

[0133] In the fifth embodiment, the holding unit 332 outputs the held comparison result as VCOφ2 to the control unit 333 and the frame memory 350. The frame memory 350 holds data in which the comparison results VCOφ2 of all pixels are arranged as a frame, and outputs this data to the edge determination circuit 340 for each column within the next frame period. The edge determination circuit 340 determines the presence or absence of an edge based on the comparison result VCOφ1 from the comparator 331 and the comparison result VCOφ2 from the frame memory 350.

[0134] 22 is a circuit diagram showing a configuration example of a pixel 250 according to a fifth embodiment of the present technology. The pixel 250 according to the fifth embodiment differs from the pixel 250 according to the fourth embodiment in that a reset transistor 261 is further included.

[0135] The reset transistor 261 initializes the floating diffusion layer 256 in accordance with a reset signal RSTF from the vertical scanning circuit 210. The control signal EG of the previous frame is held in the analog memory 260. This held value is referred to as MEM.

[0136] 23 is a timing chart showing an example of a readout operation of the image sensor 200 according to the fifth embodiment of the present technology. In the fifth embodiment, the control up to timing T2 is the same as in the first embodiment.

[0137] Here, the analog memories 260 of the pair of pixels respectively store the control signals EG0 and EG1 of the previous frame as stored values ​​MEM0 and MEM1. In the figure, MEM0 is at low level and MEM1 is at high level. These stored values ​​control the charge-voltage conversion efficiency of one of the pair of pixels.

[0138] The timing control circuit 230 supplies a high-level latch enable signal LAT to the downstream signal processing unit 290 during the period from timing T2 to T3. In response to this signal, the signal processing unit 290 captures and holds the edge determination result at timing T2. The comparison result VCOφ1 from the comparator 331 at this time corresponds to the comparison result after gain control.

[0139] Then, at timing T3, the timing control circuit 230 supplies the auto-zero signal AZ and the reset signal EGRST at high levels for the entire pulse period. This causes the auto-zero operation to be performed, and the control signals EG0 and EG1 are controlled to be high for the entire pulse period. As a result, the voltages of the vertical signal lines VSL0 and VSL1 become the same, and the gains of the pair of pixels are initialized.

[0140] Then, at timing T4, the vertical scanning circuit 210 supplies the reset signals RST and RSTF for a pulse period, thereby causing the levels of the vertical signal lines VSL0 and VSL1 to become P-phase.

[0141] Then, at timing T5, the timing control circuit 230 supplies the latch enable signal LTEN for the pulse period. The frame memory 350 holds the P-phase comparison result VCOφ2 obtained at the time of gain initialization. Because the gain has been initialized, this comparison result VCOφ2 corresponds to the comparison result before gain control.

[0142] Then, the vertical scanning circuit 210 supplies the FDG enable signal FDGEN to the selected row during the period from timing T6 to T7, and the timing control circuit 230 supplies the reset enable signal RSTEN during that period.

[0143] The comparison result VCOφ1 is an example of a comparison result after gain control as set forth in the claims, and the comparison result VCOφ2 is an example of a comparison result before gain control as set forth in the claims.

[0144] As shown in the figure, after gain control, the timing control circuit 230 transmits the auto-zero signal AZ, and after transmitting the auto-zero signal AZ, the vertical scanning circuit 210 transmits the reset signals RST and RSTF. As a result, similar to the third embodiment, the edge detection accuracy is improved by the analog CDS.

[0145] 24 is a diagram showing an example of the operation of the edge determination circuit 340 according to the fifth embodiment of the present technology. When ΔVSL1 is much larger than ΔVSL0, the comparison result VCOφ1 is at a low level and the comparison result VCOφ2 is at a high level. Based on these comparison results, the edge determination circuit 340 outputs a high-level determination result OUT indicating the presence of an edge.

[0146] If VSL1 is greater than ΔVSL0 but the difference between them is not so great, the comparison results VCOφ1 and VCOφ2 will both be high. Based on these comparison results, the edge determination circuit 340 outputs a low-level determination result OUT indicating that there is no edge.

[0147] If VSL0 is greater than ΔVSL1 but the difference between them is not that great, the comparison results VCOφ1 and VCOφ2 are both low. Based on these comparison results, the edge determination circuit 340 outputs a low-level determination result OUT indicating that there is no edge.

[0148] If ΔVSL0 is much larger than ΔVSL1, the comparison result VCOφ1 is high and the comparison result VCOφ2 is low. Based on these comparison results, the edge determination circuit 340 outputs a high-level determination result OUT indicating that an edge is present.

[0149] As shown in the figure, in the fifth embodiment, the edge determination circuit 340 can be realized by an XOR (exclusive OR) gate.

[0150] The second embodiment can be applied to the fifth embodiment.

[0151] As described above, according to the fifth embodiment of the present technology, in a configuration in which only a selected row is connected to the vertical control line VCL, the timing control circuit 230 transmits the auto-zero signal AZ after gain control, and after that, the vertical scanning circuit 210 transmits the reset signal RST. This makes it possible to improve the edge detection accuracy based on the same principle as analog CDS.

[0152] 6. Sixth Embodiment In the first embodiment described above, the vertical control line VCL and the vertical signal line VSL are wired for each column, but it is preferable to reduce the number of wires. The image sensor 200 in this sixth embodiment differs from the first embodiment in that a selector that switches the connection destination of the vertical signal line VSL is added.

[0153] 25 is a circuit diagram showing a configuration example of a pixel 250 according to a sixth embodiment of the present technology. In the sixth embodiment, a vertical signal line VSL is wired for each column in a pixel array unit 240, but a vertical control line VCL is not wired and is therefore reduced.

[0154] The pixel 250 of the sixth embodiment also differs from that of the first embodiment in that it further includes an FDG enable switch 259 and an analog memory 260. For example, an nMOS transistor is used as the FDG enable switch 259. A capacitor is used as the analog memory 260.

[0155] The FDG enable switch 259 opens and closes the path between the vertical signal line VSL 0 and the gate of the gain control transistor 255 in accordance with an FDG enable signal FDGEN from the vertical scanning circuit 210 .

[0156] The analog memory 260 is inserted between the gate of the gain control transistor 255 and the ground terminal.

[0157] 26 is a block diagram showing an example configuration of the edge detection unit 330 according to the sixth embodiment of the present technology. The edge detection unit 330 according to the sixth embodiment differs from the first embodiment in that it further includes selectors 335 and 336.

[0158] The selector 335 selects either the control section 333 or the non-inverting input terminal (-) of the comparator 331 in accordance with a switching signal VSLSW from the timing control circuit 230, and connects it to the vertical signal line VSL0.

[0159] The selector 336 selects either the control section 333 or the inverting input terminal (+) of the comparator 331 in accordance with the switching signal VSLSW, and connects it to the vertical signal line VSL1.

[0160] These selectors allow pixel signals or control signals EG to be transmitted via the vertical signal lines VSL, thereby reducing the number of vertical control lines VCL.

[0161] FIG. 27 is a timing chart showing an example of a readout operation of the image sensor 200 according to the sixth embodiment of the present technology.

[0162] The timing control circuit 230 sets the switching signal VSLSW to a low level over a pulse period at timing T0, and then sets it to a high level. When the switching signal VSLSW is at a low level, the selectors 335 and 336 connect the vertical signal lines VSL0 and VSL1 to the control unit 333. On the other hand, when the switching signal VSLSW is at a high level, the selectors 335 and 336 connect the vertical signal lines VSL0 and VSL1 to the comparator 331.

[0163] Then, at timing T3, the vertical scanning circuit 210 supplies a high-level FDG enable signal FDGEN for the pulse period. The timing control circuit 230 sets the switching signal VSLSW to a low level during the period from timing T3 to T4, and then to a high level. During this period from timing T3 to T4, a high-level control signal EG1 and a low-level control signal EG0 are supplied to a pair of pixels.

[0164] The control of each signal other than the FDG enable signal FDGEN and the switching signal VSLSW is the same as in the first embodiment.

[0165] The table of the operation of the edge determination circuit 340 in the sixth embodiment is similar to that in the first embodiment shown in FIG.

[0166] Furthermore, each of the second to fifth embodiments can be applied to the sixth embodiment.

[0167] As described above, according to the sixth embodiment of the present technology, the selectors 335 and 336 select either the control unit 333 or the comparator 331 and connect it to the vertical signal lines VSL0 and VSL1, thereby reducing the number of vertical control lines VCL.

[0168] 7. Seventh Embodiment In the first embodiment described above, the control unit 333 controls the charge-voltage conversion efficiency based on the comparison result VCOφ1, but can also control the charge accumulation period. The image sensor 200 in this seventh embodiment differs from the first embodiment in that the charge accumulation period is further controlled based on the comparison result VCOφ1.

[0169] 28 is a block diagram showing an example of the configuration of the edge detection unit 330 according to the seventh embodiment of the present technology. In the seventh embodiment, a frame memory 350 is also provided, similar to the fifth embodiment.

[0170] The holding unit 332 outputs the comparison result VCOφ1 to the control unit 333 and the frame memory 350. Instead of the edge enable signal EGEN, edge enable signals EGENa and EGENb are input to the control unit 333. These are set to a high level when enabled and to a low level when disabled.

[0171] The frame memory 350 stores data in which the comparison results VCOφ2 of all pixels are arranged as a frame, and outputs the data as VCOφ2′ to the edge determination circuit 340 and the control unit 333 of each column within the next frame period.

[0172] The edge determination circuit 340 determines whether or not an edge exists based on the comparison result VCOφ1 from the comparator 331 and the comparison result VCOφ2′ of the previous frame.

[0173] 29 is a circuit diagram showing a configuration example of a pixel 250 according to a seventh embodiment of the present technology. The pixel 250 according to the seventh embodiment differs from the first embodiment in that it further includes an analog memory 260, an OFG enable switch 262, an AND (logical product) gate 263, and a charge drain transistor 264. For example, an nMOS transistor is used as the OFG enable switch 262 and the charge drain transistor 264. For example, a capacitor is used as the analog memory 260.

[0174] In the seventh embodiment, the reset transistor 253 is inserted between the power supply voltage and the floating diffusion layer 256. The gain control transistor 255 and the capacitor 254 are inserted in series between the floating diffusion layer 256 and the ground terminal.

[0175] The OFG enable switch 262 opens and closes the path between the vertical control line VCL and the analog memory 260 in accordance with an OFG enable signal OFGEN. The analog memory 260 holds the control signal EG0 as MEM0. The connection node between the OFG enable switch 262 and the analog memory 260 is connected to the input terminal of an AND gate 263.

[0176] The AND gate 263 outputs the logical product of the control signal OFG from the vertical scanning circuit 210 and the control signal EG 0 from the analog memory 260 to the gate of the charge discharging transistor 264 .

[0177] The charge discharging transistor 264 discharges the charge of the photoelectric conversion element 251 in accordance with the output signal of the AND gate 263 .

[0178] 30 is a diagram illustrating an example of the operation of the control unit 333 according to the seventh embodiment of the present technology. When the reset signal EGRST is at a high level, the control unit 333 outputs the control signals EG0 and EG1 at a high level.

[0179] Furthermore, when the reset signal EGRST and the edge enable signals EGENa and EGENb are all at a low level, the control section 333 outputs low-level control signals EG0 and EG1.

[0180] When the edge enable signal EGENa is at a high level (enabled), the edge enable signal EGENb is controlled to a low level. In this case, if the comparison result VCOφ2 of the current frame from the holding unit 332 is at a low level, the control unit 333 outputs a high-level control signal EG0 and a low-level control signal EG1. On the other hand, if the edge enable signal EGENa is at a high level and the comparison result VCOφ2 is at a high level, the control unit 333 outputs a low-level control signal EG0 and a high-level control signal EG1.

[0181] When the edge enable signal EGENb is at a high level (enabled), the edge enable signal EGENa is controlled to a low level. In this case, if the comparison result VCOφ2′ of the previous frame from the frame memory 350 is at a low level, the control unit 333 outputs a low-level control signal EG0 and a high-level control signal EG1. On the other hand, if the edge enable signal EGENb is at a high level and the comparison result VCOφ2′ is at a high level, the control unit 333 outputs a high-level control signal EG0 and a low-level control signal EG1.

[0182] 31 is a timing chart showing an example of the operation of an image sensor according to the seventh embodiment of the present technology. The diagram shows an example of the operation from the start of exposure to readout of one frame. In the diagram, the vertical axis indicates row addresses, and the horizontal axis indicates time. Furthermore, thin diagonal lines indicate the timing of initialization of the photoelectric conversion elements 251 and floating diffusion layers 256 for each row, and dashed dotted lines indicate the timing of initialization of the photoelectric conversion elements 251 for each row. Thick diagonal lines indicate the timing of readout for each row.

[0183] The vertical scanning circuit 210 sequentially selects rows and supplies pulses of a reset signal RST and a transfer signal TRG to the selected row. This initializes the photoelectric conversion elements 251 and floating diffusion layers 256 of the selected row, and exposure (in other words, charge accumulation) begins. The initialization timing of the photoelectric conversion elements 251 and floating diffusion layers 256 of a certain row is defined as T1.

[0184] The vertical scanning circuit 210 then selects rows in sequence and supplies a pulse of the control signal OFG to the selected row. This initializes only the photoelectric conversion elements 251 in the selected row. The initialization timing of the photoelectric conversion elements 251 in a certain row is T2. However, if the retention value MEM of the control signal EG in the previous frame is low, the photoelectric conversion elements 251 of that pixel 250 are not initialized. Therefore, if the retention value MEM is low (i.e., ΔVSL is relatively small), T1 is the timing to start charge accumulation. If the retention value MEM is high (i.e., ΔVSL is relatively large), T2 is the timing to start new charge accumulation.

[0185] The vertical scanning circuit 210 then selects rows in order and supplies a high-level selection signal SEL to the selected rows during the period from timing T10 to T18, etc. This ends charge accumulation and the edge determination result is read out. Details of this readout operation will be described later.

[0186] As shown in the figure, the charge accumulation period is controlled according to the retention value MEM of the previous frame, i.e., the value of ΔVSL of the previous frame. In the figure, when ΔVSL is relatively small, the charge accumulation period is the period from T1 to T10, and when ΔVSL is relatively large, the charge accumulation period is the period from T2 to T10.

[0187] FIG. 32 is a timing chart showing an example of a readout operation of the image sensor 200 according to the seventh embodiment of the present technology.

[0188] The vertical scanning circuit 210 sets the selection signal SEL to high level over the period from timing T10 to T17, and also supplies a high level reset signal RST to the selected row over the pulse period at timing T10.

[0189] Furthermore, at timing T10, the timing control circuit 230 supplies the auto-zero signal AZ and the reset signal EGRST to the comparator 331 and the control unit 333 over the pulse period.

[0190] Then, at timing T11, the vertical scanning circuit 210 supplies a high-level transfer signal TRG to the selected row over a pulse period.

[0191] Furthermore, the analog memories 260 of the pair of pixels each hold the control signals EG0 and EG1 of the previous frame as held values ​​MEM0 and MEM1.

[0192] Then, during the period from timing T12 to T13, the timing control circuit 230 supplies a high-level latch enable signal LAT to the downstream signal processing unit 290. In accordance with this signal, the signal processing unit 290 captures and holds the edge determination result at timing T12. The comparison result VCOφ1 from the comparator 331 at this time corresponds to the comparison result after control of the charge accumulation period.

[0193] Then, at timing T13, the timing control circuit 230 supplies the auto-zero signal AZ and the reset signal EGRST at high levels for the entire pulse period, thereby performing the auto-zero operation and controlling the control signals EG0 and EG1 to be at high levels for the entire pulse period.

[0194] Then, at timing T14, the vertical scanning circuit 210 supplies a high-level reset signal RST for a pulse period, causing the levels of the vertical signal lines VSL0 and VSL1 to become P-phase.

[0195] Then, the timing control circuit 230 supplies the latch enable signal LTEN over the pulse period at timing T15. The frame memory 350 holds the comparison result VCOφ2 of the P phase. This comparison result VCOφ2 corresponds to the comparison result before control of the charge accumulation period.

[0196] Then, the vertical scanning circuit 210 supplies the FDG enable signal FDGEN to the selected row during the period from timing T16 to T17, and the timing control circuit 230 supplies the reset enable signal RSTEN during that period.

[0197] The comparison result VCOφ1 is an example of a comparison result after controlling the accumulation period as set forth in the claims, and the comparison result VCOφ2 is an example of a comparison result before controlling the accumulation period as set forth in the claims.

[0198] As illustrated in FIGS. 31 and 32, the control section 333 controls the charge accumulation period in addition to the gain control based on the comparison result VCOφ2, thereby further improving the accuracy of edge detection.

[0199] 33 is a diagram showing an example of the operation of the edge determination circuit 340 according to the seventh embodiment of the present technology. When ΔVSL1 is much larger than ΔVSL0, the comparison result VCOφ1 is at a low level and the comparison result VCOφ2′ of the previous frame is at a high level. Based on these comparison results, the edge determination circuit 340 outputs a high-level determination result OUT indicating the presence of an edge.

[0200] If VSL1 is greater than ΔVSL0 but the difference between them is not so great, the comparison results VCOφ1 and VCOφ2′ will both be high. Based on these comparison results, the edge determination circuit 340 outputs a low-level determination result OUT indicating that there is no edge.

[0201] If VSL0 is greater than ΔVSL1 but the difference between them is not that great, the comparison results VCOφ1 and VCOφ2′ are both low. Based on these comparison results, the edge determination circuit 340 outputs a low-level determination result OUT indicating that there is no edge.

[0202] If ΔVSL0 is much larger than ΔVSL1, the comparison result VCOφ1 is high and the comparison result VCOφ2′ is low. Based on these comparison results, the edge determination circuit 340 outputs a high-level determination result OUT indicating that an edge is present.

[0203] The second embodiment can be applied to the seventh embodiment.

[0204] As described above, according to the seventh embodiment of the present technology, the control unit 333 controls the charge accumulation period based on the comparison result VCOφ2, and therefore, the accuracy of edge detection can be improved.

[0205] 8. Eighth Embodiment In the first embodiment described above, the reset transistor 253 and the gain control transistor 255 are connected in series within the pixel 250, but the present invention is not limited to this circuit configuration. The image sensor 200 in this eighth embodiment differs from the first embodiment in that the circuit configuration of the pixel 250 is changed.

[0206] 34 is a circuit diagram showing a configuration example of a pixel 250 according to an eighth embodiment of the present technology. In the eighth embodiment, a reset transistor 253 is inserted between a power supply voltage and a floating diffusion layer 256. Furthermore, a gain control transistor 255 and a capacitor 254 are inserted in series between the floating diffusion layer 256 and a ground terminal. In this manner, the reset transistor 253 and the gain control transistor 255 are connected in parallel to the floating diffusion layer 256.

[0207] It is also possible to use the circuit configurations shown in FIGS. 35 and 36.

[0208] 35 is a circuit diagram showing a configuration example of an FD sharing block 270 according to the eighth embodiment of the present technology. The pixel array unit 240 is divided into a plurality of FD sharing blocks 270. A plurality of pixels that share a floating diffusion layer 256 are arranged in each of the FD sharing blocks 270. For example, it is assumed that two pixels share the floating diffusion layer 256.

[0209] For example, the FD shared block 270 is composed of two pixels with coordinates (0,0) and (1,0), and the FD shared block 270 is composed of two pixels with coordinates (0,1) and (1,1). In this case, an edge is detected between either of the two pixels on the left side and either of the two pixels on the right side. The two pixels with coordinates (0,0) and (1,0) are an example of the first and second pixels described in the claims.

[0210] The FD shared block 270 includes, for example, photoelectric conversion elements 251-1 and 251-2, and transfer transistors 252-1 and 252-2. The FD shared block 270 further includes a reset transistor 253, a capacitor 254, a gain control transistor 255, a floating diffusion layer 256, an amplification transistor 257, and a selection transistor 258.

[0211] The transfer transistor 252-1 transfers charges from the photoelectric conversion element 251-1 to the floating diffusion layer 256 in accordance with a transfer signal TRG1 from the vertical scanning circuit 210. The transfer transistor 252-2 transfers charges from the photoelectric conversion element 251-2 to the floating diffusion layer 256 in accordance with a transfer signal TRG2 from the vertical scanning circuit 210.

[0212] The connection configuration of the reset transistor 253, the capacitor 254, the gain control transistor 255, the floating diffusion layer 256, the amplifying transistor 257, and the selection transistor 258 is the same as in the first embodiment.

[0213] In the figure, two pixels share the floating diffusion layer 256, but it can also be shared by more than two pixels, such as four or eight pixels. The sharing structure illustrated in the figure makes it possible to reduce the circuit scale per pixel compared to when there is no sharing.

[0214] 36 is a circuit diagram showing a configuration example of an FD link block 275 according to the eighth embodiment of the present technology. The pixel array unit 240 is divided into a plurality of FD link blocks 275. A plurality of pixels to which floating diffusion layers can be connected are arranged in each of the FD link blocks 275.

[0215] For example, two pixels at coordinates (0,0) and (1,0) constitute the FD link block 275, and two pixels at coordinates (0,1) and (1,1) constitute the FD link block 275. In this case, an edge is detected between either of the two pixels on the left side and either of the two pixels on the right side.

[0216] As described above, two pixels are arranged within the FD link block 275. One of the two pixels includes a photoelectric conversion element 251-1, a transfer transistor 252-1, a reset transistor 253-1, a gain control transistor 255-1, a floating diffusion layer 256-1, an amplification transistor 257-1, and a selection transistor 258-1. The other of the two pixels includes a photoelectric conversion element 251-2, a transfer transistor 252-2, a reset transistor 253-2, a gain control transistor 255-2, a floating diffusion layer 256-2, an amplification transistor 257-2, and a selection transistor 258-2.

[0217] The gain control transistors 255-1 and 255-2 are connected in series between the floating diffusion layer 256-1 and the floating diffusion layer 256-2. These gain control transistors 255-1 and 255-2 open and close the path between the floating diffusion layer 256-1 and the floating diffusion layer 256-2 in accordance with a control signal EG. By turning on these transistors, the control unit 333 can increase the combined capacitance and reduce the charge-voltage conversion efficiency. By making the pair of floating diffusion layers connectable in this way, the capacitor 254 becomes unnecessary.

[0218] The connection configuration of the elements other than the gain control transistors 255-1 and 255-2 is the same as in the first embodiment.

[0219] The gain control transistors 255-1 and 255-2 are examples of the first and second gain control transistors set forth in the claims. The floating diffusion layers 256-1 and 256-2 are examples of the first and second floating diffusion layers set forth in the claims.

[0220] The second embodiment can be applied to the eighth embodiment.

[0221] As described above, according to the eighth embodiment of the present technology, the circuit configuration of the pixel 250 is changed, and therefore it is possible to achieve a reduction in circuit scale in various circuit configurations.

[0222] 9. Ninth Embodiment In the first embodiment described above, the circuits are arranged on a single semiconductor chip, but this configuration may make it difficult to miniaturize pixels. Image sensor 200 in this ninth embodiment differs from the first embodiment in that the circuits are distributed across multiple stacked semiconductor chips.

[0223] 37 is a diagram showing an example of a stacked structure of an image sensor 200 according to a ninth embodiment of the present technology. The image sensor 200 according to the ninth embodiment includes a circuit chip 202 and a pixel chip 201 stacked on the circuit chip 202. These chips are electrically connected via connecting portions such as vias. Note that, in addition to vias, they can also be connected by Cu-Cu bonding or bumps.

[0224] The pixel chip 201 includes a pixel array unit 240, a north column signal processing circuit 301, and a south column signal processing circuit 302.

[0225] The north column signal processing circuit 301 reads pixel signals and edge determination results from half of the pixels (such as odd-numbered columns) in the pixel array unit 240, and the south column signal processing circuit 302 reads pixel signals and the like from the remaining half. Various peripheral circuits such as a signal processing unit 290 are arranged on the circuit chip 202.

[0226] As shown in FIG. 38, it is also possible to arrange only the pixel array section 240 on the pixel chip 201 and arrange the remaining circuits on the circuit chip 202.

[0227] 37 and 38, miniaturization of pixels is facilitated by distributing circuits among stacked pixel chips 201 and circuit chips 202. It is also possible to stack three or more semiconductor chips and arrange circuits on them.

[0228] It should be noted that each of the second to eighth embodiments can be applied to the ninth embodiment.

[0229] In this way, according to the ninth embodiment of the present technology, since the circuits are distributed and arranged on the stacked pixel chip 201 and circuit chip 202, it becomes easy to miniaturize the pixels.

[0230] 10. Application Examples to Mobile Bodies The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may be realized as a device mounted on any type of mobile body, such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, personal mobility, an airplane, a drone, a ship, or a robot.

[0231] FIG. 39 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile object control system to which the technology according to the present disclosure can be applied.

[0232] The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. In the example shown in Fig. 39, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside-vehicle information detection unit 12030, an inside-vehicle information detection unit 12040, and an integrated control unit 12050. Also shown as functional components of the integrated control unit 12050 are a microcomputer 12051, an audio / video output unit 12052, and an in-vehicle network I / F (Interface) 12053.

[0233] The drivetrain control unit 12010 controls the operation of devices related to the drivetrain of the vehicle in accordance with various programs. For example, the drivetrain control unit 12010 functions as a control device for a drive force generating device for generating a drive force of the vehicle, such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating a braking force of the vehicle.

[0234] The body system control unit 12020 controls the operation of various devices equipped in the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as headlamps, backup lamps, brake lamps, turn signals, and fog lamps. In this case, radio waves transmitted from a portable device that serves as a key or signals from various switches can be input to the body system control unit 12020. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door lock device, power window device, lamps, etc.

[0235] The outside-vehicle information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the outside-vehicle information detection unit 12030. The outside-vehicle information detection unit 12030 causes the imaging unit 12031 to capture images outside the vehicle and receives the captured images. The outside-vehicle information detection unit 12030 may perform object detection processing or distance detection processing for people, cars, obstacles, signs, characters on the road surface, etc. based on the received images.

[0236] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0237] The in-vehicle information detection unit 12040 detects information inside the vehicle. For example, a driver state detection unit 12041 that detects the state of the driver is connected to the in-vehicle information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 may calculate the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041, or may determine whether the driver is dozing off.

[0238] The microcomputer 12051 can calculate control target values ​​for the driving force generating device, steering mechanism, or braking device based on the information inside and outside the vehicle acquired by the outside-vehicle information detection unit 12030 or the inside-vehicle information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing the functions of an ADAS (Advanced Driver Assistance System), including vehicle collision avoidance or impact mitigation, following driving based on the distance between vehicles, maintaining vehicle speed, vehicle collision warning, vehicle lane departure warning, etc.

[0239] In addition, the microcomputer 12051 can perform cooperative control for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on driver operation, by controlling the driving force generating device, steering mechanism, braking device, etc. based on information about the surroundings of the vehicle obtained by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040.

[0240] Furthermore, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information outside the vehicle acquired by the outside information detection unit 12030. For example, the microcomputer 12051 can control the headlamps according to the position of a preceding vehicle or an oncoming vehicle detected by the outside information detection unit 12030, and perform cooperative control aimed at preventing glare, such as switching from high beams to low beams.

[0241] The audio / video output unit 12052 transmits at least one of audio and video output signals to an output device capable of visually or audibly notifying information to vehicle occupants or the outside of the vehicle. In the example of Fig. 39, the output devices are exemplified by an audio speaker 12061, a display unit 12062, and an instrument panel 12063. The display unit 12062 may include, for example, at least one of an on-board display and a head-up display.

[0242] FIG. 40 is a diagram showing an example of the installation position of the imaging unit 12031.

[0243] In FIG. 40, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.

[0244] The imaging units 12101, 12102, 12103, 12104, and 12105 are provided, for example, at positions such as the front nose, side mirrors, rear bumper, back door, and the top of the windshield inside the vehicle cabin of the vehicle 12100. The imaging unit 12101 provided on the front nose and the imaging unit 12105 provided on the top of the windshield inside the vehicle cabin mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 provided on the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 provided on the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The imaging unit 12105 provided on the top of the windshield inside the vehicle cabin is mainly used to detect preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, etc.

[0245] 40 shows an example of the imaging ranges of the imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of the imaging unit 12104 provided on the rear bumper or back door. For example, by overlaying the image data captured by the imaging units 12101 to 12104, an overhead image of the vehicle 12100 viewed from above can be obtained.

[0246] At least one of the image capturing units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the image capturing units 12101 to 12104 may be a stereo camera made up of multiple image capturing elements, or may be an image capturing element having pixels for phase difference detection.

[0247] For example, based on the distance information obtained from the imaging units 12101 to 12104, the microcomputer 12051 can calculate the distance to each three-dimensional object within the imaging ranges 12111 to 12114 and the change in this distance over time (relative speed with respect to the vehicle 12100), thereby extracting as a preceding vehicle, in particular, the three-dimensional object that is the closest three-dimensional object on the path of the vehicle 12100 and traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (e.g., 0 km / h or higher). Furthermore, the microcomputer 12051 can set a vehicle-to-vehicle distance to be maintained in advance in front of the preceding vehicle, and perform automatic braking control (including follow-up stop control), automatic acceleration control (including follow-up start control), etc. In this way, cooperative control can be performed for the purpose of autonomous driving, which runs autonomously without relying on driver operation.

[0248] For example, the microcomputer 12051 classifies and extracts three-dimensional object data regarding three-dimensional objects into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on distance information obtained from the imaging units 12101 to 12104, and can use the data for automatic obstacle avoidance. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. The microcomputer 12051 then determines a collision risk that indicates the risk of collision with each obstacle, and when the collision risk is equal to or greater than a set value and a collision is possible, the microcomputer 12051 can provide driving assistance for collision avoidance by outputting an alarm to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or avoidance steering via the drive system control unit 12010.

[0249] At least one of the image capturing units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether a pedestrian is present in the images captured by the image capturing units 12101 to 12104. Such pedestrian recognition is performed, for example, by extracting feature points from the images captured by the image capturing units 12101 to 12104 as infrared cameras and performing pattern matching on a series of feature points that indicate the outline of an object to determine whether the object is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the images captured by the image capturing units 12101 to 12104 and recognizes the pedestrian, the audio / image output unit 12052 controls the display unit 12062 to superimpose a rectangular outline on the recognized pedestrian for emphasis. The audio / image output unit 12052 may also control the display unit 12062 to display an icon or the like indicating the pedestrian at a desired position.

[0250] An example of a vehicle control system to which the technology according to the present disclosure can be applied has been described above. The technology according to the present disclosure can be applied to, for example, the image capturing unit 12031 of the above-described configuration. Specifically, the image capturing device 100 in FIG. 1 can be applied to the image capturing unit 12031. By applying the technology according to the present disclosure to the image capturing unit 12031, the circuit size of the image capturing unit 12031 can be reduced.

[0251] Note that the above-described embodiment shows an example for realizing the present technology, and the matters in the embodiment and the matters specifying the invention in the claims correspond to each other. Similarly, the matters specifying the invention in the claims and the matters in the embodiment of the present technology having the same name correspond to each other. However, the present technology is not limited to the embodiment, and can be realized by applying various modifications to the embodiment within the scope of the gist thereof.

[0252] The effects described in this specification are merely examples and are not limiting, and other effects may also be obtained.

[0253] The present technology may also be configured as follows: (1) An image sensor comprising: a comparator that compares the voltages of a pair of vertical signal lines and outputs a comparison result; a holding unit that holds the comparison result and outputs it as a pre-gain control comparison result; a control unit that controls a charge-voltage conversion efficiency of a pixel connected to one of the pair of vertical signal lines to a value different from that of a pixel connected to the other vertical signal line based on the pre-gain control comparison result; and an edge determination circuit that determines the presence or absence of an edge based on the pre-gain control comparison result and a post-gain control comparison result that is the comparison result when the charge-voltage conversion efficiency is controlled. (2) The image sensor according to (1), further comprising: an offset control unit that applies an offset voltage to one of the pair of vertical signal lines, wherein the control unit selects one of the pair of vertical signal lines based on the pre-gain control comparison result and causes the offset control unit to apply the offset voltage. (3) The image sensor according to (1) or (2), further comprising a vertical scanning circuit that supplies a transfer signal, a reset signal, and a control signal, wherein each of the pixels comprises: a transfer transistor that transfers charge from a photoelectric conversion element to a floating diffusion layer in accordance with the transfer signal, a reset transistor that initializes the floating diffusion layer in accordance with the reset signal, and a gain control transistor that controls the charge-to-voltage conversion efficiency in accordance with the control signal. (4) The image sensor according to (3), further comprising a timing control circuit that outputs a latch enable signal to the holding unit after the charge is transferred, wherein the holding unit captures and holds the comparison result in accordance with the latch enable signal. (5) The image sensor according to (4), wherein the timing control circuit sends an auto-zero signal to the comparator after sending the latch enable signal, and the comparator controls the voltages of the pair of vertical signal lines to be the same value in accordance with the auto-zero signal, and the vertical scanning circuit sends the reset signal after sending the auto-zero signal. (6) The image sensor according to (4) or (5), wherein the reset transistor and the gain control transistor are connected in series between a power supply voltage and the floating diffusion layer.(7) The image sensor according to (4) or (5), wherein the reset transistor and the gain control transistor are connected in parallel to the floating diffusion layer. (8) The image sensor according to any of (4) to (7), wherein the pixel includes first and second pixels, and the first and second pixels share the floating diffusion layer. (9) The image sensor according to any of (4) to (7), wherein the pixel includes first and second pixels, and the gain control transistor includes a first gain control transistor in the first pixel and a second gain control transistor in the second pixel, the floating diffusion layer includes a first floating diffusion layer in the first pixel and a second floating diffusion layer in the second pixel, and the first and second gain control transistors open and close a path between the first floating diffusion layer and the second floating diffusion layer in accordance with the control signal. (10) The image sensor according to any one of (4) to (9), wherein the pixel further comprises an enable switch that opens and closes a path between a vertical control line that transmits the control signal and the gate of the gain control transistor. (11) The image sensor according to (10), wherein the pixel further comprises an analog memory that stores the control signal. (12) The image sensor according to (11), wherein the pixel further comprises a charge drain transistor that initializes the photoelectric conversion element according to a signal that is a logical product of the control signal stored in the analog memory and a charge drain signal from the vertical scanning circuit. (13) The image sensor according to (1), further comprising a pair of selectors that select either the comparator or the control unit and connect the selector to the pair of vertical signal lines. (14) The image sensor according to any one of (1) to (13), further comprising a signal processing unit that processes a determination result of the edge determination circuit, wherein the pixel, the comparator, the holding unit, the control unit, and the edge determination circuit are arranged on a pixel chip, and the signal processing unit is arranged on a circuit chip. (15) The image sensor according to any one of (1) to (13), wherein the pixels are arranged on a pixel chip, and the signal processing unit, the comparator, the holding unit, the control unit, and the edge determination circuit are arranged on a circuit chip.(16) The image sensor according to any one of (1) to (15), wherein the image sensor is a back-illuminated image sensor. (17) The image sensor according to any one of (1) to (15), wherein the image sensor is a front-illuminated image sensor. (18) An image sensor comprising: a comparator that compares the voltages of a pair of vertical signal lines and outputs a comparison result, a holding unit that holds the comparison result and outputs it as a comparison result before accumulation period control, a control unit that controls a charge accumulation period of a pixel connected to one of the pair of vertical signal lines to a value different from that of a pixel connected to the other vertical signal line based on the comparison result before accumulation period control, and an edge determination circuit that determines the presence or absence of an edge based on the comparison result before accumulation period control and a comparison result after accumulation period control that is the comparison result when the charge accumulation period is controlled. (19) A control method for an image sensor, comprising: a comparison step of comparing the voltages of a pair of vertical signal lines and outputting a comparison result; a holding step of holding the comparison result and outputting it as a comparison result before gain control; a control step of controlling the charge-voltage conversion efficiency of a pixel connected to one of the pair of vertical signal lines to a value different from that of a pixel connected to the other vertical signal line based on the comparison result before gain control; and an edge determination step of determining whether or not an edge exists based on the comparison result before gain control and a comparison result after gain control, which is the comparison result when the charge-voltage conversion efficiency is controlled.

[0254] 100 Imaging device 110 Optical unit 120 DSP circuit 130 Display unit 140 Operation unit 150 Bus 160 Frame memory 170 Storage unit 180 Power supply unit 200 Image sensor 201 Pixel chip 202 Circuit chip 210 Vertical scanning circuit 220 DAC 230 Timing control circuit 240 Pixel array unit 250 Pixel 251, 251-1, 251-2 Photoelectric conversion element 252, 252-1, 252-2 Transfer transistor 253, 253-1, 253-2, 261 Reset transistor 254 Capacitor 255, 255-1, 255-2 Gain control transistor 256, 256-1, 256-2 Floating diffusion layer 257, 257-1, 257-2 Amplification transistor 258, 258-1, 258-2 Selection transistor 259 FDG enable switch 260 Analog memory 262 OFG enable switch 263 AND gate 264 Charge discharge transistor 270 FD sharing block 275 FD link block 280 Horizontal scanning circuit 290 Signal processing unit 300 Column signal processing circuit 301 North column signal processing circuit 302 South column signal processing circuit 320 ADC 330 Edge detection unit 331 Comparator 332 Holding unit 333 Control unit 334 Offset control unit 335, 336 Selector 340 Edge determination circuit 350 Frame memory 411 On-chip lens 412 Color filter 420 Wiring layer 430 Substrate 12031 Imaging unit

Claims

1. An image sensor comprising: a comparator that compares the voltages of a pair of vertical signal lines and outputs the comparison result; a holding unit that holds the comparison result and outputs it as a pre-gain control comparison result; a control unit that controls the charge-voltage conversion efficiency of a pixel connected to one of the pair of vertical signal lines to a value different from that of a pixel connected to the other vertical signal line based on the pre-gain control comparison result; and an edge determination circuit that determines the presence or absence of an edge based on the pre-gain control comparison result and a post-gain control comparison result that is the comparison result when the charge-voltage conversion efficiency is controlled.

2. The image sensor according to claim 1, further comprising an offset control section that applies an offset voltage to one of the pair of vertical signal lines, wherein the control section selects one of the pair of vertical signal lines based on the pre-gain control comparison result and causes the offset control section to apply the offset voltage.

3. An image sensor according to claim 1, further comprising a vertical scanning circuit that supplies a transfer signal, a reset signal, and a control signal, each of said pixels comprising: a transfer transistor that transfers charge from a photoelectric conversion element to a floating diffusion layer in accordance with said transfer signal; a reset transistor that initializes said floating diffusion layer in accordance with said reset signal; and a gain control transistor that controls said charge-to-voltage conversion efficiency in accordance with said control signal.

4. The image sensor according to claim 3, further comprising a timing control circuit that outputs a latch enable signal to the holding unit after the charges have been transferred, and the holding unit acquires and holds the comparison result in accordance with the latch enable signal.

5. The image sensor according to claim 4, wherein the timing control circuit sends an auto-zero signal to the comparator after sending the latch enable signal, the comparator controls the voltages of the pair of vertical signal lines to the same value in accordance with the auto-zero signal, and the vertical scanning circuit sends the reset signal after sending the auto-zero signal.

6. The image sensor according to claim 4, wherein the reset transistor and the gain control transistor are connected in series between a power supply voltage and the floating diffusion layer.

7. The image sensor according to claim 4, wherein the reset transistor and the gain control transistor are connected in parallel to the floating diffusion layer.

8. The image sensor according to claim 4, wherein the pixels include first and second pixels, and the first and second pixels share the floating diffusion layer.

9. The image sensor according to claim 4, wherein the pixel includes a first pixel and a second pixel, the gain control transistor includes a first gain control transistor in the first pixel and a second gain control transistor in the second pixel, the floating diffusion layer includes a first floating diffusion layer in the first pixel and a second floating diffusion layer in the second pixel, and the first and second gain control transistors open and close a path between the first floating diffusion layer and the second floating diffusion layer in accordance with the control signal.

10. The image sensor according to claim 4, wherein the pixel further comprises an enable switch that opens and closes a path between a vertical control line that transmits the control signal and the gate of the gain control transistor.

11. The image sensor according to claim 10, wherein the pixel further comprises an analog memory for storing the control signal.

12. The image sensor according to claim 11, wherein the pixel further comprises a charge drain transistor that initializes the photoelectric conversion element in accordance with a signal that is a logical product of the control signal stored in the analog memory and a charge drain signal from the vertical scanning circuit.

13. The image sensor according to claim 1, further comprising a pair of selectors for selecting either the comparator or the control section and connecting it to the pair of vertical signal lines.

14. The image sensor according to claim 1, further comprising a signal processing unit that processes the determination result of the edge determination circuit, wherein the pixels, the comparator, the holding unit, the control unit and the edge determination circuit are arranged on a pixel chip, and the signal processing unit is arranged on a circuit chip.

15. The image sensor according to claim 1, wherein the pixels are arranged on a pixel chip, and the signal processing unit, the comparator, the holding unit, the control unit, and the edge determination circuit are arranged on a circuit chip.

16. The image sensor according to claim 1, wherein the image sensor is a back-illuminated image sensor.

17. The image sensor according to claim 1, wherein the image sensor is a front-illuminated image sensor.

18. An image sensor comprising: a comparator that compares the voltages of a pair of vertical signal lines and outputs a comparison result; a holding unit that holds the comparison result and outputs it as a comparison result before accumulation period control; a control unit that controls the charge accumulation period of a pixel connected to one of the pair of vertical signal lines to a value different from that of a pixel connected to the other vertical signal line based on the comparison result before accumulation period control; and an edge determination circuit that determines the presence or absence of an edge based on the comparison result before accumulation period control and the comparison result after accumulation period control, which is the comparison result when the charge accumulation period is controlled.

19. A control method for an image sensor comprising: a comparison step of comparing the voltages of a pair of vertical signal lines and outputting a comparison result; a holding step of holding the comparison result and outputting it as a pre-gain control comparison result; a control step of controlling the charge-voltage conversion efficiency of a pixel connected to one of the pair of vertical signal lines to a value different from that of a pixel connected to the other vertical signal line based on the pre-gain control comparison result; and an edge determination step of determining the presence or absence of an edge based on the pre-gain control comparison result and a post-gain control comparison result which is the comparison result when the charge-voltage conversion efficiency is controlled.

Images