Da conversion device and ad conversion device

Abstract

The present invention provides a DA conversion device and the like that use the range of low voltage dependency of a MOS capacitor to make it possible to reduce nonlinearity of an output voltage. A charge scaling type DA conversion device comprising a high-order bit side capacitor array and a low-order bit side capacitor array that are connected via an attenuation capacitor comprises a control circuit that applies a voltage, to a plurality of capacitors of the high-order bit side capacitor array and a plurality of capacitors of the low-order bit side capacitor array, so that all of the capacitors have a positive bias voltage or a negative bias voltage at the times of reset and conversion of the DA conversion device, wherein at least one of a reference voltage of the low-order bit side capacitor array and a reset voltage is set to a value different from a reference voltage of the high-order bit side capacitor array.

Description

DA conversion device and AD conversion device

[0001] The present invention relates to a DA converter using, for example, a MOS type semiconductor element, and an AD converter including the DA converter.

[0002] 12 is a circuit diagram showing the configuration of a charge scaling DA converter according to Conventional Example 1, disclosed in Non-Patent Document 1. In FIG. 12, the charge scaling DA converter includes a plurality of capacitors that are a binary weighted capacitance cell array, and each capacitor is connected to a reference voltage V ＲＥＦ A plurality of N switches S for switching between connecting to the ground or ０ ~S Ｎ－１ The output reset switch SW101 resets the output voltage, and a buffer circuit including an operational amplifier 101 whose output terminal and inverting input terminal are connected.

[0003] The charge scaling type DA converter configured as above operates as follows: (1) The output reset switch SW101 is turned on, and the output terminal is set to a predetermined reset voltage. (2) The output reset switch SW101 is turned off, and the output terminal is returned to high impedance. (3) In each capacitor of the binary weight capacitance cell array, the terminal voltage on the side not connected to the DA converter output is set by the switch S in accordance with the input code. ０ ~S Ｎ－１ By controlling and switching between them, the reference voltage V ＲＥＦ The output voltage is obtained according to the capacitance division.

[0004] This charge scaling type DA converter is suitable for low power consumption because no steady current flows. ０ ~S Ｎ－１ , SW101 and a plurality of capacitors, and has been widely used to this day because it can take advantage of the scaling advantages of the miniaturization of the manufacturing process. When a load is connected to the output terminal, a buffer circuit including an operational amplifier 101 is connected, but when a comparator with a high capacitance impedance, such as a successive approximation type AD converter, is connected to the output, the output terminal is directly connected to the comparator.

[0005] 13 is a circuit diagram showing the configuration of a charge scaling DA converter according to Conventional Example 2. In the charge scaling DA converter of FIG. 13, when the resolution is increased, the number of unit cells of the capacitive DA converter is two. Ｎ－１ In order to reduce the number of unit cells, the capacitor array is divided into two, a higher-bit side capacitor array 121 and a lower-bit side capacitor array 122, and the attenuation capacitor C Ｓ where the damping capacitor C Ｓ is also referred to as scaling capacitance or bridging capacitance in some literature. Ｓ The lower-bit capacitor array 122 has the attenuation capacitor C Ｓ is expressed by the following equation so as to be scaled to the output voltage range of the most significant bit side capacitor array 121 via

[0006] C Ｓ = (number of unit capacitances of the lower-bit side capacitor array 122) / (number of unit capacitances of the upper-bit side capacitor array 121)×C ｕ

[0007] Here, C ｕ is the unit capacity.

[0008] Next, application examples of these charge scaling type DA converters will be briefly described below.

[0009] For example, Patent Document 2 discloses an image recognition system equipped with a solid-state imaging element integrated with a readout circuit. The image recognition system includes a solid-state imaging device (image sensor) as a sensor unit and an image signal processing device such as an image recognition device. The solid-state imaging device includes a pixel unit, a readout circuit unit for reading out pixel signals, and vertical (row) and horizontal (column) scanning circuits for controlling the readout of the arrayed pixels. The pixel unit outputs pixel signals to the readout circuit in the following procedure: (1) Input light is converted into electric charges by photoelectric conversion in the photodiode PD. (2) The RST gate (reset gate) is turned on, resetting the floating diffusion FD to the power supply voltage. (3) The transfer gate is turned on, and the signal charge generated in the photodiode PD is transferred to the floating diffusion FD for conversion into a voltage signal. (4) The pixel signal of the row selected by the row selection switch SEL is buffered and output via a source follower amplifier connected to the floating diffusion FD.

[0010] In the pixel disclosed in Non-Patent Document 3, in order to maximize the amount of incident light captured by the photodiode PD, it is necessary to reduce the thickness of the wiring layer and the number of wiring layers used so as to shorten the distance from the chip surface to the photodiode PD. Next, in the readout circuit, the pixel signal is extracted by sampling the difference between the reset signal of the floating diffusion FD and the pixel signal, and correlated double sampling (CDS) is performed to remove reset noise (kT / C) and threshold variation of the source follower amplifier. The voltage sampled by the CDS is converted into a digital signal by an AD converter. Furthermore, the AD converter in the readout circuit may be a successive approximation type, and the aforementioned charge scaling type capacitive DA converter is used to generate a reference voltage inside the AD converter.

[0011] US Patent No. 4,077,035 JP 2022-102604 A

[0012] Phillip E. et al., "CMOS Analog Circuit Design," Oxford University Press, pp. 44-46, 2002. Y.S. Yee et al., "A two-stage weighted capacitor network for D / AA / D conversion," IEEE Journal of Solid-state circuits, Vol. SC-14, No. 4, pp. 778-781, Aug. 1979. Takahashi, "Pixel reduction technology for CMOS image sensors," Journal of the Institute of Image Information and Television Engineers, Vol. 60, No. 3, pp. 295-298, 2006.

[0013] The readout circuit disclosed in Patent Document 2 requires a capacitance element to perform CDS and AD conversion. When the readout circuit and the sensor unit are mounted together, the number of wiring layers is limited in order to maximize the amount of incident light that can be captured by the photodiode PD. Therefore, there is a problem in that it is difficult to use a capacitance that uses a wiring layer due to wiring constraints.

[0014] To reduce the cost of the semiconductor processes used to fabricate these semiconductor devices, the number of wiring layers is often limited to two or three in order to reduce the number of masks used in the semiconductor process. To use a metal-insulator-metal (MIM) capacitor, which has a structure in which an insulating layer with good characteristics and low voltage and temperature dependence is sandwiched between metal plates, requires an additional mask for element formation, increasing costs. To solve this problem, wiring capacitors with good electrical characteristics could be used, but they are rarely used because of the large area required due to the low wiring processing accuracy and low capacitance density in inexpensive manufacturing processes.

[0015] As described above, under the above technical background, there are cases where it is not possible to use capacitance devices such as MIM devices with good electrical characteristics, and it is necessary to use MOS capacitance devices.

[0016] FIG. 14 is a cross-sectional view showing the capacitance of a MOS field effect transistor (MOSFET) used in a semiconductor device according to Conventional Example 3. FIG. 15 is a graph showing the voltage dependence of MOS capacitance, showing the capacitance value versus gate-source and drain voltages in FIG. 14. As shown in FIG. 14, the MOS capacitance used in the semiconductor device is an NMOS transistor or a depletion-type MOS field effect transistor on an N-type well 202 so that a channel exists even when the gate-substrate voltage Vgb=0 V. In FIG. 14, after an N-type well 202 is formed in a semiconductor substrate 201, a source electrode 212 and a drain electrode 213 are formed, and a gate electrode 211 is formed via a gate oxide film 203 and polysilicon 204.

[0017] 15, when the gate-to-substrate voltage Vgb is sufficiently high, a channel consisting of majority carriers is formed under the gate, resulting in an accumulation state, and the capacitance value is determined by the distance between the gate oxide film 203 and the channel under the gate and the dielectric constant of the gate oxide film 203. On the other hand, when the gate-to-substrate voltage Vgb approaches 0 V, minority carriers gather under the channel, forming a depletion layer under the gate. The capacitance value decreases because it depends on the thickness of the gate oxide film 203 as well as the thickness of the depletion layer, which is an insulating layer, and there is a possibility that the capacitance value will have voltage dependency on the gate-to-substrate voltage Vgb.

[0018] As described above, when the number of wiring layers is limited as described above, it is not possible to use capacitance elements with good electrical characteristics, and when MOS capacitance is used, there is a problem that the linearity of the charge scaling type capacitance DA converter deteriorates.

[0019] An object of the present invention is to solve the above problems and to provide, for example, a DA converter using MOS-type semiconductor elements, which can reduce the nonlinearity of the DA converter by using a range in which the voltage dependency of the MOS capacitance is low compared to conventional techniques, and an AD converter equipped with the DA converter.

[0020] A DA conversion device according to one embodiment of the present invention is a charge scaling DA conversion device comprising a higher-order bit side capacitor array and a lower-order bit side capacitor array connected via attenuation capacitors, wherein the higher-order bit side capacitor array includes a plurality of capacitors with MOS capacitance having a binary-weighted capacitance ratio, and the lower-order bit side capacitor array includes a plurality of capacitors with MOS capacitance having a binary-weighted capacitance ratio, and the DA conversion device further comprises a control circuit that applies a positive bias voltage or a negative bias voltage to the plurality of capacitors in the higher-order bit side capacitor array and the plurality of capacitors in the lower-order bit side capacitor array at the time of resetting and conversion of the DA conversion device, and at least one of the reference voltage and the reset voltage of the lower-order bit side capacitor array is set to a value different from the reference voltage of the higher-order bit side capacitor array.

[0021] Therefore, according to the D / A conversion device of the present invention, in a charge scaling D / A conversion device that uses MOS capacitance, by increasing the attenuation capacitor and, for example, lowering the reference voltage of the lower-bit side capacitor array, it is possible to set the bias voltage of the MOS capacitance so that the MOS capacitance operates in a range with substantially low voltage dependency, thereby reducing the nonlinearity of the D / A conversion device.

[0022] 6 is a circuit diagram showing an example of the configuration of a charge scaling DA converter 1 according to a first embodiment. FIG. 7 is a timing chart of each signal showing the operation of the charge scaling DA converter 1 of FIG. 1. FIG. 8 is a circuit diagram showing the case where the inter-capacitor potential difference in the most significant bit capacitor array 21 of FIG. 1 is a minimum value. FIG. 9 is a circuit diagram showing the case where the inter-capacitor potential difference in the attenuation capacitor array 22 of FIG. 1 is a minimum value. FIG. 10 is a circuit diagram showing an example of the configuration of a charge scaling DA converter 1A according to a second embodiment. FIG. 6 is a timing chart of each signal showing the operation of the charge scaling DA converter 1A of FIG. 6. FIG. 7 is a block diagram showing an example of the configuration of a successive approximation AD converter 31 according to a third embodiment. FIG. 8 is a block diagram showing an example of the configuration of a successive approximation AD converter 32 according to a fourth embodiment. FIG. 9 is a block diagram showing an example of the configuration of a successive approximation AD converter 33 according to a fifth embodiment. FIG. 9 is a block diagram showing an example of the configuration of a successive approximation AD converter 34 according to a sixth embodiment. FIG. 11 is a circuit diagram showing the configuration of a charge scaling DA converter according to a first conventional example. 14 is a circuit diagram showing the configuration of a charge scaling DA converter according to Conventional Example 2. It is a cross-sectional view showing the capacitance of a MOS field effect transistor (MOSFET) used in a semiconductor device according to Conventional Example 3. It is a graph of the voltage dependency of MOS capacitance, showing the capacitance value with respect to the gate-source and drain voltages of FIG.

[0023] Hereinafter, embodiments and modifications of the present invention will be described with reference to the drawings, in which the same or similar components are designated by the same reference numerals.

[0024] 1 is a circuit diagram showing an example of the configuration of a charge scaling DA converter 1 according to a first embodiment. In FIG. 1, the charge scaling DA converter 1 has a feature that, compared to the prior art, the reference voltage V ｒｅｆ２ｐ , V ｒｅｆ２ｍ is the reference voltage V of the upper bit side capacitor array 21. ｒｅｆ１ｐ , V ｒｅｆ１ｍ It is characterized by being separated from the

[0025] In FIG. 1, the plurality of capacitors that are the binary-weighted capacitance cell array include (n+1) capacitors C1 belonging to the upper bit side capacitor array 21 and having a binary-weighted capacitance. ０ ~C1 ｎ and (m+1) capacitors C2 belonging to the lower-bit side capacitor array 22 and having a binary-weighted capacitance. ０ ~C2 ｍ and capacitor C2 ０ Termination capacitor C2 connected to ｔ where the termination capacitor C2 ｔ are provided to adjust the full-scale output voltage range of the DA conversion device. ０ ~C1 ｎ and (m+1) capacitors C2 belonging to the lower-bit side capacitor array 22. ０ ~C2 ｍ is the damping capacitor C ａ are connected via

[0026] Here, the (n+1) capacitors C1 belonging to the upper bit side capacitor array 21 ０ ~C1 ｎ and (m+1) capacitors C2 belonging to the lower-bit side capacitor array 22. ０ ~C2 ｍ and the termination capacitor C2 ｔ and a damping capacitor C ａ The capacitor C1 is composed of a MOS capacitor such as an N-channel MOS field effect transistor (hereinafter referred to as an NMOS transistor). The MOS capacitor has, for example, the element configuration shown in FIG. 14 and the electrical characteristics shown in FIG. 15. ０ ~C1 ｎ and capacitor C2 ０ ~C2 ｍ As will be described later, the unit capacity C ｕ The NMOS transistor may be configured by one NMOS transistor having the above-mentioned structure or by connecting a plurality of NMOS transistors in parallel.

[0027] The charge scaling DA converter 1 further includes: (1) (n+1) capacitors C1 belonging to the most significant bit side capacitor array 21; ０ ~C1 ｎ The other end of each is connected to a reference voltage V ｒｅｆ１ｐ or V ｒｅｆ１ｍ (n+1) switches SW ｍ＋１ ~SW ｎ＋ｍ＋１ (2) (m+1) capacitors C2 belonging to the lower-order bit capacitor array 22 ０ ~C2 ｍ The other end of each is connected to a reference voltage V ｒｅｆ２ｐ or V ｒｅｆ２ｍ (m+1) switches SW ０ ~SW ｍ (3) (n+1) capacitors C1 belonging to the upper bit side capacitor array 21 ０ ~C1 ｎ Each end of the reset voltage V ｒｓｔ１ A reset switch SW switches whether to connect to the ｒｓｔ１ (4) (m+1) capacitors C2 belonging to the lower-bit side capacitor array 22 ０ ~C2 ｍ Each end of the reset voltage V ｒｓｔ２ A reset switch SW switches whether to connect to the ｒｓｔ２ and,

[0028] In this specification, the symbol of each capacitor also indicates the capacitance value. The reset signal RST1 goes from L level to H level at a predetermined time T1 in the reset period, and the reset signal RST2 goes from L level to H level at a predetermined time T2 (<T1) in the reset period. Furthermore, the (m+1) capacitors C2 belonging to the lower-bit side capacitor array 22 ０ ~C2 ｍ The voltage at each end of the output voltage V ｏ２ and (n+1) capacitors C1 belonging to the upper bit side capacitor array 21 ０ ~C1 ｎ The voltage at each end of the output voltage Vｏ１ and the output voltage V ｏ１ is the output voltage of the charge scaling DA converter 1 of FIG.

[0029] The charge scaling DA converter 1 further includes a switch SW ０ ~SW ｎ＋ｍ＋１ The bit signal b that controls the switching of ０ ~b ｎ＋ｍ＋１ and a control circuit 10 that generates reset signals RST1 and RST2.

[0030] Fig. 2 is a timing chart of each signal showing the operation of the charge scaling DA converter 1 of Fig. 1. The operation of the charge scaling DA converter 1 of Fig. 1 will be described below with reference to Fig. 2.

[0031] In FIG. 2, first, a bit signal b corresponding to a desired output voltage is ０ ~b ｎ＋ｍ＋１ Based on this, the switch SW ０ ~SW ｎ＋ｍ＋１ By controlling the capacitor C1 ０ ~C1 ｎ , C2 ０ ~C2 ｍ The terminal voltages at the other ends of the ｒｅｆ１ｐ , V ｒｅｆ２ｐ or V ｒｅｆ１ｍ , V ｒｅｆ２ｍ where the bit signal b ０ ~b ｎ＋ｍ＋１ When the value of is 1, the capacitor C1 ０ ~C1 ｎ , C2 ０ ~C2 ｍ The other end of each is a reference voltage V ｒｅｆ１ｐ , V ｒｅｆ２ｐ and the bit signal b ０ ~b ｎ＋ｍ＋１ When the value of is 0, the capacitor C1 ０ ~C1 ｎ , C2 ０ ~C2 ｍ The other end of each is a reference voltage V ｒｅｆ１ｍ , V ｒｅｆ２ｍ At the same time, by controlling the reset signals RST1 and RST2, the switch SW ｒｓｔ１, SW ｒｓｔ２ is turned on, and the output voltage V ｏ１ , V ｏ２ are the initial voltage, the reset voltage V ｒｓｔ１ , V ｒｓｔ２ Set to.

[0032] Next, the output voltage V ｏ１ SW ｒｓｔ２ In order to prevent errors such as charge injection that occur when the switch is turned on and off, the reset signal RST2 is controlled first, and then the reset signal RST1 is controlled. ｒｓｔ２ , SW ｒｓｔ１ This causes the output voltage V ｏ２ , V ｏ１ Each terminal is set to high impedance and the reset voltage is sampled.

[0033] Then, a bit signal b corresponding to the desired output voltage is ０ ~b ｎ＋ｍ＋１ Based on this, the switch SW ０ ~SW ｎ＋ｍ＋１ , capacitor C1 ０ ~1 ｎ , C2 ０ ~C2 ｍ The terminal voltage at the other end is controlled to be connected to a reference voltage of the opposite polarity to that at the time of reset, and the reference voltage V ｒｅｆ１ｐ , V ｒｅｆ２ｐ or the reference voltage V ｒｅｆ１ｍ , V ｒｅｆ２ｍ The capacitance ratio connected to the bit signal b ０ ~b ｎ＋ｍ＋１ The output voltage V ｏ１ In order to obtain the following DA conversion output, the output voltage V ｏ１ , V ｏ２ If each terminal can maintain high impedance, the bit signal b can be continued without resetting. ０ ~b ｎ＋ｍ＋１ may be controlled by switching between the above.

[0034] Here, capacitor C1 ｎ , C2 ｍ are the unit capacitances C1 ｕ , C2 ｕare expressed by equations (1) and (2), respectively.

[0035]

[0036]

[0037] The total capacitance value C1 of the most significant bit capacitor array 21 is expressed by equation (3), and the total capacitance value C2 of the least significant bit capacitor array 22 is expressed by equation (4).

[0038]

[0039]

[0040] Here, the termination capacitor C2 ｔ The capacitance value of the unit capacitance C2 is set so that the voltage difference between the full code voltage and the zero code voltage is (reference voltage - 1 LSB voltage). ｕ is set to

[0041] Output voltage V of the DA conversion device 1 ｏ１ (1) Output voltage V ｏ１ When the lower-bit side capacitor array 22 is viewed from the terminal ａ and the series capacitance value C12 of the total capacitance value C2 of the lower-bit side capacitor array 22. ａ (5) expressing the output voltage V ｏ２ When the upper bit side capacitor array 21 is viewed from the terminal ａ and the series capacitance value C21 of the total capacitance value C1 of the upper bit side capacitor array 21. ａ (3) Equation (7) representing the gain G1 of the upper bit side capacitor array 21; and (4) Equation (8) representing the output voltage V ｏ２ Output voltage V ｏ１ (5) Equation (9) representing the gain G2 of the lower-bit side capacitor array 22; and (6) Equation (10) representing the output voltage V ｏ１(7) Expressions (11) and (12) representing the reference voltage difference when the reference voltages of the upper-bit side capacitor array 21 and the lower-bit side capacitor array 22 are switched, and

[0042]

[0043]

[0044]

[0045]

[0046]

[0047]

[0048]

[0049]

[0050]

[0051] Here, p ｉ indicates the polarity value of the output voltage control of each bit signal, and the reference voltage at the time of reset is the reference voltage V ｒｅｆ１ｐ From the above, the reference voltage V at the time of output of the DA conversion device 1 is ｒｅｆ１ｍ , the polarity value p ｉ is the reference voltage V ｒｅｆ２ｐ to the reference voltage V ｒｅｆ２ｍ If you switch to it, it becomes -1, and if you do the opposite, it becomes +1, and if you don't switch it, it becomes 0.

[0052] Similarly, the output voltage V of the lower-order bit capacitor array 22 ｏ２ (1) Output voltage V ｏ１ Output voltage V ｏ２ (2) the output voltage V from the upper-bit side capacitor array 21; ｏ２ The transfer gain G21 to the terminal of the

[0053]

[0054]

[0055]

[0056] Furthermore, a damping capacitor C ａ The capacitance value of the output voltage V ｏ１ is the bit signal b ｎ＋ｍ＋１ Since it is controlled by a binary weight, the output voltage V ｏ１ and the output voltage V of the lower-bit capacitor array 22 at (full code + 1 LSB) ｏ１ It is necessary to satisfy the conditional expression (17) that

[0057]

[0058] Therefore, by substituting equations (7) and (10) into equation (17), the capacitance value of the attenuation capacitor Ca can be obtained from equation (18).

[0059]

[0060] The output voltage range of the DA conversion device 1 in FIG. ｎ , C2 ｍ All capacitors C1 ０ ~C1 ｎ and C2 ０ ~C2 ｍ , the reference voltage V ｒｅｆ１ｐ , V ｒｅｆ２ｐ When connected to and reset, the output voltage V ｏ１ The minimum value V ｏ１ｍｉｎ is the control of all bits of the bit signal from 1 to 0, and the polarity value p ｉ = -1, which is expressed by the following equation.

[0061] V ｏ１ｍｉｎ =V ｒｓｔ１ -V ｒｅｆ１ × (1-1 / 2 ｎ＋ｍ＋２ ) ≒ V ｒｓｔ１ -V ｒｅｆ１

[0062] In addition, the output voltage V ｏ１ The maximum value of V ｏ１ｍａｘThe polarity value p ｉ = 0, it is expressed by the following equation.

[0063] V ｏ１ｍａｘ =V ｒｓｔ１

[0064] On the other hand, capacitor C1 ｎ , C2 ｍ are all connected to a reference voltage V ｒｅｆ１ｍ , V ｒｅｆ２ｍ When connected to and reset, the output voltage V ｏ１ The minimum value V ｏ１ｍｉｎ is the polarity value p ｉ = 0, it is expressed by the following equation.

[0065] V ｏ１ｍｉｎ =V ｒｓｔ１

[0066] In addition, the output voltage V ｏ１ The maximum value of V ｏ１ｍａｘ is the control of all bits of the bit signal from 0 to 1, and the polarity value p ｉ = 1, which is expressed by the following equation.

[0067] V ｏ１ｍａｘ =V ｒｓｔ１ +V ｒｅｆ１ × (1-1 / 2 ｎ＋ｍ＋２ ) ≒ V ｒｓｔ１ +V ｒｅｆ１

[0068] In this way, at the time of reset, capacitor C1 ｎ , C2 ｍ The output voltage range can be set by changing the connection destination of the reference voltage of the capacitor C1. ｎ , C2 ｍ If the capacitance value of has voltage dependency, the charge scaling type capacitive DA converter generates nonlinearity because its output voltage is determined by the binary-weighted capacitance ratio. However, in order to reduce the nonlinearity due to the voltage dependency, a damping capacitor C ａ Therefore, it is possible to set the bias voltage applied at the time of resetting and outputting to either positive or negative.ｒｅｆ２ Or reset voltage V ｒｓｔ２ By setting at least one of these to a value different from that of the upper bit side capacitor array 21 and ensuring a predetermined bias voltage, the MOS capacitor can be operated in a range with low voltage dependency.

[0069] FIG. 3 is a circuit diagram when the potential difference between the capacitances in the upper bit side capacitor array 21 of FIG. 1 becomes the minimum value.

[0070] Here, as an example, (1) the reference voltages are V ｒｅｆ１ｐ >0, V ｒｅｆ２ｐ >0, V ｒｅｆ１ｍ =V ｒｅｆ２ｍ = 0, (2) all capacitors C1 ０ ~C1 ｎ , C2 ０ ~C2 ｍ are the reference voltages V ｒｅｆ１ｐ , V ｒｅｆ２ｐ (3) Capacitor C1 of the upper bit side capacitor array 21 ０ ~C1 ｎ and one end of the attenuation capacitor C ａ The top plate (gate) of the output voltage V ｏ１ (4) each capacitor C2 of the lower-bit side capacitor array 22 is connected to the terminal ０ ~C2 ｍ The top plate (gate) of the output voltage V ｏ２ (5) Connect all capacitors C1 ０ ~C1 ｎ , C2 ０ ~C2 ｍ Unit capacity C ｕ Consider the case where an NMOS transistor is used for the MOS capacitor shown in FIGS. 15 and 16 and a positive bias voltage is applied so that the potential difference across the capacitance is equal to or greater than a predetermined positive bias voltage Vb higher than the ground voltage (hereinafter referred to as the first case).

[0071] In the first case, in the upper bit side capacitor array 21, the capacitor C1 ０ Only the reference voltage V ｒｅｆ１ｐThe potential difference between the capacitances is smallest when the capacitors are connected to the

[0072] V ｒｓｔ１ -V ｒｅｆ１ｐ ≧V ｒｅｆ１ｐ +Vb (19)

[0073] FIG. 4 is a circuit diagram of the charge scaling DA converter 1 of FIG. 1 when the potential difference across the attenuation capacitors is at its minimum value (hereinafter referred to as the second case).

[0074] In the second case, the damping capacitor C ａ Regarding the capacitor C1 of the upper bit side capacitor array 21, ０ ~C1 ｎ The other end of each of the ｒｅｆ１ｍ , and the capacitor C2 of the lower-order bit capacitor array 22 is connected to ０ ~C2 ｍ The other end of each of the ｒｅｆ２ｐ When the capacitor is connected to the resistor R, the potential difference between the attenuation capacitors is minimized and the following equation must be satisfied: The circuit diagram for this case is shown in FIG.

[0075] V ｒｓｔ１ -V ｒｅｆ１ｐ ≧V ｒｓｔ２ +Vb (20)

[0076] FIG. 5 is a circuit diagram showing the case where the potential difference between the capacitances in the lower-order bit capacitor array 22 in FIG. 1 is at a minimum (hereinafter referred to as the third case).

[0077] In the third case, the lower-order bit capacitor array 22 also has the capacitor C2 ０ Only the reference voltage V ｒｅｆ２ｐ When the capacitor is connected to the load, the potential difference between the capacitors is at a minimum value, and the following equation must be satisfied: The circuit diagram for this case is shown in Figure 5.

[0078] V ｒｓｔ２ -V ｒｅｆ２ｐ ≧V ｒｅｆ２ｐ +Vb (21)

[0079] Therefore, the reset voltage V is set to satisfy all of the equations (19), (20), and (21). ｒｓｔ１, V ｒｓｔ２ , and the reference voltage V ｒｅｆ１ｐ , V ｒｅｆ２ｐ Just set it as follows.

[0080] Furthermore, to reduce the voltage, the reset voltage V ｒｓｔ１ In order to lower the reference voltage V ｒｅｆ２ｐ At this time, it becomes necessary to lower the damping capacitor C ａ is adjusted to be the formula (18). ０ ~C2 ｍ The accuracy required for the capacitance value is ０ ~C1 ｎ Therefore, the bias voltage Vb in equation (21) may be set lower than the bias voltage Vb of the upper bit side capacitor array 21, allowing for a higher voltage dependency of the capacitance. Furthermore, in order to reduce the number of terminals, the reference voltage V ｒｅｆ１ｍ and the reference voltage V ｒｅｆ２ｍ can be set to be equal to each other to make it a common terminal, or if all of the equations (19), (20), and (21) are satisfied, the reset voltage V ｒｓｔ2 and the reference voltage V ｒｅｆ１ｐ may be set equal to each other to form a common terminal.

[0081] As described above, according to the first embodiment, in the charge scaling DA converter 1, the unit capacitance C ｕ When there is a voltage dependency like a MOS capacitance, the unit capacitance C ｕ By setting the bias voltage so that the operating point is substantially in a range with low voltage dependency, the nonlinearity of the output voltage of the DA conversion device 1 can be reduced.

[0082] In addition, the output voltage V ｏ１ When a load is connected to the output terminal of the input terminal, a buffer circuit including an operational amplifier may be connected, and when a comparator having a high capacitive impedance, such as a successive approximation type AD converter, is connected to the output, the output terminal is directly connected to the comparator. This configuration is similar to that in other embodiments.

[0083] In the first embodiment, (1) each capacitor C1 of the upper bit side capacitor array 21 ０ ~C1 ｎ The top plate (gate) of the output voltage V ｏ１ (2) a damping capacitor C ａ and each capacitor C2 of the lower-order bit side capacitor array 22 ０ ~C2 ｍ The top plate (gate) of the output voltage V ｏ２ By connecting to the terminal, the output voltage V ｏ１ , V ｏ２ damping capacitor C ａ By reversing the connection direction and setting it as follows, the reset voltage V ｒｓｔ２ may be set higher.

[0084] (1) Each capacitor C1 of the upper bit side capacitor array 21 ０ ~C1 ｎ At a bias voltage Vb of V ｒｓｔ１ -V ｒｅｆ１ｐ ≧V ｒｅｆ１ｐ +Vb (22) (2) Damping capacitor C ａ At a bias voltage Vb of V ｒｓｔ２ -V ｒｅｆ２ｐ ≧V ｒｓｔ１ +Vb (23) (3) Each capacitor C2 of the lower-order bit side capacitor array 22 ０ ~C2 ｍ At a bias voltage Vb of V ｒｓｔ２ -V ｒｅｆ２ｐ ≧V ｒｅｆ２ｐ +Vb (24)

[0085] The reset voltage V is set so as to satisfy all of the above equations (22), (23), and (24). ｒｓｔ１ , V ｒｓｔ２ , and the reference voltage V ｒｅｆ１ｐ , V ｒｅｆ２ｐ may be set.

[0086] In the first embodiment, even when the capacitance element is used with a negative bias, the reference voltage V ｒｅｆ２ｐ or reset voltage V ｒｓｔ２At least one of the voltages is set to the reference voltage V ｒｅｆ１ｐ or reset voltage V ｒｓｔ１ By setting it to a value different from ｕ The nonlinearity of the output voltage of the DA conversion device 1 may be reduced by setting the bias voltage so that the operating point of is substantially in a range with low voltage dependency.

[0087] (Embodiment 2) Fig. 6 is a circuit diagram showing an example of the configuration of a charge scaling DA converter 1A according to embodiment 2. In Fig. 6, the charge scaling DA converter 1A according to embodiment 2 is characterized in that, compared to the charge scaling DA converter 1 of Fig. 1, a lower-order bit side capacitor array 23 having a configuration similar to that of the lower-order bit side capacitor array 22 and its peripheral circuits are added below the lower-order bit side capacitor array 22, thereby improving the resolution of the DA converter. The charge scaling DA converter 1A according to embodiment 2 differs from the charge scaling DA converter 1 of Fig. 1 in the following ways.

[0088] (1) The damping capacitor C in FIG. ａ is expressed as C ａ１ (2) Damping capacitor C ａ１ A damping capacitor C ａ２ (3) Each capacitor C3 of the lower-order bit side capacitor array 23 ０ ~C3 ｋ (4) In the lower-bit side capacitor array 23, a termination capacitor C3 ｔ (5) Each capacitor C3 of the lower-order bit side capacitor array 23 ０ ~C3 ｋ , and each bit signal b ０ ~b ｋ The switch SW ０ ~SW ｋ (6) Each capacitor C3 of the lower-order bit side capacitor array 23 ０ ~C3 ｋ The reset switch SW is connected to one end of the reset signal RST3.ｒｓｔ３ via the reset voltage V ｒｓｔ３ Each capacitor C3 ０ ~C3 ｋ The output voltage at each end of V ｏ３ (7) The sign of the switch in the upper bit side capacitor array 21 is SW ｍ＋ｋ＋２ ~SW ｎ＋ｍ＋ｋ＋２ The sign of the bit signal that controls the switch is b ｍ＋ｋ＋２ ~b ｎ＋ｍ＋ｋ＋２ (8) The code of the switch of the lower-order bit side capacitor array 22 is SW ｋ＋１ ~SW ｍ＋ｋ＋１ The sign of the bit signal that controls the switch is b ｋ＋１ ~b ｍ＋ｋ＋１ (9) Instead of the control circuit 10 in FIG. ０ ~b ｎ＋ｍ＋ｋ＋２ and a control circuit 10A that generates reset signals RST1, RST2, and RST3.

[0089] As described above, in the second embodiment, the lower-order bit capacitor array 23 is added, and the attenuation capacitor C ａ２ and the output voltage V of the lower-bit side capacitor array 22 via the lower-bit side capacitor array 22. ｏ２ Further voltage division and scaling are performed to increase the resolution of the DA converter.

[0090] Fig. 7 is a timing chart of each signal showing the operation of the charge scaling DA converter 1A of Fig. 6. Note that the reset signal RST1 changes from L level to H level at a predetermined time T1 within the reset period, the reset signal RST2 changes from L level to H level at a predetermined time T2 (<T1) within the reset period, and the reset signal RST3 changes from L level to H level at a predetermined time T3 (<T2) within the reset period.

[0091] In FIG. 7, first, a bit signal b corresponding to a desired output voltage is ０ ~b ｎ＋ｍ＋ｋ＋２ Based on the switch SW ０ ~SW ｎ＋ｍ＋ｋ＋２By controlling the capacitors C1 in the capacitor arrays 21, 22, and 23, ０ ~C1 ｎ , C2 ０ ~C2 ｍ , C3 ０ ~C3 ｋ The other terminal of each of the ｒｅｆ１ｐ , V ｒｅｆ２ｐ , V ｒｅｆ３ｐ or the reference voltage V ｒｅｆ１ｍ , V ｒｅｆ２ｍ , V ｒｅｆ３ｍ where the bit signal b ０ ~b ｎ＋ｍ＋ｋ＋２ When the value of is 1, the capacitor C1 ０ ~C1 ｎ , C2 ０ ~C2 ｍ , C3 ０ ~C3 ｋ The other end of each is a reference voltage V ｒｅｆ１ｐ , V ｒｅｆ２ｐ， V ｒｅｆ３ｐ and the bit signal b ０ ~b ｎ＋ｍ＋ｋ＋２ When the value of is 0, the capacitor C1 ０ ~C1 ｎ , C2 ０ ~C2 ｍ， C3 ０ ~C3 ｋ The other end of each is a reference voltage V ｒｅｆ１ｍ , V ｒｅｆ２ｍ , V ｒｅｆ３ｍ At the same time, by controlling the reset signals RST1, RST2, and RST3, the switches SW ｒｓｔ１ , SW ｒｓｔ２ , SW ｒｓｔ３ is turned on, and the output voltage V ｏ１ , V ｏ２ , V ｏ３ are the initial voltage, the reset voltage V ｒｓｔ１ , V ｒｓｔ２ , V ｒｓｔ３ Set to.

[0092] Next, the reset signals RST3, RST2, and RST1 are controlled in this order to turn on the switch SW ｒｓｔ３ , SW ｒｓｔ２ , SW ｒｓｔ１are turned off in this order, and the output voltage V ｏ３ , V ｏ２ , V ｏ１ Each terminal is set to high impedance and the reset voltage is sampled.

[0093] Then, a bit signal b corresponding to the desired output voltage is ０ ~b ｎ＋ｍ＋ｋ＋２ Based on this, the switch SW ０ ~SW ｎ＋ｍ＋ｋ＋２ In each of the capacitor arrays 21, 22, and 23, the capacitor C1 ０ ~C1 ｎ , C2 ０ ~C2 ｍ， C3 ０ ~C3 ｋ The other terminal voltage of each of the switches SW1 and SW2 is connected to a reference voltage of the opposite polarity to that at the time of reset. ０ ~SW ｎ＋ｍ＋ｋ＋２ By controlling the reference voltage V ｒｅｆ１ｐ , V ｒｅｆ２ｐ , V ｒｅｆ３ｐ or the reference voltage V ｒｅｆ１ｍ , V ｒｅｆ２ｍ , V ｒｅｆ３ｍ The capacitance ratio connected to the bit signal b ０ ~b ｎ＋ｍ＋ｋ＋２ By switching according to ｏ１ get.

[0094] For example, (1) for the reference voltage, V ｒｅｆ１ｐ >0 V ｒｅｆ２ｐ >0 V ｒｅｆ３ｐ >0 V ｒｅｆ１ｍ =V ｒｅｆ２ｍ =V ｒｅｆ３ｍ = 0, (2) each capacitor C1 ０ ~C1 ｎ , C2 ０ ~C2 ｍ， C3 ０ ~C3 ｋ are the reference voltages V ｒｅｆ１ｐ , V ｒｅｆ２ｐ , V ｒｅｆ３ｐ (3) Connect each capacitor C1 of the upper bit side capacitor array 21 to ０ ~C1 ｎ The top plate (gate) of the output voltage Vｏ１ (4) a damping capacitor C ａ１ , C ａ２ and each capacitor C2 of the lower-order bit side capacitor array 22 ０ ~C2 ｍ The top plate (gate) of the output voltage V ｏ２ (5) each capacitor C3 of the lower-bit side capacitor array 23 is connected to the terminal ０ ~C3 ｋ Top plate (gate) output voltage V ｏ３ (6) When an N-channel field effect transistor is used as a unit capacitor and a positive bias voltage is applied to the unit capacitor so that the potential difference between the capacitors is equal to or greater than the positive bias voltage Vb, the reset voltage V is set to satisfy all of the following equations: ｒｓｔ１ , V ｒｓｔ２ , V ｒｓｔ３ and the reference voltage V ｒｅｆ１ｐ , V ｒｅｆ２ｐ , V ｒｅｆ３ｐ Just set it as follows.

[0095] (1) Each capacitor C1 of the upper bit side capacitor array 21 ０ ~C1 ｎ At a bias voltage Vb of V ｒｓｔ１ -V ｒｅｆ１ｐ ≧V ｒｅｆ１ｐ +Vb (2) damping capacitor C ａ１ At a bias voltage Vb of V ｒｓｔ２ -V ｒｅｆ２ｐ ≧V ｒｓｔ１ +Vb (3) Each capacitor C2 of the lower-order bit side capacitor array 22 ０ ~C2 ｍ At a bias voltage Vb of V ｒｓｔ２ -V ｒｅｆ２ｐ ≧V ｒｅｆ２ｐ +Vb (4) Damping capacitor C ａ２ At a bias voltage Vb of V ｒｓｔ２ -V ｒｅｆ２ｐ ≧V ｒｓｔ３ +Vb (5) Each capacitor C3 of the lower-order bit side capacitor array 23 ０ ~C3 ｋ At a bias voltage Vb of V ｒｓｔ３ -Vｒｅｆ３ｐ ≧V ｒｅｆ３ｐ +Vb

[0096] Here, the reference voltage V ｒｅｆ２ｐ , V ｒｅｆ３ｐ To lower the ａ１ is the output voltage V at 1 LSB of the most significant bit side capacitor array 21 ｏ１ and the output voltage V of the lower-bit capacitor array 22 at (full code + 1 LSB) ｏ１ (2) the damping capacitor C ａ２ is the output voltage V of the lower bit side capacitor array 22 at 1 LSB of the lower bit side capacitor array 22 ｏ２ and the output voltage V of the lower bit side capacitor array 22 at (full code + 1 LSB) of the lower bit side capacitor array 23. ｏ２ should be set so that they are equal.

[0097] As described above, according to the charge scaling DA converter 1A of the second embodiment, by configuring the three-stage capacitor arrays 21, 22, and 23, it is possible to increase the resolution of the DA converter compared to the charge scaling DA converter 1 of the first embodiment, and also to reduce the unit capacitance C ｕ When there is a voltage dependency like a MOS capacitance, the unit capacitance C ｕ By setting the bias voltage so that the operating point of the DA converter 1A is substantially in a range with low voltage dependency, the nonlinearity of the output voltage of the DA converter 1A can be reduced. In other words, the charge scaling DA converter 1A according to the second embodiment has the same effects as the charge scaling DA converter 1 according to the first embodiment.

[0098] 8 is a block diagram showing an example of the configuration of a successive approximation type AD converter 31 according to the third embodiment. In FIG. 8, the successive approximation type AD converter 31 according to the third embodiment comprises: (1) the charge scaling type DA converter 1 according to the first embodiment of FIG. 1; and (2) an input voltage V ｉｎ Sampling capacitor 2 (capacity C ｓ ) and (3) the sampled input voltage V based on the reset signal RST11.ｉｎ Reset switch SW to switch whether to pass or block Ｓ (4) Sampled input voltage V ｉｎ and the output voltage V from the DA conversion device 1, which serves as the reference voltage. ｏ１ (5) a comparator 3 that compares the two and outputs a comparison result signal; and (6) a comparator 3 that compares the two and outputs a comparison result signal, and outputs a bit signal b ０ ~b ｎ＋ｍ＋１ and outputs it to the DA conversion device 1 via a control circuit 10B, and (6) a control circuit 10B provided in place of the control circuit 10 in Fig. 1. The SAR control logic circuit 4 and the control circuit 10B operate based on a clock CLOCK. The differences will be explained below.

[0099] In FIG. 8, the control circuit 10B outputs a reset signal RST11 at H level to the reset switch SW ｓ By outputting to the control terminal of the switch SW ｓ Next, the control circuit 10B turns on the input voltage V ｉｎ The reset switch SW is switched by controlling the L-level reset signal RST11 at the timing of sampling the ｓ After that, the control circuit 10B turns off the input voltage V ｉｎ is connected to a predetermined fixed potential. ｓ The input voltage V ｉｎ When the fixed potential connected to is 0V, the input terminal of the comparator 3 has a voltage (V ｒｓｔ１１ -V ｉｎ ) is sampled and input.

[0100] Here, in order to remove errors in the previous stage of the AD conversion device 31, a predetermined input reset voltage V is first applied instead of the input voltage Vin. ｉｎｒｓｔ and then turn the reset switch SW ｓ At the timing when the input signal voltage V ｉｎｓｉｇ Alternatively, correlated double sampling may be used, in which a reset voltage V ｒｓｔ１１ is the reset voltage V of the charge scaling DA converter 1 ｒｓｔ１Alternatively, when a comparator 3 with auto-zero function and an input offset storage function is used, the output voltage of the comparator 3 during auto-zero when the input and output terminals of the comparator 3 are shorted may be used. Furthermore, the reset signal RST1 of the charge scaling DA converter 1 may be used as the reset signal RST11.

[0101] Input voltage V ｉｎ After sampling, the SAR control logic circuit 4 controls the output voltage V ｏ１ at a predetermined voltage (V ｒｅｆｐ -V ｒｅｆｍ ) / 2 via the control circuit 10B. ｒｅｆｐ , V ｒｅｆｍ are the reference voltages of the DA conversion device 1, where V ｒｅｆｐ >V ｒｅｆｍ Then, the comparator 3 detects the input voltage V ｉｎ and the output voltage V of the DA conversion device 1 ｏ１ The SAR control logic circuit 4 then compares the output voltage V of the DA conversion device 1, which serves as the comparison reference voltage for the comparator 3 for the next bit conversion, to obtain the conversion result of the most significant bit MSB. ｏ１ Based on the conversion result of the MSB, ｒｅｆｐ -V ｒｅｆｍ ) / 2 ± (V ｒｅｆｐ -V ｒｅｆｍ ) / 4. After that, the SAR control logic circuit 4 performs similar comparisons up to the least significant bit LSB, and updates the output voltage V ｏ１ is updated, and the output voltage V ｏ１ and the input voltage V of the comparator 3 ｉｎ A / D conversion is performed by sequentially performing a binary search based on the comparison result so that the values ​​are equal to each other.

[0102] The successive approximation type AD converter 31 according to the third embodiment configured as described above improves the nonlinearity of the DA converter 1 used to generate its reference voltage, thereby improving the linearity of the AD converter 31. Furthermore, by making it possible to use a MOS capacitor with the highest capacitance density per unit area in the semiconductor process used for the reference capacitor of the DA converter 1, it is possible to achieve the function in a small area.

[0103] In the third embodiment described above, the charge scaling DA converter 1 is used, but the present invention is not limited to this, and the charge scaling DA converter 1A according to the second embodiment may also be used.

[0104] 9 is a block diagram showing an example of the configuration of a successive approximation type AD converter 32 according to a fourth embodiment. In FIG. 9, the successive approximation type AD converter 32 according to the fourth embodiment differs from the successive approximation type AD converter 31 of FIG. 8 in the following respects: (1) a sampling capacitor 2 (capacitance C ｓ ) and reset switch SW Ｓ (2) A DA conversion device 1B including a control circuit 10C is provided instead of the DA conversion device 1. (3) The comparator 3 compares a predetermined common voltage Vcm with the output voltage from the DA conversion device 1B. The SAR control logic circuit 4 and the control circuit 10C operate based on a clock CLOCK. The differences will be explained below.

[0105] The DA conversion device 1B is a DA conversion device 1 in which the switches SW of the reference voltage of the upper bit side capacitor array 21 are ｍ＋１ ~SW ｎ＋ｍ＋１ In this case, the input voltage V of the AD converter ｉｎ By adding an input terminal (input terminal c in FIG. 9) to which the above signal is input, a comparator 3 and an SAR control logic circuit 4 are added, as in the third embodiment, to form a successive approximation type AD conversion device 32.

[0106] In the AD conversion device 32 configured as above, the input voltage V ｉｎ The SAR control logic circuit 4 controls the control circuit 10C to turn on the reset switch SW based on the reset signal RST1 at H level. ｒｓｔ１ is turned on, and the switch SW ｍ＋１ ~SW ｎ＋ｍ＋１ By switching each to the input terminal c side, the input voltage V ｉｎ After that, the control circuit 10C connects the L-level reset signal RST1 to the reset switch SW ｒｓｔ１By outputting to the control terminal of ｒｓｔ１ Turn it off.

[0107] Next, the input voltage V ｉｎ After sampling, the SAR control logic circuit 4 controls the DA converter of the lower-bit side capacitor array 22 to output the output voltage V ｏ１ is controlled so that the following equation is satisfied, and the comparator 3 detects the common voltage V ｃｍ A comparison is made to the

[0108] V ｏ１ = (V ｒｅｆｐ -V ｒｅｆｍ ) / 2-V ｉｎ

[0109] Then, in the AD conversion of the next bit, the DA converter of the lower-bit side capacitor array 22 is used to obtain the output voltage V ｏ１ is updated based on the DA conversion result in the most significant bit capacitor array 21 so as to satisfy the following equation:

[0110] V ｏ１ = (V ｒｅｆｐ -V ｒｅｆｍ ) / 2 ± (V ｒｅｆｐ -V ｒｅｆｍ ) / 4-V ｉｎ

[0111] Thereafter, the comparison is similarly performed up to the least significant bit LSB, and the output voltage of the DA converter of the lower-bit side capacitor array 22 is updated, and the output voltage V ｏ１ is the common voltage V ｃｍ Based on the comparison result of the comparator 3, the SAR control logic circuit 4 performs AD conversion by sequentially performing a binary search.

[0112] The successive approximation type AD conversion device 32 of the fourth embodiment configured as described above has the unique effect of reducing the changes in the offset and kickback noise of the comparator 3 that depend on the input voltage of the comparator 3, since the input voltage of the comparator 3 that is updated in accordance with the successive approximation operation asymptotically approaches the reference common voltage Vcm, independent of the input voltage of the AD conversion device, compared to the second embodiment.

[0113] In the fourth embodiment described above, the charge scaling DA converter 1 is used, but the present invention is not limited to this, and the charge scaling DA converter 1A according to the second embodiment may also be used.

[0114] (Fifth Embodiment) Fig. 10 is a block diagram showing an example of the configuration of a successive approximation type AD converter 33 according to a fifth embodiment. In Fig. 10, the successive approximation type AD converter 33 according to the fifth embodiment is characterized in that the successive approximation type AD converter 32 according to the third embodiment has a differential configuration. Therefore, compared to the successive approximation type AD converter 32, the successive approximation type AD converter 33 has the following configuration: (1) A sampling capacitor 2 (capacitance C ｓ ) is configured by a pair of DA conversion devices 1, 1 according to the first embodiment. (2) The output voltage of the first DA conversion device 1 is output to a first input terminal of a comparator 3A, and the first input terminal is connected to a reset signal RST1 of the first DA conversion device 1 as a sample-and-hold signal SH and a reset switch SW ｒｓｔ１ Sampling switch SW ｓｐ , the reset voltage V ｒｓｔ１ is the first input voltage V ｉｎｐ and based on the sample-and-hold signal SH from the control circuit 10D, ｉｎｐ The sampling switch SW ｓｐ (3) The output voltage of the second DA conversion device 1 is output to the second input terminal of the comparator 3A, and the reset signal RST1 of the second DA conversion device 1 is input to the second input terminal as the sample and hold signal SH via the reset switch SW. ｒｓｔ１ Sampling switch SW ｓm , the reset voltage V ｒｓｔ１ to the second input voltage V ｉｎm and based on the sample-and-hold signal SH from the control circuit 10D, ｉｎｍ The sampling switch SW ｓｍ (4) The SAR control logic circuit 4A, which is provided in place of the SAR control logic circuit 4, controls the operation of the DA conversion devices 1, 1 via the control circuit 10D. The bit signal bp of the control circuit 10D ０ ~bp ｎ＋ｍ＋１indicates the switch SW of the first DA conversion device 1 ０ ~SW ｎ＋ｍ＋１ Switch between bm ０ ~bm ｎ＋ｍ＋１ indicates the switch SW of the second DA conversion device 1 ０ ~SW ｎ＋ｍ＋１ The SAR control logic circuit 4A and the control circuit 10D operate based on a clock CLOCK.

[0115] In the successive approximation type AD converter 33 configured as above, first, the sampling switch SW ｓｐ , SW ｓｍ is turned on, then turned off, and the differential input voltage V ｉｎｐ , V ｉｎｍ The differential input voltage V ｉｎｐ , V ｉｎｍ After sampling, the comparator 3A compares the pair of differential input voltages from the DA conversion devices 1 and outputs a comparison judgment result signal to the SAR control logic circuit 4A. Based on the comparison judgment result signal, the SAR control logic circuit 4A controls the output voltages of the DA conversion devices 1 and 1 so that the input differential voltage to the comparator 3A becomes smaller. Thereafter, based on the comparison judgment result signal of the comparator 3A, the output voltages of the DA conversion devices 1 and 1 are controlled so that the input differential voltage to the comparator 3A becomes smaller in the same manner, and the SAR control logic circuit 4A performs AD conversion by sequentially performing a binary search.

[0116] As described above, according to the fifth embodiment, the AD conversion device of the fourth embodiment can be configured as a differential converter, and a pair of differential input voltages V ｉｎｐ , V ｉｎｍ can be AD converted.

[0117] In the fifth embodiment described above, the DA conversion devices 1, 1 are used, but the present invention is not limited to this, and the DA conversion devices 1A, 1A may also be used.

[0118] Sixth Embodiment Fig. 11 is a block diagram showing an example of the configuration of a successive approximation register AD converter 34 according to the sixth embodiment. In Fig. 11, the successive approximation register AD converter 34 according to the sixth embodiment differs from the successive approximation register AD converter 33 according to the fifth embodiment shown in Fig. 10 in the following respects: (1) The DA converters 1, 1 of the successive approximation register AD converter 33 are configured using the DA converters 1B, 1B shown in Fig. 9, respectively. (2) A control circuit 10E is provided instead of the control circuit 10D. Note that the SAR control logic circuit 4A and the control circuit 10E operate based on a clock CLOCK.

[0119] In the successive approximation type AD conversion device 34 according to the sixth embodiment configured as described above, the pair of DA conversion devices 1B, 1B performs a sampling operation similar to that of the DA conversion device 1B according to the fourth embodiment, and then performs AD conversion similar to the operation after sampling of the AD conversion device 33 according to the fifth embodiment.

[0120] As described above, according to the sixth embodiment, a differential configuration can be achieved using the DA conversion devices 1B, 1B of the third embodiment, and a pair of differential input voltages V ｉｎｐ , V ｉｎｍ can be AD converted.

[0121] In the above embodiment, the reference voltage V ｒｅｆ１ｍ , V ｒｅｆ１ｐ and the reference voltage V ｒｅｆ２ｍ , V ｒｅｆ２ｐ However, the present invention is not limited to this, and two different reference voltages may be used.

[0122] As described above in detail, according to the semiconductor device of the present invention, in a charge scaling D / A converter that uses MOS capacitance, by increasing the size of the attenuation capacitor and, for example, lowering the reference voltage of the lower-bit side capacitor array, it is possible to set the bias voltage of the MOS capacitance so that the MOS capacitance operates in a range with substantially low voltage dependency, thereby reducing the nonlinearity of the output voltage of the D / A converter.

[0123] 1, 1A, 1B DA conversion device 2 Sampling capacitor 3, 3A Comparator 4, 4A Successive approximation control logic circuit (SAR control logic circuit) 10, 10A, 10B, 10C, 10D, 10E Control circuit 21 High-order bit side capacitor array 22, 23 Low-order bit side capacitor array 31 to 34 AD conversion device C1 ０ ~C1 ｎ Capacitor C2 ０ ~C2 ｍ Capacitor C ａ Damping capacitor SW ｒｓｔ１ , SW ｒｓｔ２ , SW ｒｓｔ３ , SW ｓ Reset switch SW ０ ~SW ｍ , SW ｍ＋１ ~SW ｎ＋ｍ＋１ , SW ０ ~SW ｋ , SW ｋ＋１ ~SW ｍ＋ｋ＋１ , SW ｍ＋ｋ＋１ ~SW ｎ＋ｍ＋ｋ＋２ Switch SW ｓｐ , SW ｓｍ Sampling Switch

Claims

1. A charge scaling D / A conversion device comprising a higher-order bit side capacitor array and a lower-order bit side capacitor array connected via attenuation capacitors, wherein the higher-order bit side capacitor array includes a plurality of MOS capacitance capacitors having a binary-weighted capacitance ratio, and the lower-order bit side capacitor array includes a plurality of MOS capacitance capacitors having a binary-weighted capacitance ratio, the D / A conversion device further comprising a control circuit that applies a positive bias voltage or a negative bias voltage to the plurality of capacitors of the higher-order bit side capacitor array and the plurality of capacitors of the lower-order bit side capacitor array when the D / A conversion device is reset or during conversion, and at least one of the reference voltage and the reset voltage of the lower-order bit side capacitor array is set to a value different from the reference voltage of the higher-order bit side capacitor array.

2. The DA conversion device according to claim 1, further comprising another lower-bit side capacitor array, connected via another attenuation capacitor to the lower-bit side of the lower-bit side capacitor array, and including a plurality of capacitors of MOS capacitance having a binary-weighted capacitance ratio.

3. An AD conversion device comprising: the DA conversion device according to claim 1 or 2; a sampling capacitor that samples an input voltage; a reset switch that resets the sampled input voltage; a comparator that compares the sampled input voltage with an output voltage from the DA conversion device and outputs a comparison result signal; and a successive approximation control logic circuit that controls the DA conversion device based on the comparison result signal from the comparator to perform AD conversion of the input voltage.

4. An AD conversion device comprising the DA conversion device according to claim 1 or 2, wherein the DA conversion device further comprises a plurality of switches that selectively switch between inputting an input voltage and inputting two mutually different reference voltages to each of a plurality of capacitors in a higher-order bit side capacitor array, and the AD conversion device further comprises: a comparator that compares a predetermined common voltage with the output voltage from the DA conversion device and outputs a comparison result signal; and a successive approximation control logic circuit that controls the plurality of switches via the DA conversion device based on the comparison result signal from the comparator to AD convert the input voltage.

5. A successive approximation type AD conversion device that performs AD conversion on a pair of differential input voltages including first and second input voltages, comprising: a pair of DA conversion devices that are the DA conversion devices according to claim 1 or 2; a comparator that samples the first and second input voltages, respectively, compares the pair of sampled differential voltages with each other, and outputs a comparison result signal; and a successive approximation control logic circuit that performs AD conversion on the pair of differential input voltages by controlling the pair of DA conversion devices based on the comparison result signal from the comparator.

6. A successive approximation type AD converter that performs AD conversion on a pair of differential input voltages including first and second input voltages, comprising: a pair of DA converters that are the DA converters according to claim 4; one of the pair of DA converters receives the first input voltage and the other of the pair of DA converters receives the second input voltage; a comparator that compares the output voltages from the pair of DA converters and outputs a comparison result signal; and a successive approximation control logic circuit that performs AD conversion on the pair of differential input voltages by controlling the pair of DA converters based on the comparison result signal from the comparator.

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