Substrate for semiconductor package, low-temperature fired glass ceramic plate, and method for manufacturing substrate for semiconductor package

Abstract

Disclosed is a substrate 1 for a semiconductor package, which contains a glass phase and a crystal phase, and has a rectangular shape having a substrate size of 300 mm × 300 mm or larger, or a circular shape having a diameter of 300 mm or more.

Description

Substrate for semiconductor package, low-temperature fired glass ceramic plate, and method for manufacturing substrate for semiconductor package

[0001] The present invention relates to a substrate for a semiconductor package.

[0002] The semiconductor package includes a core substrate, a semiconductor element, and an interposer disposed between the core substrate and the semiconductor element.

[0003] Conventionally, organic substrates made of resin or the like have been widely used as core substrates, but there has been a problem in that they are difficult to meet the recent demand for finer wiring. Therefore, in order to achieve finer wiring, it has been proposed to use a glass substrate as the core substrate (see, for example, Patent Document 1).

[0004] JP 2024-050818 JP 9-169559

[0005] Masahiro Ashizuka and two others, "Mechanical Properties of Various Silicate Crystals (1st Report)", Journal of the Ceramic Society of Japan, 1989, Vol. 97, No. 5, pp. 544-548

[0006] In semiconductor package substrates used as core substrates, etc., multiple holes (vias) are formed to electrically connect wiring. As wiring becomes finer, the diameter of these holes and the distance between adjacent holes become very small. Therefore, laser drilling, which is capable of fine processing, is sometimes used as a drilling method.

[0007] However, when a glass substrate is used as a substrate for a semiconductor package, laser drilling can easily cause damage such as cracks around the holes. This problem becomes particularly pronounced when the size of the glass substrate is increased. In other words, increasing the size of the glass substrate increases the number of holes to be formed, which inevitably increases the number of laser shots. As a result, distortion accumulates, making damage such as cracks more likely to occur around the holes. It goes without saying that cracks here do not refer to very small scratches (microcracks) that remain on the surface, but rather to cracks that propagate through the glass phase. The presence of these cracks makes the glass more susceptible to breakage.

[0008] An object of the present invention is to provide a substrate for a semiconductor package that is not easily damaged even when holes are drilled using a laser.

[0009] (1) The present invention, which was invented to solve the above problems, is a substrate for a semiconductor package, characterized in that it has a glass phase and a crystalline phase, and is a rectangular substrate having a size of 300 mm x 300 mm or more, or a circular substrate having a diameter of 300 mm or more.

[0010] In this way, since the semiconductor package substrate has a glass phase and a crystalline phase, the disadvantage of the glass phase, which is that it is easily broken, can be compensated for by the crystalline phase. In other words, the crystalline phase can suppress the formation and propagation of cracks around the holes during laser drilling. Therefore, even if the substrate size of the semiconductor package substrate is increased as described above, breakage during laser drilling is less likely to occur.

[0011] (2) In the above configuration (1), the substrate for a semiconductor package preferably has a flatness of 10 μm or less over the entire central portion excluding a peripheral portion having a width of 10 mm.

[0012] This reduces the number of times that focusing is required during photolithography to form wiring, thereby improving the manufacturing efficiency of semiconductor packages.

[0013] (3) In the above configuration (1) or (2), it is preferable that the substrate for a semiconductor package has a waviness of 100 μm or less over the entire central portion excluding the peripheral portion having a width of 10 mm.

[0014] In this way, swell (warpage) of the substrate obtained from the semiconductor package substrate is suppressed, and therefore, disconnection of the wiring due to swell of the obtained substrate during mounting can be suppressed.

[0015] (4) In any of the above configurations (1) to (3), the substrate for a semiconductor package is preferably used as a core substrate.

[0016] The core substrate is thicker than the interposer, etc., and is prone to thermal stress during laser drilling. Therefore, the effect of the present invention, which is to reduce the risk of breakage during laser drilling, becomes even more effective.

[0017] (5) In any of the above configurations (1) to (4), the substrate for a semiconductor package is preferably a sintered body.

[0018] This makes it possible to more reliably prevent cracks from forming around the holes when the holes are drilled using a laser.

[0019] (6) In any of the configurations (1) to (5) above, the substrate for semiconductor package preferably has a hole formation region in which a plurality of holes having a diameter of 100 μm or less are densely formed, and the number of holes provided within the hole formation region is preferably 2 to 30,000 per 10 mm square.

[0020] In other words, the semiconductor package substrate according to the present invention allows such fine holes to be formed at a high density, thereby fully meeting the demand for finer wiring in core substrates and the like.

[0021] (7) In any of the above configurations (1) to (6), the substrate for semiconductor package preferably has a thickness of 0.3 mm to 1.4 mm.

[0022] This provides a thickness suitable for use as a substrate for a semiconductor package.

[0023] (8) In any of the above configurations (1) to (7), the substrate for a semiconductor package preferably has a Young's modulus of 40 GPa to 90 GPa.

[0024] This makes it difficult for the semiconductor package substrate to deform.

[0025] (9) In any of the configurations (1) to (8) above, the semiconductor package substrate is made of a glass ceramic substrate, and when the thermal expansion coefficient of the crystalline phase is α1 [ppm / K] and the thermal expansion coefficient of the glass phase is α2 [ppm / K], it is preferable that the relationship 2≦α1 / α2≦8 holds.

[0026] Based on common knowledge, it would be expected that in order to suppress damage such as cracks around the hole during laser drilling, it would be effective to have no difference between the thermal expansion coefficient α1 of the crystalline phase and the thermal expansion coefficient α2 of the glass phase (α1 / α2 = 1). However, as a result of the inventor's diligent research, contrary to this expectation, it was found that in order to suppress damage such as cracks around the hole during laser drilling, it is effective to have a difference between the thermal expansion coefficient α1 of the crystalline phase and the thermal expansion coefficient α2 of the glass phase, such that 2≦α1 / α2≦8. In other words, if the relationship 2≦α1 / α2≦8 is established, damage such as cracks is less likely to occur around the hole even when laser drilling is performed.

[0027] (10) In the above-mentioned (9), it is preferable that the content of the crystalline phase is 2 to 50% by weight, and the content of the glass phase is 50 to 98% by weight.

[0028] The crystalline phase is more difficult to drill with a laser than the glass phase, so in order to efficiently drill with a laser, it is preferable that the content of the glass phase in the semiconductor package substrate is equal to or greater than the content of the crystalline phase, as in the above configuration.

[0029] (11) In the configuration of (9) or (10) above, the substrate for semiconductor package preferably has a thermal expansion coefficient α1 of the crystalline phase of 6 to 20 ppm / K and a thermal expansion coefficient α2 of the glass phase of 0.6 to 5 ppm / K.

[0030] (12) In any of the above (9) to (11), the thermal expansion coefficient of the entire semiconductor package substrate is preferably 2.5 to 15 ppm / K.

[0031] This suppresses thermal expansion of the semiconductor package substrate due to localized heating during the laser hole drilling process, making it more difficult for damage such as cracks to occur around the holes.

[0032] (13) In any of the configurations (9) to (12) above, it is preferable that the hole formation region has a plurality of holes having a diameter of 100 μm or less densely arranged, the number of holes is 1 to 4,000 per 10 mm square in the hole formation region, and the thickness is 0.1 to 1.0 mm.

[0033] With the semiconductor package substrate according to the present invention, even if the substrate has a thickness within the above-mentioned range, holes with the above-mentioned minute diameters can be formed without cracks. Furthermore, even if holes are formed at a density per 10 mm square as described above, the holes can be formed without cracks. Therefore, the substrate can fully meet the demand for finer wiring in, for example, interposers, core substrates, image sensors, etc.

[0034] (14) In any of the above (9) to (13), the substrate for a semiconductor package is preferably for an interposer.

[0035] (15) In any of the above (9) to (13), the substrate for a semiconductor package is preferably for use as a core substrate.

[0036] (16) In any of the above configurations (9) to (13), the substrate for a semiconductor package is preferably a substrate for an image sensor.

[0037] (17) In any one of the above (9) to (16), the substrate for semiconductor package has a fracture toughness K ＩＣ is 1.0 to 2.5 MPa m １／２ It is preferable that:

[0038] This makes it difficult for microcracks formed around the holes during the hole drilling process to develop into scratches.

[0039] (18) In any of the above (9) to (17), the substrate for semiconductor package preferably has a Young's modulus of 40 to 90 GPa.

[0040] This makes it difficult for microcracks formed around the holes during the hole drilling process to develop into scratches.

[0041] (19) In any of the above (9) to (18), the substrate for semiconductor package preferably includes a layer containing an interlayer insulating material on the substrate.

[0042] (20) The present invention, which has been invented to solve the above problems, is a low-temperature fired glass ceramic plate, characterized in that the flatness of the entire central portion excluding the peripheral portion having a width of 10 mm is 10 μm or less, and a plurality of core substrates are obtained from the plate.

[0043] This allows the low-temperature-fired glass ceramic plate to prevent cracks from forming around the holes and their propagation during laser drilling. Therefore, even for large substrates from which multiple core substrates are obtained, damage during laser drilling is less likely to occur. Furthermore, the number of focusing operations during photolithography to form wiring can be reduced.

[0044] (21) The present invention, which has been invented to solve the above problems, is a low-temperature fired glass ceramic plate, characterized in that the waviness is 100 μm or less over the entire central portion excluding the 10 mm wide peripheral portion, and that multiple core substrates for semiconductor packages are obtained from the plate.

[0045] In this way, because it is a low-temperature fired glass ceramic plate, the formation and propagation of cracks around the holes during laser drilling can be suppressed. Therefore, even for large substrate sizes from which multiple core substrates are extracted, breakage during laser drilling is less likely to occur. In addition, because undulation of the extracted core substrates is suppressed, wiring breakage due to undulation of the core substrates during mounting can be suppressed.

[0046] (22) The present invention, which has been invented to solve the above problems, is a method for manufacturing a substrate for a semiconductor package, comprising: a preparation step of preparing a substrate for a semiconductor package having any of the configurations of (9) to (19) above; and a step of applying CO ２ and a hole-making process for forming holes by irradiating a laser.

[0047] This makes it less likely that damage such as cracks will occur around the holes in the semiconductor package substrate during the hole drilling process using a laser.

[0048] According to the present invention, it is possible to provide a substrate for a semiconductor package that is not easily damaged even when holes are drilled using a laser.

[0049] FIG. 7 is a plan view showing a semiconductor package substrate according to the present embodiment. FIG. 8 is a view for explaining a method for measuring flatness (TTV). FIG. 9 is a view for explaining a method for measuring waviness (Warp). FIG. 10 is a cross-sectional view showing an enlarged hole formation region of the semiconductor package substrate of FIG. 1. FIG. 11 is a cross-sectional view showing a semiconductor package according to the present embodiment. FIG. 12 is a flow chart showing a method for manufacturing a semiconductor package substrate according to the present embodiment. FIG. 13 is a plan view for explaining an example of a substrate molding process using slip cast molding. FIG. 14 is a cross-sectional view taken along the line A-A of FIG. 7. FIG. 15 is a cross-sectional view for explaining an example of a substrate molding process using extrusion molding.

[0050] Hereinafter, an embodiment of the present invention will be described with reference to the accompanying drawings.

[0051] 1, the semiconductor package substrate 1 according to this embodiment is a glass ceramic plate (preferably a low-temperature fired glass ceramic plate) having a glass phase and a crystalline phase. The glass phase has the disadvantage of being easily broken, but has the advantage of reducing voids in the semiconductor package substrate 1 and contributing to denser wiring. On the other hand, the crystalline phase has the advantage of suppressing breakage of the glass phase.

[0052] The glass phase may contain, for example, in weight percent, SiO ２The glass phase preferably contains 40 to 100%, more preferably 50 to 90%, and particularly preferably 60 to 80% of the glass phase. The glass phase has the disadvantage of being easily broken, but has the advantage of being able to reduce voids in the semiconductor package substrate 1 and contribute to densifying the wiring.

[0053] The crystalline phase may be, for example, SiO 2 in weight percent. ２ The crystalline phase preferably contains 10 to 100%, more preferably 20 to 80%, and particularly preferably 30 to 60% of the crystalline phase. The crystalline phase has the advantage of suppressing breakage of the glass phase. In other words, the crystalline phase can suppress the formation and propagation of cracks around holes during laser drilling.

[0054] The crystalline phase may be a phase in which components of the glass phase have crystallized, or may be an inorganic filler that is a component different from glass. Alternatively, the crystalline phase may contain both a phase in which components of the glass phase have crystallized and an inorganic filler. Examples of inorganic fillers include silica (SiO ２ ), forsterite (2MgO.SiO ２ ), cordierite (2MgO.2Al ２ O ３ 5SiO ２ ), mullite (Al ２ O ３ 2SiO ２ ), spinel (MgO.Al ２ O ３ ), wollastonite (CaO.SiO ２ ), monticerranite (CaO.MgO.SiO ２ ), Diopside (CaO.MgO.2SiO ２ ), merwinite (3CaO.MgO.2SiO ２ ), Akerumite (2CaO.MgO.2SiO ２ ), magnesia (MgO), alumina (Al ２ O ３ ), anorthite (CaO·Al ２ O ３ 2SiO ２ ), enstatite (MgO.SiO２ ), magnesium borate (2MgO.B ２ O ３ ), B ２ O ３ ・2MgO・2SiO ２ , MgTiO ３ , (Mg,Zn)TiO ３ , TiO ２ , SrTiO ３ , MgAl ２ O ４ , ZnAl ２ O ４ , Zn ２ SiO ４ , SrAl ２ Si ２ O ８ , (Sr,Ca)Al ２ Si ２ O ８ The compound may contain at least one selected from the group consisting of:

[0055] The semiconductor package substrate 1 is rectangular, with a vertical dimension L1 and a horizontal dimension L2 of 300 mm x 300 mm or more. From the perspective of producing multiple core substrates, the substrate size (L1 x L2) of the semiconductor package substrate 1 is preferably 350 mm x 350 mm or more, more preferably 400 mm x 400 mm or more, even more preferably 450 mm x 450 mm or more, and particularly preferably 500 mm x 500 mm or more. However, if the substrate size of the semiconductor package substrate 1 is excessively large, manufacturing the substrate itself becomes difficult. Therefore, the substrate size (L1 x L2) of the semiconductor package substrate 1 is preferably 700 mm x 700 mm or less, more preferably 650 mm x 650 mm or less, even more preferably 600 mm x 600 mm or less, and particularly preferably 550 mm x 550 mm or less.

[0056] The thickness of the semiconductor package substrate 1 is preferably 0.1 to 1.4 mm. The upper limit of the thickness of the semiconductor package substrate 1 is more preferably 1.1 mm or less, 1.0 mm or less, 0.8 mm or less, 0.6 mm or less, and most preferably 0.5 mm or less. On the other hand, the lower limit of the thickness of the semiconductor package substrate 1 is more preferably 0.2 mm or more, 0.3 mm or more, and most preferably 0.4 mm or more. Such a thickness makes it easier to ensure the rigidity of the semiconductor package substrate 1, making it suitable for use as a core substrate, etc.

[0057] The flatness (TTV) of the semiconductor package substrate 1 is preferably 10 μm or less, more preferably 5 μm or less, and even more preferably 3 μm or less, throughout the entire central portion 1b excluding the peripheral edge portion 1a having a width W of 10 mm. This reduces the number of times focusing is required during photolithography to form wiring on the substrate surface 1x (or substrate back surface 1y) of the semiconductor package substrate 1. Here, as shown in FIG. 2 , the flatness (TTV) is expressed as the difference between the maximum value Max and the minimum value Min of the distance (thickness) from the substrate back surface 1y to the substrate surface 1x when the substrate back surface 1y of the semiconductor package substrate 1 is fixed by suction to a surface plate.

[0058] The waviness (Warp) of the semiconductor package substrate 1 is preferably 100 μm or less, more preferably 80 μm or less, and even more preferably 60 μm or less throughout the entire central portion 1b. This suppresses the waviness of the semiconductor package substrate 1, thereby preventing wiring breakage due to the waviness of the semiconductor package substrate 1 during mounting. As shown in FIG. 3 , the waviness (Warp) is expressed as the difference between the maximum value (Max) and minimum value (Min) of the distance between a specified reference plane B and the substrate center plane C when the semiconductor package substrate 1 is not fixed by suction. Reference plane B is determined by the least squares method, and the substrate center plane C is set so that the difference between the maximum value (Max) and the minimum value (Min) is minimized. The side where the maximum value (Max) exists is defined as the convex surface, and the side where the minimum value (Min) exists is defined as the concave surface.

[0059] In the semiconductor package substrate (glass ceramic substrate) 1, when the thermal expansion coefficient of the crystalline phase is α1 [ppm / K] and the thermal expansion coefficient of the glass phase is α2 [ppm / K], it is preferable that the relationship 2≦α1 / α2≦8 is satisfied. ２ Even when holes are drilled using a laser, compressive stress is applied to the glass phase, making it less likely that damage such as cracks will occur around the holes. α1 / α2 is preferably 2.5 to 7.5, 3.0 to 7.0, 3.5 to 6.5, 4.0 to 6.0, 4.5 to 6.0, or 5.0 to 6.0, and particularly preferably 5.5 to 6.0. Unless otherwise specified below, the thermal expansion coefficient is measured at 30 to 380°C.

[0060] The lower limit of the thermal expansion coefficient α1 of the crystalline phase is preferably 6 ppm / K or more, 6.5 ppm / K or more, 7 ppm / K or more, and particularly preferably 10 ppm / K or more. This makes it easier to increase the thermal expansion coefficient of the semiconductor package substrate 1 obtained by sintering. In addition, the difference in thermal expansion coefficient with the glass phase becomes larger, making it more unlikely that damage such as cracks will occur around the holes.

[0061] The upper limit of the thermal expansion coefficient α1 of the crystalline phase is preferably 20 ppm / K or less, 18 ppm / K or less, 16 ppm / K or less, and particularly preferably 15 ppm / K or less. In this way, it becomes easier to reduce the thermal expansion coefficient of the semiconductor package substrate 1 obtained by sintering.

[0062] The lower limit of the thermal expansion coefficient α2 of the glass phase is preferably 0.6 ppm / K or more, 0.7 ppm / K or more, 0.9 ppm / K or more, 1.1 ppm / K or more, 1.3 ppm / K or more, 1.5 ppm / K or more, 1.7 ppm / K or more, 1.9 ppm / K or more, and particularly preferably 2.1 ppm / K or more. This makes it easier to increase the thermal expansion coefficient of the semiconductor package substrate 1 obtained by sintering.

[0063] The upper limit of the thermal expansion coefficient α2 of the glass phase is preferably 5 ppm / K or less, 4.5 ppm / K or less, 4.0 ppm / K or less, 3.5 ppm / K or less, 3.0 ppm / K or less, or 2.7 ppm / K or less, and particularly preferably 2.5 ppm / K or less. This makes it easier to reduce the thermal expansion coefficient of the semiconductor package substrate 1 obtained by sintering. In addition, the difference in thermal expansion coefficient with the crystalline phase becomes larger, making it less likely that damage such as cracks will occur around the holes.

[0064] Here, the thermal expansion coefficient α1 of the crystalline phase is determined as follows. First, the crystalline phase contained in the semiconductor package substrate 1 is identified using an X-ray diffractometer (XRD). Next, the thermal expansion coefficient of the crystalline phase identified by XRD is identified using literature values ​​(for example, values ​​described in Patent Document 2 or Non-Patent Document 1), and the identified value is defined as the thermal expansion coefficient α1. Note that when the semiconductor package substrate 1 contains multiple types of crystalline phases, the thermal expansion coefficient of the crystal having the highest thermal expansion coefficient is defined as α1.

[0065] The thermal expansion coefficient α2 of the glass phase is determined as follows. First, the glass phase contained in the semiconductor package substrate 1 is confirmed using a transmission electron microscope (TEM). Next, the composition of the glass phase is identified using energy dispersive X-ray spectroscopy (TEM-EDX) attached to the TEM. Then, the thermal expansion coefficient α2 of the glass phase is determined based on the identified composition of the glass phase. Specifically, for example, glass having the same composition as the identified glass phase is actually produced, and its thermal expansion coefficient is measured using a thermal expansion measurement device (TMA method), and the measured value is defined as the thermal expansion coefficient α2. Note that the thermal expansion coefficient α2 may be estimated from the composition of the identified glass phase. However, from the perspective of obtaining a highly accurate thermal expansion coefficient α2, it is preferable to produce glass having the same composition as the identified composition and measure the thermal expansion coefficient.

[0066] The thermal expansion coefficient α2 of the glass phase can also be determined as follows. First, the crystalline phase composition and crystallinity of the semiconductor package substrate 1 are determined by XRD. Next, the semiconductor package substrate 1 is melted and solidified to obtain a solid. From the obtained solidified material, the overall composition of the semiconductor package substrate 1 is determined by a method such as fluorescent X-ray analysis. Then, the composition of the glass phase is identified (calculated) from the overall composition, crystalline phase composition, and crystallinity. Then, the thermal expansion coefficient α2 of the glass phase is determined based on the identified glass phase composition. Specific methods for determining the thermal expansion coefficient α2 from the identified glass phase composition include a method of actually measuring the thermal expansion coefficient of glass having the same composition as the identified glass phase composition, and a method of estimating the thermal expansion coefficient from the identified glass phase composition.

[0067] The composition of the glass phase having a thermal expansion coefficient α2 is, in weight percent, SiO ２ 50-80%, B ２ O ３ 15-30%, Li ２ O + Na ２ O+K ２ It is preferable that the content of O is 0.1 to 2% by weight. ２ O / (Li ２ O + Na ２ O+K ２ O) 0.10-0.50, Na ２ O / (Li ２ O + Na ２ O+K ２ O) 0.25-0.65, K ２ O / (Li ２ O + Na ２ O+K ２ O) is preferably 0.05 to 0.35. ２ O + Na ２ O+K ２ "O" is Li ２ O, Na ２ O and K ２ The total amount of Li and O. ２ O / (Li ２ O + Na ２ O+K ２ O) is Li ２ The content of O is Li２ O, Na ２ O and K ２ The value is divided by the total amount of Na ２ O / (Li ２ O + Na ２ O+K ２ O) is Na ２ The content of O is Li ２ O, Na ２ O and K ２ The value is divided by the total amount of O. ２ O / (Li ２ O + Na ２ O+K ２ O) is K ２ The content of O is Li ２ O, Na ２ O and K ２ This is the value divided by the total amount of O.

[0068] The crystalline phase having the thermal expansion coefficient α1 may be a phase in which a component of the glass phase is crystallized, or may be an inorganic filler that is a component different from glass. Alternatively, the crystalline phase may include both a phase in which a component of the glass phase is crystallized and an inorganic filler.

[0069] Examples of inorganic fillers include quartz (α-SiO ２ ), alumina (Al ２ O ３ ), diopside (MgCaSi ２ O ６ ), anorthite (CaAl ２ Si ２ O ８ ), cordierite (Mg ２ Al ４ Si ５ O １８ ), forsterite (Mg ２ SiO ４ The thermal expansion coefficients α1 (literature values) of these inorganic fillers are shown in Table 1.

[0070]

[0071] In the semiconductor package substrate 1, the content of the crystalline phase having the thermal expansion coefficient α1 is preferably 2 to 50 wt %, and the content of the glass phase having the thermal expansion coefficient α2 is preferably 50 to 98 wt %.

[0072] The upper limit of the content of the crystalline phase having a thermal expansion coefficient α1 is more preferably 45 wt % or less, 40 wt % or less, 35 wt % or less, and most preferably 30 wt % or less. In this way, the content of the glass phase becomes higher than the content of the crystalline phase. The glass phase is easier to process with a laser than the crystalline phase, and if the content of the glass phase is relatively high, holes can be formed without cracks even when laser processing is performed with relatively weak energy output.

[0073] The lower limit of the content of the glass phase having a thermal expansion coefficient α2 is more preferably 55 wt % or more, 60 wt % or more, 65 wt % or more, and most preferably 70 wt % or more. In this way, the content of the glass phase becomes higher than the content of the crystalline phase. The glass phase is easier to process with a laser than the crystalline phase, and if the content of the glass phase is relatively high, holes can be formed without cracks even when laser processing is performed with relatively weak energy output.

[0074] Here, the content of the crystalline phase and glass phase having thermal expansion coefficients α1 and α2 can be determined by peak separation of the diffraction line profile from 10 to 60° at 2θ values ​​obtained by powder X-ray diffraction measurement using CuKα radiation into crystalline diffraction lines and amorphous halos. Specifically, from the total scattering curve obtained by subtracting the background from the diffraction line profile, the integrated intensity obtained by peak separation of the broad diffraction line (amorphous halo) from 10 to 45° is Ia, and the sum of the integrated intensities obtained by peak separation of each crystalline diffraction line detected from 10 to 60° is Ic. The weight % Xc of the crystalline phase and the weight % Xa of the glass phase (amorphous phase) can be calculated from the following formulas: Xc = [Ic / (Ic + Ia)] × 100(%) Xa = 100 - Xc(%)

[0075] The crystal grain size of the inorganic filler in the semiconductor package substrate 1 is preferably 10 μm or less, 8 μm or less, and particularly preferably 5 μm or less. The crystal grain size of the inorganic filler in the sintered body is preferably 0.01 μm or more, and particularly preferably 0.1 μm or more.

[0076] The crystal grain size can be measured, for example, as follows. First, a fractured cross section of a sample of a glass ceramic substrate (sintered body) is formed. Next, the sample is heat-treated. This heat treatment is preferably performed by thermal etching in an electric furnace. The heat treatment temperature can be, for example, 900°C or higher and 1600°C or lower. The heat treatment time can be, for example, 1 minute or higher and 60 minutes or lower. Next, the cross section of the heat-treated sample is observed using a scanning electron microscope (SEM). For example, any 200 particles in the obtained SEM image are counted for each particle using image analysis software, and the average particle size is determined. This allows the crystal grain size to be determined. In image analysis, the diameter of the crystal grain is defined as the equivalent circle diameter of the area of ​​the crystal grain.

[0077] The lower limit of the thermal expansion coefficient α3 of the entire semiconductor package substrate 1 is preferably 2.5 ppm / K or more, 3.0 ppm / K or more, 3.5 ppm / K or more, and particularly preferably 4 ppm / K or more. The upper limit of the thermal expansion coefficient α3 of the entire semiconductor package substrate 1 is preferably 15 ppm / K or less, 13 ppm / K or less, 11 ppm / K or less, 9 ppm / K or less, 7 ppm / K or less, and particularly preferably 6 ppm / K or less. In this way, thermal expansion of the semiconductor package substrate 1 during laser drilling is suppressed, making it less likely that damage such as cracks will occur around the holes. The thermal expansion coefficient α3 can be measured, for example, using a thermal expansion measurement device (TMA method).

[0078] Fracture toughness K of semiconductor package substrate 1 ＩＣ is 1.0 to 2.5 MPa m １／２ In this way, it is possible to prevent damage from progressing from microcracks formed around the holes during the hole drilling process using a laser. ＩＣ The lower limit is 1.1 MPa m １／２More preferably, it is 1.2 MPa m or more. １／２ It is more preferable that the fracture toughness K is equal to or greater than this. ＩＣ The upper limit is 2.4 MPa m １／２ More preferably, it is 2.3 MPa m or less. １／２ It is more preferable that K is: ＩＣ can be measured by the Indentation Fracture method (IF method) in accordance with JIS R1607. ＩＣ For example, it can be measured using the SEPB method or calculated based on the Miller constant.

[0079] The Young's modulus of the semiconductor package substrate 1 is preferably 40 to 90 GPa. This makes it easier to ensure the rigidity of the semiconductor package substrate 1 and also makes it less likely for scratches to develop from microcracks formed around the holes during laser drilling. The lower limit of the Young's modulus is preferably 40 GPa or more, more preferably 45 GPa or more, and even more preferably 50 GPa or more. The upper limit of the Young's modulus is preferably 90 GPa or less, more preferably 85 GPa or less, and even more preferably 80 GPa. Here, the Young's modulus was measured using a free resonance type elastic modulus measuring device (JE-RT3 manufactured by Nippon Technoplus Co., Ltd.). The measurement was performed at room temperature (25°C).

[0080] If the Young's modulus is too high, rigidity increases but the effect of dispersing force against impact decreases, making the semiconductor package substrate 1 more susceptible to damage. Therefore, if an impact is applied during the manufacturing process of the semiconductor package substrate 1, the semiconductor package substrate 1 may be damaged. On the other hand, if the Young's modulus is too low, the semiconductor package substrate 1 may bend when moved during the manufacturing process of the semiconductor package substrate 1, and may come into contact with peripheral devices such as moving devices. Therefore, from the perspective of preventing such problems, it is preferable that the Young's modulus of the semiconductor package substrate 1 be within the above numerical range.

[0081] The dielectric constant of the semiconductor package substrate 1 is preferably 1 to 20, 2 to 16, 3 to 12, 4 to 9, or 4 to 7, and particularly preferably 4 to 6. The dielectric dissipation factor of the semiconductor package substrate 1 is preferably 0.0001 to 0.007, 0.001 to 0.006, and particularly preferably 0.0015 to 0.005. This reduces transmission signal loss and signal processing speed degradation, even when the semiconductor package is used as a high-frequency circuit component. The dielectric constant and dielectric dissipation factor refer to values ​​measured at a temperature of 25°C and a frequency of 16 GHz, based on the method for measuring microwave dielectric properties of fine ceramic substrates (JIS R1627).

[0082] As shown in Fig. 4, a hole formation region in which a plurality of holes H are densely formed may be formed in the central portion 1b of the semiconductor package substrate 1. The hole formation region may be, for example, a rectangular region in a plan view, and a plurality of hole formation regions may be formed in the central portion 1b of the semiconductor package substrate 1. When a plurality of hole formation regions are formed, a strip-shaped region without holes H is formed between adjacent hole formation regions. The holes H are used, for example, as vias for electrically connecting wirings. The holes H are holes that penetrate the semiconductor package substrate 1 in the thickness direction, and are formed by, for example, laser irradiation using a carbon dioxide laser (CO ２ It is formed by irradiating it with a laser.

[0083] The upper limit of the diameter D of the hole H is preferably 100 μm or less, 90 μm or less, 80 μm or less, or 75 μm or less, particularly preferably 60 μm or less. The lower limit of the diameter D of the hole H is not particularly limited, but is 10 μm or more.

[0084] It is preferable that 1 to 30,000 holes H are provided per 10 mm square in the hole formation region. The upper limit of the number of holes H per 10 mm square in the hole formation region is more preferably 20,000 or less, 15,000 or less, 10,000 or less, 4,000 or less, 3,600 or less, 3,200 or less, 2,800 or less, 2,500 or less, and particularly preferably 1,600 or less. Furthermore, the lower limit of the number of holes H per 10 mm square in the hole formation region is more preferably 2 or more, 10 or more, 50 or more, 100 or more, 500 or more, and particularly preferably 1,000 or more.

[0085] The width W of the peripheral portion 1a of the semiconductor package substrate 1 is preferably 10 mm or less, more preferably 5 mm or less, and even more preferably 3 mm or less. By reducing the width W of the peripheral portion 1a, the area of ​​the central portion 1b from which a core substrate or the like can be extracted can be increased.

[0086] 5, the semiconductor package 11 according to this embodiment includes a core substrate 12, a semiconductor element 13, and an interposer 14 disposed between the core substrate 12 and the semiconductor element 13. Although not shown, the core substrate 12 and the interposer 14 are formed with wiring and holes (via holes) that electrically connect the wirings.

[0087] The core substrate 12 is a single-layer substrate taken from the central portion 1b of the semiconductor package substrate 1. In other words, in this embodiment, a plurality of core substrates 12 are taken from the central portion 1b of the semiconductor package substrate 1.

[0088] Although not shown in the drawings, it is preferable that an interlayer insulating material is laminated on the core substrate 12. A rewiring layer is formed by forming metal wiring on the interlayer insulating material and laminating it in multiple layers, which makes it possible to design finer circuits in the semiconductor package substrate.

[0089] Examples of interlayer insulating materials include organic materials containing resin and inorganic materials containing glass. The difference between the thermal expansion coefficient of the interlayer insulating material and that of the core substrate 12 is preferably within 5.0 ppm / K. This configuration makes it less likely for warping to occur due to the difference in thermal expansion when heat is applied during the manufacturing process of the semiconductor package.

[0090] The interposer 14 is a relay substrate for electrically connecting the core substrate 12 and the semiconductor element 13. The semiconductor package 11 does not necessarily have to include the interposer 14. In other words, the semiconductor package 11 may have a configuration in which the semiconductor element 13 is directly disposed on the core substrate 12.

[0091] <Method for manufacturing substrate for semiconductor package> As shown in FIG. 6, the method for manufacturing the substrate 1 for semiconductor package according to this embodiment includes a substrate forming step S1, a firing step S2, an annealing step S3, an edge removing step S4, and a polishing step S5, in this order.

[0092] In the substrate forming step S1, first, a slurry, which is a liquid mixed raw material, is prepared by mixing glass powder, a binder (e.g., acrylic), a solvent, etc., which will form the glass phase (or glass phase and crystalline phase) of the semiconductor package substrate 1. Next, the slurry is molded into a plate to obtain a molded body. If the crystalline phase of the semiconductor package substrate 1 contains an inorganic filler, the slurry further contains inorganic filler powder. Examples of molding methods that can be used to mold the slurry into a plate-shaped molded body include slip casting, extrusion molding, pressure molding, and injection molding.

[0093] The conventional method of laminating and sintering green sheets is not suitable because the green sheets themselves contain a large amount of binder, and the additional layering of substrates reduces flatness and tends to cause waviness. Molding using slip casting, extrusion, pressure molding, injection molding, etc. is preferable because it reduces the binder content and allows the formation of a plate of a specified thickness without layering substrates, making it less likely to cause flatness to deteriorate and waviness to occur.

[0094] 7 and 8, for example, in the substrate molding step S1 using slip casting, a plaster mold 21 is used. The plaster mold 21 includes a plate-shaped lower mold 22 and a rectangular frame-shaped upper mold 23 placed on an upper surface 22a of the lower mold 22.

[0095] The flatness and waviness of the upper surface 22a of the lower mold 22 are controlled. In this embodiment, the flatness of the upper surface 22a of the lower mold 22 is 10 μm or less, and the waviness is 100 μm or less.

[0096] The upper die 23 is composed of a plurality of (four in the illustrated example) split dies 23a to facilitate removal of the molded body 26, which will be described later. The size within the frame of the upper die 23 is the substrate size of the semiconductor package substrate 1. In other words, the size within the frame of the upper die 23 is set to 300 mm x 300 mm or more.

[0097] In the substrate molding process S1 using slip casting, first, a slurry 24 is poured into the frame of an upper mold 23 placed on a lower mold 22. The slurry 24 is a liquid mixture of glass ceramic powder, a binder (e.g., acrylic), and water. Next, air bubbles in the slurry 24 poured into the frame of the upper mold 23 are crushed with a spoon or the like. The slurry 24 is then left in this state for a predetermined time (e.g., 2 to 4 hours). During this time, the plaster mold 21 absorbs water from the slurry 24 and dries it, thereby forming a rectangular sheet-shaped molded body 26 from the slurry 24. Once the molded body 26 is formed, the upper mold 23 is removed. The molded body 26 is then slid from the lower mold 22 onto a setter (not shown). The molded body 26 is then dried on the setter at room temperature for a predetermined time (e.g., 12 hours or more). The moisture content of the molded body 26 is, for example, 2 to 5%.

[0098] 9, for example, in the substrate molding step S1 using extrusion molding, a manufacturing apparatus 31 is used. The manufacturing apparatus 31 includes an extruder 32 and a dryer 33.

[0099] The extruder 32 is a multi-stage extruder (in the illustrated example, an upper / lower two-stage extruder) that includes a hopper 37 into which the mixed raw material 36 is introduced, an upper mixing / kneading zone 38 into which the mixed raw material 36 is introduced via the hopper 37, a lower compression / extrusion zone 39 into which the mixed raw material 36 is introduced after passing through the mixing / kneading zone 38, and a forming section (die) 40 located at the downstream end of the compression / extrusion zone 39.

[0100] In this embodiment, a clay-like mixed raw material 36 containing glass ceramic powder, a binder (for example, cellulose), and water is charged into the hopper 37 .

[0101] The mixing and kneading zone 38 includes a casing 38a that defines the zone 38, and a screw 38b that is disposed within the casing 38a and that mixes and kneads the mixed raw material 36. The mixed raw material 36 is preferably vacuum degassed between the outlet of the mixing and kneading zone 38 and the inlet of the compression extrusion zone 39. In this case, the mixed raw material 36 is preferably formed into a plurality of string-like intermediate formed bodies at the outlet of the mixing and kneading zone 38 so that the vacuum degassing is facilitated.

[0102] The compression extrusion zone 39 includes a casing 39a that defines the zone 39, and a screw 39b that is disposed in the casing 39a and that compresses and extrudes the mixed raw material 36. The casing 39a and the screw 39b are cooled with cooling water (for example, 5 to 20°C) to prevent the mixed raw material 36 from gelling.

[0103] The molding unit 40 has a slit 40a for molding the mixed raw material 36 into a sheet-like molded body 41. The width of the slit 40a in the direction perpendicular to the paper surface is the width of the semiconductor package substrate 1. In other words, the width of the slit 40a in the direction perpendicular to the paper surface is set to 300 mm or more.

[0104] Although not shown, a regulating member (baffle member) is disposed inside the forming unit 40 to regulate the flow path in a portion where the thickness of the formed body 41 increases (a portion where the supply of the mixed raw material 36 becomes excessive) so that the thickness of the formed body 41 formed in the slit 40a is constant. For example, the regulating member is disposed at the center in the width direction (direction perpendicular to the paper surface) inside the forming unit 40, and at the position where the regulating member is disposed, the flow path area at both ends in the width direction (direction perpendicular to the paper surface) of the flow path is large and the flow path area at the center in the width direction (direction perpendicular to the paper surface) of the flow path is small.

[0105] The dryer 33 is a continuous drying furnace. In the dryer 33, hot air X (for example, 40 to 70°C) is blown from below onto the compact 41, which is conveyed by a plurality of conveying rollers 42, to dry the compact 41. In this embodiment, a flexure (concave curved portion) 41a is provided in the compact 41 between the molding section 40 and the conveying rollers 42. This flexure 41a of the compact 41 prevents the tension acting on the compact 41 by the conveying rollers 42 from affecting the discharge speed of the compact 41 as it is discharged from the slit 40a of the molding section 40. Alternatively, a belt-like conveying path may be used and the compact 41 may be dried from above with a heater.

[0106] After drying, the molded body 41 is cut to a predetermined length of 300 mm or more. The moisture content of the dried molded body 41 is set to, for example, 1 to 3%. After drying, the molded body 41 may be wound up by a winder.

[0107] In the substrate forming process S1 using extrusion molding, first, a sheet-like molded body 41 is continuously formed from the mixed raw material 36 by an extruder 32. Next, the sheet-like molded body 41 is dried in a dryer 33 while being conveyed. The dried sheet-like molded body 41 is cut to a predetermined length of 300 mm or more.

[0108] In the firing step S2, the rectangular molded body obtained in the substrate molding step S1 is fired to densify the molded body. The firing temperature is, for example, 700 to 1000° C., and the firing time is, for example, 2 to 15 hours.

[0109] In the annealing step S3, the compact fired in the firing step S2 is heat-treated to reduce waviness. The annealing temperature is, for example, 500 to 700°C, and the annealing time is, for example, 10 minutes to 15 hours, or 1 to 15 hours. The annealing step S3 may be performed immediately after the firing step S2. The annealing may also be performed under load.

[0110] In the edge removing step S4, the edges of the molded body are removed. In this embodiment, the edges of all four sides of the molded body are removed. Examples of edge removing methods include cutting, grinding, and cutting.

[0111] In the polishing step S5, at least one of the front and back surfaces of the molded body is polished to reduce waviness, thereby producing a semiconductor package substrate 1 from the molded body.

[0112] At least one of the annealing step S3, the edge removing step S4, and the polishing step S5 may be omitted as appropriate.

[0113] In addition, in the manufacturing method of the semiconductor package substrate 1, if necessary, a CO ２ The method may further include a hole-punching step of irradiating a laser to form a plurality of holes. In this case, the method for manufacturing the semiconductor package substrate 1 may further include a cutting step of extracting a plurality of substrates (e.g., core substrates) of a size to be mounted in the semiconductor package 11 from the central portion 1b of the semiconductor package substrate 1 after the hole-punching step.

[0114] The present invention is not limited to the configuration of the above-described embodiment, nor is it limited to the above-described effects. The present invention can be modified in various ways without departing from the spirit of the present invention.

[0115] In the above embodiment, the semiconductor package substrate 1 is described as being rectangular with a substrate size of 300 mm x 300 mm or more, but is not limited thereto. For example, the semiconductor package substrate 1 may be circular with a diameter of 300 mm or more.

[0116] In the above embodiment, the semiconductor package substrate 1 is used as the core substrate 12, but the present invention is not limited to this. For example, the semiconductor package substrate 1 may be used as an interposer 14, a substrate for an image sensor, or the like.

[0117] It goes without saying that glass ceramics include two types: one consisting of a glass phase and a crystalline phase containing an inorganic filler, and the other consisting of a glass phase and a crystalline phase precipitated from the glass phase without containing an inorganic filler.

[0118] The present invention also includes the following inventions.

[0119] (1) A glass-ceramic substrate for semiconductor packaging having a crystalline phase and a glass phase, characterized in that, when the thermal expansion coefficient of the crystalline phase is α1 [ppm / K] and the thermal expansion coefficient of the glass phase is α2 [ppm / K], the relationship 2≦α1 / α2≦8 holds.

[0120] (2) In the above-mentioned (1), it is preferable that the content of the crystalline phase is 2 to 50% by weight, and the content of the glass phase is 50 to 98% by weight.

[0121] (3) In the above configuration (1) or (2), the glass ceramic substrate for semiconductor packaging preferably has a thermal expansion coefficient α1 of the crystalline phase of 6 to 20 ppm / K and a thermal expansion coefficient α2 of the glass phase of 0.6 to 5 ppm / K.

[0122] (4) In any of the above (1) to (3), the thermal expansion coefficient of the entire glass ceramic substrate for semiconductor packaging is preferably 2.5 to 15 ppm / K.

[0123] (5) In any of the configurations (1) to (4) above, it is preferable that the hole formation region has a plurality of holes having a diameter of 100 μm or less densely arranged, the number of holes is 1 to 4,000 per 10 mm square in the hole formation region, and the thickness is 0.1 to 1.0 mm.

[0124] (6) In any of the above configurations (1) to (5), the glass ceramic substrate for semiconductor packages is preferably for use in an interposer.

[0125] (7) In any of the above (1) to (5), the glass ceramic substrate for semiconductor packages is preferably for use as a core substrate.

[0126] (8) In any of the above (1) to (5), the glass ceramic substrate for semiconductor packages is preferably used as a substrate for an image sensor.

[0127] (9) In any one of the above (1) to (8), the glass ceramic substrate for semiconductor packaging has a fracture toughness K ＩＣ is 1.0 to 2.5 MPa m １／２ It is preferable that:

[0128] (10) In any of the above (1) to (9), the glass ceramic substrate for semiconductor packages preferably has a Young's modulus of 40 to 90 GPa.

[0129] (11) In any of the above (1) to (10), the glass ceramic substrate for semiconductor packages preferably has a layer containing an interlayer insulating material on the substrate.

[0130] (12) The present invention, which has been invented to solve the above-mentioned problems, is a method for manufacturing a glass-ceramic substrate for a semiconductor package, the method comprising the steps of: preparing a glass-ceramic substrate having a crystalline phase and a glass phase, wherein the relationship 2≦α1 / α2≦8 holds when the thermal expansion coefficient of the crystalline phase is α1 [ppm / K] and the thermal expansion coefficient of the glass phase is α2 [ppm / K]; ２ and a hole-making process for forming holes by irradiating a laser.

[0131] The present invention will be described in detail below based on examples, but the present invention is not limited to these examples.

[0132] The following Samples No. 1 and No. 2 were prepared as semiconductor package substrates according to the examples. The following Sample No. 3 was prepared as a semiconductor package substrate according to the comparative example.

[0133] The semiconductor package substrate according to Sample No. 1 (Example) was a rectangular substrate having a size of 300 mm x 300 mm and a thickness of 0.4 mm, and was made of a low-temperature fired glass ceramic plate having a glass phase and a crystalline phase.

[0134] The semiconductor package substrate according to Sample No. 2 (Example) was a rectangular substrate having a size of 500 mm x 500 mm and a thickness of 0.4 mm, and was made of a low-temperature fired glass ceramic plate having a glass phase and a crystalline phase.

[0135] The semiconductor package substrate according to Sample No. 3 (Comparative Example) was rectangular, measuring 300 mm×300 mm and 0.4 mm thick, and was made of an amorphous glass plate having no crystalline phase.

[0136] For each of the semiconductor package substrates according to Sample No. 1, Sample No. 2, and Sample No. 3, CO ２ Using a laser, 4,356 holes with a diameter of 75 μm or less were drilled per 10 mm square. A total of approximately 17,000 holes were drilled per substrate for Sample No. 1 and Sample No. 3. A total of approximately 40,000 holes were drilled per substrate for Sample No. 2.

[0137] As a result, in the semiconductor package substrates (low-temperature fired glass ceramic plates) of Samples No. 1 and No. 2, which are examples, the percentage of holes containing cracks was reduced to 0%. On the other hand, in the semiconductor package substrate (glass plate) of Sample No. 3, which is a comparative example, the percentage of holes containing cracks was greater than 2%. This also shows that the semiconductor package substrates (low-temperature fired glass ceramic plates) of Samples No. 1 and No. 2, which are examples, are less likely to be damaged by laser drilling, even when the substrate size is increased, compared to the semiconductor package substrate (glass plate) of Sample No. 3, which is a comparative example.

[0138] Here, the substrate for a semiconductor package according to Example Sample No. 1 had a flatness of 5 μm and a waviness of 80 μm over the entire central portion excluding the 10 mm-wide peripheral portion. The substrate for a semiconductor package according to Example Sample No. 2 had a flatness of 8 μm and a waviness of 100 μm over the entire central portion excluding the 10 mm-wide peripheral portion.

[0139] Table 2 shows the composition of the glass raw materials, fillers, and their physical properties used to prepare semiconductor package substrates made of glass ceramic plates. The thermal expansion coefficients of the glass raw materials and fillers were measured by the TMA method for their respective bulks. Samples Nos. 4 to 11 are examples. Samples Nos. 4 to 8 are more preferable examples than Samples Nos. 9 to 11.

[0140]

[0141] Table 3 shows the physical properties, firing conditions, and laser processability of the glass ceramic substrate for semiconductor packaging after firing.

[0142] The mass of the glass phase and the mass of the crystalline phase in the fired glass-ceramic substrate for semiconductor packaging were determined by a method in which a diffraction line profile between 10 and 60° in 2θ value obtained by powder X-ray diffraction measurement using CuKα radiation was separated into peaks of crystalline diffraction lines and amorphous halos.

[0143] The thermal expansion coefficient α1 of the crystalline phase was determined as follows: First, the crystalline phase in the glass ceramic substrate for semiconductor packaging was identified by XRD, and the literature value of the thermal expansion coefficient of the identified crystalline phase was taken as the thermal expansion coefficient α1.

[0144] The thermal expansion coefficient α2 of the glass phase was determined as follows. First, the crystalline phase composition and crystallinity of the glass-ceramic substrate for semiconductor packaging were determined by XRD. Next, the glass-ceramic substrate for semiconductor packaging was melted and solidified, and the overall composition of the glass-ceramic substrate for semiconductor packaging was determined from the solidified product by X-ray fluorescence analysis. Then, the composition of the glass phase was determined (calculated) from the overall composition, crystalline phase composition, and crystallinity. Then, glass was prepared so as to have the determined glass phase composition, and the thermal expansion coefficient of the obtained glass was measured by TMA, and the value was defined as the thermal expansion coefficient α2.

[0145] The thermal expansion coefficient α3 was determined by measuring the thermal expansion coefficient of the fired glass ceramic substrate for semiconductor packaging by the TMA method.

[0146] The relative permittivity and dielectric loss tangent were values ​​measured at a measurement temperature of 25° C. and a frequency of 16 GHz based on the method for measuring microwave dielectric properties of fine ceramic substrates (JIS R1627).

[0147] The laser processability was evaluated as follows. First, fired glass-ceramic substrates for semiconductor packages corresponding to each example and each comparative example were prepared. Each glass-ceramic substrate for semiconductor packages was rectangular, measuring 300 mm x 300 mm and 0.4 mm thick. Next, CO ２ A hole having a diameter of 100 μm was formed in the center of each glass-ceramic substrate for semiconductor packages using a laser under the following conditions: wavelength 9.4 μm, pulse width 2 μs, power density 7 MW / cm２ In this case, the sample in which crack-free hole formation was possible was evaluated as "Good", and the sample in which cracks occurred was evaluated as "Poor". Note that by increasing the hole diameter to 100 μm, conditions were set in which cracks were likely to occur.

[0148]

[0149] Table 4 shows the results of changing the number of holes provided in a 10 mm x 10 mm area with a hole diameter of 75 μm in Sample No. 5 of Table 3. ２ A laser was used, with a wavelength of 9.4 μm, a pulse width of 2 μs, and a power density of 7 MW / cm ２ Holes were formed under the following conditions. Examples 5-1 to 5-7 show that crack-free hole formation is possible when the hole diameter is 100 μm or less and the number of holes per 10 mm square is 4,000 or less. In contrast, in Example 5-8, where the hole diameter is 100 μm or less but the number of holes is 4,356, cracks occurred in 2% of the holes.

[0150]

[0151] REFERENCE SIGNS LIST 1 Semiconductor package substrate 11 Semiconductor package 12 Core substrate 13 Semiconductor element 14 Interposer 21 Plaster mold 22 Lower mold 23 Upper mold 24 Slurry 26 Molded body 31 Manufacturing apparatus 32 Extruder 33 Dryer 36 Mixed raw material 37 Hopper 38 Mixing and kneading zone 39 Compression extrusion zone 40 Molding section 41 Molded body H Hole S1 Substrate molding process S2 Firing process S3 Annealing process S4 Edge removal process S5 Polishing process

Claims

1. A substrate for semiconductor packaging, characterized by having a glass phase and a crystalline phase, and having a rectangular substrate size of 300 mm x 300 mm or more, or a circular substrate with a diameter of 300 mm or more.

2. The substrate for semiconductor package according to claim 1, wherein the flatness is 10 μm or less over the entire central portion excluding the peripheral portion having a width of 10 mm.

3. The substrate for semiconductor package according to claim 1 or 2, wherein the waviness is 100 μm or less over the entire central portion excluding the 10 mm wide peripheral portion.

4. The substrate for semiconductor package according to claim 1 or 2, which is used as a core substrate.

5. The substrate for semiconductor package according to claim 1 or 2, which is a sintered body.

6. A substrate for semiconductor packaging according to claim 1 or 2, which has a hole formation region in which a plurality of holes having a diameter of 100 μm or less are densely arranged, and the holes are arranged in a number of 2 to 30,000 per 10 mm square within the hole formation region.

7. The substrate for semiconductor package according to claim 1 or 2, which has a thickness of 0.3 mm to 1.4 mm.

8. The substrate for semiconductor package according to claim 1 or 2, which has a Young's modulus of 40 GPa to 90 GPa.

9. A substrate for semiconductor packaging according to claim 1, which is made of a glass ceramic substrate, and where the thermal expansion coefficient of the crystalline phase is α1 [ppm / K] and the thermal expansion coefficient of the glass phase is α2 [ppm / K], the relationship 2≦α1 / α2≦8 holds.

10. The substrate for semiconductor packaging according to claim 9, wherein the content of said crystalline phase is 2 to 50% by weight, and the content of said glass phase is 50 to 98% by weight.

11. The substrate for semiconductor packaging according to claim 10, wherein the thermal expansion coefficient α1 of the crystalline phase is 6 to 20 ppm / K, and the thermal expansion coefficient α2 of the glass phase is 0.6 to 5 ppm / K.

12. The substrate for semiconductor package according to any one of claims 9 to 11, wherein the thermal expansion coefficient of the entire substrate for semiconductor package is 2.5 to 15 ppm / K.

13. A substrate for semiconductor packaging according to any one of claims 9 to 11, having a hole formation region in which a plurality of holes having a diameter of 100 μm or less are densely arranged, with 1 to 4,000 of said holes arranged per 10 mm square within said hole formation region, and having a thickness of 0.1 to 1.0 mm.

14. The substrate for a semiconductor package according to any one of claims 9 to 11, which is used for an interposer.

15. The substrate for semiconductor package according to any one of claims 9 to 11, which is used as a core substrate.

16. The substrate for a semiconductor package according to any one of claims 9 to 11, which is used as a substrate for an image sensor.

17. Fracture toughness K ＩＣ However, 1.0 to 2.5 MPa m １／２ The substrate for semiconductor package according to any one of claims 9 to 11, wherein 18. The substrate for semiconductor package according to any one of claims 9 to 11, which has a Young's modulus of 40 to 90 GPa.

19. The substrate for a semiconductor package according to any one of claims 9 to 11, further comprising a layer containing an interlayer insulating material on the substrate.

20. A low-temperature fired glass ceramic plate characterized by having a flatness of 10 μm or less over the entire central portion excluding a 10 mm wide peripheral portion, and from which multiple core substrates are obtained.

21. A low-temperature fired glass ceramic plate characterized in that the waviness is 100 μm or less throughout the entire central portion excluding the 10 mm wide peripheral portion, and from which multiple core substrates are obtained.

22. A preparation step of preparing a semiconductor package substrate according to any one of claims 9 to 11, and applying CO ２ and a hole-making process step of irradiating a laser to form holes.

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