Hybrid processing elements in memory

Abstract

A memory system can be implemented with a hybrid device that includes a digital core and an analog core. The digital core can receive a first plurality of bits from the array and can perform a first MAC operation using the first plurality of bits. The analog core can receive a second plurality of bits from the array and can perform a second MAC operation using the second plurality of bits. The memory system can also include shift accumulate circuitry coupled to the digital core and the analog core. The shift accumulate circuitry can perform a summation operation using a first result of the first MAC operation and a second result of the second MAC operation.

Description

10023840012 HYBRID PROCESSING ELEMENTS IN MEMORY Technical Field

[0001] The present disclosure relates generally to memory, and more particularly to apparatuses and methods associated with implementing hybrid processing elements in memory. Background

[0002] Memory devices are typically provided as internal, semiconductor, integrated circuits in computers or other electronic devices. There are many different types of memory including volatile and non-volatile memory. Volatile memory can require power to maintain its data and includes random-access memory (RAM), dynamic random access memory (DRAM), and synchronous dynamic random access memory (SDRAM), among others. Non- volatile memory can provide persistent data by retaining stored data when not powered and can include NAND flash memory, NOR flash memory, read only memory (ROM), Electrically Erasable Programmable ROM (EEPROM), Erasable Programmable ROM (EPROM), and resistance variable memory such as phase change random access memory (PCRAM), resistive random access memory (RRAM), and magnetoresistive random access memory (MRAM), among others.

[0003] Memory is also utilized as volatile and non-volatile data storage for a wide range of electronic applications. Non-volatile memory may be used in, for example, personal computers, portable memory sticks, digital cameras, cellular telephones, portable music players such as MP3 players, movie players, and other electronic devices. Memory cells can be arranged into arrays, with the arrays being used in memory devices. Brief Description of the Drawings

[0004] FIG.1 is a block diagram of an apparatus in the form of a computing system including a memory system in accordance with a number of embodiments of the present disclosure.

[0005] FIG.2 illustrates an example of a hybrid memory device in accordance with some embodiments of the present disclosure.10023840012

[0006] FIG.3A illustrates an example of a monitor in accordance with some embodiments of the present disclosure.

[0007] FIG.3B illustrates an example of most significant bits in accordance with some embodiments of the present disclosure.

[0008] FIG.4 illustrates an example of a static random-access memory device in accordance with some embodiments of the present disclosure.

[0009] FIG.5 illustrates an example of a processing element in accordance with some embodiments of the present disclosure.

[0010] FIG.6 illustrates an example of a resistive random-access memory device in accordance with some embodiments of the present disclosure.

[0011] FIG.7 illustrates an example of the coupling of a digital core and an analog core to shift accumulate circuitry in accordance with some embodiments of the present disclosure.

[0012] FIG.8 illustrates an example flow diagram of a method for implementing a digital core and an analog core processing element in memory in accordance with a number of embodiments of the present disclosure. Detailed Description

[0013] The present disclosure includes apparatuses and methods related to implementing hybrid processing elements in memory. The hybrid processing elements can include a digital core processing element and an analog core processing element. A digital core and an analog core can be implemented in a processing element (PE) of a memory device. The digital core and the analog core can be coupled to an array of the memory device. The digital core can receive a first plurality of bits from the array. The digital core can perform a first multiply-accumulate (MAC) operation using the first plurality of bits. The analog core can receive a second plurality of bits from the array. The analog core can perform a second MAC operation using the second plurality of bits. The PE can also include shift accumulate circuitry and / or a monitor. The shift accumulate circuitry can be coupled to the digital core and the analog core. The shift accumulate circuitry can perform a summation operation using a first result of the first MAC operation and a second result of the second MAC operation. The results of the summation operation can be an output of the PE. As used herein, “bit” is a binary digit. The term “bit” is used as one example of a digit.10023840012 The examples described herein can be used in / with non-binary applications. The examples described herein can also be implemented utilizing digits.

[0014] A PE can be implemented using static random-access memory (SRAM) or resistive random-access memory (RRAM). Operations performed utilizing SRAM have the benefit of being accurate, as compared to operations performed using different types of memory. However, operations performed utilizing SRAM may have the disadvantage of having a high computational cost (e.g., low energy efficiency), as compared to operations performed utilizing different types of memory.

[0015] In order to address these and other deficiencies of current approaches, embodiments of the present disclosure implement PEs utilizing a hybrid compute-in-memory (CIM) architecture (e.g., an architecture that includes a digital core and an analog core). The analog core can be implemented using RRAM, for example. Operations performed utilizing RRAM can have a high energy efficiency, as compared to operations performed using SRAM, but may not be applicable for task requiring high precision. By combining a digital core and an analog core to perform operations using PEs, operations can be performed that utilize less resources than performing operations using only SRAM and that are more accurate than using only RRAM. For example, performing operations in PEs utilizing digital cores and analog cores can reduce operations performed by the digital cores by 60% to save power with negligible accuracy loss.

[0016] In various instances, higher order bits of an output can be calculated using the digital core while lower order bits of the output are calculated using the analog core. Although the examples provided herein are given in the context of calculating higher order bits using the digital core and lower order bits using the analog core, the higher order bits can be calculated using the analog core and the lower order bits can be calculated using the digital core.

[0017] The bit assignment between the digital core and the analog core can be adjusted dynamically. For example, the highest order bits generated using the digital core can be used to adjust the boundary between higher order bits and lower order bits. Dynamically adjust the analog-digital boundary allows for power dissipation to be balanced with accuracy loss. As used herein, the analog-10023840012 digital boundary defines the boundary between the higher order bits and the lower order bits.

[0018] The higher order bits can be generated by the digital core concurrently with the generation of the lower order bits by the analog core. The higher order bits generated by the digital core and the lower order bits generated by the analog core can be merged to generate an output.

[0019] The output generated using the PEs can be, for example, an activation for an artificial neural network (ANN). As used herein, AI refers to the ability to improve an apparatus through “learning” such as by storing patterns and / or examples which can be utilized to take actions at a later time. Deep learning refers to a device’s ability to learn from data provided as examples. Deep learning can be a subset of AI. ANNs, among other types of networks, can be classified as deep learning.

[0020] As used herein, the ANN can provide learning by forming probability weight associations between an input and an output. The probability weight associations can be provided by a plurality of nodes that comprise the ANN. The nodes together with weights, biases, and activation functions can be used to generate an output of the ANN based on the input to the ANN. A plurality of nodes of the ANN can be grouped to form layers of the ANN. The propagation of signals through an ANN utilizing weights, biases, and activation functions can be implemented utilizing the MAC units. For example, the weights (e.g., first input) and forward propagation signals (e.g., second input) can be multiplied in a MAC unit using the examples described herein. The forward propagation signals can be referred to as activation signals or activations.

[0021] As used herein, “a number of” something can refer to one or more of such things. For example, a number of memory devices refers to one or more memory devices. A “plurality” of something intends two or more. Additionally, designators such as “N,” as used herein, particularly with respect to reference numerals in the drawings, indicates that a number of the particular feature so designated can be included with a number of embodiments of the present disclosure.

[0022] The figures herein follow a numbering convention in which the first digit or digits correspond to the drawing figure number and the remaining digits identify an element or component in the drawing. Similar elements or10023840012 components between different figures may be identified by the use of similar digits. As will be appreciated, elements shown in the various embodiments herein can be added, exchanged, and / or eliminated so as to provide a number of additional embodiments of the present disclosure. In addition, the proportion and the relative scale of the elements provided in the figures are intended to illustrate various embodiments of the present disclosure and are not to be used in a limiting sense.

[0023] FIG.1 illustrates an example computing system 100 that includes a memory system 103 in accordance with some embodiments of the present disclosure. The memory system 103 can include media, such as one or more volatile memory devices (e.g., memory device 110), one or more non- volatile memory devices (e.g., memory device 109), one or more hybrid memory devices (e.g., hybrid memory device 112), or a combination of such.

[0024] A memory system 103 can be a storage device, a memory module, or a hybrid of a storage device and memory module. Examples of a storage device include a solid-state drive (SSD), a flash drive, a universal serial bus (USB) flash drive, an embedded Multi-Media Controller (eMMC) drive, a Universal Flash Storage (UFS) drive, a secure digital (SD) card, and a hard disk drive (HDD). Examples of memory modules include a dual in-line memory module (DIMM), a small outline DIMM (SO-DIMM), and various types of non- volatile dual in-line memory modules (NVDIMMs).

[0025] The computing system 100 can be a computing device such as a desktop computer, laptop computer, server, network server, mobile device, a vehicle (e.g., airplane, drone, train, automobile, or other conveyance), Internet of Things (IoT) enabled device, embedded computer (e.g., one included in a vehicle, industrial equipment, or a networked commercial device), or such computing device that includes memory and a processing device.

[0026] In other embodiments, the computing system 100 can be deployed on, or otherwise included in a computing device such as a desktop computer, laptop computer, server, network server, mobile computing device, a vehicle (e.g., airplane, drone, train, automobile, or other conveyance), Internet of Things (IoT) enabled device, embedded computer (e.g., one included in a vehicle, industrial equipment, or a networked commercial device), or such computing device that includes memory and a processing device. As used10023840012 herein, the term “mobile computing device” generally refers to a handheld computing device that has a slate or phablet form factor.

[0027] The computing system 100 can include a host system 102 that is coupled to one or more memory systems 103. In some embodiments, the host system 102 is coupled to different types of memory system 103. FIG.1 illustrates one example of a host system 102 coupled to one memory system 103. As used herein, “coupled to” or “coupled with” generally refers to a connection between components, which can be an indirect communicative connection or direct communicative connection (e.g., without intervening components), whether wired or wireless, including connections such as electrical, optical, magnetic, and the like.

[0028] The host system 102 can include a processor chipset and a software stack executed by the processor chipset. The processor chipset can include one or more cores, one or more caches, a memory controller (e.g., an SSD controller), and a storage protocol controller (e.g., PCIe controller, SATA controller). The host system 102 uses the memory system 103, for example, to write data to the memory system 103 and read data from the memory system 103.

[0029] The host system 102 includes a processing unit 104. The processing unit 104 can be a central processing unit (CPU) that is configured to execute an operating system.

[0030] The host system 102 can be coupled to the memory system 103 via a physical host interface. Examples of a physical host interface include, but are not limited to, a serial advanced technology attachment (SATA) interface, a peripheral component interconnect express (PCIe) interface, universal serial bus (USB) interface, Fibre Channel, Serial Attached SCSI (SAS), Small Computer System Interface (SCSI), a double data rate (DDR) memory bus, a dual in-line memory module (DIMM) interface (e.g., DIMM socket interface that supports Double Data Rate (DDR)), Open NAND Flash Interface (ONFI), Double Data Rate (DDR), Low Power Double Data Rate (LPDDR), Compute Express Link (CXL), or any other interface. The physical host interface can be used to transmit data between the host system 102 and the memory system 103. The host system 102 can further utilize an NVM Express (NVMe) interface to access components (e.g., memory devices 109) when the memory system 103 is10023840012 coupled with the host system 102 by the PCIe interface. The physical host interface can provide an interface for passing control, address, data, and other signals between the memory system 103 and the host system 102. FIG.1 illustrates a memory system 103 as an example. In general, the host system 102 can access multiple memory systems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0031] The memory devices 109, 110 can include any combination of the different types of non-volatile memory devices and / or volatile memory devices. The volatile memory devices (e.g., memory device 110) can be, but are not limited to, random access memory (RAM), such as dynamic random-access memory (DRAM) and synchronous dynamic random-access memory (SDRAM).

[0032] Some examples of non-volatile memory devices (e.g., memory device 109) include negative-and (NAND) type flash memory and write-in-place memory, such as three-dimensional cross-point (“3D cross-point”) memory device, which is a cross-point array of non-volatile memory cells. A cross-point array of non-volatile memory can perform bit storage based on a change of bulk resistance, in conjunction with a stackable cross-gridded data access array. Additionally, in contrast to many flash-based memories, cross-point non-volatile memory can perform a write in-place operation, where a non-volatile memory cell can be programmed without the non-volatile memory cell being previously erased. NAND type flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0033] Each of the memory devices 109, 110 can include one or more arrays of memory cells. One type of memory cell, for example, single level cells (SLC) can store one bit per cell. Other types of memory cells, such as multi-level cells (MLCs), triple level cells (TLCs), quad-level cells (QLCs), and penta-level cells (PLC) can store multiple bits per cell. In some embodiments, each of the memory devices 109 can include one or more arrays of memory cells such as SLCs, MLCs, TLCs, QLCs, or any combination of such. In some embodiments, a particular memory device can include an SLC portion, and an MLC portion, a TLC portion, a QLC portion, or a PLC portion of memory cells. The memory cells of the memory devices 109 can be grouped as pages that can refer to a10023840012 logical unit of the memory device used to store data. With some types of memory (e.g., NAND), pages can be grouped to form blocks.

[0034] Although non-volatile memory components such as three- dimensional cross-point arrays of non-volatile memory cells and NAND type memory (e.g., 2D NAND, 3D NAND) are described, the memory device 109 can be based on any other type of non-volatile memory or storage device, such as such as, read-only memory (ROM), phase change memory (PCM), self- selecting memory, other chalcogenide based memories, ferroelectric transistor random-access memory (FeTRAM), ferroelectric random access memory (FeRAM), magneto random access memory (MRAM), Spin Transfer Torque (STT)-MRAM, conductive bridging RAM (CBRAM), resistive random access memory (RRAM), oxide based RRAM (OxRAM), negative-or (NOR) flash memory, and electrically erasable programmable read-only memory (EEPROM).

[0035] The memory system controller 105 (or controller 105 for simplicity) can communicate with the memory devices 109 to perform operations such as reading data, writing data, or erasing data at the memory devices 109 and other such operations. The memory system controller 105 can include hardware such as one or more integrated circuits and / or discrete components, a buffer memory, or a combination thereof. The hardware can include digital circuitry with dedicated (i.e., hard-coded) logic to perform the operations described herein. The memory system controller 105 can be a microcontroller, special purpose logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc.), or another suitable processor.

[0036] The memory system controller 105 can include a processor 106 (e.g., a processing device) configured to execute instructions stored in a local memory 107. In the illustrated example, the local memory 107 of the memory system controller 105 includes an embedded memory configured to store instructions for performing various processes, operations, logic flows, and routines that control operation of the memory system 103, including handling communications between the memory system 103 and the host system 102.

[0037] In some embodiments, the local memory 107 can include memory registers storing memory pointers, fetched data, etc. The local memory 107 can also include read-only memory (ROM) for storing micro-code. While10023840012 the example memory system 103 in FIG.1 has been illustrated as including the memory system controller 105, in another embodiment of the present disclosure, a memory system 103 does not include a memory system controller 105, and can instead rely upon external control (e.g., provided by an external host, or by a processor or controller separate from the memory system).

[0038] In general, the memory system controller 105 can receive commands or operations from the host system 102 and can convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory device 109 and / or the memory device 110. The memory system controller 105 can be responsible for other operations such as wear leveling operations, garbage collection operations, error detection and error-correcting code (ECC) operations, encryption operations, caching operations, and address translations between a logical address (e.g., logical block address (LBA), namespace) and a physical address (e.g., physical block address, physical media locations, etc.) that are associated with the memory devices 109. The memory system controller 105 can further include host interface circuitry to communicate with the host system 102 via the physical host interface. The host interface circuitry can convert the commands received from the host system into command instructions to access the memory device 109 and / or the memory device 110 as well as convert responses associated with the memory device 109 and / or the memory device 110 into information for the host system 102.

[0039] The memory system 103 can also include additional circuitry or components that are not illustrated. In some embodiments, the memory system 103 can include a cache or buffer (e.g., DRAM) and address circuitry (e.g., a row decoder and a column decoder) that can receive an address from the memory system controller 105 and decode the address to access the memory device 109 and / or the memory device 110.

[0040] In some embodiments, the memory device 109 includes local media controllers 111 that operate in conjunction with memory system controller 105 to execute operations on one or more memory cells of the memory devices 109. An external controller (e.g., memory system controller 105) can externally manage the memory device 109 (e.g., perform media management operations on the memory device 109). In some embodiments, a memory device 109 is a managed memory device, which is a raw memory device combined with a local10023840012 controller (e.g., local controller 111) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0041] The memory system 103 can include PE controller 108. Although not shown in FIG.1 so as to not obfuscate the drawings, the PE controller 108 can include various circuitry to facilitate aspects of the disclosure described herein. In some embodiments, the PE controller 108 can include special purpose circuitry in the form of an ASIC, FPGA, state machine, hardware processing device, and / or other logic circuitry that can allow the PE controller 108 to control PEs of the hybrid memory device 112.

[0042] In some embodiments, the memory system controller 105 includes at least a portion of the PE controller 108. For example, the memory system controller 105 can include a processor 106 (processing device) configured to execute instructions stored in local memory 107 for performing the operations described herein. In some embodiments, the PE controller 108 is part of the host system 103, an application, or an operating system. The PE controller 108 can be resident on the memory system 103 and / or the memory system controller 105. As used herein, the term “resident on” refers to something that is physically located on a particular component. For example, the PE controller 108 being “resident on” the memory system 103 refers to a condition in which the hardware circuitry that comprises the PE controller 108 is physically located on the memory system 103. The term “resident on” may be used interchangeably with other terms such as “deployed on” or “located on,” herein.

[0043] The hybrid device 112 can include a DRAM device, an SRAM device, and an RRAM device. The DRAM device can be bonded to the SRAM device and the RRAM device as described further in FIG.2. In various examples, The DRAM device can provide data to the SRAM device and the RRAM device, and the SRAM device and the RRAM device can provide data to the DRAM utilizing through silicon vias (TSVs). The DRAM device can be described as being stacked with the SRAM device and the RRAM device given that the DRAM device is bonded to the SRAM device and the RRAM device.

[0044] The SRAM device and the RRAM can comprise the PEs. The PEs can comprise one or more SRAM cells of the SRAM device or one or more RRAM cells of the RRAM device.10023840012

[0045] The SRAM device can also include logical gates that can receive the data stored in the SRAM device and data stored in the DRAM device simultaneously. The logical gates can perform operation on the data received from the SRAM device and the DRAM device. The RRAM device can comprise RRAM cells that can be used to perform operations.

[0046] The PE controller 108 can manage the movement of data from the DRAM device to the SRAM device and the RRAM device and / or from the SRAM device and the RRAM device to the DRAM device. For example, the PE controller 108 can cause data to be read from the DRAM device, can cause the data to be moved to the SRAM device and / or the RRAM device, and / or can cause the data to be stored in the SRAM device and / or the RRAM device. In various examples, the SRAM device may not include sensing circuitry while the DRAM device includes sensing circuitry. The PE controller 108 can also control PEs of the hybrid device 112 to cause operations to be performed on the data moved from the DRAM device to the SRAM device and / or the RRAM device.

[0047] The data stored in the SRAM device and / or the RRAM device can be weights of a ANN. The weights can initially be stored in the DRAM device. The weights can be read from the DRAM device and provided to the SRAM device and / or the RRAM device. The SRAM device and the RRAM device can store the weights in the memory cells of the PEs. The SRAM device and the RRAM device can utilize the weights and data stored in the DRAM device to perform a plurality of operations utilized to implement a ANN. Although a single hybrid memory device 112 is shown, multiple hybrid memory devices can be implemented in the memory system 103.

[0048] FIG.2 illustrates an example of a hybrid memory device 212 in accordance with some embodiments of the present disclosure. The hybrid memory device 212 can be a device, such as device 112 in FIG.1, and can include an SRAM device 221, an RRAM device 227, and a DRAM device 222. The SRAM device 221 can be referred to as a digital core and the RRAM device 227 can be referred to as an analog core. The SRAM device 221 can be referred to as digital (e.g., digital core) because the SRAM device performs operations utilizing digital signals. The RRAM device 227 can be referred to as analog (e.g., analog core) because the RRAM device performs operations utilizing analog signals. The hybrid memory device 212 also includes shift accumulate10023840012 circuitry 225 and a monitor 226. The operations performed by the SRAM device 221 and the RRAM device 227 can refer to multiply-accumulate (MAC) operations. In various instances, multiplication operations can be performed by the SRAM device 221 and the RRAM device 227 and accumulation operations can be performed by the shift accumulate circuitry 225.

[0049] The hybrid memory device 212 can be a three-dimensional (3D) integrated circuit (IC). The 3D IC can be a metal-oxide semiconductor (MOS) IC manufactured by stacking semiconductor wafers or dies and interconnecting them vertically using, for example, TSVs or metal connections, to function as a single device to achieve performance improvements at reduced power and smaller footprint than conventional two-dimensional processes.

[0050] The SRAM device 221 and the RRAM device 227 can be bonded to the DRAM device 222. For example, the SRAM device 221 and the RRAM device 227 can be bonded to the DRAM device 222 via a wafer-on- wafer bond 223. The SRAM device 221 and the RRAM device 227 can be a first wafer and the DRAM device 222 can be a second wafer that are bonded using the wafer-on-wafer bond 223.

[0051] After fabrication of the electronic devices (e.g., the SRAM device 221, RRAM device 227, and the DRAM device 222) on a first wafer and a second wafer, the first wafer and the second wafer can be diced (e.g., by a rotating saw blade cutting along streets of the first wafer and the second wafer). However, according to at least one embodiment of the present disclosure, after fabrication of the devices on the first wafer and the second wafer, and prior to dicing, the first wafer and the second wafer can be bonded together by a wafer- on-wafer (WoW) bonding process. Subsequent to the wafer-on-wafer bonding process, the dies (e.g., a first die including the SRAM device and the RRAM device and a second die including the DRAM device) can be singulated. For example, the SRAM and RRAM wafer can be bonded to the DRAM wafer in a face-to-face orientation meaning that their respective substrates (wafers) are both distal to the bond while the SRAM and RRAM dies and the DRAM dies are proximal to the bond 223. This enables individual SRAM and RRAM die and DRAM die to be singulated together as a single package after the SRAM and RRAN wafer and the DRAM wafer are bonded together. The bond 223 can be formed by a low temperature (e.g., room temperature) bonding process. In some10023840012 embodiments, the bond 223 can be further processed with an annealing step (e.g., at 300 degrees Celsius).

[0052] In various examples, the SRAM device 221 and the RRAM device 227 can be a top wafer and the DRAM device 222 can be a bottom wafer. However, “top” and “bottom” are not intended to describe an absolute orientation but rather are intended to describe an orientation relative to each other (e.g., the SRAM device 221, the RRAM device 227, and the DRAM device 222). In various examples, the DRAM device 222 can be the top wafer and the SRAM device 221 and the RRAM device are the bottom wafer.

[0053] The TSVs 224 can be used for communication of data between or through stacked memory die. For example, the TSVs 224 can provide signals between the DRAM device 222 and the SRAM device 221 and the RRAM device 221. For instance, parameters (e.g., weights, biases, and / or activation functions, among others) of an ANN can be stored in the DRAM device 222 and can be provided to the SRAM device 221 and the RRAM device 221 through the TSVs 224. In various instances, the parameters can be updated in the SRAM device 221 and the RRAM device 221. The updated parameters can be provided from the SRAM device 221 and the RRAM device 227 to the DRAM device 222 via the TSVs 224. The updated parameters can be stored in the DRAM device 222.

[0054] In various instances, the parameters provided from the DRAM device 222 to the SRAM device 221 and the RRAM device 227 can be stored in the SRAM device 221 and the RRAM device 227. The parameters can be utilized to process an input to the ANN. For example, the input to the ANN can also be provided from the DRAM device 222 to the SRAM device 221 and the RRAM 227 via the TSVs 224. Forward propagation signals from hidden layers of the ANN can also be processed utilizing the parameters. The forward propagation signals can also be provided from the DRAM device 222 to the SRAM device 221 and the RRAM 227 via the RSVs 224.

[0055] The SRAM device 221 and the RRAM device 227 can comprise the PEs. The SRAM device 221 and the RRAM device 227 can be coupled to the shift accumulate circuitry 225 and / or the monitor 226. The shift accumulate circuitry 225 can be utilized to perform operations utilizing the parameters of the ANN and the input signals and / or the forward propagation10023840012 signals. The monitor 226 can be utilized to define a digital-analog boundary. The shift accumulate circuitry 225 and the monitor 226 can be hardware and / or firmware. The shift accumulate circuitry 225 can perform operations to shift input data and to accumulate a plurality of outputs of the shift and accumulate circuitry 225 as described below. FIG.3A shows the monitor 226. FIG.4 shows the SRAM device 221 (e.g., the SRAM die). FIG.6 shows the RRAM device 227.

[0056] FIGs.3A and 3B illustrate an example of a monitor 326 and MSBs 331-4 in accordance with some embodiments of the present disclosure. The monitor 326 includes comparators 333-1, 333-2, 333-3, referred to as comparators 333. The comparators 333-1, 333-2, 333-3 can be hardware and / or firmware. The monitor 326 can receive bits 331-4 and thresholds (e.g., Vref level 1, Vref level 2, and Vref level 3) 332-1, 332-2, 332-3. The monitor 326 can generate bits which can be utilized to set the digital-analog boundary.

[0057] The bits 331-4 can be the most significant bits (MSBs) (e.g., four most significant bits) generated by the digital core. The bits 331-4 can also be referred to as the MSBs 331-4. / The bits 331-1, 331-2, 331-3 can be generated by the analog core and / or the digital core. For example, the bits 331-1, 331-2 can be generated by the analog core. The bits 331-3 can be generated by the analog core and / or the digital core. The bits 331-1 can include three bits. Each of the bits 331-2, 331-3, 331-4 can include four bits. The bits 331-1, 331-2, 331-3, 331-4 can be referred to as bits 331.

[0058] The bits 331 can be generated by multiplying a first vector (w) by a second vector (x). For example, the 0 bit can be the result of multiplying the w0 value with the x0 value. The 1 bit can be the result of multiplying the w0 value with the x1 value and adding the output to the output of multiplying the w1 value with the x0 value. The output of the multiplication operations can be bit- shifted.

[0059] The bits 331-4 can be compared to the thresholds 332-1, 332-2, 332-3. For example, the comparator 333-1 can compare the bits 331-4 to the threshold 332-1. If the bits 331-4 have a greater value than the threshold 332-1, then the comparator 333-1 can output a 1-bit. If the bits 331-4 have a smaller value than the threshold 332-1, the comparator 333-1 can output a 0-bit. If the bits 331-4 have a greater value than the threshold 332-2, the comparator 333-210023840012 can output a 1-bit. If the bits 331-4 have a smaller value than the threshold 332- 2, the comparator 333-2 can output a 0-bit. If the bits 331-4 have a greater value than the threshold 332-3, the comparator 333-1 can output a 1-bit. If the bits 331-4 have a smaller value than threshold 332-3, then the comparator 333-1 can output a 0-bit.

[0060] The output of the comparator 333-1 can be an MSB and the output of the comparator 333-3 can be a least significant bit (LSB) when combining the output of the comparators 333-1, 333-2, 333-3 to generate a value (e.g., bit string) 334. The value 334 can have one of the possible values 334-1, 2, 334-3, 334-4. The value 334-1 can be the bits

[0000] , the value 334-2 can be the bits

[0001] , the value 334-3 can be the bits

[0011] , the value 334-4 can be the bits

[0111] .

[0061] The monitor 326 can evaluate the value 334 to determine which of the bits 331 are to be generated by the digital core or the analog core. For example, if the value 334-1 is generated by the comparators 333, then the monitor 326 can cause the digital core to generate the bits 331-4 and the analog core to generate the bits 331-2, 331-3. The bits 331-1 can be discarded. Discarding the bits 331-1 can indicate that the bits 331-1 are not generated or if they are generated by the analog core, they are not utilized by the shift accumulate circuitry. If the value 334-2 is generated by the comparators 333, then the monitor 326 can cause the digital core to generate the bits 331-4 and the analog core to generate the bits 331-1, 331-2, 331-3. If the value 334-3 is generated by the comparators 333, then the monitor 326 can cause the digital core to generate the bits 331-4, 331-3 and the analog core to generate the bits 331-2 while the bits 331-1 are discarded. If the value 334-4 is generated by the comparators 333, then the monitor 326 can cause the digital core to generate the bits 331-4, 331-3 and the analog core to generate the bits 331-1, 331-2.

[0062] The digital-analog boundary describes which of the bits 331-1, 331-2, 331-3, 331-4 are generated by the digital core and the analog core. The monitor 326 can define the digital-analog boundary based on the four MSB generated by the digital core. Table 330 shows the use of the values 334 to define the digital-analog boundary.

[0063] FIG.4 illustrates an example of a SRAM device 421 in accordance with some embodiments of the present disclosure. The SRAM10023840012 device 421 is analogous to the SRAM device 221 of FIG.2. The SRAM device 421 includes the PEs 441 (e.g., the PEs 441-1, 441-2, 441-3, 441-4). The SRAM device 421 can also include logic (e.g., Adder Tree) 444-1, 444-2 and shift accumulate circuitry 425. The SRAM device 421 can also include TSVs 424 that couple the SRAM device 421 to the DRAM device.

[0064] Each of the PEs 441 can include a number of memory cells (e.g., SRAM<0>, …, SRAM<7>). For example, each of the PEs 441 can include eight memory cells. Each of the PEs 441 can also include logic (not shown) for performing logical operations. The logic for performing logical operations is shown in FIG.5 as logic circuitry 557.

[0065] Each of the PEs 441 can be coupled to data lines of the SRAM device 421. For example, each of the PEs 441 can be coupled to complementary data lines shown as data lines 556-1, 556-2 (e.g., DATAT, DATAF) if FIG.5. The complementary data lines can also be coupled to the TSVs 424. Such that data provided by the TSVs 424 can be stored in the memory cells of the PEs 441. The TSVs 424 can couple the SRAM device 421 to a DRAM device (e.g., the DRAM device 222 of FIG.2) such that the DRAM device can provide data to the SRAM device 421 via the TSVs 424. The TSVs 424 can provide the data received from the DRAM device to the data lines of the SRAM device 421. The data lines can provide the data to the PEs 441. The PEs 441 can store the data in the memory cells of the SRAM device 421.

[0066] In various instances, the PEs 441 can perform operations using the data stored in the memory cells and separate data provided by the TSVs 424. The TSVs 424 can provide first data at a first time and second data at a second time. The first data can be stored in the PEs 441. The second data may not be stored in the PEs 441 but may be used by the PEs 441 to perform operations in conjunction with the use of the first data.

[0067] The logic 444-1, 444-2 can receive the results of the operations performed by the PEs 441. The logic 444-1, 444-2 can perform a plurality of additional operations using the results of the operations performed by the PEs 441. For example, the logic 444-1, 444-2 can perform summation operations. The logic 444-1, 444-2 can sum a quantity of bits of the results of the operations performed by the PEs 441. For example, the logic 444-1, 444-2 can sum “1” bits10023840012 of the results of the operations performed by the PEs 441. The logic 444-1, 444- 2 can sum “0” bits of the results of the operations performed by the PEs 331.

[0068] Each of the logic 444-1, 444-2 can be coupled to a different PE group. For example, the logic 444-1 can be coupled to the PEs 441-1, 441-2 (e.g., a first PE group). The PEs 441-1, 441-2 can generate the bits 331-4 (e.g., bits <14:11>) of FIG.3B. The logic 44-2 is coupled to the PE 441-3, 441-4 (e.g., a second PE group). The PEs 441, 441-2 can generate the bits 331-3 (e.g., bits <10:7>) of FIG.3B. The shift accumulate circuitry 425 can perform additional operations on the outputs of the logic 444-1, 444-2. For example, the shift accumulate circuitry 425 can be coupled to the logic 444-1 and the logic 444-2 and can perform operations on the output of the logic 444-1 and the logic 444-2.

[0069] In various examples, the PEs 441, the logic 444-1, 444-2, and the shift accumulate circuitry 425 can perform operations to implement an ANN. For example, a layer of the ANN can include performing a sliding dot product. In a sliding dot product, a filter can stride along the input feature map and can take the dot product between them. In various examples, the filter weights can be reused throughout striding the whole input feature map. The filter weights can be reused because the filter weights can be stored in the memory cells of the PEs 441.

[0070] A sliding dot product can be used to implement a multi-bit bit- serial MAC computation which is expresses as: ேି^ ^ି^ ொି^ ேି^The441. The expression∑ ே^ୀି^^ can be performed by the logic 444-1, 444-2. The expression2^ା^ is performed by the shift accumulate circuitry 425. The databe stored in the memory cells of the PEs 441 while data ^^^[^^] isprovided by the TSVs 424 without being stored in the memory cells of the PEs 441. In various instances, the data ^^^[^^] can be stored in the memory cells of the PEs 441 while data ^^^[^^] is provided by the TSVs 424.

[0071] In various examples, 128 PEs 441 are placed between complementary data lines (DATAT and DATAF). Each PE group can consist of10023840012 a filter (e.g., convolution neural network (CNN) filter) which can be utilized to implement convolution neural networks. Each of the PE groups can implement parallel computations simultaneously. Performing operations in parallel using the PE groups can improve throughput of the SRAM device 421.

[0072] FIG.5 illustrates an example of a PE 541 in accordance with some embodiments of the present disclosure. The PE 541 can correspond to an SRAM device (e.g., the SRAM device 221 of FIG.2 and the SRAM device 421 of FIG.4). The PE 541 can include pre-charge circuitry 558, memory cells 553- 1, …, 553-8, and logic circuitry 557. The memory cells 553-1, …., 443-8 can also be referred to as memory cells 553. The PE 541 can be coupled to complementary data lines 556-1, 556-2. The memory cells 553 can be coupled to complementary GUT lines (e.g., GUTT, GUTF) 551-1, 551-2, referred to as GUT lines 551, and word lines 552-1, …, 552-8. The GUT lines 551 can act as “local digit lines”. The data lines 556 act as “global digit lines”. In various examples, the memory cells 553 can be 6T memory cells. The memory cells 553 can be implemented as a different type of memory cell and are not limited to 6T memory cells.

[0073] The PE 541 can also include select circuitry 555-1, 555-2, referred to as select circuitry 555. The select circuitry 555 can be coupled to a select line 554 that can be used to couple the data lines 556 to the GUT lines 551. For instance, a first data value can be read from a DRAM device such as the DRAM device 222 of FIG.2. The first data value can be provided from the DRAM device to the SRAM device via TSVs. The TSVs can provide the first data value to the data lines 556. The select lines 554 may be activated to activate the select circuitry 555 to cause the first data value to be provided to the GUT lines 551 from the data lines 556. The select circuitry 555 can couple the data lines 556 to the GUT lines 551. The GUT lines 551 can provide the data value to the memory cells 553. The memory cells 553 can store the data values provided by the GUT lines 551.

[0074] A second data value can be read from the DRAM device. The second data value can be provided from the DRAM device to the SRAM device via the TSVs. The TSVs can provide the second data value to the data lines 556. Signals (e.g., not the data lines) can be provided through the select lines 554 to cause the select circuitry 555 to remain inactive such that the second data value10023840012 is provided to the logic circuitry 557 and not the GUT lines 551. The pre-charge circuitry 558 can also cause the memory cells 553 to be read such that the first data value is provided through the GUT lines 551 to the logic circuitry 557. The logic circuitry 557 can perform an operation using the first data value read from the memory cells 553 and the second data value provided by the data lines 556.

[0075] The logic circuitry 557 can be implemented as an AND gate. The AND gate can perform the operation ^^^^[^^]^^^^[^^]. The output 559 of the AND gate can be the output of the PE 541. The output 559 of the PE 541 can be provided to the logic (Adder Tree). Given that the output 559 of the PE 541 is not provided through a global I / O, the output 559 of the PE 541 is not provided to a sense amplifier. The output of the PE 541 is not amplified. The inputs to the logic circuitry 557 are also not amplified by sense amplifiers of the SRAM device given that the SRAM device can be implemented without sense amplifiers. Storing the first data value in the memory cells 553 can allow the first data value to be reused multiple times without refreshing the memory cells 553 allows for a more efficient use of power as compared to refreshing the first data value in memory cells each time the first data value is read from the memory cells.

[0076] The second value can be a single bit while the first value can be multiple bits. For example, ^^0can be the second value while ^^0is the first bit of the first value. The operations ^^0^^0, ^^1^^0, …, ^^7^^0are performed prior to receipt of a different input value (e.g., ^^1) from the DRAM device. The weights (first value) can be reused to perform the operations ^^0^^1, ^^1^^1, …, ^^7^^1. The same process can be repeated until the operations ^^0^^7, ^^1^^7, …, ^^7^^7. are performed.

[0077] The processing element controller of the SRAM device and / or the memory system can control the data lines 556, the GUT lines 551, the word lines 552, the select line 554, the pre-charge circuitry 558, and / or the select circuitry 555. While the function of a single PE 541 is described in FIG.5, the processing element controller can control multiple PEs to perform multiple operations (AND operations) at relatively the same time.

[0078] A DRAM device has the advantage of high cell density as compared to an SRAM device, but does not support weight reuse because the cell data is destructive. Once the cell data is read out through charge sharing, the10023840012 cell cap is written back through digit lines. The same weight data is accessed repeatedly during the whole CONV (convolution) computation, which deteriorates the throughput and the energy efficiency. The SRAM device uses latches as memory cells. The storage node is non-destructive and can be accessed while performing computation, entailing weight reuse with high throughput and energy efficiency. However, the SRAM cell density is low as compared to the DRAM device and is not capable of storing large quantities of data as compared to the DRAM device during the deep learning computation cycle. The power dissipation of data transition between SRAM macro and system RAM (DRAM) occupies most of the power in the system, which becomes the bottleneck for practical use of SRAM-based compute-in-memory (CIM) system. The examples described herein integrate the advantages of both DRAM devices and SRAM devices to realize a CIM solution with both high cell density that supports weight reuse.

[0079] The SRAM device may utilize more energy to operate than the RRAM. However, the SRAM device may provide greater accuracy in reading and performing operations in the logic 557 than the RRAM device. It may be beneficial to perform operations that require greater accuracy in the PEs 541 of the SRAM device and the remainder of the operations in PE of the RRAM.

[0080] FIG.6 illustrates an example of an RRAM device 627 in accordance with some embodiments of the present disclosure. The RRAM device 627 is analogous to the RRAM device 227 of FIG.2. The RRAM device 627 can include digital to analog converters (DAC) 661-1, 661-2, 661-3, referred to as DAC 661. The RRAM device 627 can also include analog to digital converters (ADC) 662-1, 662-2, 662-3, referred to as ADC 662. The RRAM device 627 can include a plurality of memory cells 664. The memory cells 664 are coupled to various signal lines, such as sense lines 665 and access lines 667.The DAC 661 can convert digital signals X (e.g., ^^^, ^^^, ^^ଶ) to analog signals V(e.g., ^^^, ^^^,^^ଶ). The ADC 662 can convert analog signals I (e.g., ^^^, ^^^, ^^ଶ) todigital signals Y (e.g., ^^^,^^^,^^^). In various examples, the memory cells 664 can act as the PEs or groupings of the memory cells 664 can act as PEs of the RRAM device 627.10023840012

[0081] The memory cells 664 can be resistive memory cells 664. The resistive memory cells 664 can comprise terminals that couple the memory cells 664 to the sense lines 665 and the access lines 667. The terminals of the memory cells 664 can be coupled to each other via resistive elements 663. The resistive elements 663 can be a resistance variable material (e.g., a material programmable to multiple different resistance states, which can represent multiple different data states) such as, for example, a transition metal oxide material, or a perovskite including two or more metals (e.g., transition metals, alkaline earth metals, and / or rare earth metals). Other examples of resistance variable materials that can be included in the storage element of resistive memory cells 664 can include various materials employing trapped charges to modify or alter conductivity, chalcogenides formed of various doped or undoped materials, binary metal oxide materials, colossal magnetoresistive materials, and / or various polymer based resistive variable materials, among others. Embodiments are not limited to a particular resistance variable material or materials. The resistive elements 663 can control the conductance of the memory cells 664. In various instances, the conductance of the memory cells 664 can be programmed by programming the resistive element 663. For instance, control circuitry of a memory system can program the resistive elements 663. As used herein, actions performed by the RRAM device 627, a memory array of the RRAM device 627, the memory cells 664, the DAC 661, and / or the ADC 662 can be performed by a control circuitry of the memory system that comprises the RRAM device 627 (e.g., that comprises the hybrid device that includes the RRAM device 627).

[0082] In a number of examples, the conductance and / or resistance of a memory cell 664 represents a weight value of an ANN. With respect to programming the memory cells 664 and / or representing weight values with the memory cells 664, the terms resistance and conductance are used interchangeably herein since any change in resistance is accompanied by a proportional change in conductance. The conductance of the memory cells 664 can represent weight values of a layer of the ANN. For instance, the conductance of the memory cells 664 can represent a weight of a node of the ANN. As used herein, the terms weights and weight values are used interchangeably.10023840012

[0083] The memory cells 664 can be used to perform a plurality of operations. The memory cells 664 can be controlled to perform matrix multiplication in parallel and locally to the RRAM device 627. Matrix multiplication can be performed utilizing inputs, provided using the DAC 661, and a plurality of weight values represented by the resistance of the resistive elements 663. The inputs can be provided by the DRAM device via the TSVs coupled to the DAC 661 via a plurality of lines (not shown). The inputs can be provided as an input vector. The input vector is denoted as V (e.g., ^^^,^^^,^^ଶ). The plurality of weight values can be provided as a weight matrix and is stored by programming the memory cells 663 accordingly prior to applying the inputs(e.g., input vector V). The weight values are denoted as G (e.g.,^^^^,^^^^,^^^^,^^^^,^^^^,^^^^,^^^ଶ,^^^ଶ,^^^ଶ) The resistances of the memory cells664 collectively represent the weight matrix. ^^^

[0084] The inputs are denoted as V and comprise the^⋮൩^^^although only three values are shown in the example of FIG.6.of the inputs (e.g., ^^^… ^^^) can be provided to the RRAM device 627 via a plurality of signal lines such as the sense lines 665 or the access lines 667. Each of the access lines 667 can provide a portion of the input. For example, a first access line can provide the input value ^^^, …, and a last access line can provide the input value ^^^, wherein n isto a quantity of access lines 667 or is less than the quantity of access lines 667.

[0085] The inputs vector V can be multiplied with a weight matrix comprising the weight values stored by the memory cells 664 and which are represented in the conductance of the memory cells 664. The weight matrix is ^^^^ ⋯ ^^^^denoted as ^ ⋮ ⋱ ⋮ ൩. Each of the memory cells 664 can store a different^^^^ ⋯ ^^^^weight value represented by a conductance of a corresponding memory cell.

[0086] The outputs 228 (e.g., ^^) of the matrix multiplication can be ^^^provided as an output vector อ⋮อ. The example of FIG.6 shows an output ^^^vector that includes three values but an output vector may include more or less than the three values. Each of the outputs (e.g., ^^^… ^^^) can be provided via a10023840012 different one of the signal lines such as the sense lines 665 or the access lines 667. The outputs are shown as being provided via the sense lines 667. Matrix multiplication is denoted as ^^^[^^]^^^[^^] where ^^^[^^] is the G vector (e.g., a column of the G matrix) and ^^^[^^] is the V vector. The expression Σ^ଷୀ^is performed by the shift accumulate circuitry 668.

[0087] The memory cells 664 can be reprogramed by resetting the conductance of the memory cells 664. Resetting the conductance of the memory cells 664 can reprogram the memory array 664 to function as a different layer of the ANN.

[0088] The output vector Y can be provided from the RRAM device 627 to the shift accumulate circuitry 668-1, 668-2, 668-3 as digital signals. The shift accumulate circuitry 668-1, 668-2, 668-3 can be referred to as shift accumulate circuitry 668. The shift accumulate circuitry 668 can be different than the shift accumulate circuitry 425 of FIG.4. The shift accumulate circuitry 668 can generate the bits 631-1, 631-2, 631-3 that are analogous to bits 331-1, 331-2, 331-3 of FIG.3B. The shift accumulate circuitry 668 can be coupled to the shift accumulate circuitry 425 of FIG.4.

[0089] FIG.7 illustrates an example of the coupling of a digital core 721 and an analog core 727 to shift accumulate circuitry 725 in accordance with some embodiments of the present disclosure. The hybrid device can include the digital core 721, the analog core 727, the shift accumulate circuitry 725, and the monitor 726.

[0090] The monitor 726 can receive the bits 731-4 from the digital core 721. The monitor 726 can determine whether the bits 731-3 are to be generated by the digital core 721 or the analog core 727 even though they may be generated both the digital core 721 and the analog core 727 at a first time. The monitor 726 can compare the bits 731-4 to thresholds which can be used to generate output bits (e.g., <B,A,S>). The output bits can be used to determine the boundary 771 which defines whether the bits 731-3 are to be generated by the digital core 721 or the analog core 727.

[0091] The bits 731-1, 731-2, 731-3, 731-4 are provided to the shift accumulate circuitry 725. The shift accumulate circuitry 725 can be coupled to the digital core 721 and the analog core 727. The shift accumulate circuitry 72510023840012 is coupled to the digital core 721 via the logic 444 (e.g., adder tree) of FIG.4. The shift accumulate circuitry 725 is coupled to the analog core 727 via different shift accumulate circuitry (e.g., shift accumulate circuitry 668 of FIG.6).

[0092] The expression ∑^ି^^ୀ^ ∑ொି^^ୀ^ 2^ା^ is performed by the shiftaccumulate circuitry 725. The expression ∑ேି^^ୀ^ ^^^[^^]^^^[^^] is performed by thedigital core 721 and the analog core 727. The digital core 721 and the analogcore 727 can perform the expression ∑ேି^^ୀ^ ^^^[^^]^^^[^^] simultaneously togenerate the bits 731. As used herein,or expressions simultaneously and / or concurrently can define that the operations are performed at relatively the same time. The output of the shift accumulate circuitry 725 can be an output to a layer of an ANN (e.g., hidden layer or output layer of the ANN).

[0093] In various example, the digital core 721 can generate the bits 731- 4 prior to the digital core 721 and / or the analog core 727 generating the bits 731- 1, 731-2, 731-3. For example, in a first iteration the digital core 721 can generate the bits 731-4 and provide the bits 731-4 to the monitor 726. Based on the bits 731-4, the monitor 726 can determine the boundary 771 such that the digital core generate the bits 731-3, 731-4 and the analog core generates the bits 731-1, 731- 2. In a second iteration, the digital core 721 generates and provides the bits 731- 3, 731-4 to the shift accumulate circuitry 725 and the analog core 727 generates and provides the bits 731-1, 731-2.

[0094] In other examples, the digital core 721 can generate and provide the bits 731-3, 731-4 to the shift accumulate circuitry 725 and the analog core 727 can generate and provide the bits 731-1, 731-2, 731-3 to the shift accumulate circuitry 725 at relatively the same time. For example, the bits 731- 1, 731-2, 731-3, 731-4 can be generated and provided to the shift accumulate circuitry 725 concurrently. The digital core 721 can provide the bits 731-4 to the monitor concurrently with the providing of the bits 731-4 to the shift accumulate circuitry 725 and the providing of the bits 731-3, 731-4 by the digital core 721 and the bits 731-1, 731-2, 731-3 by the analog core 727 to the shift accumulate circuitry 725.

[0095] The shift accumulate circuitry 725 can receive an indication from the monitor 726 of the boundary 771. Based on the boundary 771, the shift10023840012 accumulate circuitry 725 can utilize the bits 731-3 from the digital core 721 or the analog core 727 in addition to the bits 731-1, 731-2, 731-4 to perform operations as described herein.

[0096] In various examples, the monitor 276 can control whether the bits 731-3 are generated by the digital core 721 or the analog core 727 by routing input bits used to generate the bits 731-3 to the digital core 721 or the analog core 727. The monitor 276, based on the bits 731-4 of a first iteration, can rout input bits used to generate the bits 731-3 to the digital core 721 or the analog core 727. For example, the input data can be received from the DRAM via the TSVs. The monitor 726 can cause the input data, used to generate the bits 731-3 in a second iteration to be provided to the digital core 721 or the analog core 727. If the digital core receives the input data, then the digital core 721 can generate the bits 731-3. If the analog core 727 receives the input data, then the analog core 727 can generate the bits 731-3. The monitor 276 can cause the bits 731-3 to be provided to the shift accumulate circuitry 725 from the digital core 721 or the analog core 727. The monitor 276 can control who generates the bits 731-3 by controlling which of the digital core 721 or the analog core 727 receives the input data used to generate the data 731-3.

[0097] FIG.8 illustrates an example flow diagram of a method 880 for mapping an input to a multiply-accumulate unit in accordance with a number of embodiments of the present disclosure. The method can be executed by a memory device of a computing system. For example, the method can be executed by a controller or a PU of the memory device. The method 880 can be performed by processing logic that can include hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, integrated circuit, etc.), software (e.g., instructions run or executed on a processing device), or a combination thereof. In some embodiments, the method 880 is performed by the hybrid memory device 112 of FIG.1 and the hybrid memory device 212 of FIG.2. Although shown in a particular sequence or order, unless otherwise specified, the order of the processes can be modified. Thus, the illustrated embodiments should be understood only as examples, and the illustrated processes can be performed in a different order, and some processes can be performed in parallel. Additionally, one or more processes can10023840012 be omitted in various embodiments. Thus, not all processes are required in every embodiment. Other process flows are possible.

[0098] At 881, a digital core coupled to an array of memory cells can receive a first plurality of digits from the array. At 882, the digital core can perform a first MAC operation using the first plurality of digits. The digital core can store the first plurality of digits in memory cells of the digital core prior to using the first plurality of digits to perform the MAC operations or may utilize the first plurality of digits to perform the MAC operations without storing the first plurality of digits in the memory cells.

[0099] At 883, monitor logic coupled to the digital core can compare a result of the first MAC operation to a plurality of thresholds. Each of the thresholds can be different from the other thresholds. At 884, responsive to comparing the result to the plurality of thresholds, the monitor can determine a first plurality of digits from different data to provide to the digital core for performance of a second MAC operation and a second plurality of digits from the different data to provide to an analog core for performance of a third MAC operation, wherein the analog core is coupled to the array. The monitor can control which of the first plurality of digits are to provided to the digital core and which of the second plurality of digits are provided to the analog core to control which digits (e.g., output digits) are provided to the shift analog circuitry from the digital core or the analog core. At 885, the digital core can receive the first plurality of digits and the analog core can receive the second plurality of digits based on the monitors determination.

[0100] The monitor can compare the four MSBs to the thresholds. For example, the monitor can compare the four MSBs to three different thresholds. The monitor can compare four MSBs to each of the thresholds. Each of the comparisons can generate a 1-digit value if the four MSBs are greater than a corresponding threshold. The monitor can also generate a 0-digit value if the four MSBs are smaller than the corresponding threshold. Given that there are three comparisons, the monitor can generate three digit values.

[0101] The monitor can utilize the three digit values generated by comparing the four MSBs of the result (e.g., the result of the first MAC operation) to the three different thresholds to determine a digital-analog boundary between the first plurality of digits and the second plurality of digits.10023840012 The digital-analog boundary can determine which of the input digits are provided as the first plurality of digits to the digital core or the second plurality of digits to the analog core. The digital-analog boundary can also define which of the output digits of the digital core and the analog core are provided to the shift accumulate circuitry.

[0102] For example, a first result of the second MAC operation can be provided from the digital core to shift accumulate circuitry. The second result of the third MAC operation can be provided from the analog core to the shift accumulate circuitry. The quantity of digits in the first result and the second result can change based on the digital-analog boundary.

[0103] The output of the shift accumulate circuitry can be the output of ANN or an output of a layer of the ANN. The shift accumulate circuitry can store the output in a register. The output can be accessed or the output can be provided to input / output (I / O) lines of the memory system. For example, the output can be provided to the host via the I / O lines.

[0104] In various examples, a memory system can include an array of memory cells, a digital core, an analog core, and a shift accumulate circuitry. The digital core and the analog core can be coupled to the array. The digital core can receive a first plurality of digits from the array. The digital core can receive the first plurality of digits via TSVs that couple the digital core to the array of memory cells. The digital core can perform a first MAC operation using the first plurality of digits. A first result of the first MAC operation can be provided to the shift accumulate circuitry.

[0105] The analog core can receive a second plurality of digits from the array. The analog core can also perform a second MAC operation using the second plurality of digits. The analog core can provide a second result of the second MAC operation to the shift accumulate circuitry. The shift accumulate circuitry coupled to the digital core and the analog core can perform a summation operation using a first result of the first MAC operation and a second result of the second MAC operation.

[0106] The memory system can also include a monitor configured to assign higher order digits from input data to the first plurality of digits and lower order digits from the input data to the second plurality of digits. For example, the four MSBs or the eight MSBs of the input data can be assigned and provided to10023840012 the analog core while the seven LSBs or the eleven LSBs of the input data are provided to the analog core.

[0107] The monitor can also dynamically adjust a digital-analog boundary between the higher order digits and the lower order digits. The monitor can update the digital-analog boundary based on MAC operations being performed. For example, if more accuracy is needed to implement the ANN, then the digital core can receive more digits from the input data than if the more accuracy is not needed to implement the ANN.

[0108] The monitor can adjust the digital-analog boundary using the output of the first MAC operation. For example, the monitor can compare the output of the first MAC operation to a plurality of thresholds. Based on the output of the comparison, the monitor can adjust the digital-analog boundary.

[0109] The digital core can include a plurality of SRAM cells used to perform the first MAC operation. The analog core can include a plurality of RRAM cells used to perform the second MAC operation. The array of memory cells can be implemented in a DRAM device bonded to the digital core, the analog core, the shift accumulate circuitry, and / or the monitor.

[0110] The array of memory cells can store the first plurality of digits and the second plurality of digits. The array can provide the first plurality of digits to the digital core and the second plurality of digits to the analog core via a plurality of TSVs. The first plurality of digits and the second plurality of digits represent a weight of an ANN, an input to the ANN, or an activation of a layer of the ANN.

[0111] In various examples, the memory system can include an array of memory cells, a digital core, an analog core, and a monitor. The digital core can be coupled to the array and can be configured to receive a first plurality of digits from the array. The digital core can also perform a first MAC operation using the first plurality of digits. The digital core can receive a second plurality of digits from the array and perform a second MAC operation using the second plurality of digits.

[0112] The analog core can be coupled to the array and can be configured to receive the second plurality of digits from the array and perform a third MAC operation using the second plurality of digits. The monitor can be coupled to the digital core and can be configured to compare a first result of the10023840012 first MAC operation to a plurality of thresholds. The monitor can, responsive to comparing the first result to the plurality of thresholds, determine whether to provide a second result of the second MAC operation or a third result of the third MAC operation to shift accumulate circuitry.

[0113] The memory system can also include shift accumulate circuitry coupled to the digital core and the analog core. The shift accumulate circuitry can receive a selected result wherein the selected result is one of the second result and the third result. The shift accumulate circuitry can perform a summation operation and / or a shift operation using the selected result.

[0114] In some examples, the digital core can receive a third plurality of digits from the array and perform a fourth MAC operation using the third plurality of digits. The digital core can receive a fourth plurality of digits from the array and perform, responsive to the selected result, a fifth MAC operation using the fourth plurality of digits. The analog core can receive a fifth plurality of digits from the array and can perform a sixth MAC operation using the fifth plurality of digits.

[0115] In other examples, the digital core can receive a third plurality of digits from the array and perform a fourth MAC operation using the third plurality of digits. The analog core can receive a fourth plurality of digits from the array and perform a fifth MAC operation using the fourth plurality of digits. The analog core can also receive a fifth plurality of digits from the array and perform, responsive to the selected result, a sixth MAC operation using the fifth plurality of digits.

[0116] Some portions of the preceding detailed descriptions have been presented in terms of algorithms and symbolic representations of operations on data digits within a computer memory. These algorithmic descriptions and representations are the ways used by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art. An algorithm is here, and generally, conceived to be a self-consistent sequence of operations leading to a desired result. The operations are those requiring physical manipulations of physical quantities. Usually, though not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, combined, compared, and otherwise manipulated. It has proven convenient at times, principally for reasons of common usage, to refer to these10023840012 signals as digits, values, elements, symbols, characters, terms, numbers, or the like.

[0117] It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The present disclosure can refer to the action and processes of a computer system, or similar electronic computing device, that manipulates and transforms data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system memories or registers or other such information storage systems.

[0118] The present disclosure also relates to an apparatus for performing the operations herein. This apparatus can be specially constructed for the intended purposes, or it can include a general purpose computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program can be stored in a computer readable storage medium, such as, but not limited to, any type of disk including floppy disks, optical disks, CD- ROMs, and magnetic-optical disks, read-only memories (ROMs), random access memories (RAMs), EPROMs, EEPROMs, magnetic or optical cards, or any type of media suitable for storing electronic instructions, each coupled to a computer system bus.

[0119] The algorithms and displays presented herein are not inherently related to any particular computer or other apparatus. Various general purpose systems can be used with programs in accordance with the teachings herein, or it can prove convenient to construct a more specialized apparatus to perform the method. The structure for a variety of these systems will appear as set forth in the description below. In addition, the present disclosure is not described with reference to any particular programming language. It will be appreciated that a variety of programming languages can be used to implement the teachings of the disclosure as described herein.

[0120] The present disclosure can be provided as a computer program product, or software, that can include a machine-readable medium having stored thereon instructions, which can be used to program a computer system (or other electronic devices) to perform a process according to the present disclosure. A machine-readable medium includes any mechanism for storing information in a10023840012 form readable by a machine (e.g., a computer). In some embodiments, a machine-readable (e.g., computer-readable) medium includes a machine (e.g., a computer) readable storage medium such as a read only memory (“ROM”), random access memory (“RAM”), magnetic disk storage media, optical storage media, flash memory devices, etc.

[0121] In the foregoing specification, embodiments of the disclosure have been described with reference to specific example embodiments thereof. It will be evident that various modifications can be made thereto without departing from the broader spirit and scope of embodiments of the disclosure as set forth in the following claims. The specification and drawings are, accordingly, to be regarded in an illustrative sense rather than a restrictive sense.

Claims

10023840012 What is claimed is:

1. An apparatus, comprising: an array of memory cells; a digital core coupled to the array and configured to: receive a first plurality of digits from the array; perform a first multiply-accumulate (MAC) operation using the first plurality of digits; an analog core coupled to the array and configured to: receive a second plurality of digits from the array; perform a second MAC operation using the second plurality of digits; and shift accumulate circuitry coupled to the digital core and the analog core and configured to perform a summation operation using a first result of the first MAC operation and a second result of the second MAC operation.

2. The apparatus of claim 1, further comprising monitor logic configured to: assign higher order digits from input data to the first plurality of digits; and assign lower order digits from input data to the second plurality of digits.

3. The apparatus of claim 2, wherein the monitor logic is further configured to dynamically adjust a digital-analog boundary between the higher order digits and the lower order digits.

4. The apparatus of claim 3, wherein the monitor logic is further configured to adjust the digital-analog boundary using the output of the first MAC operation.

5. The apparatus of any one of claims 1-4, wherein the digital core includes a plurality of static random-access memory (SRAM) cells used to perform the first MAC operation.10023840012 6. The apparatus of any one of claims 1-4, wherein the analog core includes a plurality of resistive random-access memory (RRAM) cells used to perform the second MAC operation.

7. The apparatus of any one of claims 1-4, wherein the array of memory cells is implemented in a dynamic random-access memory (DRAM) device bonded to the digital core, the analog core, and the shift accumulate circuitry.

8. The apparatus of claim 7, wherein the array of memory cells is configured to: store the first plurality of digits and the second plurality of digits; provide the first plurality of digits to the digital core and the second plurality of digits to the analog core through a plurality of through silicon vias (TSVs).

9. The apparatus of any one of claims 1-4, wherein the first plurality of digits and the second plurality of digits represent a weight of an artificial neural network (ANN).

10. A method, comprising: receiving, at a digital core coupled to an array of memory cells, a first plurality of digits from the array; performing, at the digital core, a first multiply-accumulate (MAC) operation using the first plurality of digits; comparing, at monitor logic coupled to the digital core, a result of the first MAC operation to a plurality of thresholds; responsive to comparing the result to the plurality of thresholds, determining, at the monitor logic, a first plurality of digits from different data to provide to the digital core for performance of a second MAC operation and a second plurality of digits from the different data to provide to an analog core for performance of a third MAC operation, wherein the analog core is coupled to the array; and providing the first plurality of digits to the digital core and the second plurality of digits to the analog core.10023840012 11. The method of claim 10, wherein comparing the result of the first MAC operation to the plurality of thresholds includes comparing four most significant digits of the result to three different thresholds.

12. The method of claim 11, further comprising generating a 1-digit value if the four most significant digits are greater than a corresponding threshold.

13. The method of claim 12, further comprising generating a 0-digit value if the four most significant digits are smaller than the corresponding threshold.

14. The method of claim 13, further comprising utilizing three digit values generated by comparing the four most significant digits of the result to the three different thresholds to determine a digital-analog boundary between the first plurality of digits and the second plurality of digits.

15. The method of any one of claims 10-14, further comprising: providing a first result of the second MAC operation from the digital core to shift accumulate circuitry; and providing a second result of the third MAC operation from the analog core to the shift accumulate circuitry.

16. The method of claim 15, further comprising accessing an output of the shift accumulate circuitry as an output of an artificial neural network (ANN).

17. An apparatus, comprising: an array of memory cells; a digital core coupled to the array and configured to: receive a first plurality of digits from the array; perform a first multiply-accumulate (MAC) operation using the first plurality of digits; receive a second plurality of digits from the array; perform a second MAC operation using the second plurality of digits;10023840012 an analog core coupled to the array and configured to: receive the second plurality of digits from the array; perform a third MAC operation using the second plurality of digits; and monitor logic coupled to the digital core and configured to: compare a first result of the first MAC operation to a plurality of thresholds; responsive to comparing the first result to the plurality of thresholds, determine whether to provide a second result of the second MAC operation or a third result of the third MAC operation to shift accumulate circuitry.

18. The apparatus of claim 17, further comprising the accumulator logic coupled to the digital core and the analog core and configured to: receive a selected result wherein the selected result is one of the second result and the third result; perform a summation operation and a shift operation using the selected result.

19. The apparatus of claim 18, wherein: the digital core is further configured to: receive a third plurality of digits from the array; perform a fourth MAC operation using the third plurality of digits; receive a fourth plurality of digits from the array; perform, responsive to the selected result, a fifth MAC operation using the fourth plurality of digits; and the analog core is further configured to: receive a fifth plurality of digits from the array; perform a sixth MAC operation using the fifth plurality of digits.

20. The apparatus of claim 18, wherein: the digital core is further configured to: receive a third plurality of digits from the array;10023840012 perform a fourth MAC operation using the third plurality of digits; the analog core is further configured to: receive a fourth plurality of digits from the array; perform a fifth MAC operation using the fourth plurality of digits; and receive a fifth plurality of digits from the array; perform, responsive to the selected result, a sixth MAC operation using the fifth plurality of digits.

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