System, method, and apparatus for read optimized 3D nor memory

Abstract

An integrated circuit device is disclosed that comprises multiple vertical structures categorized into distinct bit-line and select-line groups. Each vertical structure includes an insulating vertical-plug column (612), surrounded by adjacent source (616) and drain (614) electrode columns, and a channel column (620) encircling these components. Additionally, a ferroelectric column (618) is wrapped around the channel column, contributing to the device's functionality. The architecture also integrates several horizontal gate-electrode layers, each positioned at a specific vertical interval from one another and adjacent to the vertical structures. The device includes a set of bit lines, each linked to a source electrode column of a corresponding bit-line group, and a set of select lines, each connected to a drain electrode column of a corresponding select-line group..

Description

SYSTEM, METHOD, AND APPARATUS FORREAD OPTIMIZED 3D NOR MEMORYCROSS-REFERNCE TO RELATED APPLICATION

[0000] This application claims priority to the U.S. provisional application number 63 / 652,777 filed on May 29, 2024, which is hereby incorporated by reference in its entirety.BACKGROUNDRelevant Field

[0001] The present disclosure relates to transistors with ferroelectric materials. In particular, the present disclosure relates to ferroelectric transistor devices, systems, and methods of manufacturer.Description of Related Art

[0002] Field-effect transistors (“FETs”) are transistors that utilize an electric field to control or modify current flowing between a source terminal and a drain terminal. The electric field is generated by a voltage applied to a gate terminal of the FET. FETs use electrons and / or holes as charge carriers to achieve this effect. FETs can be predominantly majority-charge-carrier devices or minority-charge-carrier devices. The voltage applied to the gate of the FET creates an active channel through which the charge carriers flow from the source terminal to the drain terminal. The nonlinear impedance through this channel can be varied by applying different voltages to the gate terminal relative to the source and / or drain terminals. However, these characteristics are ephemeral because as soon as the voltage is no longer applied, the FET quickly returns to its original, resting state.

[0003] Ferroelectric field-effect transistors (“FeFETs”) are FETs that include a ferroelectric material. Ferroelectric materials are materials that have electric polarization (or polarization density). The electric field polarization of the ferroelectric material can be used to create an active channel within the FeFET. By utilizing this property of the ferroelectric material, the electric field polarization in the ferroelectric material may be used to retain the FeFET’s state in the absence of any electrical bias. That is, the FeFET can retain information in the ferroelectric material without havingany external power applied to it. This feature makes FeFETs suitable for non-volatile memory applications that involve discrete or continuous values.SUMMARY

[0004] The integrated circuit device may comprise a plurality of vertical structures arranged into bit-line groups and select-line groups. Each vertical structure is a member of only a single bit-line group and a single select-line group. The vertical structures may optionally include an insulating vertical-plug column, with a source electrode column and a drain electrode column disposed on either side adjacent to the plug. A channel column is disposed surrounding the plug and electrode columns. Enveloping the channel column is a ferroelectric column.

[0005] Additionally, the device includes multiple horizontal gate-electrode layers vertically spaced a predetermined distance apart from one another. The gateelectrode layers are positioned adjacent the vertical structures.

[0006] The device further comprises bit lines and select lines. The bit lines each correspond to a particular bit-line group and connect electrically to the source electrode column of the group's vertical structures. Similarly, the select lines each correspond to a specific select-line group and connect electrically to the drain electrode column of that group's vertical structures.

[0007] In some embodiments, the bit-line groups of vertical structures are arranged electrically orthogonal to the select-line groups of vertical structures. That is, the plurality of vertical structures arranged in bit-line groups and select-line groups, where each vertical structure is a member of only a single bit-line group and a single select-line group. This orthogonal electrical arrangement allows for selective activation of individual vertical structures by applying voltages to the corresponding bit lines and select lines.

[0008] The integrated circuit device may further comprise a plurality of dielectric layers interdigitated with the plurality of horizontal gate-electrode layers, in some embodiments. That is, the dielectric layers may be positioned between adjacent horizontal gate-electrode layers in an alternating pattern along the vertical direction. The inclusion of these dielectric layers can serve to electrically isolate the horizontal gate-electrode layers from one another, preventing leakage currents or shorting between layers.

[0009] In some embodiments, the integrated circuit device is configured such that when a bit line from the plurality of bit lines is activated and a select line from the plurality of select lines is activated, a single vertical structure from the plurality of vertical structures is activated. This allows for selective activation of individual vertical structures. The orthogonal arrangement of the bit lines and select lines enables discrete selection of a target memory cell for access by applying voltages to the corresponding lines. When a read or write operation occurs, the appropriate vertical structure containing the ferroelectric field effect transistor memory cell is chosen by the coordinated application of signals to the bit line and select line that intersect at that structure. This selectivity helps confine operational currents to only the desired vertical structure while minimizing leakage current in non-selected structures, improving energy efficiency.

[0010] In some embodiments, when a single vertical structure is activated by turning on the corresponding bit line and select line, current flows through that particular vertical structure. More specifically, the architecture allows individual vertical structures to be selectively activated for memory access operations. When a specific bit line and select line are activated, the vertical structure at the intersection of those lines is chosen and current flows through the source electrode column, channel column, and drain electrode column of that structure. The selective activation is enabled by the orthogonal arrangement of vertical structures into distinct bit-line groups and select-line groups. This selective flow of current through only the active vertical structure helps minimize leakage current, benefiting metrics like power consumption, read times, and device longevity. Overall, the selective accessing capabilities supported by the architecture facilitate vital memory functions.

[0011] In some embodiments, when a bit line and select line are activated to access a vertical structure, current flows through only that single activated vertical structure. The integrated circuit device is configured such that the non-selected vertical structures remain electrically disconnected. Therefore, the path of operational current is confined to the individual vertical structure that has been chosen for access, minimizing background leakage currents in other parts of the array. This isolation of the accessed vertical structure improves energy efficiency, speed, and longevity of the FeFET memory array.

[0012] In some embodiments, the bit lines which connect the vertical structures to external circuitry may be arranged substantially in parallel. That is, each of the plurality of bit lines corresponding to respective bit line groups are oriented extending in the same direction without intersecting. This parallel configuration allows signals to propagate along the bit lines for accessing the desired vertical structures efficiently. Since the bit lines interface the memory array with peripheral circuits, having parallel bit lines provides a neat and orderly routing scheme. Moreover, parasitic capacitance and crosstalk between adjacent bit lines is minimized compared to other arrangements, enabling faster signal transmission.

[0013] In an additional embodiment of the integrated circuit device, each of the plurality of select lines described previously may be arranged substantially parallel to each other. This parallel configuration allows the select lines to efficiently access the individual vertical structures along the select-line dimension. By activating a specific select line, the corresponding select group of vertical structures is selected. The select lines being orientated parallel to one another facilitates this group-based vertical structure selection and access. Overall, the parallel layout of select lines enables efficient integration, routing, decoding, and voltage biasing within the memory architecture to choose target groups for reading and writing data.

[0014] The integrated circuit device may further comprise a plurality of source select transistors, where each of the plurality of source select transistors is coupled to a respective select line of the plurality of select lines. In some embodiments, the source select transistors act as switches to control current flow from the select lines into individual vertical structures. When activated, the source select transistors allow current to pass through, enabling operations such as reading or writing data to the memory cells within the vertical structures. The integration of the source select transistors facilitates the specific selection of vertical structures for memory access while confining operational currents to only the desired columns. This helps minimize power loss due to leakage, improving the energy efficiency of the memory architecture.

[0015] The plurality of vertical structures described in the integrated circuit device is configured to form a 3D-N0R memory array in some embodiments. Specifically, the vertical structures with their arrangement of components like the insulating vertical-plug column, source electrode column, drain electrode column, channel column, and ferroelectric column allow for the creation of a 3D architecturenon-volatile memory array with NOR type behavior. This 3D stacking of NOR memory cells can provide benefits like increased storage density and smaller chip footprint compared to a planar layout. The select lines and bit lines interfacing with the vertical structures enable individual memory cells to be addressed for operations, contributing to the NOR functionality.

[0016] The integrated circuit device may include a plurality of bit lines that are arranged orthogonal to the plurality of select lines. In some embodiments, each of the bit lines corresponds to a respective bit-line group and is electrically coupled to a source electrode column of the vertical structures within that group. Meanwhile, the select lines each correspond to a select-line group and interface with the drain electrode columns. The orthogonal configuration of these bit lines relative to the select lines facilitates the discrete electrical access of individual vertical structures. When voltage signals are applied to a specific bit line and select line pair, their intersection activates the desired vertical structure for memory operations. This selective activation reduces leakage current, saves power, speeds up reads, and extends device longevity.

[0017] In some embodiments, each of the plurality of bit lines may not have a respective bit-line selector transistor. The bit lines can directly interface with the vertical structures without needing an accompanying selector transistor for each line. By avoiding having a dedicated selector transistor, the overall circuit density can be increased. Additionally, eliminating separate selector transistors for each bit line can reduce fabrication costs. However, in alternative embodiments, selector transistors could be incorporated to provide additional control over the bit line signals if desired.

[0018] In some embodiments, the source electrode column and drain electrode column within each vertical structure may be formed from a common conductive material. Using the same material to construct both columns can simplify the manufacturing process and ensure compatibility between the two components. Potential conductive materials include metals (e.g. copper, aluminum), heavily doped semiconductor materials, conductive ceramic compounds, or other suitable electrical conductors. Forming the source and drain electrode columns from a shared material allows them to possess similar physical, electrical and thermal characteristics, facilitating coordinated functioning. The choice of material can be optimized to achieve low resistance, high current density tolerance, excellent conductivity, and stability within the operating conditions inside the vertical structures.

[0019] In some embodiments, the plurality of bit lines may be electrically coupled to a respective source electrode column of the plurality of vertical structures. This electrical coupling connects each bit line to the source electrode of the vertical structures within the corresponding bit-line group. When a specific bit line is activated, it can transmit signals to the attached source electrodes of those vertical structures for memory access operations. The orthogonal architecture, with bit lines and select lines activating individual vertical structures, allows for selective control over memory read and write functions.

[0020] In some embodiments, the vertical structures may have an elliptical cross-sectional shape. Configuring the vertical structures to have an elliptical crosssection rather than a circular or standard shape can influence the electric field distribution within the memory cell. This in turn can impact device performance characteristics such as switching speeds, endurance, retention time, and more. The ability to tailor the geometry of the vertical structures adds flexibility in optimizing the FeFET memory cells for factors like power consumption, read / write speed, and data retention time depending on the target application and specifications.

[0021] Some embodiments include features in the vertical structures to minimize capacitive coupling between adjacent bit-line groups. Configuring the vertical structures in this way reduces capacitive crosstalk and signal leakage between vertical structures connected to different bit-lines. This can improve signal integrity for read and write operations in high density memory architectures with tightly packed vertical structures. Techniques to minimize capacitive coupling may involve material choices, geometries, and layouts optimized for reduced parasitic capacitance between structures belonging to different bit-line groups.

[0022] In some embodiments, the horizontal gate-electrode layers of the integrated circuit device include a dielectric layer interposed between each horizontal gate-electrode layer. The inclusion of this dielectric layer serves to electrically isolate the vertical structures from the horizontal gate-electrode layers, preventing current leakage between these components. The dielectric layer may be composed of materials such as silicon dioxide or other insulating substances optimized to provide adequate electrical isolation while maintaining sufficient capacitive coupling for proper device functionality. By incorporating a dielectric layer, gate leakage current can be reduced, improving energy efficiency and device longevity.

[0023] The integrated circuit device may comprise a plurality of horizontal gate-electrode layers. In some embodiments, these horizontal gate-electrode layers are disposed at predetermined vertical distances from one another. The predetermined vertical distances between the horizontal gate-electrode layers may be optimized.

[0024] In some embodiments, the plurality of vertical structures may be configured as a three-dimensional array in the integrated circuit device, arranged into distinct bit-line groups and select-line groups. The arrangement of the bit-line groups which are electrically connected to respective source electrode columns, along with the select line groups which are electrically coupled to corresponding drain electrode columns, may enable the plurality of vertical structures to collectively form a nonvolatile memory unit, leveraging the ferroelectric properties of the vertical structures to facilitate data storage without continuous power.

[0025] In some embodiments, the integrated circuit device comprises a plurality of vertical structures arranged in distinct bit-line groups and select-line groups. Each vertical structure may be a member of only a single bit- line group and a single selectline group. The vertical structures can comprise a source electrode, a drain electrode, a channel disposed in electrical communication between the source and drain electrodes, and a ferroelectric material positioned in spaced relation to the channel in order to influence the channel.

[0026] Additionally, the device may include multiple horizontal gate-electrode layers, where each layer is disposed at a predetermined vertical distance from one another and adjacent to the vertical structures. The integrated circuit device may also comprise a plurality of bit lines, where each bit line corresponds to a respective bit-line group and is electrically coupled to the source electrode of the vertical structures in that group. Furthermore, there may be a plurality of select lines included, where each select line corresponds to a particular select-line group and is electrically connected to the drain electrode of the vertical structures in that select-line group.

[0027] The integrated circuit device may be configured such that when a bit line from the plurality of bit lines is activated and a select line from the plurality of select lines is simultaneously activated, a single vertical structure from the plurality of vertical structures becomes activated. In some embodiments, this allows current to flow through the activated single vertical structure. The bit lines and select lines are arranged orthogonal to each other and correspond to distinct bit-line groups and select-linegroups respectively. Therefore, activating a specific bit line and select line combination selects the intersection point, which maps to selecting a single vertical structure. This selective activation of individual vertical structures enables optimized memory operations within the integrated circuit device.

[0028] In some embodiments, when a specific bit line and select line are activated to address an individual vertical structure, current flows through that single activated vertical structure. More specifically, the integrated circuit device is configured such that activating a particular bit line in combination with a particular select line ensures one and only one vertical structure is selected at a time. In this activated state, electrical current passes through the source electrode column, channel column, and drain electrode column exclusively within that single vertical structure, while the remaining non-selected vertical structures do not conduct current. This selective activation facilitates precision memory access and helps minimize leakage current that might otherwise flow through multiple structures simultaneously.

[0029] In some embodiments, the integrated circuit device is configured such that current flows through only the one or more vertical structures that are actively selected from the plurality of vertical structures. Specifically, when a bit line and a select line are activated to choose a target vertical structure for a read or write operation, current is directed exclusively through that particular structure. The remaining nonselected vertical structures in the array are electrically isolated from the operational currents. This selective activation and confinement of current flow enhances the energy efficiency of the memory architecture, while also improving parameters like read access times, reducing electrical noise, and potentially extending the operational lifespan of the device. By limiting current to only targeted vertical structures, issues like leakage through inactive components can be mitigated.

[0030] The integrated circuit device may comprise a plurality of bit lines that are substantially parallel to each other. In particular embodiments, the plurality of bit lines correspond to respective bit-line groups and are electrically coupled to source electrodes of respective vertical structures. By arranging the bit lines in a substantially parallel configuration, certain advantages may be achieved in some embodiments.

[0031] In some embodiments, the plurality of select lines in the integrated circuit device are arranged substantially in parallel with one another. This parallelconfiguration allows each of the select lines to interface with its respective select-line group of vertical structures uniformly.

[0032] Some embodiments may include source select transistors coupled to each of the select lines in the integrated circuit device. In these embodiments, there are a plurality of source select transistors, with each source select transistor connected to one of the select lines in a one-to-one manner. The purpose of the source select transistors is to act as a switch to control current flow from a select line into a selected vertical structure for memory read operations. The inclusion of these transistors within the architecture provides a means to selectively enable the vertical structures while helping to minimize leakage current through unselected structures.

[0033] The plurality of vertical structures may form a 3D-N0R memory array in some embodiments. Specifically, the vertical structures, with their arrangement into distinct bit-line groups and select-line groups, source electrodes, drain electrodes, channel regions, and ferroelectric elements, may be configured as NOR flash memory cells organized in a three-dimensional architecture. This 3D-NOR configuration can provide benefits such as high density and storage capacity compared to conventional planar NOR flash. The selective activation of individual vertical structures made possible by the orthogonal bit lines and select lines allows for control and programming of each NOR flash cell within the 3D array.

[0034] In some embodiments, the bit lines and select lines of the integrated circuit device are arranged in an orthogonal configuration. Specifically, the plurality of bit lines, which are electrically coupled to the source electrodes of the vertical structures, are oriented perpendicular to the plurality of select lines, which interface with the drain electrodes. This orthogonal wiring layout allows each vertical structure to be uniquely addressed via the intersection of its corresponding bit line and select line. When a particular select line and bit line are activated concurrently, only the single vertical structure linked to both lines is selected, while the remaining structures stay inactive.

[0035] In some embodiments, the integrated circuit device may incorporate a plurality of bit lines, which correspond to respective groups of vertical structures, without requiring the presence of a bit-line selector transistor associated with each individual bit line. The bit lines can directly interface with the source electrodes of the corresponding vertical structures to provide access for memory operations, while selectlines coupled to the drain electrodes and source select line transistors facilitate selection of target vertical structures. This approach can serve to simplify the overall circuit architecture for potential area and cost benefits, relying on the existing select components to impart necessary selectivity, rather than necessitating additional transistor elements for every bit line in the device.

[0036] In some embodiments, each of the plurality of bit lines is electrically coupled to a respective source electrode of the plurality of vertical structures within the integrated circuit device.

[0037] The plurality of vertical structures of the integrated circuit device may be arranged in a three-dimensional array configuration. In some embodiments, the organization of the vertical structures is not constrained to a single plane, but rather consists of multiple layered arrangements.

[0038] In some embodiments, the method of manufacturing the integrated circuit device involves forming the bit-line groups of vertical structures such that they are electrically orthogonal to the select-line groups of vertical structures. More specifically, when forming the distinct bit-line groups and select-line groups comprised of vertical structure columns, the bit-line groups are configured to connect electrically to the source electrode columns in an orientation perpendicular to how the select-line groups are configured to connect electrically to the drain electrode columns. This orthogonal wiring arrangement of the bit lines relative to the select lines allows a particular vertical structure to be uniquely addressed and activated based on the specific bit line and select line that intersect at that structure. By activating a vertical structure's corresponding bit line and select line, that structure is chosen, enabling current to flow through that particular column.

[0039] The integrated circuit device may further comprise a plurality of dielectric layers interdigitated with the plurality of horizontal gate-electrode layers, in some embodiments. That is, the dielectric layers may be positioned between adjacent horizontal gate-electrode layers in an alternating pattern along the vertical direction. The inclusion of these dielectric layers can serve to electrically isolate the horizontal gate-electrode layers from one another, preventing leakage currents or shorting between layers.

[0040] In some embodiments, the integrated circuit device comprises a plurality of vertical structures arranged in distinct bit-line groups and select-line groups. Eachvertical structure may be a member of only a single bit-line group and a single selectline group. Additionally, the device may include multiple bit lines and select lines, corresponding to the respective groups. The method by which the device is manufactured may allow for the selective activation of a single vertical structure when a particular bit line and select line are activated concurrently. Specifically, configuring the bit lines and select lines to interface with distinct groups of vertical structures enables individual structures to be addressed based on the intersection point of an active bit line and select line pair. This selective activation scheme facilitates precision memory access while confining operational currents to only targeted structures within the memory architecture.

[0041] In some embodiments, when a specific bit line and select line are activated to address an individual vertical structure, current flows through that single activated vertical structure. More specifically, the integrated circuit device is configured such that activating a particular bit line in combination with a particular select line ensures one and only one vertical structure is selected at a time. In this activated state, electrical current passes through the source electrode column, channel column, and drain electrode column exclusively within that single vertical structure, while the remaining non-selected vertical structures do not conduct current. This selective activation facilitates precision memory access and helps minimize leakage current that might otherwise flow through multiple structures simultaneously.

[0042] In some embodiments, when a specific bit line and select line are activated to address an individual vertical structure, current flows through that single activated vertical structure. More specifically, the integrated circuit device is configured such that activating a particular bit line in combination with a particular select line ensures one and only one vertical structure is selected at a time. In this activated state, electrical current passes through the source electrode column, channel column, and drain electrode column exclusively within that single vertical structure, while the remaining non-selected vertical structures do not conduct current. This selective activation facilitates precision memory access and helps minimize leakage current that might otherwise flow through multiple structures simultaneously.

[0043] In some embodiments, the bit lines which connect the vertical structures to external circuitry may be arranged substantially in parallel. That is, each of the plurality of bit lines corresponding to respective bit line groups are oriented extendingin the same direction without intersecting. This parallel configuration allows signals to propagate along the bit lines for accessing the desired vertical structures efficiently. Since the bit lines interface the memory array with peripheral circuits, having parallel bit lines provides a neat and orderly routing scheme. Moreover, parasitic capacitance and crosstalk between adjacent bit lines is minimized compared to other arrangements, enabling faster signal transmission.

[0044] In some embodiments, the plurality of select lines in the integrated circuit device are arranged substantially in parallel with one another. This parallel configuration allows each of the select lines to interface with its respective select-line group of vertical structures uniformly. The select lines, which are electrically coupled to the drain electrodes of the vertical structures, can thus access the appropriate columns of structures in a consistent manner by the application of suitable voltages.

[0045] Some embodiments may include source select transistors coupled to each of the select lines. In these embodiments, there are a plurality of source select transistors, with each source select transistor connected to one of the select lines in a one-to-one manner. The purpose of the source select transistors is to act as a switch to control current flow from a select line into a selected vertical structure for memory read operations.

[0046] Some embodiments may configure the plurality of vertical structures to form a 3D-NOR memory array. Specifically, the vertical structures, with their arrangement into distinct bit-line groups and select-line groups, source electrodes, drain electrodes, channel regions, and ferroelectric elements, may be configured as NOR flash memory cells organized in a three-dimensional architecture.

[0047] In some embodiments, the integrated circuit device comprises a plurality of bit lines that are arranged orthogonal to the plurality of select lines. In particular embodiments, the plurality of bit lines correspond to respective groups of vertical structures, and are electrically coupled to source electrodes of respective vertical structures. Meanwhile, the plurality of select lines correspond to other respective groups of vertical structures, and are electrically coupled to drain electrodes. This orthogonal wiring layout allows each vertical structure to be uniquely addressed via the intersection of its corresponding bit line and select line. Specifically, when a particular select line and bit line are activated concurrently, only the single vertical structure linked to both lines is selected, while the remaining structures stay inactive.

[0048] In some embodiments, the source electrode column and drain electrode column within each vertical structure may be formed from a common conductive material. Using the same material to construct both columns can simplify the manufacturing process and ensure compatibility between the two components. Potential conductive materials include metals (e.g. copper, aluminum), heavily doped semiconductor materials, conductive ceramic compounds, or other suitable electrical conductors. Forming the source and drain electrode columns from a shared material allows them to possess similar physical, electrical and thermal characteristics, facilitating coordinated functioning.

[0049] The integrated circuit device of some embodiments may comprise vertical structures configured to have an elliptical cross-sectional shape. In particular, the vertical structures which contain components like the insulating vertical-plug column, source electrode column, drain electrode column, channel column, and ferroelectric column are formed to possess an elliptical geometry in cross-section rather than a standard circular or square shape in some embodiments.

[0050] Some embodiments include features in the vertical structures to minimize capacitive coupling between adjacent bit-line groups. Configuring the vertical structures in this way reduces capacitive crosstalk and signal leakage between vertical structures connected to different bit-lines. This can improve signal integrity for read and write operations in high density memory architectures with tightly packed vertical structures.

[0051] The method of manufacturing the integrated circuit device may involve forming a dielectric layer in the horizontal gate-electrode layers. In some embodiments, the plurality of horizontal gate-electrode layers described previously may be disposed at predetermined vertical distances from one another. These predetermined vertical distances between the horizontal gate-electrode layers may be optimized.

[0052] In some embodiments, when forming the plurality of vertical structures, they may be arranged such that the bit-line groups and select-line groups collectively enable the vertical structures to serve as a non-volatile memory unit. Specifically, the composition of the vertical structures, including elements such as the insulating vertical-plug column, source electrode column, drain electrode column, channel column, and encapsulating ferroelectric column, allows them to operate as non-volatile memory.

[0053] In some embodiments, the integrated circuit device is configured such that when a bit line from the plurality of bit lines is activated and a select line from the plurality of select lines is activated, a single vertical structure from the plurality of vertical structures becomes activated.

[0054] In some embodiments, when a specific bit line and select line are activated to address an individual vertical structure, current flows through that single activated vertical structure. In this activated state, electrical current passes through the source electrode column, channel column, and drain electrode column exclusively within that single vertical structure, while the remaining non-selected vertical structures do not conduct current. This selective activation facilitates precision memory access and helps minimize leakage current that might otherwise flow through multiple structures simultaneously.

[0055] In some embodiments, the plurality of bit lines in the integrated circuit device are arranged substantially in parallel with one another. Specifically, during the forming of each of the plurality of bit lines, which are electrically coupled to respective source electrodes of the vertical structures within corresponding bit-line groups, the bit lines are aligned extending in the same direction without intersecting. This parallel configuration of the bit lines provides certain advantages.

[0056] In some embodiments, the integrated circuit device comprises a plurality of select lines that are substantially parallel to each other. In particular, the plurality of select lines that interface with the vertical structures in a one-to-one manner within distinct select line groups are formed such that they are orientated extending in the same direction without intersecting. This parallel layout of the select lines enables them to uniformly access the individual vertical structures along the select line dimension in an orderly fashion.

[0057] In some embodiments, the integrated circuit device further comprises a plurality of source select transistors, where each of the plurality of source select transistors is coupled to a respective select line of the plurality of select lines. The purpose of the source select transistors is to act as switches to control current flow from the select lines into individual vertical structures for read operations. The inclusion of these transistors within the architecture provides a means to selectively enable the vertical structures while helping to minimize leakage current through unselected structures.

[0058] In some embodiments, the plurality of vertical structures described in the integrated circuit device may be configured as a three-dimensional NOR flash memory array. Specifically, the vertical structures, with their arrangement into distinct bit-line groups and select-line groups, source electrodes, drain electrodes, channel regions, and ferroelectric elements, may be architected as NOR flash memory cells organized in a three-dimensional layout.

[0059] In some embodiments, the integrated circuit device comprises a plurality of bit lines that are arranged orthogonal to the plurality of select lines. In particular embodiments, the plurality of bit lines correspond to respective groups of vertical structures, where each bit line electrically couples to the source electrode of each vertical structure within its respective group. Meanwhile, the plurality of select lines are electrically connected to the drain electrodes of the vertical structures, with each select line corresponding to a particular select-line group. This orthogonal orientation between the bit lines and select lines facilitates the discrete electrical access of individual vertical structures. Specifically, when suitable voltage signals are applied to a particular bit line in combination with a particular select line, the intersection point activates the desired vertical structure for memory operations. The remaining nonselected vertical structures stay inactive. This selective activation reduces leakage current, saves power, speeds up reads, and extends device longevity.

[0060] In some embodiments, the integrated circuit device may incorporate a plurality of bit lines, which correspond to respective groups of vertical structures, without requiring the presence of a bit-line selector transistor associated with each individual bit line. The bit lines can directly interface with the source electrodes of the corresponding vertical structures to provide access for memory operations, while select lines coupled to the drain electrodes and source select line transistors facilitate selection of target vertical structures.

[0061] In some embodiments, the plurality of bit lines described in the integrated circuit device are configured to be electrically coupled to the respective source electrode columns of the plurality of vertical structures. Specifically, each individual bit line interfaces electrically with the source electrode within the vertical structures belonging to the corresponding bit-line group. This direct connectivity allows each bit line to transmit voltage signals in order to operate the memory cells integrated within the vertical structure during vital functions like reading or writing data. Theelectrical coupling of the bit lines to the source electrodes facilitates the transfer of data to and from the ferroelectric elements within individual vertical structures via the connected source electrode column and adjacent channel column.

[0062] The integrated circuit device may comprise a plurality of vertical structures arranged in a three-dimensional array configuration. In some embodiments, the organization of the vertical structures is not constrained to a single plane, but rather consists of multiple layered arrangements.

[0063] The integrated circuit device may further comprise a plurality of word lines in additional embodiments. Each of these word lines couples electrically to one of the plurality of horizontal gate-electrode layers dispersed between the vertically oriented structures. The word lines serve to interface the gate-electrode layers with control circuitry external to the memory array. By applying suitable voltages to a specific word line, the corresponding gate-electrode layer can be activated, thereby enabling programming, reading or erasure of the adjacent memory cells integrated within the vertical structures.

[0064] The plurality of vertical structures in some embodiments may be configured to store data in a non-volatile manner. Specifically, the polarization states induced in the ferroelectric columns allow information to be retained without continuous power being supplied to the memory cells. Once written, the data persists in the absence of an applied voltage to the FeFET gate terminals. This non- volatility originates from the ability of these specially engineered ferroelectric domains to exhibit hysteresis, preserving their polarity even when the original programming field is removed. Their non-linear polarization response facilitates two or more stable states that can encode binary, multi-state or analog data values without static power drain.

[0065] In some embodiments, the integrated circuit device is incorporated within a system for managing operations and facilitating external communication. This system comprises a control unit that oversees device operations like data reading, writing, and erasure. It also contains a voltage regulation module responsible for supplying the required operating voltages to the integrated circuit device for performance. Additionally, there is a data interface included that enables communication between the device and an external processor, allowing data transfer to and from the system. Finally, a timing module is configured to control the timing of signals dispatched to the integrated circuit device through features like synchronization.

[0066] In some embodiments, the integrated circuit device system’s voltage regulation module, which supplies various operating voltages to the device, includes a plurality of voltage converters that each convert an input voltage to a different output voltage. This enables the voltage regulation module to provide multiple distinct output voltages suitable for different operations of the integrated circuit device. Specifically, each voltage converter may be designed and configured to provide a specific output voltage required for particular memory access functions like read, write, or erase. The inclusion of multiple voltage converters tailored for specialized voltages facilitates the diverse voltage needs of the memory architecture for reliable performance across a range of operations.

[0067] In some embodiments, the system for managing the integrated circuit device further comprises a thermal management unit configured to monitor and control the temperature of the integrated circuit device. More specifically, this thermal management unit may involve components like temperature sensors that are distributed across the integrated circuit device to detect readings at various locations. Additionally, the thermal management unit may incorporate a cooling control circuit that is designed to activate cooling mechanisms, if needed, based on the temperature measurements from the sensors. By monitoring the temperature and engaging cooling when certain thresholds are exceeded, this thermal management unit serves to regulate the operating temperature of the integrated circuit device.

[0068] In some embodiments, the integrated circuit device may comprise a thermal management unit to monitor and control the temperature. This thermal management unit could include temperature sensors positioned across the integrated circuit device. Using data from these distributed sensors, a cooling control circuit within the thermal management unit may activate cooling mechanisms when needed based on the sensor temperature readings.

[0069] In some embodiments, the system for managing the integrated circuit device may comprise a power management unit configured to manage power consumption of the integrated circuit device during various operational states. More specifically, this power management unit may be incorporated to actively control and adjust the power usage of the integrated circuit device under different modes of operation or functionality. For instance, when the device transitions to an idle or standby state, the power management unit may reduce voltage levels, deactivate non-essential components, alter refresh rates of memory arrays, or take other measures to curtail power usage during these inactive periods. By adaptively minimizing unnecessary power consumption this way, improved energy efficiency, thermal management, and battery life may be achieved.

[0070] In some embodiments, the system further comprises a power management unit configured to manage power consumption of the integrated circuit device during various operational states. Specifically, the power management unit may be designed to reduce power consumption of the integrated circuit device during idle or inactive states when no read, write, or erase operations are being performed. By lowering the power usage during these idle periods, overall energy efficiency can be improved. Techniques to cut power draw could potentially involve reducing operating voltages, slowing or halting clocks, powering down unused blocks, or transitioning components into low-power modes. This ability to curtail power consumption when the integrated circuit device is not actively being accessed allows energy savings that can prolong battery life for mobile applications.

[0071] In some embodiments, the system for managing the integrated circuit device further comprises a diagnostics module configured to perform diagnostics on the integrated circuit device to identify potential faults. Specifically, the diagnostics module is designed to carry out testing procedures on the integrated circuit device based on pre-defined schedules or in response to detected anomalies during operations. The purpose of these diagnostic tests is to check for issues that could lead to faults or failures and detect them early, before they impact functioning. By actively monitoring the health of the integrated circuit device, potential problems can be flagged so preventative measures can be taken or replacements made prior to actual failure.

[0072] In some embodiments, the system for managing the integrated circuit device may comprise a timing module configured to control timing of signals sent to the device. Specifically, the timing module may optionally include a phase-locked loop (PLL) circuit that synchronizes the timing of signals based on an external clock source. The inclusion of this PLL circuit allows the control signals and data transmission to and from the device to occur at optimized instances referenced to the external clock. By synchronizing to the same external timing source, the integrated circuits within the system can coordinate effectively to manage functions like data storage, retrieval, refresh, and erase operations.BRIEF DESCRIPTION OF THE DRAWINGS

[0073] These and other aspects will become more apparent from the following detailed description of the various embodiments of the present disclosure with reference to the drawings wherein:

[0074] Fig. 1 shows a block diagram of an artificial intelligence accelerator that utilizes FeFET memory in accordance with an embodiment of the present disclosure;

[0075] Fig. 2 shows a diagram of a memory cell utilizing a FeFET transistor in accordance with an embodiment of the present disclosure;

[0076] Fig. 3 illustrates operating characteristics of the FeFET of Fig. 2 when used to store binary states in accordance with an embodiment of the present disclosure;

[0077] Fig. 4 illustrates operating characteristics of the FeFET of Fig. 2 when used to store multiple values, such as a weight of a neuromorphic cell, in accordance with an embodiment of the present disclosure;

[0078] Fig. 5 shows an integrated circuit device where the FeFETs are arranged in an orthogonal wiring configuration in accordance with an embodiment of the present disclosure;

[0079] Fig. 6 A shows a 3 -dimensional memory structure of the integrated circuit device of Fig. 5 in accordance with an embodiment of the present disclosure; and

[0080] Fig. 6B shows a cross-sectional view of a vertical structure of Fig. 6A in accordance with an embodiment of the present disclosure.DETAILED DESCRIPTION

[0081] Fig. 1 shows a block diagram of an Artificial Intelligence (“Al”) accelerator 100 that utilizes FeFET memory 112 in accordance with an embodiment of the present disclosure. The Al accelerator 100 may be implemented on a semiconductor device, a custom integrate circuit, an application- specific integrated circuit (“ASIC”), a graphics processing unit (“GPU”), a field-programmable gate array (“FPGA”), any device known to one of ordinary skill in the art, or some combination thereof. The Al accelerator 100 includes a processing element (“PE”) array 102 that performs the majority of Al computation. The PE array 102 performs the Al computations using a plurality of processing elements 110. These processing elements 110 may form amanycore processor where each processing element 110 performs Al calculations in parallel with the other processing elements 110. Additionally or alternatively, the processing elements 110 may include an arithmetic logic unit, a neuromorphic computation element, a processor, a multicore processor, a manycore processor, a reduced instruction set computer (“RISC”) processor, and / or other computation device known to one of ordinary skill in the relevant art.

[0082] The processing elements 110 may each be part of a neuromorphic circuit; for example, the processing elements 110 may each form a portion of an artificial neural network where each accompanying memory 112 is an analog memory configured to act as parameters for artificial neurons (e.g., weights), in some specific embodiments. Each processing element 110 and its respective memory 112 may form an in-memory processing architecture, e.g., to enable efficient and parallel execution of multiply-accumulate operations, in yet additional embodiments.

[0083] The memories 112 are implemented using FeFETs described in further detail below. The memories 112 may store binary data and / or may store analog data in some specific embodiments. Additionally or alternatively, the memories 112 may store a combination of binary and analog data in some embodiments.

[0084] The Al accelerator 100 may also include a shared memory 108. Computations computed by the PE array 102 may be stored and / or instructed by information stored on a shared memory 104 internal to the Al accelerator and / or shared memory 108 stored off of the Al accelerator 100. The shared memory 104 and / or the shared memory 108 may utilize the FeFET memory cells as described herein. The Al accelerator 100 also includes a Network-on-Chip 106 for communicating with other devices, e.g., via TCP / IP, Ethernet, Wifi, etc.

[0085] Referring to Fig. 2, there is depicted a detailed diagram of a memory cell 200, which incorporates a Ferroelectric Field-Effect Transistor (FeFET) 202, in accordance with a specific embodiment of the present disclosure. The memory cell 200 is further equipped with a program-signal circuit 206 and a sense circuit 204 which are used for to operate the memory cell 200. The program- signal circuit 206 delivers either a series of positive- voltage pulse signals or negative- voltage pulse signals, which can serve the function of programming the FeFET 202 to store data when suitable voltage levels are used. The FeFET 202 is composed of several components: a drain 210, a source 212, and a gate 208. In some embodiments the FeFET 202 may be configuredsuch that the roles of the drain 210 and source 212 can be interchanged without affecting the fundamental operation of the FeFET 202.

[0086] The operational power for the FeFET 202 is supplied by a Vread voltage, which has a defined relationship to a reference voltage denoted as SL. The Vread voltage has several potential states: it may be set to ground, configured as a fixed voltage, programmed as a variable voltage, or it might be attached to a ground or a voltage source through an additional transistor component, which is not depicted in Fig. 2. Similarly, the SL reference voltage shares these potential states, offering versatility in the configuration of the memory cell 200. For instance, the Vread voltage and the SL reference voltage can be predetermined to maintain a constant voltage difference between the drain 210 and the source 212, whether this is applied intermittently or maintained continuously. Alternatively, in other embodiments, the Vread voltage and the SL reference voltage could be adjusted to provide a stable current flow from the drain 210 to the source 212, with the same conditions of intermittency or continuity.

[0087] The programming of the FeFET 202 is achieved through the application of voltages to the gate 208 by the program-signal circuit 206. These applied voltages induce an electric polarization within the ferroelectric material that constitutes part of the FeFET 202. This induced electric polarization may be designed to be stable, allowing it to persist, or at least substantially persist, even after the programming voltage has been withdrawn from the gate 208. The persistence of the polarization is contingent upon the voltage having been of adequate magnitude and duration to effect a change in the state of the ferroelectric material. The ferroelectric material itself is an insulator, and its property of retaining electric polarization after the cessation of an applied electric field (from the voltage applied to the gate 208) is a key feature that enables the non-volatile storage capability of the FeFET 202.

[0088] The behavior of the FeFET 202 can be modulated by the nature of the voltage biases applied to the gate 208. When the program-signal circuit 206 applies positive voltage biases or pulses to the gate 208, this action results in a decrease in the threshold voltage of the FeFET 202, which in turn brings the channel of the FeFET 202 into what is known as the accumulation mode. Conversely, when negative voltage biases or pulses are applied to the gate 208 by the program-signal circuit 206, the threshold voltage of the FeFET 202 experiences an increase, and this shift brings the channel of the FeFET 202 into the depletion mode. These two distinct states of theFeFET 202 correlate to binary values, where the first state may represent a binary 'O' and the second state may represent a binary '1', or the reverse may be true, depending on the specific design and application of the memory cell 200. To read the state of the FeFET 202, a voltage may be applied to the gate 208 so that the sense circuit 204 can examine the behavior of the ferroelectric material contained within the FeFET 202.

[0089] In an additional embodiment, the program-signal circuit 206 may be constructed with the capability to provide a range of voltage pulse amplitudes, thereby enabling the FeFET 202 to be programmed with varying levels of polarization. This feature allows for the storage of multiple values of information within a single FeFET 202, thus increasing the data density of the memory cell 200. The sense circuit 204, in this embodiment, is designed to be sensitive to these different polarization states to make it capable of detecting differences in the polarization states of the ferroelectric material so that accurate readout of the stored multi- value, multi-bit, or multi-state data.

[0090] In another embodiment, the memory cell 200 may include additional circuitry for error correction and data integrity. This could involve redundant FeFETs 202, parity checking mechanisms, or various error correction codes, which may integrated within the memory cell 200 itself.

[0091] An alternative embodiment may feature a configuration where the program- signal circuit 206 and sense circuit 204 are shared among multiple FeFETs 202, forming an array of memory cells 200. This shared circuitry approach could reduce the overall complexity and size of the memory array, resulting in a more compact and cost-effective design. The shared program- signal circuit 206 would be capable of selectively addressing individual FeFETs 202 for programming, while the shared sense circuit 204 would be capable of selectively reading data from the FeFETs 202 within the array.

[0092] In a further embodiment, the memory cell 200 may be part of a larger system that includes a controller configured to manage the programming and reading of the FeFET 202. The controller could implement algorithms to optimize the programming process, potentially extending the life of the FeFET 202 by minimizing wear and mitigating issues related to ferroelectric fatigue. Additionally, the controller could dynamically adjust the Vread voltage and the SL reference voltage in real time, based on the operating conditions and the history of the FeFET 202 usage, to achieve optimal performance and reliability.

[0093] In yet another embodiment, the FeFET 202 could be designed to operate in extreme environmental conditions, such as high temperatures or radiation-prone environments. This may involve the use of specialized materials for the ferroelectric layer and robust design techniques to ensure the FeFET 202 maintains its functionality and data retention under such conditions. The program-signal circuit 206 and sense circuit 204 in this embodiment would also be constructed with materials and designs that can withstand these harsh environments, ensuring the integrity of the entire memory cell 200.

[0094] Another embodiment may involve integrating the FeFET 202 within a three-dimensional memory structure, where multiple layers of FeFETs 202 are stacked vertically. This may be used to increase the memory density, creating a higher-capacity storage solution with a smaller footprint.

[0095] Referring now to Figs. 1 and 2: Fig 1. illustrates an Al accelerator, which facilitates Al computations through a processing element (PE) array. This Al accelerator 100 may employ FeFET memory, indicated as 112, to optimize the performance of Al-related tasks. The FeFET memory 112 may be comprised of multiple instances of the memory cell 200 as shown in Fig. 2.

[0096] The FeFET 202 within each memory cell 200, as detailed in Fig. 2, may be the storage component that is responsible for retaining the state of the memory cell through its ferroelectric polarization properties. The program-signal circuit 206 and sense circuit 204 may be used for programming and reading of the FeFET 202, respectively. These circuits can interface with the PE array 102 in the Al accelerator, coordinating the storage and retrieval of data necessary for Al computations.

[0097] In the broader scope of the Al accelerator's 100 architecture, as represented in Fig. 1, each processing element 110 within the PE array 102 may leverage the non-volatile memory capabilities of the FeFET 202 to store the weights and parameters of artificial neural networks. The processing elements 110, which may include various computational units such as arithmetic logic units or neuromorphic computation elements, perform Al calculations in parallel, utilizing the data stored within the FeFET memory 112.

[0098] The integration of the memory cell 200 into the Al accelerator architecture can allow for an in-memory processing architecture. In this configuration, the memory cell 200, with its FeFET 202, acts not only as a storage unit but also as anactive participant in the computational process. For instance, the multiply-accumulate operations, a staple of neural network computations, can be performed efficiently and in parallel, thanks to the rapid state- switching capabilities and low power consumption of the FeFET 202.

[0099] Additionally, the Al accelerator 100 described in Fig. 1 may include a shared memory 104 and / or a shared memory 108, which can also utilize the FeFET memory cells as outlined in Fig. 2. These shared memory components act as a central repository for the computed data and instructions that are too large or not frequently accessed enough to reside within the individual FeFET memory cells 200 of the PE array 102.

[0100] The Network-on-Chip (NoC) 106 in Fig. 1 facilitates communication between the Al accelerator and other devices or computational units. The operation of the NoC 106 may be tied to the performance of the FeFET memory cells 200, as the speed at which data is transferred and accessed can influence the efficiency of the Al accelerator 100.

[0101] Referring to Figs. 2-3: Fig. 3 illustrates operating characteristics of the FeFET 202 of Fig. 2 in a graph 300 when used to store binary states in accordance with an embodiment of the present disclosure. The graph 300 shows an axis 302 that shows a current, Ids, that is the current from the drain 210, through the FeFET 202, and through the source 212 to ground. The current Ids passes through a channel of the FeFET 202 where the channel has characteristics based upon the polarization of the ferroelectric material. The graph 300 also includes an axis 304 that shows the voltage at the gate 208 of Fig. 2. The Vg values applied to the gate 208 may be within a range of voltages to determine the state of the FeFET without significantly disturbing the ferroelectric material’s polarization.

[0102] Fig. 3 illustrates the relationship between the Ids and Vg based upon the state of the FeFET 202 in accordance with an embodiment of the present disclosure. A first curve 306 shows the FeFET 202 in a first state because it has a first threshold voltage 308. A second curve 308 shows the FeFET 202 in a second state because it has a second threshold voltage 312. The states of the FeFET 202 may be programmed by the program-signal circuit 206 to change the electric polarization of the ferroelectric material in the FeFET 202. These states may be detected by the sense circuit 204. In some embodiments, no Vg voltage needs to be applied to the FeFET 202 to determinethe state; however, in other embodiments, a sufficient voltage needs to be applied to the gate 208 to determine the state of the FeFET 202, but without programming the FeFET 202.

[0103] Referring to Figs. 2 and 4: Fig. 4 illustrates operating characterizes of the FeFET 202 of Fig. 2 in a graph 400 when the FeFET 202 is used to store a continuous value, such as a weight of a neuromorphic cell, in accordance with an embodiment of the present disclosure.

[0104] The graph 400 shows an axis 402 for a current Ids. Ids is the current from the drain 210 through the FeFET 202 and through the source 212 to ground. The current Ids passes through a channel of the FeFET 202 where the channel has characteristics based upon the polarization of the ferroelectric material. The graph 400 also includes an axis 404 that shows the voltage at the gate 208 of Fig. 2. The Vg values applied to the gate 208 may be within a range of voltages to determine the state of the FeFET without significantly disturbing the ferroelectric material’s polarization.

[0105] Fig. 4 illustrates the relationship between the Ids and Vg based upon the polarization of the FeFET 202 in accordance with an embodiment of the present disclosure. As the polarization changes, the characteristic curve shifts as indicated by arrow 408. These shifting curves cause the threshold voltages 406 to shift as well. These values may be mapped to different discrete values, such as a weight of an artificial neural network. For example, an arithmetic logic unit may read these values for computation within a processing element of Fig. 1 within 3 ranges thereby making the FeFET 202 a base 3 digit, e.g., a trinary digit. In some embodiments, the memory is used as in-memory-computing, and along with other analog circuit, can perform the calculations of an artificial neural net in accordance with the mapped value corresponding to a weight of a neural network cell, e.g., neuron. During a neural network training phase, the Al accelerator 100 may use the program- signal circuit 206 to change the electric polarization of the ferroelectric material in the FeFET 202 to correspond to a neuron weight. These threshold voltages 406 may be detected by the sense circuit 204. In some embodiments, no Vg voltage needs to be applied to the FeFET 202 to determine its state; however, in other embodiments, a voltage is applied to the gate 208.

[0106] Fig. 5 illustrates an integrated circuit device 500, which may also be referred to as a three-dimensional memory array structure. The device 500 facilitatesthe selective addressing of individual memory cells within a grid, allowing for data storage and retrieval. The FeFETs are arrange in an orthogonal electrical configuration. That is, the plurality of vertical structures arranged in bit-line groups and select-line groups. Each of the plurality of vertical structures is a member of only a single bit-line group and is a member of only a single select-line group.

[0107] The integrated circuit device 500 is configured to include an array of interconnected components. In some embodiments, the device 500 is engineered to incorporate a multitude of memory cells, control circuits, and access lines, which collectively contribute to the functionality of a three-dimensional memory array. The architecture of device 500 is such that it can support 3D memory cells.

[0108] The array of bit lines 502 is composed of multiple bit lines, ranging from502_a to 502_m, each denoted by BL_1 to BL_M respectively. These bit lines may be configured to transmit electrical signals corresponding to binary data within the memory array. In various embodiments, the array of bit lines 502 can be manufactured using different conductive materials and may exhibit varying widths and thicknesses to accommodate different operational requirements, such as current carrying capacity and signal integrity.

[0109] Similarly, the array of select lines 504 includes a series of select lines extending from 504_a to 504_n, each labeled as SL_1 to SL_N. These select lines can be utilized to enable the selection of specific memory cells (e.g., FeFET transistor ferroelectric state) for reading or writing operations. The select lines 504 may be fabricated from materials and in dimensions that are optimized for their selective functionality within the memory array 500, while maintaining compatibility with the overall design of the integrated circuit device 500.

[0110] Source select line transistors 506, ranging from 506_a to 506_N, correspond to the select lines labeled as SL_1 to SL_N, respectively. Each source select line transistor is associated with a respective source select line, such as 504_b labeled as SL_2 having a corresponding transistor 506_b. These transistors can act as switches to control the flow of current to the memory cells and are used for the operation of the memory array. The transistors 506 may be designed in various configurations and sizes to suit the specific operational parameters of the memory array 500.

[0111] The word lines 508, extending from 508_a to 508_p and denoted as WL_1 to WL_P, represent horizontal gate-electrode layers that are not explicitly shownin Figure 5. These word lines can be used for accessing the memory cells and can be made from a variety of materials that ensure their functionality as gate electrodes. The word lines 508 are designed to intersect with the bit and select lines, thus forming a grid that allows for the addressing of individual memory cells.

[0112] The vertical structures 510 are arranged in a grid pattern of size N by M, aligning with the N bit lines and M select lines. Each vertical structure, exemplified by 510n,m, can be selected through its corresponding select line 504_n and bit line 502_m. These structures enable the three-dimensional aspect of the memory array, where each structure is associated with a unique addressable location within the grid. The specific design and composition of these vertical structures may vary, including different types of memory cells and materials to suit various operational requirements.

[0113] Fig. 5 elucidates the orthogonal configuration of the memory array within integrated circuit device 500. This configuration allows for selective activation of individual vertical structures. The orthogonal arrangement of bit lines 502 and select lines 504 allows for the discrete activation of memory cells by applying voltage to the corresponding lines. The figure visually represents this concept, with bit lines portrayed horizontally and select lines vertically, demonstrating the orthogonal crossing of these lines and substantiating the claims related to the orthogonal architecture of the memory array. Orthogonality, as described herein, refers to the electrical wiring arrangement and not necessarily a spatial arrangement.

[0114] In a typical data storage operation, a specific vertical structure 510_n,m is targeted by selecting the corresponding bit line 502_m and select line 504_n. The source select line transistor associated with the select line, for example, 506_n, is activated to connect the select line to the vertical structure. Simultaneously, a control signal is sent through the appropriate word line 508_p to the gate electrode layers, which prepares the memory cell within the vertical structure for data writing. The bit line then carries the write data signal to the vertical structure, where the memory cell's state is altered to represent the new data.

[0115] For data retrieval, a similar selection process is employed, where the bit line and select line corresponding to the desired vertical structure are activated. However, instead of writing data, the word line induces a state in the memory cell that allows the sensing of its current state. The sensed signal is then carried back throughthe bit line, representing the stored data, which is subsequently processed by the memory controller or other peripheral circuits.

[0116] The integrated circuit device 500 orchestrates the coordination between these various components through control circuitry, which can include decoders, drivers, and sensing amplifiers. These circuits interpret commands from an external processor or controller and translate them into the necessary signals for the bit lines, select lines, word lines, and source select line transistors. The control circuitry ensures that the precise timing and voltage levels are applied to the components to facilitate the correct operation of the memory array.

[0117] The design of the integrated circuit device 500 capitalizes on the principle of selective activation, ensuring that when a command is issued to access a particular memory cell, only the designated vertical structure is activated. This selective activation may be used for managing leakage current, which is the unintended flow of electrical current within a device when it is in a non-operational state. In the context of the memory array, leakage current is relevant to the ferroelectric field-effect transistors (FeFETs) that constitute the memory cells within the vertical structures 510.

[0118] When a read or write operation is initiated, the control circuitry of the integrated circuit device 500 sends signals to activate a specific bit line 502 and select line 504, which intersect at the desired vertical structure 510. Concurrently, the corresponding source select line transistor 506, for the chosen select line, is turned on. This process electrically isolates the selected vertical structure from the rest of the array, directing operational current exclusively through the FeFETs within that structure.

[0119] The isolation of the vertical structure has a significant impact on minimizing leakage current. Since the unselected FeFETs remain electrically disconnected, the only path for leakage current is through the FeFETs within the activated vertical structure. This confinement of leakage to a single column of FeFETs reduces the overall leakage current in the memory array. The benefits of this reduction are multifold and is described as follows:

[0120] Current Savings: By limiting leakage current to a single vertical structure, the integrated circuit device 500 conserves current that would otherwise be lost through inactive FeFETs. This conservation contributes to a lower power consumption profile for the memory array, making it more energy -efficient and suitable for battery-powered applications.

[0121] Energy Efficiency: The reduction in leakage current correlates directly to energy savings. Energy that would be dissipated as heat due to leakage in unselected FeFETs is preserved, enhancing the energy efficiency of the device. This efficiency is beneficial in high-density memory arrays.

[0122] Improved Read Times: By focusing the operational current through the selected vertical structure, the integrated circuit device 500 can achieve faster read times. The sensing circuits, which detect the state of the memory cells, encounter less background noise and interference from leakage currents in other parts of the array. This allows for quicker reads of the stored data.

[0123] Enhanced Device Longevity: Leakage current not only impacts energy consumption but can also lead to increased wear and degradation of electronic components over time. By minimizing leakage current, the integrated circuit device 500 can potentially extend the operational lifespan of the memory array, as the FeFETs are subjected to less electrical stress during inactive periods.

[0124] Fig. 6A shows an integrated circuit device 600. This device 600 facilitates the selective electrical access of individual memory cells arranged vertically in columns and horizontally in rows within the array grid.

[0125] The device 600 incorporates an array of vertical structures 622 that constitute the core memory components. Each vertical structure column, labeled from 622_a,a to 622_n,m, form a functional memory cell, including source electrodes, drain electrodes, channel regions, and a ferroelectric material. The first subscript on each vertical structure indicates its association with a particular select line 602, while the second subscript correlates to a specific bit line 606. This allows each vertical structure column to be uniquely addressed via the corresponding select line 602 and bit line 606.

[0126] The vertical structures 622 are positioned orthogonal to the bit lines 606 and select lines 602, which run horizontally and vertically, respectively. The bit lines 606, labeled from 606_a to 606_m as (BL1, BL2, ..., BLM), are arranged on top of the vertical structures 622 and are electrically connected to the source electrodes of each column. The select lines 602, labeled from 602_a to 602_n as (SL1, SL2, ..., SLN), are wired alongside the vertical structures and are electrically coupled to the drain electrodes within each column.

[0127] The select lines 602 each have an accompanying source select line transistor 604, labeled as 604_a to 604_n (SSL1, SSL2, ..., SSLN). These transistorsact as switches to control current flow from the select lines 602 into the individual vertical structures 622. This allows for the specific selection of vertical structures for read or write operations.

[0128] Additionally, the integrated circuit device 600 contains horizontal gateelectrode layers, denoted as WL and ranging from WLi to WLp, that are layered underneath the vertical structures 622. By applying voltages to these layers, the electrical behavior of the memory cells within the vertical structures can be modulated, enabling control over functions like read, write and erase.

[0129] The various components within the device 600 are orchestrated through peripheral control circuits (not shown). These circuits provide precise timing and activation signals to the bit lines 606, select lines 602, source select line transistors 604, and gate-electrode layers to facilitate the storage and retrieval of data from addressed memory cell locations. They allow the integrated circuit device 600 to leverage electrical isolation and selective activation to optimize memory operations.

[0130] The integrated circuit device 600 utilizes a three-dimensional arrangement of vertically-oriented memory cell structures intersected by horizontally- wired electrical access lines. The device 600 provides capabilities to store both binary and analog data through the polarization states of the ferroelectric elements within the vertical structures 622.

[0131] In various embodiments, each vertical structure 622 may be configured as a column-type structure composed of multiple thin film layers built vertically over one another. These layers can include, from bottom to top, a vertical-plug column, source electrode column, drain electrode column, channel column surrounding the other columns, and a ferroelectric column encasing the channel column. Additional components like blocks, pads, vias, insulators, etc. can also be incorporated as needed.

[0132] The ferroelectric columns in the vertical structures 622 exhibit polarized domains that enable non-volatile data storage. The polarity and orientation of these domains can be adjusted by applying suitable voltages to the horizontal gate-electrode layers (word lines) 608 surrounding the vertical structures. This provides the programming mechanism for writing data into the vertical structures.

[0133] In some embodiments, the vertical structures 622 may feature additional elements like blocking layers, buffer layers, capping layers, cladding layers etc. to enhance functionality. For instance, layers to reduce leakage current, improveadhesiveness, provide etch selectivity, or mitigate material diffusion can be embedded within the composition of the vertical structures.

[0134] Furthermore, the dimensions of the vertical structures 622 including thickness and width of the thin film layers may be optimized to achieve desired device performance. Reducing equivalent oxide thickness and minimizing parasitic capacitance between adjacent vertical structures could be targeted through dimensional tuning.

[0135] As previously mentioned, the integrated circuit device in Fig. 6A includes a plurality of bit lines labeled 606, specifically 606_a through 606_m, that are referenced as BL1 through BLM. The bit lines 606 run horizontally across the top of the array of vertical structures 622. In some embodiments, the bit lines 606 are formed from conductive materials such as metals, doped polysilicon, silicides, or other conductive compounds or alloys. The bit lines 606 may have varying widths and thicknesses depending on desired operational parameters such as current carrying capacity, resistance, capacitance, and signal integrity. For example, wider or thicker bit lines 606 may carry more current but take up more area, while narrower or thinner bit lines may have higher resistance but allow for greater array density. The dimensions of the bit lines 606 can be optimized based on factors such as read / write speed, power consumption, and fabrication constraints.

[0136] The select lines 602, referenced as 602_a through 602_n, represent the select lines SL1 through SLN as depicted in Fig. 6A. These select lines run vertically and are electrically coupled to the source electrodes of the vertical structures 622. When a specific select line is activated, it enables the selection of the vertical structures in that particular column for memory access operations.

[0137] The select lines 602 may be manufactured from conductive materials such as metals, doped polysilicon, silicides, or other suitable materials that provide adequate conductivity and compatibility with semiconductor fabrication processes. The dimensions including line width and thickness can be optimized based on resistivity, current density requirements, scaling trends, and other device design considerations. In some embodiments, each select line 602 may have an associated source select line transistor 604, which acts as a switch to control the connection between the select line and the vertical structure source electrodes. These source select line transistors 604allow current to flow through when activated, facilitating operations such as reading or writing to the memory cells.

[0138] In typical operation scenarios, the select lines 602 receive signals from the memory array's peripheral circuits and decoders. When a read command is issued, the appropriate vertical structure 622 is activated by the coordinated application of voltages to the corresponding bit line 606 and select line 602. This prompts the associated source select line transistor 604 to allow current flow through the vertical structure. The selectivity imparted by the select lines is key for managing leakage currents and ensuring energy efficiency.

[0139] The select lines 602 may be designed with various widths and spacing to optimize performance metrics such as signal delays, crosstalk, and area efficiency. Advanced fabrication techniques like self-aligned patterning can potentially be employed to scale the select lines to tight pitches and greater densities. Overall, the select lines 602 enable vital selective accessing functions that underpin the core operations of the 3D memory array.

[0140] In some embodiments, the source select line transistors 604 may act as selection transistors for blocks of vertical structures 622, choosing an entire block rather than individual vertical structures. In other embodiments, each source select line transistor 604 maps to a single vertical structure 622 for precise selection.

[0141] The source select line transistors 604 can be manufactured directly on top of the vertical structures 622, contributing to the three-dimensional nature of the memory array architecture. Additionally, the transistors 604 may feature self-aligned gate structures for reduced cell size and enhanced density.

[0142] By operating as an address selection switch, the source select line transistors 604 help direct the operational currents through only the desired vertical structures 622, while reducing leakage currents in non-selected structures. This improves energy efficiency, speed, and longevity of the FeFET memory array.

[0143] The switching behavior of the source select line transistors 604 is controlled by appropriate bias voltages delivered through the select lines 602. The select line driver circuits modulate these bias voltages based on commands from the memory controller. This allows the controller to activate specific source select line transistors 604 integrated within the memory architecture.

[0144] In some implementations, the source select line transistors 604 are equipped with built-in current limiting or protection mechanisms to mitigate issues related to overcurrent or latchup, enhancing the reliability of the memory system. Additionally, redundant or backup source select line transistors 604 may be incorporated to circumvent potential faults or degradation of individual transistors over time.

[0145] The integration of the source select line transistors 604 into the orthogonal architecture of the ferroelectric memory array provides an efficient means of choosing target memory cells while confining operational currents to only the selected vertical structures 622. This minimizes power loss due to leakage, making the architecture suitable for energy-constrained applications.

[0146] The horizontal gate-electrode layers (WL1, WL2, ..., WLP) represent gate electrode layers that extend horizontally in the integrated circuit device. These horizontal gate-electrode layers are disposed at predetermined vertical distances from one another, with oxide layers interposed between them. The horizontal gate-electrode layers are positioned adjacent to the vertical structures in the device.

[0147] In some embodiments, the horizontal gate-electrode layers may be comprised of doped polysilicon or metal. The horizontal gate-electrode layers facilitate access to the individual memory cells within the vertical structures by applying voltage signals that induce polarization states in the ferroelectric material. This enables control over the programming, reading, and erasing operations of the FeFET memory cells.

[0148] The positioning of the horizontal gate-electrode layers relative to the vertical structures allows for efficient access to the memory cells along the vertical direction. By activating the appropriate word lines that link to specific horizontal gateelectrode layers, the memory cells at desired vertical locations can be addressed. This configuration enables stacking multiple layers of memory cells vertically, contributing to the high density and 3D nature of the memory array architecture.

[0149] In some implementations, the horizontal gate-electrode layers may include dielectric layers between them to minimize gate leakage current. Additionally, the predetermined vertical distance between horizontal gate-electrode layers can be optimized to mitigate short channel effects in the FeFETs within the vertical structures. Overall, the horizontal gate-electrode layers play a vital role in operating the 3D memory array by interfacing the external control circuitry with the individual memorycells integrated along the vertical structures. The horizontal gate-electrode layers, coupled with vertical bit lines and select lines, allow for precise addressing and control of the FeFET memory cells.

[0150] Fig. 6B shows a cross-sectional view of the vertical structure 622n,m of Fig. 6A. The vertical structure 622n,m represents an individual memory cell within the three-dimensional memory array 600. It includes a vertical stack of thin film layers: a vertical-plug column 612, source electrode column 616, drain electrode column 614, channel column 620, and a ferroelectric column 618. The vertical-plug column 612 is made of silicon nitride and acts as a barrier between the source and drain. The source electrode column 616 connects to a bit line to receive signals, while the drain electrode column 614 connects to a select line. The channel column 620 provides a conduction path modulated by the ferroelectric column 618, which stores data based on polarization states. Together, these layers form a vertically-oriented FeFET structure that enables high-density, non-volatile data storage when integrated within the memory array architecture. The vertical structure 622n,m can be individually addressed for read / write operations by activating the corresponding bit line and select line.

[0151] In alternative embodiments, a variation may involve the geometric configuration of the vertical structure 622n,m. While a cylindrical shape is a common choice, alternative geometries such as a hollow cylindrical, coaxial, or multi-faceted arrangement might be utilized. These variations in shape can influence the charge carrier flow in the channel column 620. Moreover, the vertical structure 622n,m may be designed with an inner core for the vertical-plug column 612 that features a graded composition transitioning from one material at the interface with the source electrode column 616 to another at the interface with the channel column 620. This gradation could tailor the electric field distribution within the memory cell, which in turn may optimize the read / write characteristics, reduce hot carrier injection, or improve endurance.

[0152] In yet additional embodiments, incorporation of additional elements may be used in the vertical structure 622n,m. For instance, adding a stress-mitigating layer between the oxide layer 610 and the ferroelectric column 618 may be used to alleviate mechanical stresses that arise from thermal expansion mismatches among adjacent materials to enhance the reliability of the memory cell.

[0153] The oxide layer 610 is an insulating layer disposed between the vertical structures 622 and the horizontal gate-electrode layers in the integrated circuit device. The oxide layer 610 serves to electrically isolate the vertical structures from the gateelectrode layers, preventing current leakage between these components.

[0154] In some embodiments, the oxide layer 610 is composed of silicon dioxide or other dielectric materials. The thickness of the oxide layer 610, represented as T_ox, can range from 5 nm to 50 nm in order to provide adequate electrical isolation while maintaining sufficient capacitive coupling between the vertical structures 622 and horizontal gate-electrode layers for proper device operation.

[0155] The inclusion of the oxide layer 610 facilitates the application of voltage signals to the horizontal gate-electrode layers, which induces polarization states in the ferroelectric material of the vertical structures 622. This enables control over functions like programming, reading, erasing etc. of the FeFET memory cells integrated within the vertical structures.

[0156] In some embodiments, the oxide layer 610 may incorporate high-k dielectric materials such as hafnium oxide (HfO2), zirconium dioxide (ZrO2), or a combination thereof, to enhance the dielectric constant and reduce the equivalent oxide thickness (EOT), thereby improving the electrostatic control within the memory device. The integration of such materials into the oxide layer 610 may be tailored to suit specific operational requirements. Additionally, the oxide layer 610 may be deposited using atomic layer deposition (ALD) techniques to achieve uniformity and control over layer thickness.

[0157] Further, in some specific embodiments, the oxide layer 610 may be embodied as a multi-layer structure where individual layers possess varying dielectric properties that are hierarchically organized to accomplish a predetermined effect. For instance, the oxide layer 610 may optionally consist of a silicon dioxide base layer followed by a hafnium oxide layer and a silicon nitride capping layer, creating a stratified insulation system that enhances the electrical insulation and / or the thermal stability and resistance to material diffusion from adjacent layers.

[0158] In some implementations, the oxide layer 610 may optionally include dopants such as nitrogen, aluminum, or lanthanides to modify and refine its electrical properties and structural stability. The presence of such dopants can be controlled to tailor the dielectric constant and bandgap characteristics in a manner that complementsthe operational paradigm of the memory array. Doping may also serve to suppress leakage currents and enhance the thermal stability of the oxide layer 610. In some specific embodiments, the oxide layer 610 can optionally be configured to either be uniformly distributed within the oxide layer or gradiently, with dopant concentration varying from one surface to another, thereby creating an oxide layer with spatially tuned electrical properties.

[0159] Moreover, the oxide layer 610 can possess a design that enables self- healing properties against dielectric breakdown. The inclusion of certain metallic or organic additives within the oxide material could provide the layer with the capability to repair itself upon minor electrical disruptions, thus extending the longevity and durability of the structure. This self-healing characteristic can be of significant value in applications where the device is subject to repetitive electrical cycling, potentially leading to dielectric wear and fatigue over time.

[0160] In situations where the oxide layer 610 operates within an oxidative or corrosive environment, an embodiment may include a protective layer that specifically addresses corrosion resistance. Materials such as ruthenium oxide or iridium oxide could be added to the oxide layer 610, thus bestowing upon the layer enhanced resistance against environmental attack. This protective layer may encompass the entire oxide layer or be localized to regions prone to exposure, based on the specific design requirements of the memory array.

[0161] Furthermore, in additional embodiments, to adapt to stringent scaling demands of contemporary electronics, the oxide layer 610 may optionally be designed with a graded index profile where the dielectric constant varies through the depth of the layer.

[0162] The vertical-plug column 612 is a thin film layer within the vertical structure 622n,m. It is made of silicon nitride (SiN) and is positioned between the source electrode column 616 and the drain electrode column 614, serving as an insulating barrier layer between them. The vertical-plug column 612 enables the vertical stacking of the other components like the source and drain electrode columns while preventing electrical shorts. Its integration allows for the three-dimensional nature of the memory array architecture. The dimensions including thickness of the vertical-plug column 612 may be optimized to achieve desired electrical isolation between adjacent electrode columns. Overall, the vertical -plug column 612 facilitates the high-density packing ofmemory components within the vertical structures 622n,m while mitigating leakage paths.

[0163] In some embodiments, the vertical-plug column 612 can be crafted with multiple layers, wherein each layer has differing electrical or physical characteristics to facilitate graded barrier properties. For example, one may incorporate layers that gradually transition from a highly insulating material to a semi-conductive material, thus tailoring the column’s barrier behavior in a precise manner. Additionally, the vertical-plug column 612 might be doped with various dopants to adjust its conductivity or barrier height, depending on the desired electron or hole transport characteristics.

[0164] Moreover, the concept of the vertical-plug column 612 is not delimited to a solid structure. In alternative embodiments, the vertical-plug column may embrace a composite structure, including a hollow core or a core filled with another material that provides additional functionality such as thermal management or facilitates the diffusion of dopants during manufacturing. The exterior of the vertical-plug column 612 could be treated or coated with a material that promotes adhesion with adjacent components or could have a textured surface to enhance mechanical interlocking with the channel column 620 or oxide layer 610.

[0165] The cross-sectional geometry of the vertical-plug column 612 can also be varied; beyond the simple cylindrical shape, embodiments may include shapes such as square, rectangular, hexagonal, or even more complex geometries constructed to optimize the overlap with surrounding electrode columns or to conform to specific stress profiles within the vertical structure 622n,m. Shapes may be architected to minimize stress points or to distribute applied electrical fields in a beneficial fashion.

[0166] In terms of manufacture, the vertical-plug column 612 may be deposited using a variety of techniques including, but not limited to, chemical vapor deposition, atomic layer deposition, physical vapor deposition, or electrochemical deposition. The chosen fabrication method can influence the microstructure of the column, which in turn may impact electrical or mechanical properties. Subsequent treatments like annealing or laser recrystallization could be applied to refine the microstructure or to achieve a desired phase composition of the materials present within the vertical-plug column 612.

[0167] Furthermore, the material of the vertical-plug column 612 might be selected for compatibility with other memory elements or for certain endurancecharacteristics under operational stressors such as electric field cycling or thermal cycles. This may be vital for ensuring the stability and longevity of the vertical structure 622n,m under typical operating conditions of the memory array 600.

[0168] In some embodiments, the vertical-plug column 612 is not a singular entity but rather a collection of nanowires or nanopillars which collectively serve as a plug. This nanoscale architecture can improve the overall surface area and may enhance the plug's interaction with adjacent elements. It also could provide benefits in the form of reduced impact from structural defects or allow for the exploitation of quantum effects which may be desirable in certain memory designs.

[0169] The drain electrode column 614 is disposed adjacent to the vertical-plug column 612. The drain electrode column 614 is electrically coupled to the select lines 602. The select lines 602 interface with the drain electrodes to enable selective accessing of the vertical structures 622 for memory operations. When a specific select line 602 is activated along with a bit line 606, the drain electrode column 614 of the corresponding vertical structure 622 is activated, allowing current to flow through the structure. The drain electrode column 614 provides electrical connectivity from the select lines 602 to the individual vertical structures 622 of the memory array.

[0170] The drain electrode column 614 establishes an electrical path within the memory cell array, may use various materials. In some embodiments, the drain electrode column might optionally comprise various conductive materials such as copper, tungsten, aluminum, or alloys thereof, each selected to optimize attributes such as conductivity, reliability, thermal characteristics, and compatibility with surrounding structures. To mitigate electromigration and enhance performance at high current densities, the drain electrode column may integrate a composite structure, featuring a core material for structural integrity, surrounded by a shell of a different material chosen for its superior conductive properties, in some specific embodiments.

[0171] Geometric variations of the drain electrode column are also conceivable, wherein the cross-sectional profile of the column could be tailored beyond the conventional circular or elliptical shapes, becoming polygonal or incorporating complex multidimensional profiles. Such profiles can be designed to increase surface contact with adjacent layers or to maximize packing density within the vertical structure 622n,m. This variability in column geometry may be driven by lithographic techniques and etching processes that allow for patterning of various shapes.

[0172] Furthermore, various connectivity options to the drain electrode column may be optionally utilized. For instance, in certain embodiments, the column may integrate multiple connection points, allowing for redundant or bifurcated pathways to improve signal distribution or provide alternative paths in case of partial failure. Additionally, interconnections between the drain electrode columns of adjacent vertical structures may be implemented to facilitate inter-cell communication or data redundancy schemes, improving error correction capabilities and overall memory resilience.

[0173] Additionally or alternatively, insulating materials with high dielectric constants could be selectively incorporated within or around the drain electrode column to enhance capacitive coupling for faster signal propagation or to attenuate cross-talk between adjacent columns in dense array configurations.

[0174] In additional optional embodiments, variations in the interfacing of the drain electrode column with the vertical-plug column 612 and source electrode column 616 may involve barrier layers with diffusion-blocking properties or selective adhesion characteristics, tailored to the specific materials used within each column. This could help maintain structural integrity and electrical isolation, key factors for stable and reliable operation over a wide array of environmental conditions and operational stressors.

[0175] The source electrode column 616 is a vertical conductive column that is disposed adjacent to the vertical-plug column 612. The source electrode column 616 receives electrical signals from the bit lines and conducts these signals to the channel column 620 during read / write operations. This allows data to be written to or read from the ferroelectric column 618 via the channel column 620. The source electrode column 616, along with the drain electrode column 614 on the opposite side of the channel column 620, enables selective accessing of the memory cell within each vertical structure 622n,m. The source electrode column 616 is positioned orthogonally to the select lines and is activated when both the corresponding bit line and select line are turned on. This architecture allows individual vertical structures to be addressed for memory access.

[0176] In some embodiments, the source electrode column 616 may be configured to possess a rectangular or square cross-section, rather than a round one. In further embodiments, the source electrode column 616 may not be a singular columnbut rather a composite structure consisting of multiple smaller columns or fingers. This multi-column approach may be configured togreater surface area for interface with the vertical-plug column 612, channel column 620, and oxide layer 610, thus potentially improving electrical contact and enhancing overall device performance. These miniaturized columns can be arranged in various patterns, such as parallel arrays or interlocking comb-like structures, etc.

[0177] Various materials may be used for the source electrode column 616, and may include conductive metals or conductive compounds, doped semiconductor materials, conductive ceramics, carbon-based materials such as graphene or carbon nanotubes, etc. Each material choice brings distinct electrical, thermal, and mechanical properties, thus offering the potential to tailor the source electrode column 616 to specific environmental conditions or operational demands.

[0178] In some specific embodiments, the source electrode column 616 may optionally incorporate a gradient of material compositions along its length. For instance, the base of the column, proximate to the contact with the vertical-plug column 612, may consist of a first conductive material offering additional mechanical support, while the upper sections interfacing with the channel column 620 may transition to a second material that presents a lower resistance or increased compatibility with the channel materials.

[0179] The surface characteristics of the source electrode column 616 may also vary. In some embodiments, the surface may be treated or coated to enhance its properties, such as through oxidation, nitridation, doping, or the application of conductive films. Surface treatments can change the characteristics such as conductivity, contact resistance with adjacent columns, act as diffusion barriers improving device longevity and reliability, etc.

[0180] Additionally, alternative embodiments can imbue the source electrode column 616 with multi-functional capabilities. For example, the column could be designed to serve dual roles, such as also acting as a heat sink for the vertical structure 622n,m, thereby dissipating heat generated during memory operations. This can be achieved by selecting materials with high thermal conductivity for the source electrode column 616 and configuring the column's geometry to maximize thermal dissipation.

[0181] The ferroelectric column 618 is comprised of a ferroelectric material and is disposed around the channel column 620 of each vertical structure 622. Theferroelectric column 618 retains polarization states that represent stored data bits. By applying voltages to the horizontal gate-electrode layers, the polarity of domains in the ferroelectric material can be modulated, thereby programming the state of the memory cell. When activated, a voltage difference between the source electrode column 616 and drain electrode column 614 results in a current flowing through the channel column 620 that is affected by the polarization of the surrounding ferroelectric column 618. This polarization-modulated channel current is then detected by the sense amplifiers to read the stored data state. The integration of the ferroelectric column 618 enables nonvolatile data storage capabilities for the vertical structure 622, allowing the memory cell to retain information without continuous power.

[0182] In one embodiment, the ferroelectric column 618 may incorporate stratified layers of different ferroelectric materials, each susceptible to polarization at distinct voltage thresholds. Such a layered structure can allow for multi-level data storage where different layers retain separate bits of information.

[0183] In yet another embodiment, the ferroelectric column 618 can be designed with a gradient ferroelectric material, where the composition varies continuously or step-wise along its length or radius. This gradation in the ferroelectric properties can be used to fine-tune the polarization characteristics and thus control the memory states.

[0184] The ferroelectric column 618 may also optionally feature nanostructures or dopants introduced into the ferroelectric material to create engineered domains that could help in reducing coercive fields or enhancing retention times. The distribution and concentration of these dopants can be controlled to achieve desired alterations in the ferroelectric behavior.

[0185] Additionally, in some embodiments, the ferroelectric column 618 may possess an adaptive cross-sectional shape. Rather than a circular or standard shape, the ferroelectric column can take on ellipsoidal, rectangular, or other non-standard geometric forms. These varying shapes can influence the electric field distribution within the memory cell, thereby impacting device performance characteristics such as switching speeds, endurance, retention, etc.

[0186] The ferroelectric column 618 can be manufactured using various techniques including deposition techniques such as atomic layer deposition (ALD), chemical vapor deposition (CVD), or physical vapor deposition (PVD), with eachtechnique providing a unique set of benefits in terms of film uniformity, material quality, and compatibility with underlying structures.

[0187] In an additional embodiment, the ferroelectric column 618 can be enveloped with barrier layers made of materials that help in reducing oxygen vacancies or suppressing interface reactions. These barrier layers can contribute to the stability and longevity of the ferroelectric properties, which is crucial for maintaining the integrity of the stored data over extended periods.

[0188] The channel column 620 is a component within the vertical structures 622 that provides a conduction path for charge carriers between the source electrode column 616 and drain electrode column 614. The channel column 620 is disposed surrounding the vertical-plug column 612, source electrode column 616, and drain electrode column 614. It is in turn surrounded by the ferroelectric column 618. When suitable voltages are applied to the gate electrode layers 608, an accumulation channel or depletion region can be created within the channel column 620 to enable or inhibit the flow of current between source and drain. The dimensions and composition of the channel column 620 influence parameters such as on-current, threshold voltage, subthreshold swing and channel resistance that impact the operational efficiency of the FeFET memory cells. The channel column may be optimized to achieve the desired memory cell characteristics depending on factors such as read / write speed, power consumption, data retention, etc.

[0189] Various alternatives and modifications can be devised by those skilled in the art without departing from the disclosure. Accordingly, the present disclosure is intended to embrace all such alternatives, modifications and variances. Additionally, while several embodiments of the present disclosure have been shown in the drawings and / or discussed herein, it is not intended that the disclosure be limited thereto, as it is intended that the disclosure be as broad in scope as the art will allow and that the specification be read likewise. Therefore, the above description should not be construed as limiting, but merely as exemplifications of particular embodiments. And, those skilled in the art will envision other modifications within the scope and spirit of the claims appended hereto. Other elements, steps, methods and techniques that are insubstantially different from those described above and / or in the appended claims are also intended to be within the scope of the disclosure.

[0190] The embodiments shown in the drawings are presented only to demonstrate certain examples of the disclosure. And, the drawings described are only illustrative and are non-limiting. In the drawings, for illustrative purposes, the size of some of the elements may be exaggerated and not drawn to a particular scale. Additionally, elements shown within the drawings that have the same numbers may be identical elements or may be similar elements, depending on the context.

[0191] Where the term "comprising" is used in the present description and claims, it does not exclude other elements or steps. Where an indefinite or definite article is used when referring to a singular noun, e.g., "a," "an," or "the,” this includes a plural of that noun unless something otherwise is specifically stated. Hence, the term "comprising" should not be interpreted as being restricted to the items listed thereafter; it does not exclude other elements or steps, and so the scope of the expression "a device comprising items A and B" should not be limited to devices consisting only of components A and B. This expression signifies that, with respect to the present disclosure, the only relevant components of the device are A and B.

[0192] Furthermore, the terms "first," "second," "third," and the like, whether used in the description or in the claims, are provided for distinguishing between similar elements and not necessarily for describing a sequential or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances (unless clearly disclosed otherwise) and that the embodiments of the disclosure described herein are capable of operation in other sequences and / or arrangements than are described or illustrated herein.

[0193] Each of the characteristics and examples described herein, and combinations thereof, may be said to be encompassed by the present disclosure. The present disclosure is thus drawn to the following non- limiting numbered aspects:

[0194] 1. An integrated circuit device, comprising: a plurality of vertical structures arranged in bit- line groups and select- line groups, wherein each of the plurality of vertical structures is a member of only a single bit-line group and is a member of only a single select-line group, each of the plurality of vertical structures comprising: an insulating vertical-plug column; a source electrode column disposed adjacent to the insulating vertical-plug column; a drain electrode column disposed adjacent to the insulating vertical-plug column; a channel column disposed around the insulating vertical-plug column, the source electrode column, and the drain electrodecolumn; and a ferroelectric column disposed around the channel column; a plurality of horizontal gate-electrode layers, each of the plurality of horizontal gate-electrode layers disposed a predetermined vertical distance between each other, each of the plurality of horizontal gate-electrode layers disposed adjacent to each of the plurality of vertical structures; a plurality of bit lines, each of the bit lines corresponds to a respective bit- line group, each of the bit lines electrically coupled to a respective source electrode column of the plurality of vertical structures; and a plurality of select lines, each of the select lines corresponds to a respective select-line group, each of the select lines is electrically coupled to a respective drain electrode column of the plurality of vertical structures.

[0195] 2. The integrated circuit device according to aspect 1, wherein the bit- line groups are electrically orthogonal to the select-line groups.

[0196] 3. The integrated circuit device according to aspect 1 , further comprising a plurality of dielectric layers interdigitated with the plurality of horizontal gateelectrode layers.

[0197] 4. The integrated circuit device according to aspect 1 , wherein when a bit-line of the plurality of bit lines is activated and a select line of the plurality of select lines is activated, a single one of the plurality of vertical structures is activated.

[0198] 5. The integrated circuit device according to aspect 4, wherein current flows through the single one of the plurality of vertical structures when activated.

[0199] 6. The integrated circuit device according to aspect 1 , wherein current flows through only the one or more active vertical structures of the plurality of vertical structures.

[0200] 7. The integrated circuit device according to aspect 1, wherein each of the plurality of bit lines are substantially parallel to each other.

[0201] 8. The integrated circuit device according to aspects 1 or 7, wherein each of the plurality of select lines are substantially parallel to each other.

[0202] 9. The integrated circuit device according to aspect 1 , further comprising a plurality of source select transistors, where each of the plurality of source select transistors is coupled to a single select line of the plurality of select lines.

[0203] 10. The integrated circuit device according to aspect 1, wherein the plurality of vertical structures is configured to form a 3D-N0R memory array.

[0204] 11. The integrated circuit device according to aspect 1, wherein the plurality of bit lines are orthogonal to the plurality of select lines.

[0205] 12. The integrated circuit device according to aspect 1, wherein each of the plurality of bit lines do not have a respective bit- line selector transistor.

[0206] 13. The integrated circuit device according to aspect 1, wherein the source electrode column and the drain electrode column are formed from a common material.

[0207] 14. The integrated circuit device according to any of aspects 1 to 13, wherein the plurality of bit lines electrically coupled to a respective source electrode column of the plurality of vertical structures.

[0208] 15. The integrated circuit device according to aspect 1, wherein the vertical structure is configured to have an elliptical cross-sectional shape.

[0209] 16. The integrated circuit device according to aspect 1, wherein the vertical structures are configured to minimize capacitive coupling between adjacent bit- line groups.

[0210] 17. The integrated circuit device according to aspect 1, wherein the horizontal gate-electrode layers include a dielectric layer to reduce gate leakage current.

[0211] 18. The integrated circuit device according to aspect 1, wherein the predetermined vertical distance between the horizontal gate-electrode layers is optimized to reduce short channel effects.

[0212] 19. The integrated circuit device according to aspect 1, wherein the plurality of vertical structures is arranged such that the bit-line groups and select-line groups form a non-volatile memory unit.

[0213] 20. An integrated circuit device, comprising: a plurality of vertical structures arranged in bit-line groups and select- line groups, wherein each of the plurality of vertical structures is a member of only a single bit-line group and is a member of only a single select-line group, each of the plurality of vertical structures comprising: a source electrode; a drain electrode; a channel disposed in electrical communication with the source and drain electrodes; and a ferroelectric material disposed in spaced relation to the channel to affect the channel; a plurality of horizontal gate-electrode layers, each of the plurality of horizontal gate-electrode layers disposed a predetermined vertical distance between each other, each of the plurality of horizontal gate-electrode layers disposed adjacent to each of the plurality of vertical structures; aplurality of bit lines, each of the bit lines corresponds to a respective bit- line group, each of the bit lines electrically coupled to a respective source electrode of the plurality of vertical structures; and a plurality of select lines, each of the select lines corresponds to a respective select-line group, each of the select lines is electrically coupled to a respective drain electrode of the plurality of vertical structures.

[0214] 21. The integrated circuit device according to aspect 20, wherein when a bit-line of the plurality of bit lines is activated and a select line of the plurality of select lines is activated, a single one of the plurality of vertical structures is activated.

[0215] 22. The integrated circuit device according to aspect 21, wherein current flows through the single one of the plurality of vertical structures when activated.

[0216] 23. The integrated circuit device according to aspect 20, wherein current flows through only the one or more active vertical structures of the plurality of vertical structures.

[0217] 24. The integrated circuit device according to aspect 20, wherein each of the plurality of bit lines are substantially parallel to each other.

[0218] 25. The integrated circuit device according to aspects 20 or 24, wherein each of the plurality of select lines are substantially parallel to each other.

[0219] 26. The integrated circuit device according to aspect 20, further comprising a plurality of source select transistors, where each of the plurality of source select transistors is coupled to a single select line of the plurality of select lines.

[0220] 27. The integrated circuit device according to aspect 20, wherein the plurality of vertical structures is configured to form a 3D-N0R memory array.

[0221] 28. The integrated circuit device according to aspect 20, wherein the plurality of bit lines are orthogonal to the plurality of select lines.

[0222] 29. The integrated circuit device according to aspect 21, wherein each of the plurality of bit lines do not have a respective bit-line selector transistor.

[0223] 30. The integrated circuit device according to any of aspects 20 to 29, wherein each of the plurality of bit lines electrically coupled to a respective source electrode of the plurality of vertical structures.

[0224] 31. The integrated circuit device according to aspect 1 or 20, wherein the plurality of vertical structures are arranged in a three-dimensional array configuration.

[0225] 32. The integrated circuit device according to aspect 1 or 20, further comprising a plurality of word lines, each of the plurality of word lines coupled to a respective one of the plurality of horizontal gate-electrode layers.

[0226] 33. The integrated circuit device according to aspect 1 or 20, wherein the plurality of vertical structures are configured to store data in a non-volatile manner.

[0227] 34. A method of manufacturing an integrated circuit device, the method comprising: forming a plurality of vertical structures in bit- line groups and select-line groups, wherein each vertical structure is a member of only a single bit-line group and a single select-line group, and each vertical structure is formed by: forming an insulating vertical -plug column; forming a source electrode column adjacent to the insulating vertical-plug column; forming a drain electrode column adjacent to the insulating vertical-plug column; forming a channel column disposed around the insulating vertical-plug column, source electrode column, and drain electrode column; forming a ferroelectric column disposed around the channel column; disposing a plurality of horizontal gate-electrode layers at predetermined vertical distances between each other, each adjacent to the plurality of vertical structures; electrically coupling a plurality of bit lines, each corresponding to a respective bit-line group, to a respective source electrode column of the plurality of vertical structures; electrically coupling a plurality of select lines, each corresponding to a respective select-line group, to a respective drain electrode column of the plurality of vertical structures.

[0228] 35. The method according to aspect 34, wherein forming the bit-line groups includes configuring the groups to be electrically orthogonal to the select-line groups.

[0229] 36. The method according to aspect 34, further comprising interdigitating a plurality of dielectric layers with the plurality of horizontal gateelectrode layers.

[0230] 37. The method according to aspect 34, wherein activating the bit-line and the select line results in the activation of a single vertical structure.

[0231] 38. The method according to aspect 37, wherein the activation of the single vertical structure allows current to flow through therethrough.

[0232] 39. The method according to aspect 34, further comprising allowing current to flow through only the one or more active vertical structures of the plurality of vertical structures.

[0233] 40. The method according to aspect 34, wherein forming each of the plurality of bit lines includes aligning the bit lines substantially parallel to each other.

[0234] 41. The method according to aspect 34 or 40, wherein forming each of the plurality of select lines includes aligning the select lines substantially parallel to each other.

[0235] 42. The method according to aspect 34, further comprising coupling a plurality of source select transistors, each to a single select line of the plurality of select lines.

[0236] 43. The method according to aspect 34, configuring the plurality of vertical structures to form a 3D-N0R memory array.

[0237] 44. The method according to aspect 34, wherein forming the plurality of bit lines includes configuring them to be orthogonal to the plurality of select lines.

[0238] 45. The method according to aspect 34, wherein forming the source electrode column and the drain electrode column includes using a common material.

[0239] 46. The method according to aspect 34, wherein forming the vertical structures includes configuring them to have an elliptical cross-sectional shape.

[0240] 47. The method according to aspect 34, configuring the vertical structures to minimize capacitive coupling between adjacent bit-line groups.

[0241] 48. The method according to aspect 34, including forming a dielectric layer in the horizontal gate-electrode layers to reduce gate leakage current.

[0242] 49. The method according to aspect 34, optimizing the predetermined vertical distance between the horizontal gate-electrode layers to reduce short channel effects.

[0243] 50. The method according to aspect 34, forming the plurality of vertical structures such that the bit-line groups and select-line groups form a non-volatile memory unit.

[0244] 51. The method according to aspect 34, wherein activating a bit-line and a select line results in the activation of a single vertical structure from the plurality of vertical structures.

[0245] 52. The method according to aspect 51, wherein the activation of the single vertical structure allows current to flow through it.

[0246] 53. The method according to aspect 34, wherein each of the plurality of bit lines are formed substantially parallel to each other.

[0247] 54. The method according to aspects 34 or 53, wherein each of the plurality of select lines are formed substantially parallel to each other.

[0248] 55. The method according to aspect 34, further comprising coupling each of a plurality of source select transistors to a single select line of the plurality of select lines.

[0249] 56. The method according to aspect 34, configuring the plurality of vertical structures to form a 3D-NOR memory array.

[0250] 57. The method according to aspect 34, wherein forming the plurality of bit lines includes configuring them to be orthogonal to the plurality of select lines.

[0251] 58. The method according to aspect 34, wherein no respective bit- line selector transistor is formed for each of the plurality of bit lines.

[0252] 59. The method according to any of aspects 34 to 58, wherein each of the plurality of bit lines is electrically coupled to a respective source electrode of the plurality of vertical structures.

[0253] 60. The method according to aspect 34 or 50, wherein the plurality of vertical structures are arranged in a three-dimensional array configuration.

[0254] 61. The method according to aspect 34 or 50, further comprising coupling each of a plurality of word lines to a respective one of the plurality of horizontal gate-electrode layers.

[0255] 62. The method according to aspect 34 or 50, wherein the plurality of vertical structures are configured to store data in a non-volatile manner.

[0256] 63. A system for managing an integrated circuit device, comprising: an integrated circuit device as recited in any of aspects 1-33; a control unit configured to manage operations of the integrated circuit device, including data read, write, and erase operations; a voltage regulation module configured to supply various operating voltages to the integrated circuit device; a data interface configured to facilitate data communication between the integrated circuit device and an external processor; and a timing module configured to control timing of signals sent to the integrated circuit device.

[0257] 64. The system of aspect 63, wherein the voltage regulation module includes a plurality of voltage converters, each configured to convert an input voltage to a different respective output voltage suitable for different operations of the integrated circuit device.

[0258] 65. The system of aspect 63, further comprising a thermal management unit configured to monitor and control the temperature of the integrated circuit device.

[0259] 66. The system of aspect 65, wherein the thermal management unit includes temperature sensors distributed across the integrated circuit device and a cooling control circuit configured to activate cooling mechanisms based on temperature readings.

[0260] 67. The system of aspect 63, further comprising a power management unit configured to manage power consumption of the integrated circuit device during various operational states.

[0261] 68. The system of aspect 67, wherein the power management unit is configured to reduce power consumption of the integrated circuit device during idle states.

[0262] 69. The system of aspect 63, further comprising a diagnostics module configured to perform diagnostics on the integrated circuit device to identify potential faults.

[0263] 70. The system of aspect 69, wherein the diagnostics module is configured to perform diagnostics based on pre-defined schedules or in response to detected anomalies in operation.

[0264] 71. The system of aspect 63, wherein the timing module includes a phase-locked loop (PLL) circuit configured to synchronize the timing of signals based on an external clock source.

Claims

What is claimed is:

1. An integrated circuit device, comprising: a plurality of vertical structures arranged in bit-line groups and select- line groups, wherein each of the plurality of vertical structures is a member of only a single bit-line group and is a member of only a single select-line group, each of the plurality of vertical structures comprising: an insulating vertical-plug column; a source electrode column disposed adjacent to the insulating verticalplug column; a drain electrode column disposed adjacent to the insulating verticalplug column; a channel column disposed around the insulating vertical-plug column, the source electrode column, and the drain electrode column; and a ferroelectric column disposed around the channel column; a plurality of horizontal gate-electrode layers, each of the plurality of horizontal gate-electrode layers disposed a predetermined vertical distance between each other, each of the plurality of horizontal gate-electrode layers disposed adjacent to each of the plurality of vertical structures; a plurality of bit lines, each of the bit lines corresponds to a respective bit-line group, each of the bit lines electrically coupled to a respective source electrode column of the plurality of vertical structures; and a plurality of select lines, each of the select lines corresponds to a respective select-line group, each of the select lines is electrically coupled to a respective drain electrode column of the plurality of vertical structures.

2. The integrated circuit device according to claim 1 , wherein the bit- line groups are electrically orthogonal to the select-line groups.

3. The integrated circuit device according to claim 1, further comprising a plurality of dielectric layers interdigitated with the plurality of horizontal gateelectrode layers.

4. The integrated circuit device according to claim 1 , wherein when a bit- line of the plurality of bit lines is activated and a select line of the plurality of select lines is activated, a single one of the plurality of vertical structures is activated.

5. The integrated circuit device according to claim 4, wherein current flows through the single one of the plurality of vertical structures when activated.

6. The integrated circuit device according to claim 1 , wherein current flows through only the one or more active vertical structures of the plurality of vertical structures.

7. The integrated circuit device according to claim 1 , wherein each of the plurality of bit lines are substantially parallel to each other.

8. The integrated circuit device according to claims 1 or 7, wherein each of the plurality of select lines are substantially parallel to each other.

9. The integrated circuit device according to claim 1 , further comprising a plurality of source select transistors, where each of the plurality of source select transistors is coupled to a single select line of the plurality of select lines.

10. The integrated circuit device according to claim 1, wherein the plurality of vertical structures is configured to form a 3D-N0R memory array.

11. The integrated circuit device according to claim 1 , wherein the plurality of bit lines are orthogonal to the plurality of select lines.

12. The integrated circuit device according to claim 1, wherein each of the plurality of bit lines do not have a respective bit- line selector transistor.

13. The integrated circuit device according to claim 1, wherein the source electrode column and the drain electrode column are formed from a common material.

14. The integrated circuit device according to any of claims 1 to 13, wherein the plurality of bit lines electrically coupled to a respective source electrode column of the plurality of vertical structures.

15. The integrated circuit device according to claim 1, wherein the vertical structure is configured to have an elliptical cross-sectional shape.

16. The integrated circuit device according to claim 1, wherein the vertical structures are configured to minimize capacitive coupling between adjacent bit-line groups.

17. The integrated circuit device according to claim 1, wherein the horizontal gateelectrode layers include a dielectric layer to reduce gate leakage current.

18. The integrated circuit device according to claim 1, wherein the predetermined vertical distance between the horizontal gate-electrode layers is optimized to reduce short channel effects.

19. The integrated circuit device according to claim 1, wherein the plurality of vertical structures is arranged such that the bit-line groups and select-line groups form a non-volatile memory unit.

20. A method of manufacturing an integrated circuit device, the method comprising: forming a plurality of vertical structures in bit-line groups and select- line groups, wherein each vertical structure is a member of only a single bit-line group and a single select-line group, and each vertical structure is formed by: forming an insulating vertical-plug column; forming a source electrode column adjacent to the insulating vertical-plug column; forming a drain electrode column adjacent to the insulating vertical-plug column; forming a channel column disposed around the insulating vertical-plug column, source electrode column, and drain electrode column; forming a ferroelectric column disposed around the channel column;disposing a plurality of horizontal gate-electrode layers at predetermined vertical distances between each other, each adjacent to the plurality of vertical structures; electrically coupling a plurality of bit lines, each corresponding to a respective bit- line group, to a respective source electrode column of the plurality of vertical structures; electrically coupling a plurality of select lines, each corresponding to a respective select-line group, to a respective drain electrode column of the plurality of vertical structures.

21. The method according to claim 20, wherein forming the bit-line groups includes configuring the groups to be electrically orthogonal to the select-line groups.

22. The method according to claim 20, further comprising interdigitating a plurality of dielectric layers with the plurality of horizontal gate-electrode layers.

23. The method according to claim 20, wherein activating the bit-line and the select line results in the activation of a single vertical structure.

Images