Power semiconductor device and manufacturing method for power semiconductor device

Abstract

The present invention relates to the technical field of semiconductor devices, and provides a power semiconductor device and a manufacturing method for the power semiconductor device. The power semiconductor device comprises a substrate, a semiconductor epitaxial composite layer, a p-type semiconductor layer, a source, a drain and a gate electrode layer; the p-type semiconductor layer, the source and the drain are arranged on the semiconductor epitaxial composite layer; a passivation layer is provided on the semiconductor epitaxial composite layer, and a gate through hole leading to the p-type semiconductor layer is formed in the passivation layer; the gate electrode layer fills the gate through hole and is arranged on the p-type semiconductor layer. Compared with the prior art, the present invention forms the gate electrode layer by means of the gate through hole structure, and the gate electrode layer can be spaced apart from the semiconductor epitaxial composite layer, thus reducing gate leakage; in addition, the gate through hole is obliquely arranged, and has a depth-to-width ratio greater than 2, such that the gate electrode layer can function like a gate field plate, thus reducing electric field spikes at the edge of the p-type semiconductor layer, and improving the breakdown characteristic and reliability of the device.

Description

Power semiconductor device and method for manufacturing power semiconductor device TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor devices, and in particular, to a power semiconductor device and a method for manufacturing a power semiconductor device. BACKGROUND

[0002] Based on the spontaneous polarization and piezoelectric polarization effect of wide-bandgap semiconductor gallium nitride-based materials (GaN, AlGaN, InGaN, etc.), a high-density and high-mobility 2DEG is generated in the AlGaN / GaN heterojunction channel, making the GaN-based HEMT device a solution for high-efficiency and high-power-density power devices, which can provide greater breakdown voltage and power density. Under zero bias of the gate, the 2DEG existing in the channel makes the device conductive, and the threshold voltage of the device is negative (depletion mode device). In GaN power devices, for the purpose of safety and simplifying the gate drive circuit, it is necessary to make the channel disconnected under zero bias, and the threshold voltage is positive (enhancement mode device). Currently, commercial GaN HEMT devices usually use P-GaN gate structure to realize enhancement mode.

[0003] In order to improve the power density of the device, and to be suitable for low-voltage power field, it is necessary to reduce the line width of the overall cell, including P-GaN gate, source and drain structures. However, for the P-GaN gate structure among them, it is most difficult to reduce the size, and will face problems such as increased gate leakage and concentrated electric field at the edge of the gate. TECHNICAL SOLUTION

[0004] The purpose of the present application includes, for example, to provide a power semiconductor device and a method for manufacturing a power semiconductor device, which can have a smaller gate size, can form a gate electrode layer through a gate via, can control gate leakage, can reduce the electric field peak at the edge of the gate, and can improve the breakdown characteristics and reliability of the device.

[0005] Embodiments of the present application can be implemented as follows:

[0006] In a first aspect, the present application provides a power semiconductor device, comprising:

[0007] a substrate;

[0008] a semiconductor epitaxial composite layer disposed on the substrate and generating two-dimensional electron gas;

[0009] a p-type semiconductor layer, a source and a drain disposed on the semiconductor epitaxial composite layer;

[0010] a passivation layer disposed on the semiconductor epitaxial composite layer, a gate via being formed on the passivation layer and penetrating to the p-type semiconductor layer;

[0011] a gate electrode layer is deposited in the gate via and on the p-type semiconductor layer;

[0012] The gate electrode layer includes a tungsten metal layer or a copper metal layer, a side surface of the gate electrode layer away from the p-type semiconductor layer is flush with a side surface of the passivation layer away from the substrate, a sidewall of the gate via is in contact with a surface of the p-type semiconductor layer, the sidewall of the gate via is arranged obliquely relative to the surface of the p-type semiconductor layer, a ratio of a depth of the gate via to a bottom width of the gate via is greater than 2, the gate electrode layer is isolated from the semiconductor epitaxial composite layer, and the gate electrode layer completely covers the p-type semiconductor layer on a bottom wall of the gate via.

[0013] In a second aspect, the present application provides a method for manufacturing a power semiconductor device, the method being used to manufacture the power semiconductor device according to any one of the preceding embodiments, and the method comprising:

[0014] forming a semiconductor epitaxial composite layer on a substrate;

[0015] forming a p-type semiconductor layer, a source and a drain on a surface of the semiconductor epitaxial composite layer;

[0016] depositing a passivation layer on the semiconductor epitaxial layer, the passivation layer covering the p-type semiconductor layer, the source and the drain;

[0017] forming a gate via on the passivation layer, the gate via penetrating to the p-type semiconductor layer to expose the p-type semiconductor layer;

[0018] depositing a gate electrode layer in the gate via;

[0019] planarizing the gate electrode layer;

[0020] The gate electrode layer includes a tungsten metal layer or a copper metal layer, a side surface of the gate electrode layer away from the p-type semiconductor layer is flush with a side surface of the passivation layer away from the substrate, a sidewall of the gate via is in contact with a surface of the p-type semiconductor layer, the sidewall of the gate via is arranged obliquely relative to the surface of the p-type semiconductor layer, a ratio of a depth of the gate via to a bottom width of the gate via is greater than 2, the gate electrode layer is isolated from the semiconductor epitaxial composite layer, and the gate electrode layer completely covers the p-type semiconductor layer on a bottom wall of the gate via. Advantages

[0021] The advantages of the embodiments of the present application include, for example:

[0022] The power semiconductor device and the preparation method thereof provided by the embodiment of the present application form a semiconductor epitaxial composite layer on a substrate, the semiconductor epitaxial composite layer has a heterojunction and can generate two-dimensional electron gas, then a p-type semiconductor layer, a source and a drain are formed on the semiconductor epitaxial composite layer, a passivation layer is formed on the semiconductor epitaxial composite layer, a gate through hole is formed by opening a hole on the passivation layer, and finally a gate electrode layer is formed by filling the gate through hole, wherein the gate electrode layer is flush with the passivation layer, the gate through hole adopts an inclined hole structure, the sidewall of the gate through hole is in contact with the surface of the p-type semiconductor layer and is arranged obliquely relative to the surface of the p-type semiconductor layer, the depth-width ratio of the gate through hole is greater than 2, and the gate electrode layer is separated from the semiconductor epitaxial composite layer. Compared with the prior art, the gate size can be smaller, the gate electrode layer is formed by the gate through hole structure, the gate electrode layer can be separated from the semiconductor epitaxial composite layer, the gate leakage can be reduced, the gate through hole is arranged obliquely, the depth-width ratio of the gate through hole is greater than 2, the gate electrode layer can play a role similar to that of a gate field plate, and thus the electric field peak at the edge of the p-type semiconductor layer can be reduced and the breakdown characteristics and reliability of the device can be improved. BRIEF DESCRIPTION OF DRAWINGS

[0023] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiments. It should be understood that the following drawings only show some of the embodiments of the present application, and therefore should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can also be obtained without creative labor on the basis of these drawings.

[0024] Fig. 1 is a structural schematic diagram of a power semiconductor device provided by the embodiment of the present application;

[0025] Fig. 2a is a top view of one structure of a power semiconductor device provided by the embodiment of the present application;

[0026] Fig. 2b is a top view of another structure of a power semiconductor device provided by the embodiment of the present application;

[0027] Fig. 3 is a structural schematic diagram of a power semiconductor device provided by the second embodiment of the present application;

[0028] Fig. 4 is a structural schematic diagram of a power semiconductor device provided by the third embodiment of the present application;

[0029] Fig. 5 is a structural schematic diagram of a power semiconductor device provided by the fourth embodiment of the present application;

[0030] Figs. 6 to 10 are process flow diagrams of a preparation method of a power semiconductor device provided by the embodiment of the present application.

[0031] Icon: 100 - power semiconductor device; 110 - substrate; 120 - semiconductor epitaxial composite layer; 121 - buffer layer; 123 - channel layer; 125 - barrier layer; 130 - p-type semiconductor layer; 140 - source; 150 - drain; 160 - passivation layer; 161 - gate via; 163 - first dielectric layer; 165 - second dielectric layer; 167 - field plate opening; 170 - gate electrode layer; 171 - gate bottom metal layer; 173 - gate metal layer; 180 - interconnection metal layer; 181 - first field plate; 183 - second field plate. Embodiments of the present application

[0032] In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings herein can be arranged and designed in various different configurations.

[0033] Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the claimed present application, but only represents selected embodiments of the present application. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present application without making creative efforts fall within the scope of protection of the present application.

[0034] It should be noted that: similar reference numerals and letters represent similar items in the following drawings, therefore, once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings.

[0035] In the description of the present application, it should be noted that if the terms "upper", "lower", "inner", "outer" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, or the orientation or positional relationship when the product of the present application is usually placed, which is only for the convenience of describing the present application and simplifying the description, and does not indicate or imply that the indicated device or element must have a particular orientation, be constructed and operated in a particular orientation, therefore, it cannot be understood as a limitation on the present application.

[0036] In addition, if the terms "first", "second" and the like appear, they are only used to distinguish the description, and cannot be understood as indicating or implying relative importance.

[0037] As disclosed in the background art, in the prior art, it is most difficult to reduce the size of the P-GaN gate structure because of the problems of increased gate leakage and concentrated electric field at the edge of the gate. Moreover, the conventional gate process is divided into a first-gate process and a last-gate process. The first-gate process has poor controllability because the gate metal needs to be retracted, and the process is difficult to control. If the retraction is too small, the gate metal is too close to the edge of the p-type gate, causing excessive leakage. If the retraction is too large, the gate control ability will decrease, and the overall gate metal thickness is very thin, which will also cause the gate resistance to be too large and the gate control ability to decrease. Moreover, the first-gate process can only use TiN material with a very high resistivity because the gate metal needs to undergo an ohmic contact annealing process, which causes the gate resistance to be too large and the control ability to decrease. Furthermore, the first-gate process cannot form a field plate structure, so the edge of the p-type gate has a problem of concentrated electric field, which affects the breakdown characteristics and reliability of the device. The problem of the conventional last-gate process is that it is very difficult to fill the gate via with a large aspect ratio, and the side wings of the gate metal form a high step difference with the bottom of the dielectric layer, which is not conducive to the layout of the field plate structure and the planarization of the device, and is also prone to cause metal etching residue and cracking of the dielectric layer, which is not conducive to the reliability of the device.

[0038] To solve the above problems, the embodiments of the present application provide a new type of power semiconductor device and a preparation method of the power semiconductor device. It should be noted that the features in the embodiments of the present application can be combined with each other without conflict.

[0039] Please refer to FIG. 1, the present embodiment provides a power semiconductor device 100, which can effectively reduce the size of the gate, reduce the gate leakage, reduce the electric field peak at the edge of the p-type semiconductor layer 130, improve the breakdown characteristics and reliability of the device, and realize good via filling, good planarization by combining with the CMP process, and the layout of the field plate structure.

[0040] The power semiconductor provided by the embodiment of the present application comprises a substrate 110, a semiconductor epitaxial composite layer 120, a p-type semiconductor layer 130, a source electrode 140, a drain electrode 150 and a gate electrode layer 170, wherein the semiconductor epitaxial composite layer 120 is arranged on the substrate 110 and generates two-dimensional electron gas; the p-type semiconductor layer 130, the source electrode 140 and the drain electrode 150 are arranged on the semiconductor epitaxial composite layer 120; a passivation layer 160 is arranged on the semiconductor epitaxial composite layer 120, and a gate through hole 161 penetrating to the p-type semiconductor layer 130 is formed on the passivation layer 160; the gate electrode layer 170 is filled in the gate through hole 161 and arranged on the p-type semiconductor layer 130; wherein the gate electrode layer 170 comprises a tungsten metal layer or a copper metal layer, a side surface of the gate electrode layer 170 away from the p-type semiconductor layer 130 is flush with a side surface of the passivation layer 160 away from the substrate 110, a sidewall of the gate through hole 161 is in contact with a surface of the p-type semiconductor layer 130, and the sidewall of the gate through hole 161 is arranged obliquely relative to the surface of the p-type semiconductor layer 130, a ratio of a depth of the gate through hole to a bottom width is greater than 2, the gate electrode layer 170 is isolated from the semiconductor epitaxial composite layer 120, and completely covers the p-type semiconductor layer 130 on a bottom wall of the gate through hole 161.

[0041] It is worth noting that in actual preparation of the device, a conventional epitaxial process can be used to form the semiconductor epitaxial composite layer 120 on the substrate 110, the semiconductor epitaxial composite layer 120 has a heterojunction and can generate two-dimensional electron gas, then the p-type semiconductor layer 130, the source electrode 140 and the drain electrode 150 are formed on the semiconductor epitaxial composite layer 120, the passivation layer 160 is formed on the semiconductor epitaxial composite layer 120, and the gate through hole 161 is formed by opening a hole on the passivation layer 160, and finally the gate electrode layer 170 is filled in the gate through hole 161. Since the gate electrode layer 170 is formed by the gate through hole 161 structure in the embodiment, and the gate electrode layer 170 can be spaced apart from the semiconductor epitaxial composite layer 120, gate leakage can be reduced, and at the same time, the oblique arrangement of the gate through hole 161 can make the gate electrode layer 170 play a role similar to a gate field plate, thereby reducing the electric field peak at the edge of the p-type semiconductor layer 130 and improving the breakdown characteristics and reliability of the device.

[0042] It should be noted that in some embodiments, the semiconductor epitaxial composite layer 120 includes a buffer layer 121, a channel layer 123 and a barrier layer 125, the buffer layer 121 can be an AlGaN layer and is arranged on the substrate 110; the channel layer 123 can be a GaN layer and is arranged on the buffer layer 121; the barrier layer 125 can be an AlGaN layer and is arranged on the channel layer 123, the p-type semiconductor layer 130, the source 140 and the drain 150 are arranged on the barrier layer 125, and the p-type semiconductor layer 130 is arranged between the source 140 and the drain 150, wherein a two-dimensional electron gas can be formed at the interface of the barrier layer 125 and the channel layer 123.

[0043] It should also be noted that the gate via hole 161 with a depth-to-width ratio greater than 2 is used to make the gate electrode layer 170. The depth-to-width ratio can be generally defined as the ratio of the depth to the bottom width of the gate via hole 160. The via metal is selected from W or Cu, because the via metal must first have good step coverage and gap filling capability. Conventional metal growth methods such as electron beam evaporation or magnetron sputtering are difficult to achieve high aspect ratio via filling. These methods have weak step and sidewall coverage, and it is also difficult to fill the gap. W or Cu metal can be deposited by CVD (chemical vapor deposition), which has excellent step coverage and can achieve gapless filling of high aspect ratio via, forming a high-quality metal via. In addition, W and Cu have high melting points (W 3417℃, Cu 1085℃), good high-temperature reliability. W and Cu have relatively small bulk resistivity (W 52.8μΩ-cm, Cu 1.678μΩ-cm), which can reduce gate signal delay and gate loss. W and Cu also have no problem of electric migration, stable performance and good reliability.

[0044] In some embodiments, the inclination angle of the sidewall of the gate via hole 161 relative to the surface of the p-type semiconductor layer 130 is between 45°-75°. Preferably, the inclination angle of the sidewall of the gate via hole 161 can be 60°, which can effectively reduce the problem of electric field concentration at the p-type gate edge. Since the gate via hole 161 adopts an inclined via structure, the sidewall of the gate electrode layer 170 also presents an inclined structure, and the depth-to-width ratio is greater than 2, so a structure similar to a gate field plate can be formed, thereby reducing the electric field peak at the p-type gate edge and achieving controllable edge electric field. It should be noted that the inclination angle here refers to the degree of inclination of the sidewall of the gate via hole 161, i.e. the degree of acute angle of the sidewall of the gate via hole 161 relative to the horizontal plane. The smaller the inclination angle here, the better the effect of reducing edge electric field concentration, but the higher the difficulty to be achieved in the process. Therefore, in the present embodiment, the inclination angle of the sidewall of the gate via hole 161 is set to be between 45°-75°, which can ensure the control of the electric field concentration problem while taking into account the realizability of the process.

[0045] In some embodiments, the gate electrode layer 170 includes a gate bottom metal layer 171 and a gate metal layer 173, the gate bottom metal layer 171 is disposed in the gate via hole 161 and on the p-type semiconductor layer 130, and the gate metal layer 173 is disposed in the gate via hole 161 and on the gate bottom metal layer 171, and the gate metal layer 173 is flush with the passivation layer 160. Specifically, after forming the gate via hole 161, the gate bottom metal layer 171 can be deposited in the gate via hole 161, and the gate metal layer 173 can be deposited to fill the gate via hole 161, and then the excess metal on the passivation layer 160 can be removed by CMP or etching. In some embodiments, the gate metal layer 173 includes a tungsten metal layer or a copper metal layer, and the gate bottom metal layer 171 includes at least one metal layer of Ti, Pt, Au, TiN, Al, Ni, W, Ta, Pd, Mo, Co, Cr, TaN, ZrN. Preferably, the gate metal layer 173 is tungsten (W), which can form a W plug structure, and the W plug structure has good filling performance, so as to completely fill the entire gate via hole 161 and completely cover the gate bottom metal layer 171, and is suitable for a gate via hole 161 with a large aspect ratio.

[0046] It is worth noting that the W plug structure is the core in the present embodiment, but W metal is not suitable as a contact metal with the P-GaN layer, so a gate bottom metal layer 171 must be added between the W and the P-GaN layer. In practical applications, the gate bottom metal layer 171 is generally Ti or TiN.

[0047] In some embodiments, the thickness of the gate metal layer 173 is between 50 nm and 1000 nm, and the thickness of the gate bottom metal layer 171 is between 50 nm and 500 nm. The gate bottom metal layer 171 can be a single layer or multiple layers of metal material, and the thickness is generally less than the thickness of the gate metal layer 173. Of course, the thickness of the gate bottom metal layer 171 and the gate metal layer 173 described herein is only illustrative and does not limit the description.

[0048] In some embodiments, the gate via hole 161 penetrates to the center of the p-type semiconductor layer 130, so that the gate electrode layer 170 is spaced apart from the edge of the p-type semiconductor layer 130. Specifically, the center of the gate via hole 161 overlaps the center of the p-type semiconductor layer 130, and the bottom opening size of the gate via hole 161 is smaller than the size of the p-type semiconductor layer 130, so that after depositing the gate electrode layer 170, the gate bottom metal layer 171 is spaced apart from the edge of the p-type semiconductor layer 130, reducing the gate leakage phenomenon.

[0049] In some embodiments, the thickness of the p-type semiconductor layer 130 is between 20 nm and 200 nm, and the distance between the edge of the p-type semiconductor layer 130 and the gate electrode layer 170 is between 0.02 μm and 1 μm. In some embodiments, the width of the p-type semiconductor layer 130 is between 2 μm and 4 μm, the distance between the edge of the p-type semiconductor layer 130 and the gate bottom metal layer 171 is between 0.02 μm and 1 μm, and the distance between the edge of the p-type semiconductor layer 130 and the gate bottom metal layer 171 is less than half of the width of the p-type semiconductor layer 130, so as to ensure that the gate bottom metal layer 171 is in contact with the p-type semiconductor layer 130 while maintaining a sufficient distance from the semiconductor epitaxial layer 120. It should be noted that the greater the distance between the edge of the p-type semiconductor layer 130 and the gate bottom metal layer 171, the smaller the gate leakage current, and the greater the contact area between the p-type semiconductor layer 130 and the gate bottom metal layer 171, the better the on characteristics and the lower the threshold voltage. Therefore, by limiting the distance between the edge of the p-type semiconductor layer 130 and the gate bottom metal layer 171, the leakage current and threshold voltage problems can be well balanced.

[0050] Referring to FIG. 2a, in some embodiments, the cross-sectional shape of the gate via 161 is circular, rectangular, or polygonal. Preferably, the gate via 161 is circular, and the gate via 161 can be formed by etching a hole in the passivation layer 160. Of course, the size of the gate via 161 is smaller than the size of the p-type semiconductor layer 130, and the gate via 161 can be a continuous long strip structure, as shown in FIG. 2b. Of course, the gate via 161 can also be a plurality of separate via structures, and the specific arrangement thereof is not described in detail herein.

[0051] Referring to FIG. 3, in some embodiments, an interconnection metal layer 180 is further provided on the gate electrode layer 170, the interconnection metal layer 180 covers the gate via 161 and is used to regulate the electric field. The interconnection metal layer 180 can be a plurality of metal layers, for example, the interconnection metal layer 180 can be a sandwich structure, i.e., two layers of TiN sandwiching a layer of AlCu alloy, of course, the interconnection metal layer 180 can also be a pure TiN layer or a pure Cu layer. The thickness of the interconnection metal layer 180 can be between 100 nm and 1000 nm. By opening a hole in the P-type semiconductor layer 130, the via metal layer serves as a metal gate and is directly connected to the metal interconnection layer 180. This not only reduces the additional via mask and related process steps, saving costs, but also facilitates the arrangement of the metal interconnection. Referring to FIG. 4, in some embodiments, the passivation layer 160 includes a first dielectric layer 163 and a second dielectric layer 165, the first dielectric layer 163 is provided on the semiconductor epitaxial composite layer 120 and at least partially covers the source 140, the drain 150 and the P-type semiconductor layer 130, a first field plate 181 is further provided on the first dielectric layer 163 between the P-type semiconductor layer 130 and the drain 150, the second dielectric layer 165 is provided on the first dielectric layer 163 and covers the first field plate 181, and the gate via 161 penetrates the second dielectric layer 165 and the first dielectric layer 163. Specifically, the first field plate 181 is a metal field plate, in actual production, a layer of passivation dielectric is first grown, the first field plate 181 is formed, a thicker passivation dielectric is then grown, and then CMP planarization is performed, and the gate electrode layer 170 is then opened. The advantage of this arrangement is that the distance between the first field plate 181 and the AlGaN barrier layer 125 can be small, thereby improving the electric field regulation capability.

[0052] Referring to FIG. 5, in some embodiments, a field plate opening 167 is further provided on the passivation layer 160 between the P-type semiconductor layer 130 and the drain 150, the field plate opening 167 is filled with a second field plate 183, the second field plate 183 is isolated from the gate electrode layer 170 and is isolated from the semiconductor epitaxial composite layer 120. Specifically, when the gate via 161 is opened, the field plate opening 167 can be formed at the same time, and when the gate electrode layer 170 is formed, metal can be deposited in the field plate opening 167 to form the second field plate 183. The second field plate 183 can also be divided into two layers of metal material. The advantage of this arrangement is that it does not increase the process, thereby saving costs.

[0053] The embodiments of the present application also provide a preparation method of the power semiconductor device 100, which is used for preparing the power semiconductor device 100 described above, and the preparation method includes the following steps:

[0054] S1: forming a semiconductor epitaxial composite layer 120 on a substrate 110.

[0055] Specifically, referring to FIG. 6, a conventional epitaxy process can be adopted to sequentially deposit the AlGaN buffer layer 121, the GaN channel layer 123 and the AlGaN barrier layer 125 on the substrate 110.

[0056] S2: Forming the p-type semiconductor layer 130, the source 140 and the drain 150 on the surface of the semiconductor epitaxial composite layer 120.

[0057] Specifically, referring to FIG. 7, a layer of p-GaN layer is first formed on the AlGaN barrier layer 125, and then the p-type semiconductor layer 130 of the streamer gate is selectively etched by etching the p-GaN layer, and then the source 140 and the drain 150 are deposited.

[0058] S3: Depositing the passivation layer 160 on the semiconductor epitaxial layer, the passivation layer 160 covering the p-type semiconductor layer 130, the source 140 and the drain 150.

[0059] Specifically, referring to FIG. 8, a relatively thick passivation layer 160 can be deposited, and then planarized by CMP process.

[0060] In some embodiments, the step S3 of depositing the passivation layer 160 on the semiconductor epitaxial layer can include: forming a first dielectric layer 163 on the surface of the semiconductor epitaxial composite layer 120, the first dielectric layer 163 covering the source 140, the drain 150 and the p-type semiconductor layer 130; forming a first field plate 181 on the surface of the first dielectric layer 163 between the p-type semiconductor layer 130 and the drain 150; and forming a second dielectric layer 165 on the first dielectric layer 163, the second dielectric layer 165 covering the first field plate 181, thereby completing the preparation of the first field plate 181. Specifically, the first dielectric layer 163 and the second dielectric layer 165 are both passivation dielectric materials, a passivation dielectric layer is first grown, the first field plate 181 is made, and then a relatively thick passivation dielectric layer is grown, and then CMP planarization is performed, and finally the gate electrode layer 170 is prepared. The advantage of this process is that the distance between the first field plate 181 and the AlGaN barrier layer 125 can be smaller, thereby improving the electric field adjusting capability.

[0061] S4: Forming the gate via hole 161 on the passivation layer 160, the gate via hole 161 penetrating to the p-type semiconductor layer 130 to expose the p-type semiconductor layer 130.

[0062] Specifically, referring to FIG. 9, the gate via hole 161 can be formed by etching to expose the p-type semiconductor layer 130, wherein the sidewall of the gate via hole 161 is inclined relative to the surface of the p-type semiconductor layer 130, and the inclination angle is preferably between 45° and 75°, and preferably can be 60°. The inclination angle can be controlled by etching process.

[0063] S5: A gate electrode layer 170 is deposited in the gate via 161.

[0064] Specifically, referring to Figure 10, a gate bottom metal layer 171 can be first deposited on the surface of the p-type gate within the gate via 161, and then a gate electrode layer 170 can be deposited on the surface of the gate bottom metal layer 171, filling the gate via 161. The gate bottom metal layer 171 includes at least one metal layer selected from Ti, Pt, Au, TiN, Al, Ni, W, Ta, Pd, Mo, Co, Cr, TaN, and ZrN. The gate metal layer 173 is tungsten (W), which can form a W-plug structure. The W-plug structure has excellent filling properties, thus completely filling the entire gate via 161, making it suitable for gate vias with large aspect ratios. Furthermore, the sidewalls of the gate via 161 are in contact with the surface of the p-type semiconductor layer 130, and the sidewalls of the gate via 161 are inclined relative to the surface of the p-type semiconductor layer 130. The gate electrode layer 170 is isolated from the semiconductor epitaxial composite layer 120.

[0065] In some embodiments, after step S3 of depositing and forming a passivation layer 160 on the semiconductor epitaxial layer, the fabrication method further includes: forming a field plate opening 167 on the passivation layer 160 located between the p-type semiconductor layer 130 and the drain 150; filling the field plate opening 167 to form a second field plate 183; wherein the second field plate 183 is isolated from the gate electrode layer 170 and isolated from the semiconductor epitaxial composite layer 120. Specifically, when forming the gate via 161, the field plate opening 167 can be formed simultaneously, and when forming the gate electrode layer 170, metal can be deposited in the field plate opening 167 to form the second field plate 183. The second field plate 183 can also be composed of two layers of metal material. The advantage of this arrangement is that it does not add extra steps and saves costs.

[0066] S6: Planarize the gate electrode layer 170.

[0067] Specifically, referring to Figure 1, excess metal above the passivation layer 160 can be removed by CMP or etching processes to planarize the gate electrode layer 170, making the side of the gate electrode layer 170 away from the p-type semiconductor layer 130 flush with the side of the passivation layer 160 away from the substrate 110.

[0068] In some embodiments, after step S6 is completed, an interconnection metal layer 180 can also be arranged on the gate electrode, the interconnection metal layer 180 covers the gate via 161, the interconnection metal layer 180 can be a few layers of metal stacks, for example, the interconnection metal layer 180 can be a sandwich structure, i.e. two layers of TiN sandwiching a layer of AlCu alloy, of course, the interconnection metal layer 180 here can also be a pure TiN layer or a pure Cu layer. And the thickness of the interconnection metal layer 180 here can be between 100 nm-1000 nm.

[0069] In summary, the power semiconductor device 100 and the preparation method of the power semiconductor device 100 provided by the embodiments of the present application, by forming a semiconductor epitaxial composite layer 120 on the substrate 110, the semiconductor epitaxial composite layer 120 has a heterojunction and can generate a two-dimensional electron gas, then forming a p-type semiconductor layer 130, a source 140 and a drain 150 on the semiconductor epitaxial composite layer 120, then forming a passivation layer 160 on the semiconductor epitaxial composite layer 120, and forming a gate via 161 on the passivation layer 160, and finally filling and forming a gate electrode layer 170 in the gate via 161, wherein the gate electrode layer 170 is flush with the passivation layer 160, and the gate via 161 adopts an inclined hole structure, the sidewall of the gate via 161 is in contact with the surface of the p-type semiconductor layer 130 and is arranged obliquely relative to the surface of the p-type semiconductor layer 130, and the gate electrode layer 170 is isolated from the semiconductor epitaxial composite layer 120. Compared with the prior art, in the embodiments of the present application, the gate size can be smaller, the gate electrode layer 170 is formed by the gate via 161 structure, and the gate electrode layer 170 can be spaced apart from the semiconductor epitaxial composite layer 120, which can reduce gate leakage, and at the same time, the inclined arrangement of the gate via 161 can make the gate electrode layer 170 play a role similar to that of a gate field plate, thereby reducing the electric field peak at the edge of the p-type semiconductor layer 130 and improving the breakdown characteristics and reliability of the device.

[0070] The above merely describes the specific embodiments of the present application, but the protection scope of the present application is not limited thereto, any changes or replacements within the technical range disclosed by the present application can be easily thought of by those skilled in the art, which should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A power semiconductor device, characterized by, The application relates to a semiconductor device, which comprises: a substrate; a semiconductor epitaxial composite layer arranged on the substrate and generating a two-dimensional electron gas; a p-type semiconductor layer, a source electrode and a drain electrode arranged on the semiconductor epitaxial composite layer; a passivation layer arranged on the semiconductor epitaxial composite layer, the passivation layer being provided with a gate through hole penetrating to the p-type semiconductor layer; a gate electrode layer filled in the gate through hole and arranged on the p-type semiconductor layer; wherein the gate electrode layer comprises a tungsten metal layer or a copper metal layer, a side surface of the gate electrode layer away from the p-type semiconductor layer is flush with a side surface of the passivation layer away from the substrate, a side wall of the gate through hole is in contact with a surface of the p-type semiconductor layer, the side wall of the gate through hole is arranged to be inclined relative to the surface of the p-type semiconductor layer, a ratio of a depth of the gate through hole to a bottom width is greater than 2, the gate electrode layer is isolated from the semiconductor epitaxial composite layer, and the gate electrode layer completely covers the p-type semiconductor layer on a bottom wall of the gate through hole.

2. The power semiconductor device according to claim 1, characterized in that, An inclination angle of the side wall of the gate through hole relative to the surface of the p-type semiconductor layer is between 45 DEG and 75 DEG.

3. The power semiconductor device according to claim 2, characterized in that, The gate electrode layer comprises a gate bottom metal layer and a gate metal layer, the gate bottom metal layer is arranged in the gate through hole and completely covers the p-type semiconductor layer, the gate metal layer is filled in the gate through hole and completely covers the gate bottom metal layer, the gate metal layer is flush with the passivation layer, and the gate metal layer is a tungsten metal layer or a copper metal layer.

4. The power semiconductor device according to claim 3, characterized in that, The gate bottom metal layer comprises at least one metal layer selected from Ti, Pt, Au, TiN, Al, Ni, W, Ta, Pd, Mo, Co, Cr, TaN and ZrN.

5. The power semiconductor device of claim 3, wherein, A thickness of the gate metal layer is between 50 nm and 1000 nm, and a thickness of the gate bottom metal layer is between 50 nm and 500 nm.

6. The power semiconductor device of claim 1, wherein, The gate through hole penetrates to a central position of the p-type semiconductor layer, so that the gate electrode layer is spaced from an edge of the p-type semiconductor layer.

7. The power semiconductor device according to claim 6, characterized in that, A thickness of the p-type semiconductor layer is between 20 nm and 200 nm, and a distance between the gate electrode layer and the edge of the p-type semiconductor layer is between 0.02 mu m and 1 mu m.

8. The power semiconductor device of claim 6, wherein, A cross-sectional shape of the gate through hole is circular, rectangular or polygonal.

9. The power semiconductor device of claim 1, wherein, An interconnection metal layer is further arranged on the gate electrode layer, the interconnection metal layer covers the gate through hole, and is used for regulating an electric field.

10. The power semiconductor device of claim 1, wherein, The passivation layer comprises a first dielectric layer and a second dielectric layer, the first dielectric layer is arranged on the semiconductor epitaxial composite layer and at least partially covers the source electrode, the drain electrode and the p-type semiconductor layer, a first field plate is further arranged on the first dielectric layer between the p-type semiconductor layer and the drain electrode, the second dielectric layer is arranged on the first dielectric layer and covers the first field plate, and the gate through hole penetrates the second dielectric layer and the first dielectric layer.

11. The power semiconductor device of claim 1, wherein, A field plate opening is further arranged on the passivation layer between the p-type semiconductor layer and the drain electrode, a second field plate is filled in the field plate opening, the second field plate is isolated from the gate electrode layer and is isolated from the semiconductor epitaxial composite layer.

12. A method of manufacturing a power semiconductor device for manufacturing a power semiconductor device according to any one of claims 1 to 11, characterized in that The preparation method comprises: forming a semiconductor epitaxial composite layer on a substrate; forming a p-type semiconductor layer, a source and a drain on a surface of the semiconductor epitaxial composite layer; depositing a passivation layer on the semiconductor epitaxial composite layer, the passivation layer covering the p-type semiconductor layer, the source and the drain; forming a gate via hole on the passivation layer, the gate via hole penetrating to the p-type semiconductor layer to expose the p-type semiconductor layer; depositing a gate electrode layer in the gate via hole; planarizing the gate electrode layer; wherein the gate electrode layer comprises a tungsten metal layer or a copper metal layer, a side surface of the gate electrode layer away from the p-type semiconductor layer is flush with a side surface of the passivation layer away from the substrate, a sidewall of the gate via hole is in contact with a surface of the p-type semiconductor layer, and the sidewall of the gate via hole is arranged to be inclined with respect to the surface of the p-type semiconductor layer, a ratio of a depth of the gate via hole to a bottom width is greater than 2, the gate electrode layer is isolated from the semiconductor epitaxial composite layer, and completely covers the p-type semiconductor layer on a bottom wall of the gate via hole.

13. The method of producing a power semiconductor device according to claim 12, wherein The step of depositing a gate electrode layer in the gate via hole comprises: depositing a gate bottom metal layer on a surface of the p-type gate in the gate via hole; depositing a gate electrode layer on a surface of the gate bottom metal layer, the gate electrode layer filling the gate via hole.

14. The method of producing a power semiconductor device according to claim 12, wherein After the step of planarizing the gate electrode layer, the preparation method further comprises: arranging an interconnection metal layer on the gate electrode, the interconnection metal layer covering the gate via hole.

15. The method of producing a power semiconductor device according to claim 12, wherein The step of depositing a passivation layer on the semiconductor epitaxial composite layer comprises: forming a first dielectric layer on a surface of the semiconductor epitaxial composite layer, the first dielectric layer covering the source, the drain and the p-type semiconductor layer; forming a first field plate on a surface of the first dielectric layer between the p-type semiconductor layer and the drain; forming a second dielectric layer on the first dielectric layer, the second dielectric layer covering the first field plate.

16. The method of producing a power semiconductor device according to claim 12, wherein After the step of depositing a passivation layer on the semiconductor epitaxial composite layer, the preparation method further comprises: forming a field plate opening on the passivation layer between the p-type semiconductor layer and the drain; filling a second field plate in the field plate opening; wherein the second field plate is isolated from the gate electrode layer and is isolated from the semiconductor epitaxial composite layer.

Images