Semiconductor structure and forming method therefor

Abstract

A semiconductor structure manufacturing method and a semiconductor structure. The method comprises: providing a substrate (201), forming in a first region (I) of the substrate (201) a plurality of first grooves (205), and forming on the side walls of the first grooves (205) a first dielectric layer (401); etching the substrate (201) along the bottoms of the first grooves (205), so as to form second grooves (207) located inside the substrate (201), and filling the second grooves (207) with a second dielectric layer (501); forming in a second region (II) of the substrate a third groove (209), and forming on the side wall of the third groove (209) a third dielectric layer (701); etching the substrate (201) along the bottom of the third groove (209), so as to form a fourth groove (211) located inside the substrate (201), the fourth groove (211) exposing the side surface of the second dielectric layer (501) in a first direction (X); filling the fourth groove (211) with a fourth dielectric layer (801), the fourth dielectric layer (801) located inside the substrate (201) and the second dielectric layer (501) located inside the substrate (201) being connected to each other. The formed dielectric layers can protect the substrate, so as to avoid delamination of a stacked structure and leakage current in the substrate, thus improving the electrical performance of stacked devices.

Description

Semiconductor structure and method of forming the same

[0001] The present application claims priority to the Chinese patent application No. 202410740575.0, filed on June 7, 2024, and entitled "Semiconductor structure and method of forming the same", the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0002] Embodiments of the present disclosure relate to the field of semiconductor technology, in particular to a preparation method of a semiconductor structure and the semiconductor structure. BACKGROUND

[0003] With the development of the integration density of dynamic memory towards higher direction, higher requirements are put forward for the arrangement mode of transistors and the size of transistors in the dynamic memory array structure. However, due to the limitations of photolithography machines and various electrical parasitic effects and other manufacturing factors, there is a limit to the reduction of the critical dimension, therefore, how to make a chip with higher storage density on a wafer is the research direction of many researchers and semiconductor practitioners.

[0004] The emergence of three-dimensional dynamic random memory (3D DRAM), especially 3D DRAM including multilayer horizontal cells (MHC), generally includes a plurality of transistors stacked on a substrate, which meets the above requirements. To form a stacked multilayer horizontal cell, an initial stack structure needs to be formed on the substrate, and then etching, ion implantation, deposition and other processes are performed on the stack structure. In this process, the substrate is easily etched or ion implanted, which causes the stack structure to be peeled off from the substrate or the substrate to have a leakage phenomenon, affecting the electrical performance of the finally formed storage cell.

[0005] SUMMARY

[0006] Embodiments of the present disclosure provide a preparation method of a semiconductor structure and the semiconductor structure, which at least helps to prevent etching of the substrate, helps to reduce the risk of peeling off the stack structure from the substrate, improves the leakage phenomenon of the storage cell, and improves the overall electrical performance of the storage cell.

[0007] In an aspect, a preparation method of a semiconductor structure is provided, comprising:

[0008] providing a substrate; the substrate includes a first region and a second region distributed along a first direction, and forming a stack structure on the substrate;

[0009] forming a plurality of first recesses in the first region of the substrate, the plurality of first recesses being formed in the substrate, the first recesses extending along a first direction, and the plurality of first recesses being spaced apart along a second direction, the first direction and the second direction defining a plane parallel to a surface of the substrate;

[0010] forming a first dielectric layer on sidewalls of the first recesses;

[0011] etching the substrate along a bottom of the first recesses to form second recesses in the substrate, the second recesses connecting adjacent first recesses along the second direction;

[0012] filling the second recesses with a second dielectric layer.

[0013] In some embodiments, further comprising:

[0014] forming third recesses in the second region of the substrate and extending along the second direction, the third recesses being formed in the substrate;

[0015] forming a third dielectric layer on sidewalls of the third recesses;

[0016] etching the substrate along a bottom of the third recesses to form fourth recesses in the substrate, the fourth recesses exposing sidewalls of the second dielectric layer along the first direction;

[0017] filling the fourth recesses with a fourth dielectric layer;

[0018] the fourth dielectric layer in the substrate being connected to the second dielectric layer in the substrate.

[0019] In some embodiments, before forming the plurality of first recesses, further comprising: patterning the stack structure to form an initial stack structure, the initial stack structure including a plurality of first portions in the first region and a second portion in the second region, the plurality of first portions extending along the first direction, and the second portion extending along the second direction;

[0020] the plurality of first portions being spaced apart along the second direction, and first trench isolation structures being formed between adjacent first portions;

[0021] etching the substrate along a bottom of the first trench isolation structures to form the first recesses;

[0022] the first recesses being connected to the first trench isolation structures.

[0023] In some embodiments, before forming the third recess, further comprising: performing a patterning process on a second part of the second region to form a second trench isolation structure, the second trench isolation structure extending along the second direction; etching the substrate at the bottom of the second trench isolation structure to form the third recess.

[0024] The third recess is in communication with the second trench isolation structure.

[0025] In some embodiments, the second recess separates the substrate in the first region into a first substrate below the second recess and a second substrate above the second recess, and the fourth recess separates the substrate in the second region into a third substrate below the fourth recess and a fourth substrate above the fourth recess, the first substrate and the third substrate being connected to each other, and the second substrate and the fourth substrate being connected to each other.

[0026] In some embodiments, further comprising: filling a first sacrificial dielectric layer in the first trench isolation structure, and filling a second sacrificial dielectric layer in the second trench isolation structure, the first sacrificial dielectric layer and / or the second sacrificial dielectric layer being made of polysilicon or low-k dielectric material.

[0027] In some embodiments, the first sacrificial dielectric layer and / or the second sacrificial dielectric layer is in contact with the substrate, or a second dielectric layer or a fourth dielectric layer is arranged between the first sacrificial dielectric layer and / or the second sacrificial dielectric layer and the substrate.

[0028] In some embodiments, the stack structure comprises a first semiconductor layer and a second semiconductor layer stacked in sequence, the first semiconductor layer being germanium-silicon, and the second semiconductor layer being silicon.

[0029] In some embodiments, the first dielectric layer, the second dielectric layer, the third dielectric layer, or the fourth dielectric layer is made of one or more of silicon oxide, silicon nitride, silicon oxynitride, and low-k dielectric material.

[0030] In some embodiments, along a third direction, a depth of the fourth recess is greater than or equal to a depth of the second recess, the third direction intersecting a plane determined by the first direction and the second direction.

[0031] In some embodiments, along the third direction, a thickness of the fourth dielectric layer is greater than a thickness of the second dielectric layer.

[0032] Another aspect of the embodiments of the present disclosure further provides a semiconductor structure, comprising:

[0033] a substrate, the substrate comprising a first region and a second region distributed along a first direction;

[0034] a plurality of stacked device layers on an upper surface of the substrate;

[0035] The substrate comprises a first substrate and a second substrate in the first region, and a third substrate and a fourth substrate in the second region; the first substrate and the second substrate are spaced apart along a third direction, and the third substrate and the fourth substrate are spaced apart along the third direction; the first direction is parallel to the surface of the substrate, and the third direction intersects the surface of the substrate;

[0036] a second dielectric layer between the first substrate and the second substrate;

[0037] a fourth dielectric layer between the third substrate and the fourth substrate;

[0038] The second dielectric layer and the fourth dielectric layer are connected to each other.

[0039] In the third direction, the thickness of the fourth dielectric layer is greater than the thickness of the second dielectric layer.

[0040] In some embodiments, in the first direction, the interface between the fourth dielectric layer and the third substrate and / or the fourth substrate is curved.

[0041] In some embodiments, in the second direction, the interface between the second dielectric layer and the first substrate and / or the second substrate is curved, and the plane determined by the first direction and the second direction is parallel to the surface of the substrate.

[0042] In some embodiments, the stacked device layers comprise a plurality of transistor structures and / or a plurality of capacitor structures stacked along the third direction.

[0043] The technical solutions provided by the embodiments of the present disclosure have at least the following advantages: a substrate is provided, a plurality of first grooves are formed in a first region of the substrate, a first dielectric layer is formed on the sidewalls of the first grooves, the substrate is etched along the bottom of the first grooves to form second grooves inside the substrate, and a second dielectric layer is filled in the second grooves; a third groove is formed in a second region of the substrate, a third dielectric layer is formed on the sidewalls of the third groove; the substrate is etched along the bottom of the third groove to form a fourth groove inside the substrate, the fourth groove exposes the side surface of the second dielectric layer in the first direction; a fourth dielectric layer is filled in the fourth groove; and the fourth dielectric layer inside the substrate is connected to the second dielectric layer inside the substrate. The dielectric layer formed by the embodiments of the present disclosure can protect the substrate, prevent peeling of the stacked structure and substrate leakage, and improve the electrical performance of the stacked device. BRIEF DESCRIPTION OF DRAWINGS

[0044] One or more embodiments are illustrated by way of example in the drawings and specification hereof, which constitute part of this patent document, illustrate implementations of the embodiments disclosed in this patent document (and which, alone or in combination, support the embodiments disclosed in this patent document). The embodiments disclosed in this patent document are illustrative only and not restrictive of the present disclosure, unless otherwise specified. The drawings are not necessarily to scale, except as otherwise noted. For a better understanding of the present disclosure, and to further

[0045] FIG. 1 is a flowchart of a method for preparing a semiconductor structure according to an embodiment of the present disclosure;

[0046] FIGS. 2-20 are cross-sectional views of respective steps of a method for preparing a semiconductor structure according to an embodiment of the present disclosure.

[0047] FIGS. 21-23 are schematic views of a partial cross-section of a semiconductor structure according to an embodiment of the present disclosure.

[0048] Legend of reference signs:

[0049] I: first region; II: second region; 201: substrate; 2011: first substrate; 2012: second substrate; 2013: third substrate; 2014: fourth substrate; 200: stacked structure; 202: first semiconductor layer; 203: second semiconductor layer; 300: initial layer stack; 301: first portion; 302: second portion; 204: first trench isolation structure; 208: second trench isolation structure; 206: first gap; 210: second gap; 205: first recess; 207: second recess; 209: third recess; 211: fourth recess; 400: stacked device layer; 401: first dielectric layer; 501: second dielectric layer; 601: first sacrificial dielectric layer; 701: third dielectric layer; 801: fourth dielectric layer; 901: second sacrificial dielectric layer. DETAILED DESCRIPTION

[0050] The technical solutions of the present disclosure will be further described in detail below with reference to the drawings and embodiments. Although the exemplary implementation methods of the present disclosure are shown in the drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the implementation described herein. On the contrary, these implementations are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0051] The present disclosure is described more by way of example with reference to the following paragraphs and accompanying drawings. The advantages and features of the disclosure will become more fully apparent in light of the following description and claims, appended hereto. It should be understood that the drawings are not to scale, and are merely intended for use in illustrating the embodiments of the disclosure; and where used, like reference characters designate like elements throughout the several views.

[0052] It is to be understood that the terms "on", "over", and "above" in the present disclosure are to be interpreted in the broadest possible way, such that "on" encompasses not only the meaning of "on" something without intervening intermediate features or layers (i.e., directly on something), but also the meaning of "on" something with intervening intermediate features or layers.

[0053] In the embodiments of the present disclosure, the terms "first", "second", "third", etc. are used to distinguish similar objects, and do not necessarily have to describe a specific order or sequence.

[0054] In the embodiments of the present disclosure, the term "layer" refers to a portion of material that includes a region having a thickness. The layer can extend over the entirety of an underlying or overlying structure, or can have a scope that is less than the scope of an underlying or overlying structure. Further, a layer can be a region of a homogeneous or inhomogeneous continuous structure that has a thickness that is less than the thickness of the continuous structure. For example, a layer can be located between a top surface and a bottom surface of a continuous structure, or the layer can be between any pair of horizontal planes at the top surface and the bottom surface of the continuous structure. A layer can extend horizontally, vertically, and / or along an inclined surface. A layer can include multiple sub-layers.

[0055] It should be noted that the technical solutions described in the embodiments of the present disclosure can be combined arbitrarily without conflict.

[0056] As can be known from the background art, in the preparation process of the 3D DRAM, a stack structure is usually formed on the substrate first, and then the transistors, bit lines, word lines and capacitors of the memory cells are formed by etching or ion implantation on the stack structure. The number of the stack structure directly determines the storage density of the memory cells. Therefore, the formation process of the stack structure is crucial to the final performance and storage density of the 3D DRAM. The current stack structure is usually divided into two types: one is a non-epitaxial structure (Non-EPI) stack formed by a deposition process, which is a non-epitaxial structure of a dielectric layer and a dielectric layer (ONON) or a dielectric layer and a semiconductor layer (OPOP); and the other is an epitaxial structure (EPI) stack formed by an epitaxial process, which is usually a Si-SiGe epitaxial structure. Since the stack structure formed by the epitaxial structure is usually consistent with the lattice structure of the substrate, the stack structure formed has better lattice consistency, and the electrical properties of the formed memory cells tend to be consistent. Therefore, the stack structure formed based on the EPI process is the main process method for forming the 3D DRAM. The EPI process needs to use the substrate as an epitaxial substrate for epitaxial process. Therefore, the etching stop layer cannot be formed on the surface of the substrate. In the etching process, due to the limitation of the etching selectivity, the substrate used to form the stack structure will also be etched, which causes the substrate to be unable to be effectively protected and easily be etched or ion implanted multiple times, resulting in a risk of peeling of the stack structure on the substrate. In addition, due to the ion implantation of the substrate, the substrate may have a risk of electric leakage, which seriously causes the memory cells to be unable to work normally, reduces the electrical properties of the memory cells, and affects the device yield of the finally formed 3D DRAM.

[0057] The present disclosure provides a preparation method of a semiconductor structure, which comprises: providing a substrate, forming a plurality of first grooves in a first region of the substrate, and forming a first dielectric layer on the sidewalls of the first grooves; etching the substrate along the bottom of the first grooves to form a second groove inside the substrate, and filling a second dielectric layer in the second groove; forming a third groove in a second region of the substrate, and forming a third dielectric layer on the sidewalls of the third groove; etching the substrate along the bottom of the third groove to form a fourth groove inside the substrate, and the fourth groove exposes the side surface of the second dielectric layer in the first direction; filling a fourth dielectric layer in the fourth groove; and the fourth dielectric layer inside the substrate and the second dielectric layer inside the substrate are connected to each other. The dielectric layer formed in the present disclosure can protect the substrate, prevent the peeling of the stack structure and the electric leakage of the substrate, and improve the electrical properties of the stack device. In the following, the embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. However, those skilled in the art can understand that in the embodiments of the present disclosure, many technical details are proposed in order to enable the readers to better understand the embodiments of the present disclosure. However, the technical solutions claimed by the embodiments of the present disclosure can be realized even without these technical details and various changes and modifications based on the following embodiments.

[0058] One embodiment of the present disclosure provides a method for preparing a semiconductor structure. The method for preparing a semiconductor structure provided by one embodiment of the present disclosure will be described in detail below with reference to the accompanying drawings. FIG. 1 is a flowchart of a method for preparing a semiconductor structure provided by one embodiment of the present disclosure.

[0059] Referring to FIG. 1, the method for preparing a semiconductor structure specifically includes the following steps.

[0060] S01: providing a substrate; the substrate includes a first region and a second region distributed along a first direction, and a stack structure is formed on the substrate;

[0061] S02: forming a plurality of first grooves, the plurality of first grooves being located in the first region of the substrate, and the plurality of first grooves being located in the substrate, the first grooves extending along a first direction, and the plurality of first grooves being arranged at intervals along a second direction; a plane determined by the first direction and the second direction is parallel to the surface of the substrate;

[0062] S03: forming a first dielectric layer on the sidewall of the first groove; etching the substrate along the bottom of the first groove to form a second groove located inside the substrate, along the second direction, adjacent first grooves are connected to each other through the second groove, and a second dielectric layer is filled in the second groove;

[0063] S04: forming a third groove, the third groove being located in the second region of the substrate and extending along the second direction, and the third groove being located in the substrate;

[0064] S05: forming a third dielectric layer on the sidewall of the third groove; etching the substrate along the bottom of the third groove to form a fourth groove located inside the substrate, the fourth groove exposing the side surface of the second dielectric layer along the first direction; filling a fourth dielectric layer in the fourth groove; the fourth dielectric layer located inside the substrate and the second dielectric layer located inside the substrate are connected to each other.

[0065] FIGS. 2-20 are partial schematic diagrams corresponding to each step in the method for preparing a semiconductor structure provided by an embodiment of the present disclosure. The method for preparing a semiconductor structure provided by an embodiment of the present disclosure will be described in detail below with reference to FIGS. 2-20.

[0066] Step S01: providing a substrate; the substrate includes a first region and a second region distributed along a first direction X, and forming a stack structure on the substrate; specifically including the following steps, as shown in FIG. 2, a substrate 201 is provided, according to the dashed line shown in the figure, the substrate 201 includes a first region I and a second region II distributed along a first direction X, wherein the substrate material includes monocrystalline silicon, polycrystalline silicon, amorphous silicon, germanium, silicon carbide, germanium silicon, germanium on insulator (GOI) or silicon on insulator (SOI) and the like. In the embodiment of the present disclosure, in order to form a silicon-germanium silicon stack structure on the substrate using an epitaxial process, the substrate material is selected as a monocrystalline silicon material, in some embodiments, an N-type or P-type substrate 201 can be formed by performing N-type or P-type doping treatment on the monocrystalline silicon material and performing annealing treatment, the N-type element can be a group V element such as phosphorus (P) element, bismuth (Bi) element, antimony (Sb) element or arsenic (As) element. The P-type element can be a group III element such as boron (B) element, aluminum (Al) element, gallium (Ga) element or indium (In) element. In some embodiments, only the upper surface of the substrate can be doped, an N-type doped layer or a P-type doped layer can be formed on the surface of the substrate, or the entire substrate can be doped to form an N-type substrate 201 or a P-type substrate 201. In the embodiment of the present disclosure, before epitaxially forming the stack structure on the substrate 201, the surface of the substrate 201 can be pretreated to remove impurities or natural oxide layer on the surface. As shown in FIG. 2, a multilayer stack structure 200 is formed on the substrate 201 and stacked along a third direction Z, along the third direction, the stack structure 200 includes a first semiconductor layer 202 and a second semiconductor layer 203 stacked in sequence. The first semiconductor layer 202 can be formed of or include at least one of, for example, silicon germanium, silicon oxide, silicon nitride and silicon oxynitride. In some embodiments, the first semiconductor layer 202 can be formed by an epitaxial growth method and can be, for example, a silicon germanium layer. The second semiconductor layer 203 can be formed of or include at least one of, for example, silicon, germanium, silicon germanium and indium gallium zinc oxide (IGZO). In some embodiments, the second semiconductor layer 203 can be formed of or include the same semiconductor material as the substrate 201. For example, the second semiconductor layer 203 can be formed by an epitaxial growth method and can be a monocrystalline silicon layer. In the embodiment of the present disclosure, a germanium silicon layer and a silicon layer formed by epitaxial growth are taken as examples for description, the formed stack structure has a crystal structure similar to superlattice, since the crystal lattice structures of the germanium silicon layer and the silicon layer are the same, the stack structure can be formed by epitaxial growth, which reduces the generation of defects in the stack structure and is beneficial to improve the electrical performance of the formed semiconductor structure.The embodiments of the present disclosure take forming a five-layer stack structure as an example for illustration, and in actual processes, the number of layers is not limited, and the number of layers can be selected according to actual stacking requirements.

[0067] Step S02: forming a plurality of first grooves, the plurality of first grooves being located in the first region of the substrate, and the plurality of first grooves being located in the substrate, the first grooves extending along a first direction, and the plurality of first grooves being spaced apart along a second direction; a plane determined by the first direction and the second direction is parallel to the surface of the substrate; specifically including the following steps, as shown in FIG. 3, forming a mask layer (not shown) above the stack structure 200, and performing a patterning process on the stack structure 200, the patterning process including dry etching, wet etching, or a combination of the two, and the stack structure 200 after the patterning process forms an initial layer stack structure 300, the initial layer stack structure 300 including a plurality of first portions 301 located in the first region I and a second portion 302 located in the second region II; the plurality of first portions 301 extend along a first direction X, and the second portion 302 extends along a second direction Y; the plurality of first portions are spaced apart along the second direction, and a first trench isolation structure 204 is formed between adjacent first portions along the second direction; the first trench isolation structure 204 exposes part of the surface of the substrate 201. By the exposed part of the surface, dry or wet etching is performed on the substrate 201 to form a plurality of first grooves 205 in the first region I of the substrate, FIGS. 4a and 4b are cross-sectional views along A-A' and B-B' after etching the substrate 201 in FIG. 3, referring to FIG. 3 and FIGS. 4a and 4b, by forming a mask layer (not shown) on the initial layer stack structure 300, the substrate 201 exposed by the first trench isolation structure 204 is etched to form a plurality of first grooves 205 extending into the substrate 201 along a third direction Z, the plurality of first grooves 205 extend along the first direction, and the plurality of first grooves 205 are spaced apart along the second direction Y, as can be seen from FIG. 4a, the plurality of first grooves 205 are formed by etching the substrate exposed by the plurality of first trench isolation structures 204, therefore, the plurality of first grooves 205 and the plurality of first trench isolation structures 204 are in communication with each other. In some embodiments, the first grooves 205 and the first trench isolation structures 204 can be formed in the same step, that is, while the stack structure 200 is subjected to the patterning process to form the initial layer stack structure 300, the substrate 201 is also subjected to the patterning process to form the plurality of first grooves 205 in the substrate 201, and the embodiments of the present disclosure are not limited in this regard.

[0068] Step S03: forming a first dielectric layer on the sidewall of the first recess; etching the substrate along the bottom of the first recess to form a second recess inside the substrate, along the second direction, adjacent first recesses are connected to each other through the second recess, and filling the second recess with a second dielectric layer; specifically including the following steps, as shown in FIGS. 5a and 5b, the first semiconductor layer 202 in the first part 301 in the initial layer stack structure 300 is selectively etched by the first trench isolation structure 204, and the first semiconductor layer 202 in the first part 301 is removed. In some embodiments, a wet etching process can be used to remove the first semiconductor layer 202. By using an etching selectivity ratio (for example, greater than 10:1) between the first semiconductor layer 202 and the second semiconductor layer 203, the first semiconductor layer 202 on the first region I is removed, while the second semiconductor layer 203 is not etched or is etched in a small amount, thereby forming a plurality of first gaps 206 between the second semiconductor layer 203, and the plurality of first gaps 206 are connected to each other through the first trench isolation structure 204. As shown in FIGS. 6a and 6b, a first dielectric layer 401 is deposited by a chemical vapor deposition (CVD), a physical vapor deposition (PVD), or an atomic layer deposition (ALD) process, etc. The first dielectric layer 401 fills the first gap 206, the sidewall of the first trench isolation structure 204, the sidewall and the bottom of the first recess 205. In some embodiments, after the first dielectric layer 401 is deposited, a chemical mechanical polishing (CMP) process can be used to remove the top first dielectric layer, so that the top of the polished first dielectric layer 401 is flush with the top surface of the second semiconductor layer 203 or the mask layer located in the uppermost layer. In some embodiments, the material of the deposited first dielectric layer includes one or a combination of silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), and low-k dielectric material. The low-k dielectric material refers to a material with a dielectric constant less than 3, for example, the low-k dielectric constant material can be but is not limited to one or a combination of SiOH, SiOCH, FSG (fluorosilicate glass), BSG (borosilicate glass), PSG (phosphosilicate glass), and BPSG (borophosphosilicate glass).As shown in FIGS. 7a and 7b, the first dielectric layer 401 at the bottom of the first recess 205 is etched to remove the first dielectric layer at the bottom and retain the first dielectric layer 401 at the sidewall of the first recess 205. In some embodiments, a dry etching process can be used to etch the first dielectric layer 401 at the bottom of the first recess 205. Specifically, a plasma etching process can be used to perform an anisotropic etching process on the first dielectric layer 401 to remove the first dielectric layer at the bottom of the first recess 205, while the first dielectric layer 401 at the sidewall of the first recess 205 and the first trench isolation structure 204 is not etched or etched by a small amount. By removing the first dielectric layer 401 at the bottom of the first recess 205, part of the surface of the substrate 201 is exposed. As shown in FIGS. 8a and 8b, the exposed substrate 201 at the bottom of the first recess 205 is etched using the first dielectric layer 401 at the sidewall of the first recess 205 as an etching mask to form a second recess 207 in the substrate 201. The second recess 207 is located in the first region I of the substrate 201. As shown in FIGS. 7a and 8a, 8b, the second recess 207 is formed in the interior of the substrate 201, that is, the substrate 201 in the first region I is isolated into a first substrate 2011 below the second recess 207 and a second substrate 2012 above the second recess 207 by the second recess 207. In some embodiments, the second recess 207 extends along the first direction X and the second direction Y and covers the entire first region I, that is, the first recess 205 adjacent along the second direction Y is connected to each other by the second recess 207. In some embodiments, the second recess 207 is formed by a wet isotropic etching process. In the wet etching process, the etching selectivity of the substrate 201 and the first dielectric layer 401 is relatively large (e.g., greater than 10:1), so that the first dielectric layer 401 can act as an etching barrier layer and is not etched or etched by a small amount during the etching process to remove part of the substrate 201. As shown in FIGS. 9a and 9b, a second dielectric layer 501 is deposited by a chemical vapor deposition (CVD), a physical vapor deposition (PVD), or an atomic layer deposition (ALD) process, etc. The second dielectric layer 501 fills the second recess 207 and covers the sidewall of the first dielectric layer 401. In some embodiments, the material of the deposited second dielectric layer includes one or a combination of silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), and low-k dielectric material.As shown in FIGS. 10a and 11a, the second dielectric layer 501 at the bottom of the first recess 205 is etched to remove the second dielectric layer at the bottom and retain the second dielectric layer 501 at the sidewall of the first recess 205. In some embodiments, dry etching process can be used to etch the second dielectric layer 501 at the bottom of the first recess 205, specifically, anisotropic etching process can be used to etch the second dielectric layer 501 to remove the second dielectric layer 501 at the bottom of the first recess 205. As shown in FIG. 11a, the first sacrificial dielectric layer 601 is filled in the first trench isolation structure 204 and the first recess 205, which can be formed by chemical vapor deposition, physical vapor deposition or atomic layer deposition, etc. Since the second dielectric layer 501 at the bottom of the first recess 205 is etched, the filled first sacrificial dielectric layer 601 is in direct contact with the first substrate 2011 in the substrate 201. In some embodiments, only part of the second dielectric layer 501 at the bottom of the first recess 205 can be removed, so that the first sacrificial dielectric layer 601 is not in direct contact with the first substrate 2011, but in direct contact with the remaining second dielectric layer 501. In the embodiments of the present disclosure, whether the first sacrificial dielectric layer is in direct contact with the substrate is not specifically limited. In some embodiments, the material of the first sacrificial dielectric layer 601 is polysilicon or low-k dielectric material.

[0069] Step S04: forming a third recess in the second region of the substrate and extending along the second direction, specifically comprising: as shown in FIGS. 12-13, forming a mask layer (not shown) above the second part 302 of the initial layer stack 300, and performing a patterning process on the second part 302, which includes dry etching, wet etching or a combination of the two, to form a second trench isolation structure 208 extending along the second direction Y, and the second trench isolation structure 208 exposes part of the surface of the substrate 201 in the second region II. Through the exposed part of the surface, dry or wet etching is performed on the substrate 201 to form a third recess 209 in the second region II of the substrate 201, which extends along the second direction Y and extends into the substrate 201 along the third direction Z. As can be seen from FIGS. 12-13, the third recess 209 is formed by etching the substrate exposed by the second trench isolation 208, so the third recess 209 and the second trench isolation structure 208 are in communication with each other. In some embodiments, the third recess 209 and the second trench isolation structure 208 can be formed in the same step, that is, the second part 302 is patterned at the same time, and the substrate 201 is also patterned to form the third recess 209 in the substrate 201. The embodiments of the present disclosure do not specifically limit this.

[0070] Step S05: forming a third dielectric layer on the sidewall of the third recess; etching the substrate along the bottom of the third recess to form a fourth recess inside the substrate, the fourth recess exposes the side surface of the second dielectric layer along the first direction; filling the fourth recess with a fourth dielectric layer; the fourth dielectric layer inside the substrate and the second dielectric layer inside the substrate are connected to each other, specifically including: as shown in FIG. 14, the second part 302 is selectively etched by the second trench isolation structure 208 to remove the first semiconductor layer 202 in the second part 302, in some embodiments, a wet etching process can be used to remove the first semiconductor layer 202, by using an etching selectivity ratio (such as greater than 10:1) between the first semiconductor layer 202 and the second semiconductor layer 203, the first semiconductor layer 202 on the second region II is removed, while the second semiconductor layer 203 is basically not etched or a small amount of the second semiconductor layer 203 is etched, thereby forming a plurality of second gaps 210 between the second semiconductor layer 203, the plurality of second gaps 210 are in communication with the second trench isolation structure 208. As shown in FIG. 15, a third dielectric layer 701 is deposited by a process such as chemical vapor deposition, physical vapor deposition or atomic layer deposition, the third dielectric layer 701 fills the second gap 210, the sidewall of the second trench isolation structure 208 and the sidewall and bottom of the third recess 209. In some embodiments, after the third dielectric layer 701 is deposited, a chemical mechanical polishing process can be used to remove the top third dielectric layer 701, so that the top of the third dielectric layer 701 after polishing is flush with the top surface of the uppermost second semiconductor layer 203 or the mask layer. In some embodiments, the material of the deposited third dielectric layer includes one or a combination of silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON) and low-k dielectric material. As shown in FIG. 16, the third dielectric layer 701 at the bottom of the third recess 209 is etched to remove the third dielectric layer at the bottom while retaining the third dielectric layer 701 at the sidewall of the third recess 209, in some embodiments, a dry etching process can be used to etch the third dielectric layer 701 at the bottom of the third recess 209, specifically, a plasma etching process can be used to perform an anisotropic etching process on the third dielectric layer 701, to remove the third dielectric layer at the bottom of the third recess 209, while the third dielectric layer 701 at the sidewall of the third recess 209 and the second trench isolation structure 208 is not etched or a small amount of the third dielectric layer is etched. By removing the third dielectric layer 701 at the bottom of the third recess 209, part of the surface of the substrate 201 is exposed.As shown in FIG. 17, a third dielectric layer 701 on the sidewall of the third trench 209 is used as an etching mask to etch the substrate 201 exposed at the bottom of the third trench 209 to form a fourth trench 211 inside the substrate 201, and the fourth trench 211 is located in the second region II of the substrate 201. As shown in FIG. 17, the fourth trench 211 is formed inside the substrate 201, which means that the substrate 201 in the second region II is separated into a third substrate 2013 below the fourth trench 211 and a fourth substrate 2014 above the fourth trench 211 by the third trench 209. In some embodiments, the fourth trench 211 extends along the first direction X and the second direction Y and covers the entire second region II. In some embodiments, the fourth trench 211 is formed by a wet isotropic etching process. In the wet etching process, the etching selectivity of the substrate 201 and the third dielectric layer 701 is relatively large (e.g., greater than 10: 1), so that the third dielectric layer 701 can be used as an etching stop layer and is not etched or is slightly etched during the etching of the substrate 201. As shown in FIG. 17, the fourth trench 211 inside the substrate is in communication with the third trench 209, and the fourth trench 211 exposes the side of the second dielectric layer 501 along the first direction X. As shown in FIG. 18, a fourth dielectric layer 801 is deposited by a chemical vapor deposition, physical vapor deposition or atomic layer deposition process, and the fourth dielectric layer 801 fills the fourth trench 211 and covers the sidewall of the third dielectric layer 701. In some embodiments, the material of the deposited fourth dielectric layer includes one or a combination of silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON) and low-k dielectric material. As shown in FIG. 18, the filled fourth dielectric layer 801 is connected to the second dielectric layer 501 inside the substrate in the first region I. In some embodiments, the material of the fourth dielectric layer 801 is the same as the material of the second dielectric layer 501, such as both being silicon oxide material.

[0071] As shown in FIG. 19, the fourth dielectric layer 801 at the bottom of the third recess 209 is etched to remove the fourth dielectric layer at the bottom and retain the fourth dielectric layer 801 at the sidewall of the third recess 209. In some embodiments, dry etching process can be used to etch the fourth dielectric layer 801 at the bottom of the third recess 209, specifically, plasma etching process can be used to perform anisotropic etching process on the fourth dielectric layer 801 to remove the fourth dielectric layer 801 at the bottom of the third recess 209. As shown in FIG. 19, the second sacrificial dielectric layer 901 is filled in the second trench isolation structure 208 and the third recess 209, which can be formed by chemical vapor deposition, physical vapor deposition or atomic layer deposition. Since the fourth dielectric layer 801 at the bottom of the third recess 209 is etched, the filled second sacrificial dielectric layer 901 is in direct contact with the third substrate 2013 in the substrate 201. In some embodiments, only part of the fourth dielectric layer 801 at the bottom of the third recess 209 can be removed, so that the second sacrificial dielectric layer 901 is not in direct contact with the third substrate 2013, but in direct contact with the remaining fourth dielectric layer 801. In the embodiments of the present disclosure, whether the second sacrificial dielectric layer is in direct contact with the substrate is not specifically limited. In some embodiments, the material of the second sacrificial dielectric layer 901 is polysilicon or low-k dielectric material.

[0072] In some embodiments, the first substrate 2011 and the third substrate 2013 are connected to each other, and the second substrate 2012 and the fourth substrate 2014 are connected to each other. As shown in FIG. 19, the thickness of the first substrate 2011 and the third substrate 2013 is the same, and those skilled in the art can understand that, in the process of etching the substrate to form the second recess 207 and the fourth recess 211, wet isotropic etching process is used, so that the upper surface of the first substrate 2011 and the third substrate 2013 or the lower surface of the second substrate 2012 and the fourth substrate is not a flat surface, i.e., an irregular surface with arc or curved shape. As shown in FIGS. 21-22, along the second direction Y, the interface between the second dielectric layer 501 and the first substrate 2011 and / or the second substrate 2012 has a curved surface shape, and along the first direction, the interface between the fourth dielectric layer 801 and the third substrate 2013 and / or the fourth substrate 2014 has a curved surface shape.

[0073] In some embodiments, in order to expose the side surface of the second dielectric layer 501 completely through the fourth groove 211, the etching time for etching the substrate of the second region to form the fourth groove 211 is greater than the etching time for etching the substrate of the first region to form the second groove 207, so that the depth of the fourth groove 211 etched into the substrate is greater than the depth of the second groove 207 etched into the substrate. As shown in FIG. 20, finally, the thickness of the fourth dielectric layer 801 filled in the fourth groove is greater than the thickness of the second dielectric layer 501 filled in the second groove. In some embodiments, the contact surface of the fourth dielectric layer 801 and the second dielectric layer 501 in the fourth groove 211 and the second groove 207 with the substrate (including the first substrate 2011, the second substrate 2012, the third substrate 2013 and the fourth substrate 2014) has an irregular surface with an arc-shaped curved shape, and at this time, the thickness of the fourth dielectric layer 801 filled in the fourth groove is greater than the thickness of the second dielectric layer 501 filled in the second groove refers to the average thickness.

[0074] In another aspect of the present disclosure, a semiconductor structure is disclosed, which is formed by the above method for manufacturing a semiconductor structure, as shown in FIGS. 21-23, the semiconductor structure comprises: a substrate 201, a stacked device layer 400 located above the substrate 201, the substrate 201 comprises a first substrate 2011 located in a first region I, a second substrate 2012, and a third substrate 2013 and a fourth substrate 2014 located in a second region II, a second dielectric layer 501 located between the first substrate 2011 and the second substrate 2013 along a third direction Z, and a fourth dielectric layer 801 located between the third substrate 2013 and the fourth substrate 2014, wherein the second dielectric layer 501 and the fourth dielectric layer 801 are connected to each other, the first substrate 2011 and the third substrate 2013 are connected to each other, and the second substrate 2012 and the fourth substrate 2014 are connected to each other. The thickness of the fourth dielectric layer 801 is greater than the thickness of the second dielectric layer 501.

[0075] In some embodiments, as shown in FIG. 22, along the second direction Y, the interface between the second dielectric layer 501 and the first substrate 2011 and / or the second substrate 2012 has a curved surface shape, and in some embodiments, as shown in FIG. 23, along the first direction, the interface between the fourth dielectric layer 801 and the third substrate 2013 and / or the fourth substrate 2014 has a curved surface shape.

[0076] In some embodiments, the stacked device layer 400 comprises a plurality of transistor structures (not shown) and / or a plurality of capacitor structures (not shown) stacked along the third direction Z, and each layer of transistor structures and corresponding capacitor structures are electrically connected to form a memory cell structure.

[0077] In summary, the preparation method of the semiconductor structure and the semiconductor structure provided by the embodiments of the present disclosure form an epitaxial stack structure on a substrate, improve the lattice consistency of the epitaxial structure, reduce the generation of dislocations or defects, form a first trench isolation structure and a second trench isolation structure by etching the stack structure to expose part of the surface of the substrate, etch the substrate through the first trench isolation structure and the second trench isolation structure to form a first groove and a third groove that penetrate into the interior of the substrate, and perform lateral etching on the interior of the substrate through the first groove and the third groove to form a second groove and a fourth groove in the interior of the substrate, fill an insulating layer in the second groove and the fourth groove, and the insulating layer can protect the bottom substrate from being etched and play the role of an etching stop layer. At the same time, due to the isolation effect of the insulating layer, the generation of leakage current can be effectively avoided. In addition, the upper part of the substrate and the stack structure always maintain an integral structure, which can effectively prevent the stack structure from being peeled off from the substrate, improve the stability of the stack device structure, and improve the electrical performance thereof.

[0078] The various semiconductor structures shown in the specific embodiments can be used in electronic devices with storage functions. The electronic device can be a terminal device, such as a mobile phone, a tablet computer, a smart bracelet, or a personal computer (PC), a server, a workstation, etc. The storage function in the electronic device can be realized by a memory such as a dynamic random access memory (DRAM), a ferroelectric random access memory (FRAM), a phase change memory (PCM), a magnetic random access memory (MRAM), or a resistive random access memory (RRAM).

[0079] The above merely describes the specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art can easily think of changes or replacements within the technical scope disclosed by the present disclosure, which should be covered within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A method of fabricating a semiconductor structure, characterized by, The method comprises the following steps: providing a substrate (201); the substrate comprises a first region (I) and a second region (II) distributed along a first direction (X), and a stack structure (200) is formed on the substrate; forming a plurality of first grooves (205) in the first region of the substrate, and the plurality of first grooves are formed in the substrate, the first grooves extend along a first direction, and the plurality of first grooves are arranged at intervals along a second direction (Y); the plane determined by the first direction and the second direction is parallel to the surface of the substrate; forming a first dielectric layer (401) on the sidewall of the first groove; etching the substrate along the bottom of the first groove to form a second groove (207) in the substrate, and the adjacent first grooves are connected to each other through the second groove along the second direction; filling a second dielectric layer (501) in the second groove.

2. The method of claim 1, wherein the semiconductor structure is prepared by a method comprising: The method further comprises the following steps: forming a third groove (209) in the second region of the substrate and extending along the second direction, and the third groove is formed in the substrate; forming a third dielectric layer (701) on the sidewall of the third groove; etching the substrate along the bottom of the third groove to form a fourth groove (211) in the substrate, and the fourth groove exposes the side surface of the second dielectric layer along the first direction; filling a fourth dielectric layer (801) in the fourth groove; the fourth dielectric layer in the substrate is connected to the second dielectric layer in the substrate.

3. The method of claim 2, wherein the semiconductor structure is prepared by a method comprising: Before forming the plurality of first grooves, the method further comprises the following steps: patterning the stack structure to form an initial layer stack structure (300), the initial layer stack structure comprises a plurality of first parts (301) in the first region and a second part (302) in the second region; the plurality of first parts extend along the first direction, and the second part extends along the second direction; the plurality of first parts are arranged at intervals along the second direction, and a first trench isolation structure (204) is formed between adjacent first parts; etching the substrate at the bottom of the first trench isolation structure to form the first groove; the first groove is connected to the first trench isolation structure.

4. The method of claim 3, wherein the semiconductor structure is prepared by a method comprising: Before forming the third groove, the method further comprises the following steps: patterning the second part in the second region to form a second trench isolation structure (208), the second trench isolation structure extends along the second direction, and etching the substrate at the bottom of the second trench isolation structure to form the third groove; the third groove is connected to the second trench isolation structure.

5. The method of claim 4, wherein the semiconductor structure is prepared by a method comprising: The second groove separates the substrate in the first region into a first substrate (2011) below the second groove and a second substrate (2012) above the second groove, and the fourth groove separates the substrate in the second region into a third substrate (2013) below the fourth groove and a fourth substrate (2014) above the fourth groove, and the first substrate and the third substrate are connected to each other, and the second substrate and the fourth substrate are connected to each other.

6. The method of claim 5, wherein the semiconductor structure is prepared by a method comprising: Further comprising: The first trench isolation structure is filled with a first sacrificial dielectric layer (601), and the second trench isolation structure is filled with a second sacrificial dielectric layer (901), and the material of the first sacrificial dielectric layer and / or the second sacrificial dielectric layer is polysilicon or low-k dielectric material.

7. The method of claim 6, wherein: The first sacrificial dielectric layer and / or the second sacrificial dielectric layer is in contact with the substrate, or a second dielectric layer (501) or a fourth dielectric layer (801) is arranged between the first sacrificial dielectric layer and / or the second sacrificial dielectric layer and the substrate.

8. The method of claim 1-5, wherein: The stack structure comprises a first semiconductor layer (202) and a second semiconductor layer (203) stacked in sequence, the first semiconductor layer is germanium-silicon, and the second semiconductor layer is silicon.

9. The method of claim 2, wherein: The material of the first dielectric layer, the second dielectric layer, the third dielectric layer, or the fourth dielectric layer is one or more of silicon oxide, silicon nitride, silicon oxynitride, and low-k dielectric material.

10. The method of claim 2, wherein: In the third direction, the depth of the fourth groove is greater than or equal to the depth of the second groove, and the third direction intersects the plane determined by the first direction and the second direction.

11. The method of claim 10, wherein: In the third direction, the thickness of the fourth dielectric layer is greater than the thickness of the second dielectric layer.

12. The method of claim 7, wherein the semiconductor structure is prepared by a method comprising: In the first direction, the interface between the fourth dielectric layer and the third substrate and / or the fourth substrate is curved.

13. The method of claim 7, wherein the semiconductor structure is prepared by a method comprising: In the second direction, the interface between the second dielectric layer and the first substrate and / or the second substrate is curved, and the plane determined by the first direction and the second direction is parallel to the surface of the substrate.

14. A semiconductor structure, characterized by Comprise: A substrate (201) comprising a first region (I) and a second region (II) distributed along a first direction (X); A stacked device layer (400) located on the upper surface of the substrate; The substrate comprises a first substrate (2011) and a second substrate (2012) located in the first region, and a third substrate (2013) and a fourth substrate (2014) located in the second region; the first substrate and the second substrate are spaced apart along a third direction (Z), and the third substrate and the fourth substrate are spaced apart along the third direction; the first direction is parallel to the surface of the substrate, and the third direction intersects the surface of the substrate; A second dielectric layer (501) located between the first substrate and the second substrate; A fourth dielectric layer (801) located between the third substrate and the fourth substrate; Wherein, the second dielectric layer and the fourth dielectric layer are connected to each other; In the third direction, the thickness of the fourth dielectric layer is greater than the thickness of the second dielectric layer.

15. The semiconductor structure of claim 14, wherein, In the first direction, an interface between the fourth dielectric layer and the third substrate and / or the fourth substrate is in a curved shape.

16. The semiconductor structure of claim 14, wherein, In a second direction, an interface between the second dielectric layer and the first substrate and / or the second substrate is in a curved shape, and a plane determined by the first direction and the second direction is parallel to a surface of the substrate.

17. The semiconductor structure of claim 15, wherein, The stacked device layer includes a plurality of transistor structures and / or a plurality of capacitor structures arranged in a stacked manner along a third direction.

18. The semiconductor structure of claim 14, wherein, The second dielectric layer or the fourth dielectric layer is made of one or more of silicon oxide, silicon nitride, silicon oxynitride, and low-k dielectric material.

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