Read and write processing method and apparatus for memory, and device and storage medium

Abstract

The present disclosure relates to the technical field of memories. Provided are a read and write processing method and apparatus for a memory, and a device and a storage medium. The method comprises: when a host writes target data into a memory, storing in a P2L cache a plurality of logical unit addresses corresponding to the target data, and on the basis of a first determination condition and a second determination condition, determining the P2L cache and the logical unit addresses, so as to obtain target threshold values of the logical unit addresses in the P2L cache; and when the host reads the target data from the memory, separately determining whether the target threshold values of the logical unit addresses in the P2L cache are legitimate numerical values, so as to obtain a plurality of corresponding target determination results, and on the basis of the target determination results, respectively determining whether to search the P2L cache for the logical unit addresses. In this way, it is possible to avoid the extra time consumption caused by querying a P2L cache when a logical address read by a host is not in the P2L cache, thereby improving the read performance of a memory.

Description

Read-write processing method, device and equipment of memory and storage medium

[0001] Cross-reference to related applications

[0002] The present disclosure claims priority to the Chinese patent application No. 2024107257922, filed on June 6, 2024, and entitled "Read-write processing method, device and equipment of memory and storage medium", the whole content of which is incorporated herein by reference. TECHNICAL FIELD

[0003] The present disclosure relates to the technical field of memory, and in particular to a read-write processing method, device and equipment of memory and storage medium. BACKGROUND

[0004] When the host reads data corresponding to a logical unit address from the memory, it is necessary to traverse whether the logical unit address read by the host exists in the P2L cache. When the P2L cache is close to full, the time spent is about 20us. Therefore, when the logical unit address to be queried is not in the P2L cache, an additional 20us or so of time will be wasted.

[0005] SUMMARY

[0006] Therefore, the purpose of the present disclosure is to overcome the deficiencies in the prior art and provide a read-write processing method, device and equipment of memory and storage medium to solve the problem that when the logical unit address queried by the host is not in the P2L cache, the P2L cache still needs to be traversed, resulting in wasted time.

[0007] The present disclosure provides the following technical solutions:

[0008] The present disclosure provides a read-write processing method of memory, comprising:

[0009] When the host writes target data to the memory, a plurality of logical unit addresses corresponding to the target data are stored in the P2L cache, and the P2L cache and each logical unit address are judged based on a first judgment condition and a second judgment condition to obtain a logical unit address target threshold in the P2L cache;

[0010] When the host reads the target data from the memory, it is respectively judged whether the logical unit address target threshold in each P2L cache is a legal value to obtain a plurality of corresponding target judgment results, and it is respectively determined whether to find each logical unit address from the P2L cache according to each target judgment result.

[0011] In an embodiment, the target judgment result includes a first judgment result and a second judgment result, and the target threshold of the P2L cache logical unit address includes a target maximum value and a target minimum value of the P2L cache logical unit address.

[0012] The determining whether to search the logical unit address from the P2L cache according to each target judgment result includes:

[0013] If the first judgment result is that the target threshold of the P2L cache logical unit address is an illegal value, then searching the logical unit address from the P2L cache.

[0014] If the first judgment result is that the target threshold of the P2L cache logical unit address is a legal value, then judging whether the logical unit address is greater than or equal to the target minimum value of the P2L cache logical unit address and whether the logical unit address is less than or equal to the target maximum value of the P2L cache logical unit address to obtain the second judgment result; and determining whether to search the logical unit address from the P2L cache according to the second judgment result.

[0015] In an embodiment, the determining whether to search the logical unit address from the P2L cache according to the second judgment result includes:

[0016] If the second judgment result is that the logical unit address is greater than or equal to the target minimum value of the P2L cache logical unit address and the logical unit address is less than or equal to the target maximum value of the P2L cache logical unit address, then searching the logical unit address from the P2L cache.

[0017] If the second judgment result is that the logical unit address is less than the target minimum value of the P2L cache logical unit address or the logical unit address is greater than the target maximum value of the P2L cache logical unit address, then not searching the logical unit address from the P2L cache.

[0018] In an embodiment, before the step of the host writing target data to the memory, the method includes:

[0019] The memory is started, and the target threshold of the P2L cache logical unit address is set as an illegal value.

[0020] In an embodiment, the first judging condition comprises a storage condition of the P2L cache, the host writes target data to the memory, stores a plurality of logical unit addresses corresponding to the target data into the P2L cache, and judges the P2L cache and each of the logical unit addresses based on the first judging condition and the second judging condition to obtain a logical unit address target threshold in the P2L cache, comprising:

[0021] The host writes the logical unit address to the P2L cache;

[0022] Judging whether the logical unit address target threshold in the P2L cache is an illegal value;

[0023] If the logical unit address target threshold in the P2L cache is an illegal value, judging whether the P2L cache is empty based on the first judging condition;

[0024] If the P2L cache is empty, updating the newly written logical unit address of the host to the logical unit address target threshold in the P2L cache, and storing the logical unit address into the P2L cache.

[0025] In an embodiment, the second judging condition comprises a size condition of each of the logical unit addresses, the storing of the plurality of logical unit addresses corresponding to the target data into the P2L cache, and the judging of the P2L cache and each of the logical unit addresses based on the first judging condition and the second judging condition to obtain a logical unit address target threshold in the P2L cache further comprises:

[0026] After the storing of the logical unit address into the P2L cache, comprising:

[0027] Judging whether the P2L cache is full based on the first judging condition;

[0028] If the P2L cache is full, emptying the P2L cache and re-executing the step of setting the logical unit address target threshold in the P2L cache to an illegal value;

[0029] If the P2L cache is not full, judging whether the newly written logical unit address of the host is less than a logical unit address target minimum value in the P2L cache based on the second judging condition;

[0030] If the logical unit address is less than the logical unit address target minimum value in the P2L cache, updating the logical unit address to the logical unit address target minimum value in the P2L cache, storing the logical unit address into the P2L cache, and re-executing the step of judging whether the P2L cache is full based on the first judging condition;

[0031] if the logical unit address is greater than or equal to the target minimum logical unit address in the P2L cache, judging whether the logical unit address is greater than the target maximum logical unit address in the P2L cache based on the second judging condition;

[0032] if the logical unit address is greater than the target maximum logical unit address in the P2L cache, updating the logical unit address to the target maximum logical unit address in the P2L cache, storing the logical unit address into the P2L cache, and re-executing the step of judging whether the P2L cache is full based on the first judging condition;

[0033] if the logical unit address is less than or equal to the target maximum logical unit address in the P2L cache, storing the logical unit address into the P2L cache, and re-executing the step of judging whether the P2L cache is full based on the first judging condition.

[0034] In an embodiment, after judging whether the P2L cache is empty, the method further comprises:

[0035] if the P2L cache is not empty, storing the new logical unit address written by the host into the P2L cache, and re-executing the step of judging whether the P2L cache is full based on the first judging condition;

[0036] if the target threshold of logical unit address in the P2L cache is not an illegal value, executing the step of judging whether the new logical unit address written by the host is less than the target minimum logical unit address in the P2L cache based on the second judging condition.

[0037] The present disclosure also provides a read-write processing device of a memory, the device comprising:

[0038] a first judging module configured to, when a host writes target data to a memory, store a plurality of logical unit addresses corresponding to the target data into a P2L cache, and judge the P2L cache and each of the logical unit addresses based on a first judging condition and a second judging condition, to obtain a target threshold of logical unit address in the P2L cache;

[0039] a second judging module configured to, when the host reads the target data from the memory, judge whether each of the target thresholds of logical unit address in the P2L cache is a legal value respectively, to obtain a plurality of target judging results, and determine whether to search each of the logical unit addresses from the P2L cache according to each of the target judging results.

[0040] The present disclosure also provides a computer device comprising a memory and a processor, wherein the memory stores a computer program, and the computer program, when executed by the processor, implements the steps of the read-write processing method of the memory according to the first aspect.

[0041] The present disclosure also provides a computer-readable storage medium storing a computer program, and the computer program, when executed by a processor, implements the steps of the read-write processing method of the memory according to the first aspect.

[0042] The read-write processing method of the memory, the device, the equipment and the storage medium disclosed by the present disclosure store the plurality of logical unit addresses corresponding to the target data in the P2L cache, and judge the P2L cache and each logical unit address based on the first judgment condition and the second judgment condition to obtain the logical unit address target threshold in the P2L cache; when the host reads the target data from the memory, it is respectively judged whether the logical unit address target threshold in each P2L cache is a legal value to obtain a plurality of corresponding target judgment results, and it is determined whether to search each logical unit address from the P2L cache according to each target judgment result. In this way, whether the host reads the logical unit address needs to be searched from the P2L cache is determined by the logical unit address target threshold in the P2L cache, which avoids the time loss of searching the P2L cache when searching for the logical unit address that does not exist in the P2L cache, and improves the read performance of the memory.

[0043] In order to make the above-mentioned purposes, features and advantages of the present disclosure more obvious and easy to understand, the following preferred embodiments are described in detail below, and the accompanying drawings are described as follows. BRIEF DESCRIPTION OF DRAWINGS

[0044] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the following will briefly introduce the drawings needed to be used in the embodiments. It should be understood that the following drawings only show some embodiments of the present disclosure, and therefore should not be considered as a limitation to the scope. For those skilled in the art, other related drawings can also be obtained without creative labor on the basis of these drawings.

[0045] Fig. 1 shows a first flowchart of the read-write processing method of the memory proposed by the present disclosure;

[0046] Fig. 2 shows a second flowchart of the read-write processing method of the memory proposed by the present disclosure;

[0047] Fig. 3 shows a third flowchart of the read-write processing method of the memory proposed by the present disclosure;

[0048] Fig. 4 shows a fourth flowchart of the read-write processing method of the memory proposed by the present disclosure;

[0049] FIG. 5 shows a fifth flowchart of a read-write processing method of a memory according to the present disclosure;

[0050] FIG. 6 shows a sixth flowchart of a read-write processing method of a memory according to the present disclosure;

[0051] FIG. 7 shows a seventh flowchart of a read-write processing method of a memory according to the present disclosure;

[0052] FIG. 8 shows a structural diagram of a read-write processing device of a memory according to the present disclosure. DETAILED DESCRIPTION

[0053] Embodiments of the present disclosure are described in detail below with reference to the accompanying drawings. Examples of the embodiments are illustrated in the drawings, in which like or similar elements are referred to with like reference numerals throughout the description. The embodiments described below are examples for explaining the present disclosure and should not be interpreted in a limiting manner.

[0054] It should be noted that when an element is referred to as being "on" another element, it can be directly on the other element or intervening elements can also be present. In contrast, when an element is referred to as being "directly on" another element, there are no intervening elements present. The terms "vertical", "horizontal", "left", "right", and the like as used herein are used for explanation purposes only and are not intended to limit the scope of the present disclosure.

[0055] In the present disclosure, unless explicitly or specifically defined otherwise and limited, the terms "mount", "connect", "connection", "fixed", and the like are used in a broad sense and can be, for example, fixed connection, detachable connection, or integral; can be mechanical connection, or electrical connection; can be direct connection, or indirect connection through an intermediate medium; can be internal connection of two elements, or interaction relationship between two elements. For those skilled in the art, the specific meanings of the above terms in the present disclosure can be understood according to the specific circumstances.

[0056] In addition, the terms "first", "second", etc. are used only for descriptive purposes and should not be construed as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Therefore, the features defined with "first", "second" can explicitly or implicitly include one or more of the features. In the description of the present disclosure, the meaning of "plurality" is two or more, unless explicitly and specifically limited.

[0057] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used in the description of the templates herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present disclosure. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0058] Embodiments of the present disclosure provide a memory read-write processing method, which is used to solve the problem that when the logical unit address queried by the host is not in the P2L cache, the P2L cache still needs to be traversed, thereby causing time waste.

[0059] Referring to FIG. 1, the memory read-write processing method includes steps S101-S103, which will be described in detail below.

[0060] In step S101, when the host writes target data to the memory, a plurality of logical unit addresses corresponding to the target data are stored in the P2L cache, and the P2L cache and each logical unit address are judged based on a first judgment condition and a second judgment condition to obtain a logical unit address target threshold in the P2L cache.

[0061] In this embodiment, when the host writes a group of target data to the memory, a plurality of logical unit addresses (LUA) corresponding to the target data are also sequentially written into the physical address-to-logical address (P2L) cache, and the P2L cache space is limited, so the LUA target threshold in the P2L cache will be updated constantly as the LUA is sequentially written into the P2L cache. At the same time, the P2L cache and each logical unit address can be judged according to a plurality of judgment conditions, and the LUA target threshold in the P2L cache is constantly updated. When the target data is written, the final LUA target threshold in the P2L cache is obtained.

[0062] Referring to FIG. 2, before the steps of writing target data to the memory by the host in a specific embodiment, steps S1-S2 are included, which will be described in detail below.

[0063] In step S1, the memory is started.

[0064] In step S2, the logical unit address target threshold in the P2L cache is set to an illegal value.

[0065] In the embodiment, the host needs to start the memory before writing target data to the memory. When the memory is powered on and started, the P2L cache may have recorded the LUA written by the host at the last power-off of the memory, and at this time, the LUA recorded in the P2L cache is irrelevant to the LUA written by the host this time. Therefore, the target threshold of the LUA recorded in the P2L cache at this time is acquired and set as an illegal value.

[0066] It should be noted that setting the target threshold of the LUA in the current P2L cache as an illegal value means setting the target threshold of the LUA in the current P2L cache as a value outside the LUA range accessed by the host. In the embodiment, the illegal value can be 4294967295, and 4294967295 in hexadecimal is 0xFFFFFFFF. One LUA represents 4K, and 4294967295 LUA represents 16383G. If the maximum capacity of the memory is smaller than the illegal value, the LUA range that can be accessed by the host is the memory capacity range. Therefore, the LUA accessed by the host cannot be the illegal value.

[0067] Please refer to FIG. 3. In a specific embodiment, the first judgment condition includes the storage condition of the P2L cache. When the host writes target data to the memory, a plurality of logical unit addresses corresponding to the target data are stored in the P2L cache, and the P2L cache and the logical unit addresses are judged based on the first judgment condition and the second judgment condition, including steps S3-S6, which are described in detail below.

[0068] Step S3: The host writes a logical unit address to the P2L cache.

[0069] In the embodiment, after the LUA threshold set in step S2 is set as an illegal value, the host writes a LUA to the P2L cache.

[0070] Step S4: It is judged whether the target threshold of the logical unit address in the P2L cache is an illegal value.

[0071] In the embodiment, it is further judged whether the LUA target threshold set in the P2L cache is an illegal value, which facilitates the updating of the LUA target threshold in the P2L cache.

[0072] Step S5: If the target threshold of the logical unit address in the P2L cache is an illegal value, it is judged based on the first judgment condition whether the P2L cache is empty.

[0073] In the embodiment, if the LUA target threshold in the P2L cache is an illegal value, it is judged based on the storage condition of the P2L cache whether the P2L cache is empty.

[0074] Step S6, if the P2L cache is empty, updating the host newly written logical unit address as the logical unit address target threshold in the P2L cache, and storing the logical unit address into the P2L cache.

[0075] In the embodiment, if the P2L cache is empty, updating the host newly written LNA as the LNA target threshold, and storing the LNA into the P2L cache.

[0076] Referring to FIG. 4, in a specific embodiment, the second judgment condition includes the size of each logical unit address, storing the plurality of logical unit addresses corresponding to the target data into the P2L cache, and judging the P2L cache and each logical unit address based on the first judgment condition and the second judgment condition to obtain the logical unit address target threshold in the P2L cache, further including steps S7-S13, which are described in detail as follows.

[0077] Step S7, judging whether the P2L cache is full based on the first judgment condition.

[0078] In the embodiment, after the LNA is stored into the P2L cache in step S6, whether the P2L cache is full is judged based on the storage condition of the P2L cache.

[0079] Step S8, if the P2L cache is full, emptying the P2L cache, and re-executing the step of setting the logical unit address target threshold in the P2L cache as an illegal value.

[0080] In the embodiment, if the P2L cache is full, emptying the P2L cache, and re-entering step S2 to execute step S2 and the subsequent steps. By executing the setting of the logical unit address target threshold in the P2L cache as an illegal value in step S2, the LNA target threshold when the P2L cache is full is set as an illegal value, so that the next round of updating of the LNA into the LNA target threshold in the P2L cache can be started.

[0081] Step S9, if the P2L cache is not full, judging whether the host newly written logical unit address is smaller than the logical unit address target minimum value in the P2L cache based on the second judgment condition.

[0082] In the embodiment, if the P2L cache is not full, judging whether the host newly written LNA is smaller than the LNA target minimum value in the P2L cache among the currently set LNA target threshold in the P2L cache based on the size of each LNA.

[0083] Step S10, if the logical unit address is less than the target minimum logical unit address in the P2L cache, the logical unit address is updated to the target minimum logical unit address in the P2L cache, the logical unit address is stored in the P2L cache, and the step of judging whether the P2L cache is full based on the first judging condition is re-executed.

[0084] In the embodiment, if the newly written LUA of the host is greater than or equal to the target minimum LUA in the currently set LUA target threshold, whether the newly written LUA of the host is greater than the target maximum LUA in the LUA target threshold is judged based on the size of each LUA.

[0085] Step S11, if the logical unit address is greater than or equal to the target minimum logical unit address in the P2L cache, whether the logical unit address is greater than the target maximum logical unit address in the P2L cache is judged based on the second judging condition.

[0086] In the embodiment, if the newly written LUA of the host is greater than or equal to the target minimum LUA in the currently set LUA target threshold, whether the newly written LUA of the host is greater than the target maximum LUA in the LUA target threshold is judged based on the size of each LUA.

[0087] Step S12, if the logical unit address is greater than the current maximum logical unit address in the P2L cache, the logical unit address is updated to the target maximum logical unit address in the P2L cache, the logical unit address is stored in the P2L cache, and the step of judging whether the P2L cache is full based on the first judging condition is re-executed.

[0088] In the embodiment, if the newly written LUA of the host is greater than or equal to the target minimum LUA in the currently set LUA target threshold, whether the newly written LUA of the host is greater than the target maximum LUA in the LUA target threshold is judged based on the size of each LUA.

[0089] Step S13, if the logical unit address is less than or equal to the current maximum logical unit address in the P2L cache, the logical unit address is stored in the P2L cache, and the step of judging whether the P2L cache is full based on the first judging condition is re-executed.

[0090] In the embodiment, if the newly written LUA of the host is less than or equal to the maximum LUA target value in the currently set LUA target threshold, the newly written LUA is stored in the P2L cache, and step S7 is re-entered to execute step S7 and the subsequent steps, so that the LUA target threshold in the P2L cache is updated according to the continuously written LUA of the host, until all the LUA corresponding to the target data is written, and the finally updated LUA target threshold in the P2L cache is obtained.

[0091] Please refer to FIG. 5, in a specific embodiment, after step S4, step S14 is further included, and after step S5, step S15 is further included, and each step is described in detail as follows.

[0092] Step S14, if the logical unit address target threshold in the P2L cache is not an illegal value, the step of judging whether the newly written logical unit address of the host is less than the minimum logical unit address target value in the P2L cache based on the second judging condition is executed.

[0093] In the embodiment, after step S4, if the LUA target threshold is not an illegal value, the step of judging whether the newly written logical unit address of the host is less than the minimum logical unit address target value in the P2L cache based on the second judging condition in step S9 and the subsequent steps are executed, so that the LUA target threshold in the P2L cache is updated according to the continuously written LUA of the host, until all the LUA corresponding to the target data is written, and the finally updated LUA target threshold in the P2L cache is obtained.

[0094] Step S15, if the P2L cache is not empty, the newly written logical unit address of the host is stored in the P2L cache, and the step of judging whether the P2L cache is full based on the first judging condition is re-executed.

[0095] In the embodiment, after step S5, if the P2L cache is not empty, the newly written LUA of the host is stored in the P2L cache, and step S7 is re-entered to execute step S7 and the subsequent steps, so that the LUA target threshold in the P2L cache is updated according to the continuously written LUA of the host, until all the LUA corresponding to the target data is written, and the finally updated LUA target threshold in the P2L cache is obtained.

[0096] Please refer to Fig. 1 again, in step S102, when the host reads the target data from the memory, it is judged whether the logical unit address target threshold in each P2L cache is a legal value respectively, and a plurality of target judgment results are obtained, and it is determined whether to search for each logical unit address from the P2L cache according to each target judgment result.

[0097] In the embodiment, when the host reads the target data from the memory, the corresponding data needs to be obtained according to the read LUA of the host. When the host reads the LUA, it is determined whether to search for the LUA from the P2L cache according to the target judgment result of whether the LUA target threshold of the P2L cache at this time is an illegal value. In this way, it is determined in advance whether the P2L cache needs to be searched for a certain LUA, so that the reading time is saved and the reading performance of the memory is improved.

[0098] It should be noted that the LUA target threshold used for judgment at this time is the LUA target threshold obtained after the target data is written. For example, if the LUA corresponding to the target data written by the host includes LUA1, LUA2, LUA3, LUA4, LUA5, during the judgment, LUA1 is updated as the LUA target threshold first, then LUA3 is updated as the LUA target maximum value, and later LUA5 is updated as the LUA target maximum value, so when the target data is written, the LUA target threshold obtained after the target data is written is LUA3 and LUA5, and when the host reads the target data, it is determined whether to search for the read LUA from the P2L cache according to LUA3 and LUA5.

[0099] Please refer to Fig. 6, in a specific embodiment, the target judgment result includes a first judgment result and a second judgment result, and the logical unit address target threshold includes a logical unit address target maximum value in the P2L cache and a logical unit address target minimum value in the P2L cache; determining whether to search for the logical unit address from the P2L cache according to the target judgment result includes steps S1021-S1022, which are described in detail below.

[0100] In step S1021, if the first judgment result is that the logical unit address target threshold in the P2L cache is an illegal value, the logical unit address is searched from the P2L cache.

[0101] In the embodiment, if the LUA target threshold in the P2L cache is an illegal value, it is known that the range of the LUA in the P2L cache cannot be determined at present, so it needs to be searched from the P2L cache.

[0102] Step S1022, if the first judgment result is that the logical unit address target threshold in the P2L cache is a legal value, then it is judged whether the logical unit address is greater than or equal to the logical unit address target minimum value in the P2L cache and whether the logical unit address is less than or equal to the logical unit address target maximum value in the P2L cache, to obtain a second judgment result, and it is determined according to the second judgment result whether to search for the logical unit address from the P2L cache.

[0103] In the embodiment, if the LUA target threshold in the P2L cache is not an illegal value, i.e., the LUA target threshold in the P2L cache is a legal value, then it is continuously judged whether the LUA read by the host at this time is greater than or equal to the LUA target minimum value in the P2L cache and less than or equal to the LUA target maximum value in the P2L cache, to obtain a second judgment result, and it is continuously determined according to the second judgment result whether the P2L cache needs to be traversed to search for the LUA.

[0104] Please refer to FIG. 7, in a specific embodiment, according to the second judgment result, it is determined whether to search for the logical unit address from the P2L cache, including steps S701-S702, which are described in detail as follows.

[0105] Step S701, if the second judgment result is that the logical unit address is greater than or equal to the logical unit address target minimum value in the P2L cache and less than or equal to the logical unit address target maximum value in the P2L cache, then the logical unit address is searched from the P2L cache.

[0106] In the embodiment, if the LUA read by the host is greater than or equal to the LUA target minimum value in the P2L cache and less than or equal to the LUA target maximum value in the P2L cache, then it can be determined that the LUA read by the host exists in the P2L cache, therefore, the P2L cache needs to be traversed to search for the LUA.

[0107] Step S702, if the second judgment result is that the logical unit address is less than the logical unit address target minimum value in the P2L cache or the logical unit address is greater than the logical unit address target maximum value in the P2L cache, then the logical unit address is not searched from the P2L cache.

[0108] In the embodiment, if the LUA read by the host is less than the LUA target minimum value in the P2L cache or greater than the LUA target maximum value in the P2L cache, then it can be determined that the LUA read by the host is cleared after being written into the P2L cache and does not exist in the P2L cache at present, therefore, the P2L cache does not need to be traversed to search for the LUA, which avoids wasting the time of traversing the P2L cache and improves the read performance.

[0109] The read-write processing method of the memory provided in the embodiment includes: when a host writes target data to the memory, storing a plurality of logical unit addresses corresponding to the target data in a P2L cache, and judging the P2L cache and each logical unit address based on a first judgment condition and a second judgment condition to obtain a target threshold value of the logical unit addresses in the P2L cache; when the host reads the target data from the memory, respectively judging whether the target threshold value of the logical unit addresses in each P2L cache is a legal value to obtain a plurality of corresponding target judgment results, and respectively determining whether to search for each logical unit address from the P2L cache according to each target judgment result. In this way, whether the host reads the LUA needs to be searched from the P2L cache is determined by the LUA target threshold value, which avoids the time loss of searching for the LUA that does not exist in the P2L cache, and improves the read performance of the memory.

[0110] In addition, the disclosure embodiment also provides a read-write processing device 800 of a memory, please see Figure 8, the device includes:

[0111] The first judgment module 801 is configured to, when a host writes target data to the memory, store a plurality of logical unit addresses corresponding to the target data in a P2L cache, and judge the P2L cache and each logical unit address based on a first judgment condition and a second judgment condition to obtain a target threshold value of the logical unit addresses in the P2L cache;

[0112] The second judgment module 802 is configured to, when the host reads the target data from the memory, respectively judge whether the target threshold value of the logical unit addresses in each P2L cache is a legal value to obtain a plurality of corresponding target judgment results, and respectively determine whether to search for each logical unit address from the P2L cache according to each target judgment result.

[0113] In an embodiment, the target judgment result includes a first judgment result and a second judgment result, and the target threshold value of the logical unit addresses in the P2L cache includes a target maximum value of the logical unit addresses in the P2L cache and a target minimum value of the logical unit addresses in the P2L cache; the second judgment module 802 is further configured to, if the first judgment result is that the target threshold value of the logical unit addresses in the P2L cache is an illegal value, search for the logical unit address from the P2L cache; if the first judgment result is that the target threshold value of the logical unit addresses in the P2L cache is a legal value, judge whether the logical unit address is greater than or equal to the target minimum value of the logical unit addresses in the P2L cache and whether the logical unit address is less than or equal to the target maximum value of the logical unit addresses in the P2L cache to obtain the second judgment result; and determine whether to search for the logical unit address from the P2L cache according to the second judgment result.

[0114] In an embodiment, the second judging module 802 is further configured to, if the second judging result is that the logical unit address is greater than or equal to the target minimum logical unit address in the P2L cache and less than or equal to the target maximum logical unit address in the P2L cache, search the logical unit address in the P2L cache; and if the second judging result is that the logical unit address is less than the target minimum logical unit address in the P2L cache or greater than the target maximum logical unit address in the P2L cache, not search the logical unit address in the P2L cache.

[0115] In an embodiment, the first judging module 801 is further configured to, when the memory is started, set the target threshold logical unit address in the P2L cache as an illegal value.

[0116] In an embodiment, the first judging condition comprises the storage condition of the P2L cache, and the first judging module 701 is further configured to write the logical unit address by the host into the P2L cache; judge whether the target threshold logical unit address in the P2L cache is an illegal value; if the target threshold logical unit address in the P2L cache is an illegal value, judge whether the P2L cache is empty based on the first judging condition; if the P2L cache is empty, update the newly written logical unit address by the host as the target threshold logical unit address in the P2L cache, and store the logical unit address into the P2L cache.

[0117] In an embodiment, the second judging condition comprises the size condition of each logical unit address, and the first judging module 801 is further configured to, if the P2L cache is full, empty the P2L cache and re-perform the step of setting the target threshold logical unit address in the P2L cache as an illegal value; if the P2L cache is not full, judge whether the newly written logical unit address by the host is less than the target minimum logical unit address in the P2L cache based on the second judging condition; if the logical unit address is less than the target minimum logical unit address in the P2L cache, update the logical unit address as the target minimum logical unit address in the P2L cache, store the logical unit address into the P2L cache, and re-perform the step of judging whether the P2L cache is full based on the first judging condition; if the logical unit address is greater than or equal to the target minimum logical unit address in the P2L cache, judge whether the logical unit address is greater than the target maximum logical unit address in the P2L cache based on the second judging condition; if the logical unit address is greater than the target maximum logical unit address in the P2L cache, update the logical unit address as the target maximum logical unit address in the P2L cache, store the logical unit address into the P2L cache, and re-perform the step of judging whether the P2L cache is full based on the first judging condition; and if the logical unit address is less than or equal to the target maximum logical unit address in the P2L cache, store the logical unit address into the P2L cache, and re-perform the step of judging whether the P2L cache is full based on the first judging condition.

[0118] In an embodiment, the first judging module 801 is further configured to, if the P2L cache is not empty, store the new logical unit address written by the host into the P2L cache, and re-perform the step of judging whether the P2L cache is full based on the first judging condition; and if the logical unit address target threshold in the P2L cache is not an illegal value, perform the step of judging whether the new logical unit address written by the host is less than the logical unit address target minimum value in the P2L cache based on the second judging condition.

[0119] The apparatus provided in the embodiments of the present disclosure can perform the steps of the target detection method provided in the embodiments of the present disclosure, and details are not repeated.

[0120] The read-write processing apparatus of the memory provided in the embodiments can store a plurality of logical unit addresses corresponding to target data into the P2L cache when the host writes the target data into the memory, and judge the P2L cache and each logical unit address based on the first judging condition and the second judging condition to obtain a logical unit address target threshold in the P2L cache; and when the host reads the target data from the memory, respectively judge whether the logical unit address target threshold in each P2L cache is a legal value to obtain a plurality of target judging results corresponding thereto, and respectively determine whether to search for each logical unit address from the P2L cache according to each target judging result. In this way, the LUA target threshold is used to determine whether the host-read LUA needs to be searched from the P2L cache, which avoids time loss of searching for the LUA that does not exist in the P2L cache, and improves the read performance of the memory.

[0121] In addition, the embodiments of the present disclosure further provide a computer device including a memory and a processor, the memory stores a computer program, and the computer program is executed by the processor to implement the read-write processing method of the memory in the embodiment 1.

[0122] The apparatus provided in the embodiments of the present disclosure can perform the steps of the read-write processing method of the memory provided in the embodiments of the present disclosure, and details are not repeated.

[0123] The embodiments of the present disclosure further provide a computer readable storage medium storing a computer program, and the computer program is executed by a processor to implement the read-write processing method of the memory provided in the embodiments of the present disclosure.

[0124] In the embodiments, the computer readable storage medium can be a read-only memory (READ-ONLY MEMORY, ROM for short), a random access memory (RANDOM ACCESS MEMORY, RAM for short), a magnetic disk or an optical disk, etc.

[0125] The computer readable storage medium provided in the embodiment can implement the read-write processing method of the memory provided in the embodiment 1. To avoid repetition, details are not described herein again.

[0126] In all examples shown and described herein, any specific values should be interpreted as merely exemplary and not limiting, and thus other examples of the example embodiments can have different values.

[0127] It should be noted that similar reference numbers and letters represent similar items in the following drawings, and thus, once an item is defined in one drawing, it need not be further defined and explained in subsequent drawings.

[0128] The above embodiments only express several implementation manners of the present disclosure, and the description is relatively specific and detailed, but it should not be understood as a limitation on the scope of the present disclosure. It should be pointed out that for those skilled in the art, several modifications and improvements can be made without departing from the concept of the present disclosure, and these all belong to the protection scope of the present disclosure. Industrial applicability

[0129] The embodiment of the present disclosure provides a read-write processing method, device and equipment of a memory and a storage medium. Whether a logical unit address read by a host needs to be searched from a P2L cache is determined by a logical unit address target threshold in the P2L cache, time loss of searching a logical unit address that does not exist in the P2L cache is avoided, and the read performance of the memory is improved.

Claims

1. A read / write processing method of a memory, characterized by, The method comprises: When the host writes target data to the memory, storing a plurality of logical unit addresses corresponding to the target data into a P2L cache, and judging the P2L cache and each of the logical unit addresses based on a first judging condition and a second judging condition to obtain a logical unit address target threshold in the P2L cache; When the host reads the target data from the memory, judging whether the logical unit address target threshold in each of the P2L caches is a legal value respectively to obtain a plurality of target judging results, and determining whether to search for each of the logical unit addresses from the P2L cache according to each of the target judging results.

2. The read / write processing method of memory according to claim 1, wherein, The target judging result comprises a first judging result and a second judging result, and the logical unit address target threshold in the P2L cache comprises a logical unit address target maximum value and a logical unit address target minimum value in the P2L cache; The determination whether to search for the logical unit address from the P2L cache according to each of the target judging results comprises: If the first judging result is that the logical unit address target threshold in the P2L cache is an illegal value, searching for the logical unit address from the P2L cache; If the first judging result is that the logical unit address target threshold in the P2L cache is a legal value, judging whether the logical unit address is greater than or equal to the logical unit address target minimum value in the P2L cache and whether the logical unit address is less than or equal to the logical unit address target maximum value in the P2L cache to obtain the second judging result, and determining whether to search for the logical unit address from the P2L cache according to the second judging result.

3. The read / write processing method of memory according to claim 2, wherein, The determination whether to search for the logical unit address from the P2L cache according to the second judging result comprises: If the second judging result is that the logical unit address is greater than or equal to the logical unit address target minimum value in the P2L cache and the logical unit address is less than or equal to the logical unit address target maximum value in the P2L cache, searching for the logical unit address from the P2L cache; If the second judging result is that the logical unit address is less than the logical unit address target minimum value in the P2L cache or the logical unit address is greater than the logical unit address target maximum value in the P2L cache, not searching for the logical unit address from the P2L cache.

4. The memory read / write processing method according to any one of claims 2 to 3, characterized by, Before the step of writing target data to the memory by the host, the method comprises: When the memory starts, setting the logical unit address target threshold in the P2L cache as an illegal value.

5. The read / write processing method of memory according to claim 4, wherein, The first judging condition comprises a storage condition of the P2L cache, and the writing of the plurality of logical unit addresses corresponding to the target data into the P2L cache by the host and the judgment of the P2L cache and each of the logical unit addresses based on the first judging condition and the second judging condition to obtain the logical unit address target threshold in the P2L cache comprise: The host writes the logical unit address to the P2L cache; Judging whether the logical unit address target threshold in the P2L cache is an illegal value; If the logical unit address target threshold in the P2L cache is an illegal value, determining whether the P2L cache is empty based on the first determining condition; If the P2L cache is empty, updating the host newly written logical unit address as the logical unit address target threshold in the P2L cache, and storing the logical unit address into the P2L cache.

6. The read / write processing method of memory according to claim 5, wherein, The second determining condition includes the size of each logical unit address, the storing of the plurality of logical unit addresses corresponding to the target data into the P2L cache, and the determination of the P2L cache and each logical unit address based on the first determining condition and the second determining condition to obtain the logical unit address target threshold in the P2L cache, and the method further comprises: After the storing of the logical unit address into the P2L cache, determining whether the P2L cache is full based on the first determining condition; If the P2L cache is full, emptying the P2L cache and re-executing the step of setting the logical unit address target threshold in the P2L cache as an illegal value; If the P2L cache is not full, determining whether the host newly written logical unit address is less than the logical unit address target minimum value in the P2L cache based on the second determining condition; If the logical unit address is less than the logical unit address target minimum value in the P2L cache, updating the logical unit address as the logical unit address target minimum value in the P2L cache, storing the logical unit address into the P2L cache, and re-executing the step of determining whether the P2L cache is full based on the first determining condition; If the logical unit address is greater than or equal to the logical unit address target minimum value in the P2L cache, determining whether the logical unit address is greater than the logical unit address target maximum value in the P2L cache based on the second determining condition; If the logical unit address is greater than the logical unit address target maximum value in the P2L cache, updating the logical unit address as the logical unit address target maximum value in the P2L cache, storing the logical unit address into the P2L cache, and re-executing the step of determining whether the P2L cache is full based on the first determining condition; If the logical unit address is less than or equal to the logical unit address target maximum value in the P2L cache, storing the logical unit address into the P2L cache, and re-executing the step of determining whether the P2L cache is full based on the first determining condition.

7. The read / write processing method of memory according to claim 6, wherein, After the determination of whether the P2L cache is empty, the method further comprises: If the P2L cache is not empty, storing the host newly written logical unit address into the P2L cache, and re-executing the step of determining whether the P2L cache is full based on the first determining condition; If the logical unit address target threshold in the P2L cache is not an illegal value, executing the step of determining whether the host newly written logical unit address is less than the logical unit address target minimum value in the P2L cache based on the second determining condition.

8. A read / write processing apparatus for a memory, characterized by comprising: The apparatus comprises: The first judging module is configured to store a plurality of logical unit addresses corresponding to target data when the host writes the target data to the memory, and judge the P2L cache and each of the logical unit addresses based on a first judging condition and a second judging condition to obtain a logical unit address target threshold in the P2L cache; The second judging module is configured to judge whether the logical unit address target threshold in each of the P2L caches is a legal value when the host reads the target data from the memory, obtain a plurality of target judging results corresponding to the logical unit addresses, and determine whether to search for each of the logical unit addresses from the P2L cache according to each of the target judging results.

9. A computer device, comprising: The memory and the processor, the memory stores a computer program, the computer program is executed by the processor to realize the steps of the read-write processing method of the memory as claimed in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, The memory stores a computer program, the computer program is executed by the processor to realize the steps of the read-write processing method of the memory as claimed in any one of claims 1 to 7.

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