Twin channels semiconductor device

Abstract

In some examples, a transistor device comprises a substrate, a channel region formed on the substrate, wherein the channel region comprises at least one channel pair stacked on top of each other and spaced from each other, wherein each of the at least one channel pair comprises a first channel and a second channel staked on the first channel and separated from the first channel by an oxide layer, a gate electrode surrounding each of at least one channel pair, and a pair of source / drain regions arranged, respectively, on opposite sides of the channel region, the pair of source / drain regions electrically connected to each of the at least one channel pair channels.

Description

[0001] TWIN CHANNELS SEMICONDUCTOR DEVICE

[0002] TECHNICAL FIELD

[0003] The present disclosure relates, in general, to transistor devices and methods of fabricating the same. Aspects of the disclosure relate to twin channels field effect transistors and methods of fabricating the same.

[0004] BACKGROUND

[0005] In recent years, the progress of logic scaling has slowed down. Approximately 15 years ago, the transition from planar transistors to FinFET technology marked a significant advancement in logic scaling. However, the performance gains associated with FinFET technology have been diminishing, prompting foundries to explore new architectures to sustain the scaling trajectory.

[0006] Recently, there has been an intensified focus on Gate- All-Around (GAA) architectures. Major foundries have demonstrated promising results using GAA architecture. Despite these advancements, the GAA approach presents several challenges. Firstly, electron mobility is compromised because the channel orientation is along the plane parallel to the substrate, rather than the plane is perpendicular to the substrate. Secondly, hole mobility is significantly reduced due to the lack of strain from the source / drain (S / D) region, a factor that has been critical in enhancing hole mobility since the planar technology era and maintaining a balanced N / P performance. Additionally, the number of channels cannot be arbitrarily increased due to the resulting process complexity and heightened parasitic effects.

[0007] In scaled logic, optimal performance is primarily achieved through superior RC (resistancecapacitance) optimisation, which is best accomplished by minimising parasitic elements. The current approach to reducing gate-drain / source capacitance involves altering the spacer material at the gate or inner spacer by employing a low-k dielectric material. While this method has been demonstrated to effectively reduce capacitance, it does not provide any advantages in terms of drive current. This limitation arises because the number of channels is restricted to three.

[0008] SUMMARY

[0009] An objective of the present disclosure is to reduce stack height and reduce the parasitic capacitance of a transistor device. The foregoing and other objectives are achieved by the features of the independent claims.

[0010] Further implementation forms are apparent from the dependent claims, the description and the Figures.

[0011] A first aspect of the present disclosure provides a transistor device comprising a substrate, a channel region formed on the substrate, wherein the channel region comprises at least one channel pair stacked on top of each other and spaced from each other, wherein each of the at least one channel pair comprises a first channel and a second channel staked on the first channel and separated from the first channel by an oxide layer, a gate electrode surrounding each of at least one channel pair, and a pair of source / drain regions arranged, respectively, on opposite sides of the channel region, the pair of source / drain regions electrically connected to each of the at least one channel pair channels.

[0012] Accordingly, provided is a solution that enables the implementation of at least four channels with a minor increase in the stack height. Increasing the number of channels increases the drive current of the transistor device and enables the device to handle greater current loads, thereby improving performance of the device. Advantageously, the solution presented herein reduces the gate-drain / source parasitic capacitance without the need for material replacement and without increasing the complexity of the fabrication process of the device.

[0013] The first channel and the second channel may be substantially equal in size.

[0014] A thickness of the oxide layer may be less than 1 nanometre.

[0015] The oxide layer may comprise silicon dioxide.

[0016] The oxide layer may be arranged to support epitaxial growth of a crystalline semiconductor material.

[0017] The at least one channel pair may comprise a pair of n-type channels or a pair of p-type channels.

[0018] Each of the at least one channel pair may comprise a crystalline semiconductor material. The crystalline semiconductor material may comprise silicon (Si) or silicon germanium (SiGe).

[0019] The at least one channel pair may comprise a first channel pair and a second channel pair. The second channel of the first channel pair may be separated from the first channel of the first channel pair by a first oxide layer. The second channel pair may comprise a first channel and a second channel. The second channel of the second channel pair may be stacked on top of the first channel of the second channel pair and separated from the first channel of the second channel pair by a second oxide layer.

[0020] A length of the first channel pair may be different from the length of the second channel pair.

[0021] The first channel pair and the second channel pair may comprise the same material.

[0022] A second aspect of the present disclosure provides a method for fabricating a transistor device having at least one channel pair, comprising depositing a first sacrificial layer on a substrate, depositing a first channel layer of a first channel pair of the at least one channel pair on top of the first sacrificial layer, patterning the first channel of the first channel pair from the first channel layer, depositing an oxide layer over the first channel of the first channel pair, depositing a second channel layer of a first channel pair of the at least one channel pair, and patterning / forming the second channel of the first channel pair from the second channel layer.

[0023] Depositing the second channel layer of the first channel pair of thee at least one channel pair may comprise epitaxially growing the second channel layer on top of the oxide layer.

[0024] The method may further comprise depositing a second sacrificial layer on top of the first pair of channel layers, depositing a first channel layer of a second channel pair of the at least one channel pair on top of the second sacrificial layer, patterning the first channel layer of the second channel pair of the at least one channel pair, depositing a second oxide layer over the first channel layer of the second channel pair of the at least one channel pair, depositing a second channel layer of the second channel pair of the at least one channel pair, and patterning the second channel of the second channel pair from the second channel layer. These and other aspects of the invention will be apparent from the embodiment(s) described below.

[0025] BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order that the present invention may be more readily understood, embodiments of the invention will now be described, by way of example, with reference to the accompanying drawings, in which:

[0027] Figure l is a schematic representation of a transistor device according to an example;

[0028] Figure 2 is a flow chart of a method for fabricating a transistor device having at least one channel pair according to an example; and

[0029] Figure 3 is a cross-sectional view illustrating a step of a method of fabricating a transistor device according to an example.

[0030] DETAILED DESCRIPTION

[0031] Example embodiments are described below in sufficient detail to enable those of ordinary skill in the art to embody and implement the systems and processes herein described. It is important to understand that embodiments can be provided in many alternate forms and should not be construed as limited to the examples set forth herein.

[0032] Accordingly, while embodiments can be modified in various ways and take on various alternative forms, specific embodiments thereof are shown in the drawings and described in detail below as examples. There is no intent to limit to the particular forms disclosed. On the contrary, all modifications, equivalents, and alternatives falling within the scope of the appended claims should be included. Elements of the example embodiments are consistently denoted by the same reference numerals throughout the drawings and detailed description where appropriate.

[0033] The terminology used herein to describe embodiments is not intended to limit the scope. The articles “a,” “an,” and “the” are singular in that they have a single referent, however the use of the singular form in the present document should not preclude the presence of more than one referent. In other words, elements referred to in the singular can number one or more, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes,” and / or “including,” when used herein, specify the presence of stated features, items, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, items, steps, operations, elements, components, and / or groups thereof.

[0034] Unless otherwise defined, all terms (including technical and scientific terms) used herein are to be interpreted as is customary in the art. It will be further understood that terms in common usage should also be interpreted as is customary in the relevant art and not in an idealized or overly formal sense unless expressly so defined herein.

[0035] Examples in the present disclosure can be provided as methods, systems or machine-readable instructions, such as any combination of software, hardware, firmware or the like. Such machine-readable instructions may be included on a computer readable storage medium (including but not limited to disc storage, CD-ROM, optical storage, etc.) having computer readable program codes therein or thereon.

[0036] The present disclosure is described with reference to flow charts and / or block diagrams of the method, devices and systems according to examples of the present disclosure. Although the flow diagrams described above show a specific order of execution, the order of execution may differ from that which is depicted. Blocks described in relation to one flow chart may be combined with those of another flow chart. In some examples, some blocks of the flow diagrams may not be necessary and / or additional blocks may be added. It shall be understood that each flow and / or block in the flow charts and / or block diagrams, as well as combinations of the flows and / or diagrams in the flow charts and / or block diagrams can be realized by machine readable instructions.

[0037] The machine-readable instructions may, for example, be executed by a machine such as a general-purpose computer, user equipment such as a smart device, e.g., a smart phone, a special purpose computer, an embedded processor or processors of other programmable data processing devices to realize the functions described in the description and diagrams. In particular, a processor or processing apparatus may execute the machine-readable instructions. Thus, modules of apparatus (for example, a module implementing a comparator unit, or a firewall structure and so on) may be implemented by a processor executing machine readable instructions stored in a memory, or a processor operating in accordance with instructions embedded in logic circuitry. The term 'processor' is to be interpreted broadly to include a CPU, processing unit, ASIC, logic unit, or programmable gate set etc. The methods and modules may all be performed by a single processor or divided amongst several processors.

[0038] Such machine-readable instructions may also be stored in a computer readable storage that can guide the computer or other programmable data processing devices to operate in a specific mode. For example, the instructions may be provided on a non-transitory computer readable storage medium encoded with instructions, executable by a processor.

[0039] Figure 1 is a schematic representation of a transistor device according to an example. The transistor device 100 comprises a substrate 101. The semiconductor substrate 101 may comprise silicon (Si), silicon germanium (SiGe), silicon-on-insulator (SOI), silicon germanium-on- insulator (SGOI) and / or other conventional substrates.

[0040] The transistor device 100 comprises a channel region formed on the substrate 101. The channel region comprises at least one channel pair stacked on top of each other and spaced from each other. In the embodiment shown in Figure 1, the at least one channel pair may comprise a first channel pair 102 and a second channel pair 112, but the invention is not limited thereto. The channel may be growth epitaxially.

[0041] The first channel pair 102 of the least one channel pair comprises a first channel 102a of the first channel pair 102 and a second channel 102b of the first channel pair 102. Similarly, the second channel pair 112 may comprise a first channel 112a of the second channel pair 112 and a second channel 112b of the second channel pair . The first channel 102a and the second channel 102b may be substantially equal in size. That is, the channel length and width of the first channel 102a and the channel 102b may be substantially the same.

[0042] In a scenario where more than one channel pair is present in the transistor device 100, all of the channel pairs may be substantially equal in size. However, it is worth noting that, in practice, due to the fact that the at least one channel pair is formed using an etch process, it may be possible that a bottom channel pair of the at least one channel pair (i.e., in Figure 1, the second channel pair 112) may have a slightly larger length than the first channel pair 102 of the at least one channel pair. The first channel 102a and / or the second channel 102b may have a thickness of less than 5 nanometres. To avoid repetition, it is noted that the following description of the first channel 102a and the second channel 102b of the first channel pair 102 may also refer to the first channel 112a and the second channel 112b of the second channel pair.

[0043] The first channel 102a and the second channel 102b may comprise a crystalline semiconductor material. The crystalline semiconductor material may comprise silicon (Si) or silicon germanium (SiGe). Importantly, in a scenario where more than one channel pair is present in the transistor device, all of the channel pairs may comprise the same material. In other words, the first channel 102a and the second channel 102b of the first channel pair, and the first channel 112a and the second channel 112b of the second channel pair may all comprise the same material. That is, the material cannot be alternated. The same material may also be used for doping, described in more detail below. The at least one channel pair may comprise a pair of n- type channels or a pair of p-type channels.

[0044] In the first channel pair 102, the second channel 102b is stacked on the first channel 102a and separated from the first channel 102a by an oxide layer 103a. Similarly, in the second channel pair 112, the second channel 112b may be separated from the first channel 112a by an oxide layer 103b. As such, a distance between two channels can be reduced by separating the channels using a thin oxide layer, without compromising the crystalline growth of the silicon channel on top of it. In this way, the two channels can be coupled, resulting in a large capacitance reduction with a minimal current degradation.

[0045] The oxide layer 103 (i.e., the first oxide layer 103a and / or the second oxide layer 103b) may comprise silicon dioxide, SiCh. The oxide layer 103a may have a thickness of less than 1 nanometre. Importantly, in contrast to conventional oxides, it may be possible to epitaxially grow silicon (Si) on top of the oxide layer 103. This feature enables the creation of the multiple channel devices described herein.

[0046] The transistor device 100 comprises a gate electrode 104, surrounding each of the at least one channel pair. The gate electrode may comprise a polysilicon film. The gate electrode 104 may comprise a gate stack layer 105, formed on the top surface of the gate electrode 104. The gate stack layer 105 may comprise a metal silicide for reducing a gate resistance and / or an insulating material for capping the gate electrode 104. The transistor 100 may also comprise a gate insulating layer 106, comprising a thermal oxide film or an ONO film. The transistor device 100 comprises a pair of source / drain regions arranged, respectively, on opposite sides of the channel region, the pair of source / drain regions electrically connected to each of the at least one channel pair. The transistor device 100 may also comprise field regions 107, formed as to surround the pair of source / drain regions.

[0047] The transistor device 100 may also comprise a heavily doped region 108, formed in the main portion of the substrate 101 below the channel region. The heavily doped region 108 may serve to reduce or prevent the operation of a bottom transistor causing a short channel effect.

[0048] Figure 2 is a flow chart of a method for fabricating a transistor device having at least one channel pair according to an example. The transistor device may comprise the transistor device 100, described above in relation to Figure 1 and functioning likewise.

[0049] The method comprises, in block 201, depositing a first sacrificial layer on a substrate. The substrate may comprise the substrate 101, described above in relation to Figure 1 and functioning likewise.

[0050] In block 202, the method comprises depositing a first channel layer of a first channel pair of the at least one channel pair on top of the first sacrificial layer. The first channel layer may comprise a layer of the first channel 102a, and the channel pair may comprise the at least one channel pair 102, described above in relation to Figure 1 and functioning likewise.

[0051] The method comprises, in block 203, patterning (i.e., forming) the first channel of the first channel pair from the first channel layer. In block 204, the method comprises depositing (growing) an oxide layer over the first channel of the first channel pair. The oxide layer deposited may comprise the oxide layer 103, described above in relation to Figure 1.

[0052] The method comprises, in block 205, depositing a second channel layer of a first channel pair of the at least one channel pair. The second channel layer may comprise a layer of the second channel 102b of the at least one channel pair 102, described above in relation to Figure 1 and functioning likewise. In block 206, the method comprises patterning (i.e., forming) the second channel of the first channel pair from the second channel layer. To aid understanding of the fabrication process of Figure 2, reference will now be made to Figure 3, which is a cross-sectional view illustrating a step of the method of fabricating a transistor device according to an example. For ease of understanding, the same reference numerals used in Figure 1 and Figure 3 denote the same elements and function likewise.

[0053] Referring to Figure 3, an impurity of the same conductivity as that of the substrate 101 may be implanted into a main surface of the substrate 101, whereby to form the heavily doped region 108, serving to reduce or prevent the operation of a bottom transistor causing a short channel effect.

[0054] Multiple sacrificial layers HOa-l lOc, multiple channel layers 112a-b and an oxide layer 103 may be stacked alternately upon each other on the substrate 101. First, a first sacrificial layer 110a may be formed on the substrate 101, followed by deposition of a first channel layer 112a of a first pair of the at least one channel pair on top of the first sacrificial layer 110a. The multiple sacrificial layers HOa-l lOc may comprise silicon, and the multiple channel layers 112a-l 12b may comprise silicon germanium. Alternatively, the multiple sacrificial layers 110a- 110c may comprise silicon germanium, and the multiple channel layers 112a-112b may comprise silicon.

[0055] An oxide layer 103 may be deposited on top of the first channel layer 112a, followed by deposition of a second channel layer 112b of the at least one channel pair on top of the oxide layer 103. Any suitable method of deposition / growing may be utilised to realise the oxide layer 103. In such manner, the first channel layer 112a can be separated from the second channel layer 112b, effectively increasing the number of channels present in a transistor device, with a minimal increase of the stack height.

[0056] While the invention is not limited to a specific number of channel pairs, Figure 3 shows the fabrication of a transistor device having two pairs of channels. As such, a second sacrificial layer 110b may be deposited on top of the second channel layer 112b, and the process of deposition of the channel layers may be repeated for a second channel pair.

[0057] In particular, a first channel layer 114a of a second channel pair of the at least one channel pair may be deposited on the second sacrificial layer 110b, followed by a deposition of another oxide layer 103b, serving to separate the first channel layer 114a of the second channel pair from a second channel layer 114b of the second channel pair. The deposition of the second channel layer 114b may be followed by depositing a third sacrificial layer 110c.

[0058] The first channel layer 112a and the second channel layer 112b of the first pair of the at least one channel pair, as well as the first channel layer 114a and the second channel layer 114b of the second pair of the at least one channel pair, may be subjected to patterning through a photolithography process.

[0059] Following this, an etching process may be performed to remove portions of the sacrificial layers 110, thereby exposing the underlying channel layers in the regions where the source and drain contacts will be formed. Subsequently, the device may be subjected to a doping process to introduce dopants into the exposed channel regions, creating the source and drain regions with the desired electrical properties. Ion implantation or diffusion methods may be employed to achieve precise control over the dopant concentration and distribution.

[0060] A gate dielectric layer may then be deposited over the entire structure. This layer, which may consist of a high-k dielectric material, provides electrical insulation between the gate electrode and the underlying channel layers. The gate dielectric layer may be deposited using techniques such as atomic layer deposition (ALD) or chemical vapor deposition (CVD) to ensure uniform coverage and optimal thickness control.

[0061] Next, a gate electrode material may be deposited on top of the gate dielectric layer. This material may be a metal or a highly doped polysilicon, chosen for its appropriate work function and conductivity. The gate electrode may then be patterned and etched to form the gate structure, aligned precisely with the underlying channels.

[0062] After the formation of the gate, sidewall spacers may be created along the edges of the gate structure. These spacers, typically made of a dielectric material such as silicon nitride or silicon dioxide, may be deposited and anisotropically etched to form narrow, vertical spacers. The sidewall spacers serve to isolate the gate from the source and drain regions and to define the final dimensions of the gate length.

[0063] Once the sidewall spacers are in place, an epitaxial growth process may be carried out to selectively grow additional semiconductor material on the source and drain regions. This step may help to form raised source and drain structures, enhancing the contact areas and reducing access resistance.

[0064] Finally, the device may undergo a metallization process to form electrical contacts to the source, drain, and gate regions. This process may involve depositing a metal layer, such as aluminium or copper, and patterning it to create the desired contact structures. The resulting twin channel field effect transistor may then be subjected to various post-fabrication treatments, such as annealing, to optimise its electrical performance and reliability.

[0065] While various embodiments have been described and / or illustrated herein in the context of fully functional computing systems, one or more of these exemplary embodiments may be distributed as a program product in a variety of forms, regardless of the particular type of computer- readable-storage media used to actually carry out the distribution. The embodiments disclosed herein may also be implemented using software modules that perform certain tasks. These software modules may include script, batch, or other executable files that may be stored on a computer-readable storage medium or in a computing system. In some embodiments, these software modules may configure a computing system to perform one or more of the exemplary embodiments disclosed herein. In addition, one or more of the modules described herein may transform data, physical devices, and / or representations of physical devices from one form to another.

[0066] The preceding description has been provided to enable others skilled in the art to best utilize various aspects of the exemplary embodiments disclosed herein. This exemplary description is not intended to be exhaustive or to be limited to any precise form disclosed. Many modifications and variations are possible without departing from the spirit and scope of the instant disclosure. The embodiments disclosed herein should be considered in all respects illustrative and not restrictive. Reference should be made to the appended claims and their equivalents in determining the scope of the instant disclosure.

Claims

CLAIMS1. A transistor device (100), comprising: a substrate (101); a channel region formed on the substrate (101), wherein the channel region comprises at least one channel pair (102) stacked on top of each other and spaced from each other, wherein each of the at least one channel pair (102) comprises a first channel (102a) and a second channel (102b) stacked on the first channel (102a) and separated from the first channel (102a) by an oxide layer (103 a); a gate electrode surrounding each of at least one channel pair; and a pair of source / drain regions arranged, respectively, on opposite sides of the channel region, the pair of source / drain regions electrically connected to each of the at least one channel pair channels.

2. The transistor device of claim 1, wherein the first channel (102a) and the second channel (102b) are substantially equal in size.

3. The transistor device of claim 1 or 2, wherein a thickness of the oxide layer (103a) is less than 1 nanometre.

4. The transistor device of any one of claims 1 to 3, wherein the oxide layer (103a) comprises silicon dioxide.

5. The transistor device of claim any one of claims 1 to 4, wherein the oxide layer (103a) is arranged to support epitaxial growth of a crystalline semiconductor material.

6. The transistor device of any one of claims 1 to 5, wherein the at least one channel pair (102) comprises a pair of n-type channels or a pair of p-type channels.

7. The transistor device of any one of claims 1 to 6, wherein each of the at least one channel pair (102) comprises a crystalline semiconductor material.

8. The transistor device of claim 7, wherein the crystalline semiconductor material comprises silicon, Si, or silicon germanium, SiGe.

9. The transistor device of any one of claims 1 to 8, wherein the at least one channel pair comprises a first channel pair (102) and a second channel pair (112), wherein the second channel (102b) of the first channel pair is separated from the first channel (102a) of the first channel pair by a first oxide layer (103 a), wherein the second channel pair (112) comprises a first channel (112a) and a second channel (112b), the second channel (112b) of the second channel pair stacked on top of the first channel (112a) of the second channel pair and separated from the first channel (112a) of the second channel pair by a second oxide layer (103b).

10. The transistor device of claim 9, wherein a length of the first channel pair (102) is different from the length of the second channel pair (112).

11. The transistor device of claim 9 or 10, wherein the first channel pair (102) and the second channel pair (112) comprise the same material.

12. A method for fabricating a transistor device having at least one channel pair, comprising: depositing a first sacrificial layer on a substrate (201); depositing a first channel layer of a first channel pair of the at least one channel pair on top of the first sacrificial layer (202), patterning the first channel of the first channel pair from the first channel layer (203); depositing an oxide layer over the first channel of the first channel pair (204); depositing a second channel layer of a first channel pair of the at least one channel pair (205); and patterning the second channel of the first channel pair from the second channel layer.

13. The method of claim 12, wherein depositing the second channel layer of the first channel pair of the at least one channel pair (205) comprises: epitaxially growing the second channel layer on top of the oxide layer.

14. The method of claim 12, further comprising: depositing a second sacrificial layer on top of the first pair of channel layers; depositing a first channel layer of a second channel pair of the at least one channel pair on top of the second sacrificial layer; patterning the first channel layer of the second channel pair of the at least one channel pair; depositing a second oxide layer over the first channel layer of the second channel pair of the at least one channel pair; depositing a second channel layer of the second channel pair of the at least one channel pair; and patterning the second channel of the second channel pair from the second channel layer.

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