Double-stack type semiconductor light-emitting element and method for manufacturing double-stack type semiconductor light-emitting element

Abstract

Provided is a double-stack type semiconductor light-emitting element having good output characteristics and enabling improvement of reverse voltage characteristics (reduction of leakage current).　A double-stack type semiconductor light-emitting element 100 comprises, in this order: a first n-type semiconductor layer 140; an undoped first active layer 144; a p-type pseudo tunnel junction layer 1471 having a p-type dopant; an n-type pseudo tunnel junction layer 1472 having an n-type dopant and provided in contact with the p-type pseudo tunnel junction layer 1471; an undoped second active layer 149; and a second p-type semiconductor layer 150. The maximum value of the impurity concentration of the n-type dopant included on the n-type pseudo tunnel junction layer 1472 side of the second active layer 149 is 1.0 × 1016 atoms / cm3 or less.

Description

Double-stacked semiconductor light-emitting element and method for manufacturing the same

[0001] The present invention relates to a double-stacked semiconductor light-emitting device and a method for manufacturing the double-stacked semiconductor light-emitting device.

[0002] Conventionally, a double-stack semiconductor light-emitting device has been known in which two or more light-emitting layers are fabricated and arranged perpendicular to each other to increase the output power of the semiconductor light-emitting device. Such a double-stack semiconductor light-emitting device has a tunnel junction layer doped with a high concentration of dopant between each of the two or more vertically arranged light-emitting layers.

[0003] For example, Patent Document 1 discloses an LED semiconductor in which a first active layer and a second active layer are arranged vertically stacked on top of each other, and a tunnel junction is formed between the first active layer and the second active layer.

[0004] Special Publication No. 2009-522755

[0005] However, the double-stack LED semiconductor described in Patent Document 1 has hardly been commercialized in practice. The inventors' investigations revealed that, in reality, even when two light-emitting layers are arranged, the light output at a current of 100 mA is only about 1.3 to 1.45 times that of a single-light-emitting layer. Therefore, the reality is that using multiple single-stack LEDs with one light-emitting layer is more efficient than using double-stack LEDs. Furthermore, further reductions in leakage current and increases in reverse voltage are also desired as device characteristics.

[0006] SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a double-stack type semiconductor light-emitting device that has good output characteristics and is capable of reducing leakage current and increasing reverse voltage, and a method for manufacturing the same.

[0007] The inventors have conducted extensive research into ways to solve the above-mentioned problems. They have concluded that the reason why the light output of double-stack LEDs is only about 1.3 to 1.45 times higher than that of conventional LEDs is due to unintended adverse effects of the dopants contained in the layers for forming the tunnel junction (highly doped layers). Measurements of dopant diffusion behavior revealed that the dopants doped in the n-type tunnel junction layer diffuse into the second active layer, causing a decrease in output power. The inventors have experimentally confirmed conditions for improving output power and reverse voltage characteristics, focusing on the n-type dopant concentration in the active layer on the side where the n-type tunnel layer is provided. The gist of the present invention is as follows:

[0008] (1) A semiconductor device comprising, in this order: a first n-type semiconductor layer; an undoped first active layer; a p-type pseudo tunnel junction layer having a p-type dopant; an n-type pseudo tunnel junction layer having an n-type dopant provided in contact with the p-type pseudo tunnel junction layer; an undoped second active layer; and a second p-type semiconductor layer, wherein the maximum impurity concentration of the n-type dopant contained in the second active layer on the n-type pseudo tunnel junction layer side is 1.0×10 １６ atoms / cm ３ A double-stack type semiconductor light-emitting device, characterized in that:

[0009] (2) Between the n-type pseudo tunnel junction layer and the second active layer, a Si impurity concentration of 5.0×10 １７ atoms / cm ３ Above 5.0 x 10 １８ atoms / cm ３ The double-stack type semiconductor light-emitting device according to (1) above, having a second n-type semiconductor layer that is:

[0010] (3) The average impurity concentration of the n-type dopant contained in the first active layer and the second active layer is 5.0×10 １５ atoms / cm ３ The double-stack type semiconductor light-emitting element according to (1) or (2) above, wherein:

[0011] (4) The double-stack type semiconductor light-emitting device according to any one of (1) to (3) above, wherein the n-type dopant doped into the n-type pseudo tunnel junction layer is Si.

[0012] (5) The double-stack type semiconductor light-emitting device according to any one of (1) to (4) above, wherein the p-type dopant doped into the p-type pseudo tunnel junction layer is C.

[0013] (6) The impurity concentration of the n-type dopant in the n-type pseudo tunnel junction layer is 1.5×10 １９ atoms / cm ３ The double-stack type semiconductor light-emitting element according to any one of (1) to (5) above.

[0014] (7) The impurity concentration of the p-type dopant in the p-type pseudo tunnel junction layer is 1.0×10 １９ atoms / cm ３ The double-stack type semiconductor light-emitting element according to any one of (1) to (6) above.

[0015] (8) The double-stack type semiconductor light-emitting device according to any one of (1) to (7), wherein the first active layer, the second active layer, and the p-type pseudo tunnel junction layer and the n-type pseudo tunnel junction layer contain AlGaInAs or InGaAsP.

[0016] (9) The double-stack semiconductor light-emitting element according to any one of (1) to (8), wherein a current-voltage curve when a current is passed through the p-type pseudo tunnel junction layer and the n-type pseudo tunnel junction layer without passing through the first active layer and the second active layer shows a point where the current becomes maximum in a range of 0.02 V or more and 0.2 V or less.

[0017] (10) The double-stack semiconductor light-emitting device according to any one of (1) to (9), wherein a maximum current value in a current-voltage curve when a current is passed through the p-type pseudo tunnel junction layer and the n-type pseudo tunnel junction layer without passing through the first active layer and the second active layer is 7 mA or less.

[0018] (11) A method for fabricating a semiconductor device comprising the steps of: forming a first n-type semiconductor layer on a substrate; forming an undoped first active layer on the first n-type semiconductor layer; forming a p-type pseudo tunnel junction layer having a p-type dopant on the first active layer; directly forming an n-type pseudo tunnel junction layer having an n-type dopant on the p-type pseudo tunnel junction layer; forming an undoped second active layer on the n-type pseudo tunnel junction layer; and forming a second p-type semiconductor layer on the second active layer, wherein the maximum impurity concentration of the n-type dopant contained on the n-type pseudo tunnel junction layer side of the second active layer is 1.0×10 １６ atoms / cm ３ The following describes a method for manufacturing a double-stack semiconductor light-emitting device.

[0019] (12) An upper electrode provided on the first n-type semiconductor layer, comprising: a support substrate; a junction layer provided on the support substrate; an intermediate electrode layer provided on the junction layer, in which a dielectric portion and an electrode portion are arranged in parallel; a second p-type semiconductor layer provided on the intermediate electrode layer; an undoped second active layer provided on the second p-type semiconductor layer; an n-type pseudo tunnel junction layer having an n-type dopant provided on the second active layer; a p-type pseudo tunnel junction layer having a p-type dopant provided on and in contact with the n-type pseudo tunnel junction layer; an undoped first active layer provided on the p-type pseudo tunnel layer; a first n-type semiconductor layer provided on the first active layer; and an upper electrode provided on the first n-type semiconductor layer, １６ atoms / cm ３ The following is a double-stack type semiconductor light-emitting element.

[0020] According to the present invention, it is possible to provide a double-stack type semiconductor light emitting device having good output characteristics and capable of reducing leakage current and increasing reverse voltage, and a method for manufacturing the same.

[0021] 5 is a schematic cross-sectional view illustrating a double-stacked semiconductor light-emitting device according to a first embodiment of the present invention. FIG. 6 is a schematic cross-sectional view illustrating a double-stacked semiconductor light-emitting device according to a second embodiment of the present invention. FIG. 7 is a schematic cross-sectional view illustrating a part of a manufacturing process for a double-stacked semiconductor light-emitting device according to a second embodiment of the present invention. FIG. 8 is a schematic cross-sectional view illustrating a part of a manufacturing process for a double-stacked semiconductor light-emitting device according to a second embodiment of the present invention, continuing from FIG. 3. FIG. 9 is a schematic cross-sectional view illustrating a part of a manufacturing process for a double-stacked semiconductor light-emitting device according to a second embodiment of the present invention, continuing from FIG. 4. FIG. 10 is a schematic cross-sectional view illustrating a part of a manufacturing process for a double-stacked semiconductor light-emitting device according to a second embodiment of the present invention, continuing from FIG. 11. FIG. 11 is a schematic cross-sectional view illustrating a part of a manufacturing process for a double-stacked semiconductor light-emitting device according to a second embodiment of the present invention, continuing from FIG. 12. FIG. 12 is a schematic cross-sectional view illustrating a performance confirmation element for conducting Test 1. FIG. 13 is a graph illustrating the current-light output characteristics of the double-stacked semiconductor light-emitting devices according to Examples 1 to 3 and Comparative Example 1. FIG. 14 is a graph illustrating the results of measuring the Si diffusion state of the double-stacked semiconductor light-emitting device according to Example 1 by SIMS. FIG. 15 is a graph illustrating the results of measuring the Si diffusion state of the double-stacked semiconductor light-emitting device according to Example 2 by SIMS. 1 is a graph showing the results of measuring the Si diffusion state of the double-stacked semiconductor light-emitting element according to Example 3 by SIMS, and FIG. 2 is a graph showing the results of measuring the Te diffusion state of the double-stacked semiconductor light-emitting element according to Comparative Example 1 by SIMS.

[0022] In this specification, a layer that functions electrically as p-type is referred to as a p-type semiconductor layer (sometimes abbreviated as a "p-type layer"), and a layer that functions electrically as n-type is referred to as an n-type semiconductor layer (sometimes abbreviated as an "n-type layer"). On the other hand, when a specific impurity such as Si, Te, Zn, S, or C is not intentionally added, the layer is called an "i-type" or "undoped" layer. This III-V compound semiconductor layer may contain unavoidable impurities during the manufacturing process. In the present invention, at least an undoped first active layer and an undoped second active layer are provided, and each active layer is formed as an undoped layer without flowing a dopant gas during formation. However, the influence of dopant diffusion from other layers (e.g., tunnel junction layers or pseudo-tunnel junction layers) may be observed. In the present invention, impurities are not intentionally added during layer growth, but the influence of impurity diffusion contained in other layers during the manufacturing process may be observed. In this case, the minimum impurity concentration of 1×10 in a typical n-type cladding layer or p-type cladding layer is 1×10. １６ / cm ３ If no impurity concentrations greater than 0.1 are observed, the active layer is treated as "undoped."

[0023] Generally, a "tunnel junction layer" refers to a layer having a current-voltage curve with a negative resistance region, in which the forward current increases as the forward voltage increases from 0 V, as shown in the curve of Comparative Example 1 in FIG. 9 , followed by a behavior in which the forward current decreases as the forward voltage increases. The forward current flowing before the negative resistance region is called a tunnel current. In this specification, a "pseudo tunnel junction layer" refers to a layer having a negative resistance region in the current-voltage curve, as shown in the curves of Examples 1 to 3 in FIG. 9 , but with a tunnel current close to zero (e.g., 10 mA or less). Although the layer has a region that numerically indicates negative resistance, at first glance, the curve is identical to that of a normal pn junction diode, except for the negative resistance region. It has generally been thought that elements using a tunnel junction structure require a large tunnel current to flow, as shown in Comparative Example 1 in FIG. 9 . Therefore, the present inventors initially believed that a layer with behavior similar to that of the Example in FIG. 9 could not be used as a tunnel junction layer because the tunnel current was too weak. However, when actually used in a double-stack semiconductor light-emitting device of the present invention, for reasons unknown, current flow occurred and a greater light output, lower leakage current, and higher reverse voltage were confirmed compared to the tunnel junction layer in Comparative Example 1. For example, the "pseudo tunnel junction layer" preferably has a starting point of the negative resistance region (maximum current point) in the range of 0.02 V to 0.2 V, and preferably has a maximum tunnel current (maximum current value) of 7 mA or less at the maximum current point. The p-type layer and n-type layer that contact each other within the "pseudo tunnel junction layer" are referred to as the "p-type pseudo tunnel junction layer" and the "n-type pseudo tunnel junction layer," respectively.

[0024] In this specification, the impurity concentrations of n-type and p-type dopants were measured by secondary ion mass spectrometry (SIMS, CAMECA IMS-4f manufactured by AMTEC). The analysis conditions were: primary species: Cs+, primary energy: 14.5 keV, secondary polarity: negative. The SIMS value of each layer is the average value excluding the edge (width: 5 nm) when the film thickness is greater than 40 nm, and the maximum value (peak value) of the SIMS value of the corresponding layer when the film thickness is 40 nm or less.

[0025] In this specification, the n-type pseudo tunnel junction layer side of the second active layer refers to a region from the center of the second active layer in the thickness direction to the boundary with another layer in contact with the n-type pseudo tunnel junction layer side of the second active layer, such as a barrier layer located at the end of the second active layer on the n-type pseudo tunnel junction layer side. Within this region, the maximum impurity concentration of the n-type dopant often appears at the boundary between the second active layer and another layer in contact with the n-type pseudo tunnel junction layer side of the second active layer.

[0026] Each semiconductor layer can be formed by epitaxial growth, for example, by a known thin film growth method such as metal organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE). For example, a semiconductor layer can be formed by using trimethylindium (TMIn) as an In source, trimethylgallium (TMGa) or triethylgallium (TEGa) as a Ga source, trimethylaluminum (TMAl) as an Al source, and arsine (AsH) as an As source. ３ ), or tertiarybutylarsine (TBAs), phosphine (PH ３ ), or tertiary butyl phosphine (TBP) in a predetermined mixture ratio, and these source gases are vapor-phase grown using a carrier gas, thereby forming a layer with a desired thickness depending on the growth time. When each layer is doped to p-type or n-type, a dopant source gas may be further used as desired. For example, when doping with Si, Si ２ H ６ In the case of doping with C, CBr ４ Gas or the like may be used.

[0027] First Embodiment A double-stacked semiconductor light-emitting device and a method for manufacturing the double-stacked semiconductor light-emitting device according to the first embodiment will be described with reference to FIG. 1 . The double-stacked semiconductor light-emitting device 100 has multiple active layers stacked vertically. Between these active layers, a pseudo-tunnel junction layer is sandwiched, through which current flows in the opposite direction (e.g., from n-type to p-type) relative to the conductivity type (e.g., from p-type to n-type) before and after the active layers due to a pseudo-tunnel effect. This double-stacked semiconductor light-emitting device functions as a so-called double-stacked light-emitting diode. For example, in a minimum configuration embodiment with two active layers, the first active layer and the second active layer are arranged overlapping each other vertically. The active layer closer to the p-type pseudo-tunnel junction layer 1471 included in the pseudo-tunnel junction layer 147 is referred to as the first active layer 144, and the active layer closer to the n-type pseudo-tunnel junction layer 1472 included in the pseudo-tunnel junction layer 147 is referred to as the second active layer 149. The semiconductor light-emitting device is preferably a light-emitting diode (LED), and the first and second active layers preferably emit incoherent light. Each active layer may be formed as a single quantum well (SQW) structure, a multiple quantum well (MQW) structure, a quantum wire structure, or a quantum dot structure. Even when the number of active layers is three or more, the active layers are vertically stacked one on top of the other, and any two adjacent active layers among the active layers are considered to be the first active layer 144 and the second active layer 149. If the first active layer 144, the pseudo tunnel junction layer 147, and the second active layer 149 satisfy the requirements of the present invention, the device is a double-stacked semiconductor light-emitting device 100 of the present invention.

[0028] The method for manufacturing the double-stack type semiconductor light emitting device 100 according to the first embodiment includes at least the steps of forming a first n-type semiconductor layer 140, forming an undoped first active layer 144 on the first n-type semiconductor layer 140, forming a p-type pseudo tunnel junction layer 1471 having a p-type dopant on the first active layer 144, forming an n-type pseudo tunnel junction layer 1472 having an n-type dopant directly on the p-type pseudo tunnel junction layer 1471, forming a second active layer 149 on the n-type pseudo tunnel junction layer 1472, and forming a second p-type semiconductor layer 150 on the second active layer 149. All of the semiconductor layers constituting the first n-type semiconductor layer 140 to the second p-type semiconductor layer 150 are collectively referred to as a semiconductor stack 120. The maximum impurity concentration of the n-type dopant originating from the n-type pseudo tunnel junction layer 1472 included in the second active layer 149 on the n-type pseudo tunnel junction layer 1472 side is 1.0×10 １６ atoms / cm ３ The impurity concentration of this n-type dopant is 7.0×10 １５ atoms / cm ３ More preferably, it is 5.0 × 10 or less. １５ atoms / cm ３ It is even more preferable that:

[0029] A first electron blocking layer 145 and / or a first p-type semiconductor layer 146 may be present between the first active layer 144 and the p-type pseudo tunnel junction layer 1471. A second n-type semiconductor layer 148 may be present between the n-type pseudo tunnel junction layer 1472 and the second active layer 149. A second electron blocking layer 151 may be present between the second active layer 149 and the second p-type semiconductor layer 150. An undoped spacer layer may be provided between an undoped layer and a layer that is doped to be p-type or n-type. Each step will be described in detail below.

[0030] First, the growth substrate 105 is prepared. The growth substrate 105 can be a substrate of a compound semiconductor such as GaAs, InP, InAs, GaSb, or InSb. From the viewpoint of cost, a GaAs substrate is preferable. The growth substrate 105 preferably has the same conductivity type as the layer to be grown first thereon. For example, the growth substrate is preferably an S-doped n-type InP substrate, and the first n-type semiconductor layer 140 is preferably stacked on the (100) plane of the n-type InP substrate. The thickness of the growth substrate 105 is preferably 200 μm or more and 900 μm or less.

[0031] <Step of Forming First n-Type Semiconductor Layer> A first n-type semiconductor layer 140 is formed on the growth substrate 105. The first n-type semiconductor layer 140 may be a single layer or may be composed of multiple different layers. FIG. 1 shows an n-type contact layer 141 and a first n-type cladding layer 142 as layers constituting the first n-type semiconductor layer 140. The n-type contact layer 141 may be, for example, an n-type InGaAs layer, and its thickness is preferably 2 nm to 200 nm, and more preferably 5 nm to 20 nm. The first n-type cladding layer may be, for example, an n-type InP layer, and its thickness is preferably 500 nm to 8000 nm, and more preferably 3150 nm to 3750 nm. Examples of n-type dopants used in the n-type contact layer 141 and the first n-type cladding layer 142 include Si and S. A buffer layer may also be provided between the growth substrate 105 and the n-type semiconductor layer 140.

[0032] Although not shown, a spacer layer may be provided between the first n-type semiconductor layer 140 and the undoped first active layer 144 formed thereon. The thickness of the spacer layer is preferably 10 nm to 200 nm, more preferably 70 nm to 130 nm, when in contact with a layer containing an n-type dopant. The spacer layer preferably has the same composition as the adjacent layer and is not doped with a dopant. This spacer layer reduces the amount of impurity diffusion from a doped layer to an undoped layer, for example, reducing the amount of n-type dopant diffusion from the first n-type cladding layer 142 to the first active layer 144.

[0033] <Step of Forming the First Active Layer> An undoped first active layer 144 is formed on the first n-type semiconductor layer 140. The first active layer 144 preferably contains AlGaInAs or InGaAsP. While FIG. 1 illustrates a quantum well structure in which the well layer of the first active layer is the well layer 144w and the barrier layer is the barrier layer 144b, the first active layer 144 may have a single-layer structure. The well layer 144w and the barrier layer 144b may be different layers, or the composition difference may be adjusted to apply strain to the well layer 144w. Furthermore, the first active layer 144 may be formed using, for example, InGaAlAs layers with different composition ratios. The first active layer 144 preferably has a multiple quantum well (MQW) structure as shown in FIG. 1 to suppress crystal defects and improve optical output. This multiple quantum well structure can be formed by alternating the well layer 144w and the barrier layer 144b. When a multiple quantum well structure is used, the number of combinations of well layers 144w and barrier layers 144b is preferably 3 to 40. That is, the number of combinations including the first barrier layer is preferably 3.5 to 40.5. Furthermore, the thickness of each well layer is preferably 5 to 40 nm, and the thickness of each barrier layer is preferably 10 to 50 nm. The first active layer 144 may have a wavelength range in which the central emission wavelength is 1200 nm or more.

[0034] A first electron blocking layer 145 may be provided on the first active layer 144. The first electron blocking layer 145 may be undoped or p-type, but is preferably undoped. The first electron blocking layer may be a single layer or may be composed of multiple layers. The thickness of the first electron blocking layer 145 is preferably 2 nm to 200 nm, and more preferably 5 nm to 30 nm. This first electron blocking layer 145 is a layer that injects and confines carriers into the first active layer 144. The first electron blocking layer 145 also has the effect of reducing diffusion of p-type dopants from the pseudo tunnel junction layer 147 (described later) to the first active layer 144.

[0035] Although not shown, a spacer layer may be provided between the undoped first electron blocking layer 145 and the first p-type semiconductor layer 146 formed thereon. When the spacer layer is in contact with a layer containing a p-type dopant, the thickness of the spacer layer is preferably 40 nm or more and 400 nm or less, and more preferably 170 nm or more and 330 nm or less.

[0036] <Step of Forming First P-Type Semiconductor Layer> A first p-type semiconductor layer 146 is preferably provided between the first active layer 144 and the p-type pseudo tunnel junction layer 1471. The first p-type semiconductor layer 146 may include, for example, a first p-type cladding layer. The composition of the first p-type cladding layer preferably has a smaller band gap than the composition of the first electron blocking layer 145, and examples of such a composition include InGaAsP or InP. The p-type dopant concentration of the first p-type semiconductor layer 146 is 5.0×10 １７ atoms / cm ３ Above 5.0 x 10 １８ atoms / cm ３ The first p-type semiconductor layer 146 may include a layer other than the first p-type cladding layer, and may have, for example, an InAlAs layer or an AlInGaAs layer containing a different Group V element from that of the first p-type cladding layer.

[0037] <Process for Forming Pseudo Tunnel Junction Layer and Pseudo Tunnel Junction Layer> A pseudo tunnel junction layer 147 is formed on the first p-type semiconductor layer 146, with an n-type pseudo tunnel junction layer 1472 stacked directly on a p-type pseudo tunnel junction layer 1471. The p-type pseudo tunnel junction layer 1471 and the n-type pseudo tunnel junction layer 1472 are preferably AlGaInAs or InGaAsP. Dopants that can be used for the p-type pseudo tunnel junction layer 1471 include Mg, Zn, C, and Be, with C being preferred. By using C as the dopant for the p-type pseudo tunnel junction layer 1471, the dopant diffusion phenomenon into adjacent epitaxial layers during growth can be suppressed compared to other dopants. Dopants that can be used for the n-type pseudo tunnel junction layer 1472 include Si, Te, S, Ge, Sn, and Se, with Si being preferred. By using Si as the dopant in the n-type pseudo tunnel junction layer 1472, it is possible to suppress the amount of the dopant doped in the n-type pseudo tunnel junction layer 1472 diffusing into the second active layer 149 (described later). The impurity concentration of the p-type dopant in the p-type pseudo tunnel junction layer 1471 is 1.0×10 １９ atoms / cm ３ It is preferable that the ratio is 1.02×10 or more. １９ atoms / cm ３ More preferably, it is 1.05 × 10 or more. １９ atoms / cm ３ The impurity concentration of the n-type dopant in the n-type pseudo tunnel junction layer 1472 is more preferably 1.5×10 １９ atoms / cm ３ It is preferable that the value is equal to or greater than 1.55×10 １９ atoms / cm ３ More preferably, it is 1.6×10 or more. １９ atoms / cm ３It is more preferable that the thickness and impurity concentration of the p-type pseudo tunnel junction layer 1471 and the n-type pseudo tunnel junction layer 1472 are the same or different. The impurity concentration of the p-type pseudo tunnel junction layer 1471 and the n-type pseudo tunnel junction layer 1472 does not need to be uniform within the layer, and may have a concentration gradient. The impurity concentration of the n-type dopant in the n-type pseudo tunnel junction layer 1472 is 5×10 １９ atoms / cm ３ It is even more preferable that:

[0038] Furthermore, a p-type intermediate layer may be provided between the first p-type semiconductor layer 146 and the p-type pseudo tunnel junction layer 1471. The p-type intermediate layer is a layer made of a different Group V element from the p-type pseudo tunnel junction layer 1471. For example, if the p-type pseudo tunnel junction layer 1471 is made of AlInGaAs, the p-type intermediate layer is made of InGaAsP. The p-type intermediate layer preferably has a higher impurity concentration than the first p-type cladding layer and an impurity concentration equal to or lower than that of the p-type pseudo tunnel junction layer 1471. Similarly, an n-type intermediate layer may be provided between the n-type pseudo tunnel junction layer 1472 and the second n-type semiconductor layer 148. The n-type intermediate layer is a layer made of a different Group V element from the n-type pseudo tunnel junction layer 1472. For example, if the n-type pseudo tunnel junction layer 1472 is made of AlInGaAs, the n-type intermediate layer is made of InGaAsP. The n-type intermediate layer preferably has an impurity concentration higher than that of the second n-type cladding layer and equal to or lower than that of the n-type pseudo tunnel junction layer 1472 .

[0039] Typically, to form a tunnel junction layer, the doping rate of the semiconductor must be extremely high so that the depletion layer formed at the junction interface between the p-type pseudo tunnel junction layer 1471 and the n-type pseudo tunnel junction layer 1472 is thin enough to allow quantum tunneling. In this embodiment, the thickness of the p-type pseudo tunnel junction layer 1471 is preferably 10 nm to 60 nm, more preferably 20 nm to 50 nm, and even more preferably 30 nm to 40 nm. The thickness of the n-type pseudo tunnel junction layer 1472 is preferably 5 nm to 30 nm, more preferably 10 nm to 25 nm, and even more preferably 15 nm to 20 nm.

[0040] The inventors particularly focused on the doping concentration of the Si dopant in the n-type pseudo tunnel junction layer 1472. By optimizing various growth conditions, it became possible to dope the n-type pseudo tunnel junction layer 1472 with a high concentration of Si. Compared to other dopants (e.g., Te), Si atoms have the property of being less likely to diffuse into the second active layer 149, which improves the light-emitting efficiency of the second active layer 149 and also improves the output characteristics of the double-stack semiconductor light-emitting device 100 as a whole.

[0041] A Si-doped second n-type semiconductor layer 148 may be formed on the pseudo tunnel junction layer 147. The Si impurity concentration of the second n-type semiconductor layer 148 is 1.0×10 １７ atoms / cm ３ Above 5.0 x 10 １８ atoms / cm ３ Preferably, it is 3.0 × 10 or less. １７ atoms / cm ３ Above 3.0 x 10 １８ atoms / cm ３ More preferably, it is 5.0 × 10 or less. １７ atoms / cm ３ Above 1.0 x 10 １８ atoms / cm ３The thickness of the second n-type semiconductor layer 148 is preferably 100 nm or more and 2000 nm or less, and more preferably 300 nm or more and 600 nm or less. Furthermore, a layer other than the second n-type semiconductor layer 148 may be included between the second active layer 149 (described later) and the pseudo tunnel junction layer 147, and a spacer layer may be provided between the second n-type semiconductor layer 148 and the undoped second active layer 149.

[0042] The thickness of the spacer layer formed between the second n-type semiconductor layer 148 and the undoped second active layer 149 is preferably 10 nm or more and 200 nm or less, and more preferably 70 nm or more and 130 nm or less. This spacer layer reduces the amount of impurities diffusing from the doped layer to the undoped layer, for example, reducing the amount of Si diffusing from the second n-type semiconductor layer 148 to the second active layer 149.

[0043] <Step of Forming Second Active Layer> An undoped second active layer 149 is formed on the second n-type semiconductor layer 148. The second active layer 149 preferably contains AlGaInAs or InGaAsP. Here, for the double-stack semiconductor light-emitting device 100 having the first active layer 144 and the second active layer 149, the central emission wavelength of the first active layer 144 and the central emission wavelength of the second active layer 149 may be the same wavelength or may be close to each other. If the central emission wavelengths are the same, the second active layer 149 preferably has the same configuration as the first active layer 144. For example, while FIG. 1 illustrates a quantum well structure consisting of the barrier layer 144b and the well layer 144w of the first active layer 144 using InGaAlAs layers with different composition ratios, the barrier layer 149b and the well layer 149w of the second active layer 149 preferably have the same configuration. In this case, the first active layer 144 and the second active layer 149 have the same emission wavelength, and the emission spectrum resulting from the combination of the emission spectra emitted by each active layer has a wavelength range of 1200 nm or greater. If there is no imbalance in luminous efficiency and power consumption between the active layers due to impurity diffusion into the second active layer 149 as described above, the combined emission intensity will be nearly twice as high as in the case of a single active layer. Even if the wavelengths are not the same, if the active layers have the same material composition and the emission center wavelengths are close enough that the two emission spectra partially overlap, the same effect as that of the present invention will be achieved, and the combined emission intensity will be nearly twice as high as in the case of a single active layer.

[0044] A second electron blocking layer 151 may be provided on the second active layer 149. The second electron blocking layer 151 may be undoped or p-type, but is preferably undoped. The second electron blocking layer 151 may be a single layer or may be composed of multiple layers. The thickness of the second electron blocking layer 151 is preferably 2 nm to 200 nm, more preferably 5 nm to 30 nm. This second electron blocking layer 151 is a layer that injects and confines carriers into the second active layer 149. The second electron blocking layer 151 also has the effect of reducing dopant diffusion from the second p-type cladding layer 152 (described later) to the second active layer 149. When the second electron blocking layer 151 is undoped, a spacer layer may be provided between the second electron blocking layer 151 and the second p-type semiconductor layer 150 thereon.

[0045] <Step of forming second p-type semiconductor layer> A second p-type semiconductor layer 150 is formed on the second active layer 149. The second p-type semiconductor layer 150 may be a single layer, or may be composed of multiple different layers. Figure 1 shows the p-type semiconductor layer 150 composed of a second p-type cladding layer 152 and a p-type contact layer 153.

[0046] The thickness of the second p-type cladding layer 152 is preferably 1000 nm or more and 8000 nm or less. If the second p-type cladding layer 152 is thicker than this, the light emitted from the second active layer 149 is significantly absorbed within the second p-type cladding layer 152, which is undesirable because it reduces the external extraction of light. Furthermore, the current spreads to the edge of the LED chip, increasing surface recombination, and the ohmic resistance of the element increases, which is undesirable because it reduces the light emission efficiency. On the other hand, if the second p-type cladding layer 152 is thinner than this, it is undesirable because it emits light directly below the electrode, which hinders light extraction. Examples of dopants that can be used here include Mg, Zn, C, and Be. The dopant concentration of the second p-type cladding layer 152 is 5.0 × 10 １７ atoms / cm ３ Above 3.0 x 10 １８ atoms / cm ３ It is preferable that:

[0047] A p-type contact layer 153 may be provided on the second p-type cladding layer 152, and the thickness of the p-type contact layer 153 is preferably 30 nm or more and 200 nm or less. The p-type contact layer 153 is also preferably formed from a plurality of layers containing different Group V elements so that partial etching removal by patterning is possible, and a portion of the p-type contact layer 153 excluding the p-type contact portion 163 for connection to the upper electrode 191 may be etched away. The dopant concentration of the p-type contact layer 153 is higher than that of the second p-type cladding layer 152, and is 1.0×10 １８ atoms / cm ３ Above 8.0 x 10 １９ atoms / cm ３ It is preferable that the dopant concentration is not more than 1000. Also, the dopant concentration may be graded so that the dopant concentration is higher on the surface side in contact with the electrode.

[0048] In this embodiment, a back electrode 195 may be provided on the back surface of the growth substrate 105, and an upper electrode 191 may be provided on a portion of the p-type contact layer 153. The upper electrode 191 may include a wiring portion and a pad portion of an ohmic electrode, and although not shown, the pad portion may have a metal layer or solder for bonding. Known metal materials and formation methods may be used for the upper electrode 191 and the back electrode 195. Examples of usable metal materials include Ti, Pt, Au, Ag, Al, Zn, and Ni.

[0049] The double-stack type semiconductor light emitting device 100 obtained through the above-described process has good output characteristics, and is capable of reducing leakage current and increasing reverse voltage.

[0050] A description will now be given of the double-stack type semiconductor light-emitting element 100 obtained by the above-described method for manufacturing the double-stack type semiconductor light-emitting element 100. An example of the double-stack type semiconductor light-emitting element 100 is shown with reference to FIG.

[0051] The double-stack type semiconductor light-emitting device 100 includes at least a first n-type semiconductor layer 140, an undoped first active layer 144 on the first n-type semiconductor layer 140, a p-type pseudo tunnel junction layer 1471 having a p-type dopant on the first active layer 144, an n-type pseudo tunnel junction layer 1472 having an n-type dopant and in contact with the p-type pseudo tunnel junction layer 1471, an undoped second active layer 149 on the n-type pseudo tunnel junction layer 1472, and a second p-type semiconductor layer 150 on the second active layer 149. The maximum impurity concentration of the n-type dopant contained in the second active layer 149 and resulting from the n-type pseudo tunnel junction layer 1472 is 1.0×10 １６ atoms / cm ３ is less than 7.0 × 10 １５ atoms / cm ３ More preferably, it is 5.0 x 10 or less. １５ atoms / cm ３ It is even more preferable that:

[0052] <First n-Type Semiconductor Layer> The thickness of the first n-type semiconductor layer 140 is preferably 500 nm or more and 8000 nm or less, and more preferably 3150 nm or more and 3750 nm or less. The first n-type semiconductor layer 140 may include an n-type contact layer 141 and a first n-type cladding layer 142. Although not shown, a spacer layer may be provided between the first n-type semiconductor layer 140 and the first active layer 144. Examples of dopants for the first n-type semiconductor layer 140 include S and Si.

[0053] <First Active Layer and Second Active Layer> The impurity concentrations of the n-type dopants contained in the first active layer 144 and the second active layer 149 are each 1.0×10 １６ atoms / cm ３ Preferably, it is 7.0 x 10 or less. １５ atoms / cm ３ More preferably, it is 5.0 × 10 or less. １５ atoms / cm ３ In principle, the impurity concentration of the n-type dopant contained in the first active layer 144 and the second active layer 149 is 2.0×10 １４ atoms / cm ３That's all. Furthermore, it is preferable that the first active layer 144 and the second active layer 149 each contain AlGaInAs or InGaAsP. The first active layer 144 may have a wavelength range in which the central emission wavelength is 1200 nm or more. Furthermore, in the double-stack type semiconductor light-emitting device 100 having the first active layer 144 and the second active layer 149, the central emission wavelength of the first active layer 144 and the central emission wavelength of the second active layer 149 may be the same wavelength or may be close to each other.

[0054] A first electron blocking layer 145 may be provided on the first active layer 144. The first electron blocking layer 145 may be undoped or p-type, but is preferably undoped. This first electron blocking layer 145 is a layer that injects and confines carriers into the first active layer 144. The first electron blocking layer 145 also has the effect of reducing diffusion of p-type dopants from a pseudo tunnel junction layer 147 (described later) to the first active layer 144.

[0055] For example, a first p-type cladding layer may be provided as the first p-type semiconductor layer 146 on the first electron blocking layer 145. The composition of the first p-type cladding layer preferably has a smaller band gap than the composition of the first electron blocking layer 145, and examples of such a composition include InGaAsP or InP. Although not shown, the above-mentioned spacer layer may be provided between the undoped first electron blocking layer 145 and the first p-type semiconductor layer 146 formed thereon.

[0056] <P-Type Pseudo Tunnel Junction Layer and N-Type Pseudo Tunnel Junction Layer> Dopants that can be used in the p-type pseudo tunnel junction layer 1471 include Mg, Zn, C, and Be, but it is preferable to use C. The impurity concentration of the p-type dopant in the p-type pseudo tunnel junction layer 1471 is 1.0×10 １９ atoms / cm ３ The impurity concentration is preferably 1.02×10 or more. １９ atoms / cm ３ More preferably, it is 1.05 × 10 or more. １９ atoms / cm ３The dopant that can be used in the n-type pseudo tunnel junction layer 1472 includes Si, Te, S, Ge, Sn, Se, etc., but it is preferable to use Si. The impurity concentration of the n-type dopant in the n-type pseudo tunnel junction layer 1472 is 1.0×10 １９ atoms / cm ３ It is preferable that the value is equal to or greater than 1.55×10 １９ atoms / cm ３ More preferably, it is 1.6×10 or more. １９ atoms / cm ３ The p-type pseudo tunnel junction layer 1471 and the n-type pseudo tunnel junction layer 1472 preferably contain AlGaInAs or InGaAsP. The impurity concentration of the n-type dopant in the n-type pseudo tunnel junction layer 1472 is preferably 5×10 １９ atoms / cm ３ It is more preferable that:

[0057] <Second n-Type Semiconductor Layer> A Si-doped second n-type semiconductor layer 148 is preferably provided between the n-type pseudo tunnel junction layer 1472 and the second active layer 149. The Si impurity concentration of the second n-type semiconductor layer 148 is 1.0×10 １７ atoms / cm ３ Above 5.0 x 10 １８ atoms / cm ３ Preferably, it is 3.0 × 10 or less. １７ atoms / cm ３ Above 3.0 x 10 １８ atoms / cm ３ More preferably, it is 5.0 × 10 or less. １７ atoms / cm ３ Above 1.0 x 10 １８ atoms / cm ３ The thickness of the second n-type semiconductor layer 148 is preferably 100 nm or more and 2000 nm or less, and more preferably 300 nm or more and 600 nm or less. The above-mentioned spacer layer may be provided between the second n-type semiconductor layer 148 and the undoped second active layer 149.

[0058] <Second p-Type Semiconductor Layer> The thickness of the second p-type semiconductor layer 150 is preferably 1000 nm or more and 8400 nm or less, and more preferably 2000 nm or more and 5000 nm or less. The second p-type semiconductor layer 150 may include a second p-type cladding layer 152 or a p-type contact layer 153. Examples of dopants for the second p-type semiconductor layer 150 include Zn and C. A second electron blocking layer 151 may be provided between the second active layer 149 and the second p-type semiconductor layer 150, and a spacer layer (not shown) may be provided on the second electron blocking layer 151. A p-type contact portion 163 for connection to the upper electrode 191 may be provided by removing a portion of the p-type contact layer 153.

[0059] <Characteristics of Pseudo Tunnel Junction Layer> In a current-voltage curve when a current is passed through the p-type pseudo tunnel junction layer 1471 and the n-type pseudo tunnel junction layer 1472 without passing through the first active layer 144 and the second active layer 149, it is preferable that the voltage at which the current reaches a maximum is 0.02 V or more and 0.2 V or less.

[0060] Furthermore, it is preferable that the maximum current value in a current-voltage curve when current is passed through the p-type pseudo tunnel junction layer 1471 and the n-type pseudo tunnel junction layer 1472 without passing through the first active layer 144 and the second active layer 149 is 7 mA or less.

[0061] The double-stack semiconductor light-emitting device 100 described above in detail has good output characteristics, and is capable of reducing leakage current and improving reverse voltage characteristics. Note that in the double-stack semiconductor light-emitting device 100 shown in FIG. 1, the first n-type semiconductor layer 140, the first active layer 144, the p-type pseudo tunnel junction layer 1471, the n-type pseudo tunnel junction layer 1472, the second active layer 149, and the second p-type semiconductor layer 150 are provided in this order from the bottom of the page, but this is just an example, and the stacking order may be reversed.

[0062] Second Embodiment A double-stacked semiconductor light-emitting device 200 according to a second embodiment of the present invention will be described with reference to Figure 2. The double-stacked semiconductor light-emitting device 200 is a junction-type semiconductor light-emitting device obtained by bonding a support substrate to the side of a semiconductor laminate opposite to the growth substrate side and then removing the growth substrate. In principle, components that are the same as those in the double-stacked semiconductor light-emitting device 100 are given the same reference numerals, with the last two digits of the three-digit number being used, and duplicated descriptions will be omitted.

[0063] The double-stack type semiconductor light-emitting element 200 includes at least a support substrate 280, a bonding layer 270 provided on the support substrate 280, an intermediate electrode layer 260 in which a dielectric portion 261 and an electrode portion 265 provided on the bonding layer 270 are parallel to each other, a second p-type semiconductor layer 250 provided on the intermediate electrode layer 260, an undoped second active layer 249 provided on the second p-type semiconductor layer 250, an n-type pseudo tunnel junction layer 2472 having an n-type dopant provided on the second active layer 249, a p-type pseudo tunnel junction layer 2471 having a p-type dopant provided on and in contact with the n-type pseudo tunnel junction layer 2472, an undoped first active layer 244 provided on the p-type pseudo tunnel junction layer 2471, a first n-type semiconductor layer 240 provided on the first active layer 244, and an upper electrode 291 provided on the first n-type semiconductor layer 240. The maximum impurity concentration of the n-type dopant originating from the n-type pseudo tunnel junction layer 2472 included in the second active layer 249 on the n-type pseudo tunnel junction layer 2472 side is 1.0×10 １６ atoms / cm ３ The impurity concentration of the n-type dopant is 7.0×10 １５ atoms / cm ３ More preferably, it is 5.0 × 10 or less. １５ atoms / cm ３ In principle, the impurity concentration of the n-type dopant contained in the second active layer 249 and resulting from the n-type pseudo tunnel junction layer 2472 is 2.0×10 １４ atoms / cm ３ That's all.

[0064] The double-stack type semiconductor light-emitting device 200 shown in FIG. 2 has, in order from the side opposite to the support substrate 280, a first n-type semiconductor layer 240 (an n-type contact layer 241 and a first n-type cladding layer 242), a first active layer 244, a first electron blocking layer 245, a first p-type semiconductor layer 246, a p-type pseudo tunnel junction layer 2471, an n-type pseudo tunnel junction layer 2472, a second n-type semiconductor layer 248, a second active layer 249, a second electron blocking layer 251, and a second p-type semiconductor layer 250 (a second p-type cladding layer 252 and a p-type contact layer 253).

[0065] The support substrate 280, which is different from the growth substrate, is preferably cheaper and has higher thermal conductivity than the growth substrate, and examples thereof include a compound substrate such as Si, Ge, or GaAs, a metal substrate using a metal that can suppress the thermal expansion coefficient such as copper alloy, molybdenum, tungsten, or Kovar, or a submount substrate in which a metal is attached to a ceramic substrate such as AlN. From the standpoints of processability and cost, it is also preferable to use a Si substrate as the support substrate 280.

[0066] An example of an embodiment of a double-stacked semiconductor light-emitting device 200 and a method for manufacturing the same will be described in more detail below with reference to FIGS. 3 to 7. First, a growth substrate 205 is prepared. Then, with reference to FIG. 3, a semiconductor laminate 220 is formed. At this time, an etching stop layer (not shown) may be formed on the growth substrate 205. The semiconductor laminate 220 is similar to the semiconductor laminate 120 described above.

[0067] <<Formation of Intermediate Electrode Layer>> An intermediate electrode layer 260 may be formed on the p-type contact layer 253. The intermediate electrode layer 260 includes a dielectric portion 261 having a through-hole, an electrode portion 265 provided in the through-hole, and a p-type contact portion 263 that is a part of the p-type contact layer 253. The dielectric portion 261 and the electrode portion 265 (and the p-type contact portion 263) may be arranged in parallel, or the electrode portion 265 and the p-type contact portion 263 may be arranged in series. Any specific method for forming the intermediate electrode layer 260 may be used; however, an example of a specific embodiment for forming the intermediate electrode layer 260 will be described below with reference to FIGS. 4 and 5 . Note that, for simplicity, the figures illustrate two locations in the intermediate electrode layer 260 where the electrode portion 265 and the p-type contact portion 263 are provided. However, the number of locations may be one or more. Preferably, the locations are arranged in a dispersed island or stripe pattern so that the current between the upper electrode 291 and the upper electrode 291 can be spread evenly in the in-plane direction while avoiding a location directly below the upper electrode 291.

[0068] First, a mask is formed on the p-type contact layer 253, and an electrode portion 265 is formed on the p-type contact portion 263, which is a part of the p-type contact layer 253, using a method such as sputtering. The resist is then removed, and the electrode portion 265 is removed from the area other than the p-type contact portion 263. A mask is then formed on the p-type contact layer 253, and a portion of the p-type contact layer 253 other than the area where the electrode portion 265 is formed is removed to form the p-type contact portion 263 as a convex portion. Next, the dielectric portion 261 is formed on the semiconductor stack 220. Known methods such as plasma CVD and sputtering can be used as the film formation method. Then, a resist pattern on the intermediate electrode layer 260 is formed on the dielectric portion 261 using a photomask, and the dielectric portion 261 above the electrode portion 265 is removed by etching until the electrode portion 265 is exposed. The thickness of the intermediate electrode layer 260 is preferably 500 nm to 1000 nm, and more preferably 600 nm to 800 nm.

[0069] <<Formation of Metal Reflective Layer>> As shown in FIG. 4 , it is also preferable to form a metal reflective layer 271 on the intermediate electrode layer 260. The metal reflective layer 271 can include multiple metal layers. The metal reflective layer 271 can be made of metals such as Au, Al, Pt, Ti, and Ag. The composition of the metal reflective layer 271 preferably contains 50 mass% or more of Au. Furthermore, to ensure reliable bonding with the metal bonding layer 279 in a subsequent process, it is preferable that the outermost layer of the metal reflective layer 271 (the surface opposite the semiconductor laminate 220) be an Au metal layer. The thickness of the metal reflective layer 271 is preferably 400 nm or more and 2200 nm or less, and more preferably 1500 nm or more and 2000 nm or less.

[0070] <<Bonding with Support Substrate>> The semiconductor stack 220 and the intermediate electrode layer 260 are bonded to the support substrate 280 via at least a metal bonding layer 279. By providing a metal reflective layer 271, the metal reflective layer 271 and the metal bonding layer 279 may be bonded. The metal bonding layer 279 and the metal reflective layer 271 are placed opposite each other and bonded together, and thermal compression bonding is performed at a temperature of about 250°C to 500°C, thereby bonding the two together.

[0071] <<Formation of Metal Bonding Layer>> The metal bonding layer 279 can be formed using metals such as Ti, Pt, Au, or a metal that forms a eutectic alloy with Au (such as Sn), or solder, and is preferably formed by stacking these. The thickness of the metal bonding layer 279 is preferably 1000 nm or more and 2000 nm or less, and more preferably 1200 nm or more and 1800 nm or less. The outermost layer of the metal bonding layer 279 can be made of Au metal, and the outermost layer of the metal reflective layer 271 can also be made of Au, allowing bonding between the Au layers through Au-Au diffusion. The metal reflective layer 271 and the metal bonding layer 279 bonded together are referred to as the bonding layer 270.

[0072] The support substrate 280 may be a substrate of a different type from the growth substrate 205, and may be a submount substrate based on the semiconductor substrate, metal substrate, or ceramic substrate described above. Because the above-described bonding method is used, the support substrate 280 may be lattice-mismatched with the semiconductor layers formed in this embodiment. While the support substrate 280 may be insulating depending on the application, a conductive substrate is preferred. From the standpoints of processability and cost, a Si substrate is preferably used for the support substrate 280. By using a Si substrate, the thickness of the support substrate 280 can be significantly reduced compared to conventional substrates, making it suitable for implementation in combination with various semiconductor devices. Furthermore, Si substrates are advantageous in terms of heat dissipation compared to InAs substrates.

[0073] <<Removal of Growth Substrate>> After bonding the support substrate 280, the growth substrate 205 is removed. If the growth substrate 205 is a GaAs substrate, the growth substrate 205 can be wet-etched using, for example, an ammonia-hydrogen peroxide mixture. If the growth substrate 205 is an InP substrate, the growth substrate 205 can be wet-etched using, for example, diluted hydrochloric acid.

[0074] As shown in FIG. 5 , after removing the growth substrate 205, an ohmic electrode and a pad electrode may be formed as an upper electrode 291 on the upper surface of the semiconductor laminate 220 (the surface opposite the support substrate 280). The ohmic electrode can be formed using a metal such as Au, Ge, Ni, or Ti, a metal that forms a eutectic alloy with Au (e.g., Sn), or solder. The ohmic electrode can be formed by depositing a film using a common method such as vapor deposition. The thickness of the ohmic electrode is not limited, but can be, for example, 300 nm to 1300 nm. After depositing the ohmic electrode, it is preferable to perform heat treatment for ohmic contact.

[0075] After forming the ohmic electrode, it is preferable to form a pad electrode on the ohmic electrode. The pad electrode can be formed using a metal such as Ti or Au, a metal that forms a eutectic alloy with Au (such as Sn), or solder. The pad electrode can be formed using a common method such as vapor deposition. If the n-type contact layer 241 has low optical transparency at the emission wavelength, it is preferable to remove the n-type contact layer 241 except for the region where the upper electrode 291 is to be formed, thereby exposing the surface of the first n-type cladding layer 242.

[0076] After forming the pad electrode, the upper surface of the semiconductor laminate 220 (e.g., the surface of the first n-type cladding layer 242) other than the upper electrode 291 and its periphery may be roughened. This is because roughening improves light extraction efficiency. The surface of the first n-type cladding layer 242 can be roughened by using a general method such as selective etching using a mask or wet etching. When viewed from above, the upper electrode 291 and the electrode portion 265 are preferably formed spaced apart from each other.

[0077] <<Mesa Formation>> As shown in FIG. 6 , a mesa shape may be formed in the semiconductor stack 220 by removing a portion of the semiconductor stack 220 by dry etching. The dry etching method is preferably reactive ion etching (RIE), and an inductively coupled plasma (ICP) may be used as the plasma source. Dry etching is performed on street regions having a certain width along the planned chip division lines when viewed from above. The width of the street regions (street width) is a width necessary to perform chip division without adversely affecting the active layer, etc., and is, for example, 40 to 100 μm. The street regions may be formed in a lattice pattern, and the pad electrodes formed above or the electrode portions 265 of the intermediate electrode layer 260 are disposed in areas other than the street regions when viewed from above. A mask (e.g., SiO ) having an etching rate smaller than that of the semiconductor stack 220 during dry etching and a thickness that does not disappear until the etching of the street regions is completed is formed on the first n-type cladding layer 242 so as to expose the first n-type cladding layer 242 in the street regions. ２After forming a mask (mask), dry etching is performed on the street region. This dry etching is performed until the intermediate electrode layer 260 is exposed outside the mesa shape. The angle θ between the intermediate electrode layer 260 and the second p-type semiconductor layer 250 is preferably 70° or more and 85° or less. Furthermore, it is preferable that the two active layers and the space between them have perpendicular side surfaces so that the areas of the first active layer and the second active layer are the same when viewed from above.

[0078] <Formation of Protective Film> After the mesa is formed, it is preferable to form a protective film 230 by plasma CVD or the like, as shown in FIG. ２ The SiO mask used in the mesa formation process is also usable. ２ may be a part of the protective film 230. It is also preferable that the protective film 230 does not cover the upper surface of the upper electrode 291. The thickness of the protective film 230 is preferably 50 nm or more and 500 nm or less.

[0079] Furthermore, a back electrode 295 may be formed on the back surface of the support substrate 280 .

[0080] By the above manufacturing method, the double stack type semiconductor light emitting device 200 shown in FIG. 2 can be obtained.

[0081] Example 1 First, an n-type InP growth substrate 205 (thickness: 600 μm, S-doped, dopant concentration: 2.0×10) was prepared by MOCVD. １８ / cm ３ A Si-doped n-type InP buffer layer (thickness: 120 nm, carrier concentration: 5.0×10) was formed on the (100) plane of the １７ / cm ３ ) is formed thereon, and a Si-doped n-type In is formed thereon as a first n-type semiconductor layer 240. ０．５３２ Ga ０．４６８ As contact layer 241 (thickness: 24 nm, carrier concentration: 5.0×10 １７ / cm ３ ), a Si-doped first n-type InP cladding layer 242 (thickness: 3.5 μm, carrier concentration: 5.0×10 １７ / cm ３) was formed on the first active layer 244, and an undoped InP spacer layer (thickness: 100 nm) was formed thereon. Next, a first active layer 244 (total thickness: 165 nm) with a quantum well structure having an emission center wavelength of 1500 nm was formed. The first active layer 244 was made of undoped InP so that the emission center wavelength was 1500 nm. ０．４１９ Ga ０．２９７ Al ０．２８４ As barrier layer 244w (thickness: 10 nm) and In ０．７６５ Ga ０．１２５ Al ０．１１０ As well layers 244b (thickness: 5 nm) are alternately stacked in order of 10 layers, and then In ０．４１９ Ga ０．２９７ Al ０．２８４ An As barrier layer 244w was grown, making a total of 10.5 sets including the last barrier layer. ０．５２２ Al ０．４７８ An As first electron blocking layer 245 (thickness: 20 nm) and an undoped InP spacer layer (thickness: 300 nm) were formed, and a Zn-doped first p-type InP semiconductor layer (thickness: 500 nm, carrier concentration: 7.0×10) was formed as the first p-type semiconductor layer 246. １７ / cm ３ ), Zn-doped p-type Al ０．４７８ In ０．５２２ As layer (thickness: 200 nm, carrier concentration: 1.0 × 10 １８ / cm ３ ), Zn-doped p-type Al ０．１２２ In ０．５２９ Ga ０．３４９ As layer (thickness: 20 nm, carrier concentration: 1.0 × 10 １８ / cm ３ ) was formed on the substrate. ０．７６３ Ga ０．２３７ As ０．５１２ P ０．４８８ Intermediate layer (thickness: 20 nm, carrier concentration: 1.0 × 10 １８ / cm ３ ) was formed.

[0082] Furthermore, C-doped p-type Al ０．１３７ In ０．５２９ Ga ０．３３４ As pseudo-tunnel junction layer 2471 (thickness: 36 nm, carrier concentration: 5.0×10１９ / cm ３ ) on top of which Si-doped n-type Al ０．１３７ In ０．５２９ Ga ０．３３４ As pseudo-tunnel junction layer 2472 (thickness: 18 nm, carrier concentration: 1.5×10 １９ / cm ３ The p-type pseudo tunnel junction layer 2471 was formed by doping with CBr. ４ The n-type pseudo tunnel junction layer 2472 was doped with C using a doping gas of Si. ２ H ６ Next, a Si-doped n-type In was formed on the n-type pseudo tunnel junction layer 2472. ０．７６３ Ga ０．２３７ As ０．５１２ P ０．４８８ Intermediate layer (thickness: 16 nm, carrier concentration: 1.5 × 10 １９ / cm ３ ) was formed.

[0083] A Si-doped second n-type InP semiconductor layer (thickness: 500 nm, carrier concentration: 1.5×10) was formed as a second n-type semiconductor layer 248 on the pseudo tunnel junction layer 247 via an n-type intermediate layer. １８ / cm ３ ) was formed on the first active layer 244, and an undoped InP spacer layer (thickness: 100 nm) was formed thereon. Next, a second active layer 249 (total thickness: 165 nm) having the same structure as the first active layer 244 was formed. Furthermore, an undoped InP spacer layer (thickness: 100 nm) was formed on the second active layer 249. ０．５２２ Al ０．４７８ An As second electron blocking layer 251 (thickness: 20 nm) and an undoped InP spacer layer (thickness: 300 nm) were formed. Then, a Zn-doped second p-type InP clad layer 252 (thickness: 2.4 μm, carrier concentration: 7.0×10) was formed as the second p-type semiconductor layer 250. １７ / cm ３ ) and a Zn-doped p-type InP layer (thickness: 240 nm, carrier concentration: 1.5 × 10 １８ / cm ３ ), Zn-doped p-type In ０．７４９ Ga ０．２５１ As ０．５４３ P ０．４５７layer (thickness: 60 nm, carrier concentration: 5.0 × 10 １８ / cm ３ ), and Zn-doped p-type InGa ０．４６８ As (thickness: 120 nm, carrier concentration: 1.5 × 10 １９ / cm ３ ) was formed as a p-type contact layer 253.

[0084] The composition, thickness, dopant type, and carrier concentration of each layer are shown in Table 1 below. Note that the carrier concentration is the designed impurity concentration during crystal growth. The impurity concentration measured by SIMS analysis, which will be described later, is the impurity concentration in the present invention.

[0085]

[0086] Next, the p-type InGaAs layer on the top surface of the p-type contact layer 253 was covered with photoresist except for the surface of the region that would become the p-type contact portion 263, and Ti (thickness: 10 nm) and Au (thickness: 530 nm) were deposited as the electrode portion 265 using a vapor deposition method, and the resist pattern on the region that would become the p-type contact portion 263 except for the electrode portion 265 was removed together with the metal deposited thereon. After contact annealing, a photomask was formed on the electrode portion 265, and the p-type InGaAs layer in the region that would become the p-type contact portion 263 was left, and the rest of the p-type InGaAs layer was removed by wet etching using a tartaric acid-hydrogen peroxide mixture. SiO was deposited on the entire surface of the p-type contact layer 253 using a plasma CVD method. ２ A dielectric portion 261 (thickness: 700 nm) consisting of Pt was formed. The dielectric portion 261 on the electrode portion 265 was removed by etching to form an intermediate electrode layer 260 in which the dielectric portion 261 and the electrode portion 265 (and the p-type InGaAs contact portion 263) were arranged in parallel. Next, a metal reflective layer 271 (Al (film thickness: 10 nm / Au (film thickness: 650 nm) / Pt (film thickness: 100 nm) / Au (film thickness: 900 nm))) was formed on the intermediate electrode layer 260 by vapor deposition.

[0087] Thereafter, a metal bonding layer 279 (Ti (film thickness: 650 nm) / Pt (film thickness: 20 nm) / Au (film thickness: 900 nm)) was formed on the support substrate (Si substrate) 280 by vapor deposition. Next, the metal reflective layer 271 and the metal bonding layer 279 were arranged facing each other and subjected to thermal compression bonding at 300°C to form the bonding layer 270. Next, the growth substrate 205 was removed by wet etching using a diluted hydrochloric acid solution to expose the n-type InGaAs contact layer 241.

[0088] A top ohmic electrode was formed on the n-type InGaAs contact layer 241 using a vapor deposition method. A pad electrode (Ti (thickness: 150 nm) / Pt (thickness: 100 nm) / Au (thickness: 2500 nm)) was then formed on the top ohmic electrode using a vapor deposition method. A resist-based lift-off method was used to form the electrode pattern. The n-type InGaAs contact layer 241 was then removed from the area directly below the top ohmic electrode by wet etching using a tartaric acid-hydrogen peroxide mixture.

[0089] Next, a resist mask was formed by photolithography to cover the street region along the planned chip dividing line as well as the upper surface ohmic electrode and pad electrode, and the upper surface of the light extraction surface of the first n-type InP cladding layer 242 other than the masked region was roughened by wet etching.

[0090] Then, SiO is deposited on the entire surface by plasma CVD. ２ After forming the SiO2 layer, a mask pattern is formed using a resist and then etched to expose the street areas along the planned chip dividing lines. ２A mask was formed. The width of the street region exposed by the mask pattern was 55 μm. A mesa was formed by dry etching (ICP-RIE), exposing the outer periphery of the intermediate electrode layer 260 in the street region and also exposing the side surface of the semiconductor laminate 220. The etching conditions were dry etching, stage temperature 200° C., pressure 0.2 Pa, bias power 150 W, ICP power 190 W, over-etching rate 5%, and ratio of gas species used SiCl ４ :Ar=4:8.

[0091] After the mesa is formed, the SiO ２ After removing the mask, the entire surface (the remaining SiO ２ A SiN film (thickness: 190 μm) was formed as a protective film 230 on the upper surface of the mask (including the upper surface of the mask and the exposed side surfaces and street regions of the mesa portion). Then, the SiN on the upper surface of the upper electrode 291 was removed by etching using a resist mask pattern, and the resist was then removed. Next, the rear surface of the support substrate 280 was polished or etched to reduce the thickness of the double-stacked semiconductor light-emitting device 200 to 150 μm. Next, a rear electrode 295 (Ti (thickness: 10 nm) / Pt (thickness: 50 nm) / Au (thickness: 200 nm)) was formed on the rear surface of the support substrate 280 by vapor deposition, and heat treatment was performed at 300° C. for 60 seconds by RTA. Finally, the double-stacked semiconductor light-emitting device 200 according to Example 1 was fabricated by separating the substrate into individual rectangular elements with a chip size of 1080 μm × 1080 μm using laser dicing.

[0092] Example 2 A double-stack type semiconductor light-emitting device 200 according to Example 2 was obtained in the same manner as Example 1, except that the n-type InGaAsP intermediate layer (n-InGaAsP layer) and the p-type InGaAsP intermediate layer (p-InGaAsP layer) were not provided.

[0093] Example 3 Dopant gas (Si) when forming n-type pseudo tunnel junction layer 2472 ２ H ６ A double-stack type semiconductor light-emitting device 200 according to Example 3 was obtained in the same manner as in Example 1, except that the flow rate of the gas mixture 201 was set to 3200 sccm.

[0094] Comparative Example 1 The growth temperature for forming the p-type pseudo tunnel junction layer 2471 was set to 725°C instead of 750°C, and the temperature was changed from 725°C to 630°C during growth. Furthermore, the n-type pseudo tunnel junction layer 2472 was formed using Te as the dopant and DETe (diethyl tellurium) as the dopant gas, with a flow rate of 10 sccm and a growth temperature changed from 725°C to 630°C. Aside from these conditions, the double-stacked semiconductor light-emitting device 200 according to Comparative Example 1 was obtained in the same manner as in Example 1. Hereinafter, the layer located in the pseudo tunnel junction layer 247 of Comparative Example 1 will be simply referred to as the tunnel junction layer.

[0095] Comparative Example 2 A single-stack semiconductor light-emitting device according to Comparative Example 2 was obtained in the same manner as in Example 1, except that up to the first p-type semiconductor layer 246 was formed on the growth substrate 205, and then the pseudo-tunnel junction layer 247, the second active layer 249, etc. were not formed, and the p-type contact layer 253 was formed.

[0096] Example 4 A double-stack type semiconductor light-emitting device 200 according to Example 4 was obtained in the same manner as in Example 1, except that the compositions of the first active layer 244 and the second active layer 249 were adjusted so that the central emission wavelength was 1300 nm.

[0097] Comparative Example 3 A single-stack type semiconductor light-emitting device according to Comparative Example 3 was obtained in the same manner as in Comparative Example 2, except that the compositions of the first active layer 244 and the second active layer 249 were adjusted so that the central emission wavelength was 1300 nm.

[0098] [Test 1] Test 1 evaluated the performance of the pseudo tunnel junction layer 247 of Examples 1 to 3 and the tunnel junction layer of Comparative Example 1. In order to evaluate the pure tunnel effect, the test was conducted as follows so that current could be passed through the pseudo tunnel junction layer 247 (or tunnel junction layer) without passing through the first active layer 244 and the second active layer 249.

[0099] Specifically, first, a first p-type semiconductor layer 246 (p-InP, 500 nm thick), a pseudo-tunnel junction layer 247 (or tunnel junction layer), and a second n-type semiconductor layer 248 (n-InP, 500 nm thick) were formed on a 2-inch p-type InP substrate under the conditions described above. An n-type contact layer 241 (n-InGaAs, 24 nm thick) and an InP cap layer were then grown in this order (FIG. 8, Step A). ​​The upper InP cap layer was etched using an etching solution of hydrochloric acid and acetic acid to expose the n-type contact layer 241 (FIG. 8, Step B). Next, the surface other than the top electrode pattern was covered with photoresist. After the top electrode was deposited by vapor deposition, the resist was removed together with the metal film deposited thereon to form the top electrode (FIG. 8, Step C). Next, the n-type contact layer 241 was etched away except for the area directly under and around the upper electrode, and a mesa-forming mask was formed to cover the remaining n-type contact layer 24 and the upper electrode (FIG. 8, Step D). Then, mesa etching was performed by wet etching (etching solution: Br-MeOH) (FIG. 8, Step E). After removing the mask, a back electrode was deposited on the back surface of the p-type InP substrate (FIG. 8, Step F). The fabricated device was designated as the performance verification device 10.

[0100] The performance confirmation element was placed on the stage of an LED tester (manufactured by YAC Garter, model number: LX4730A), and a probe was placed on the upper electrode to apply current for 100 ms. The upper electrode of the performance confirmation element 10 had a circular shape with a diameter of 194.4 μm and an area of ​​29681 μm. ２ Furthermore, the shape of the mesa was circular, with a diameter of 235.2 μm and an area of ​​43447 μm. ２ The results of the energization for each example and comparative example 1 are shown in FIG. 9. Table 2 also shows the epitaxial structure, dopant, film thickness, and the energization results for the p-type pseudo tunnel junction layer 2471 and n-type pseudo tunnel junction layer 2472 for each example. Table 2 also shows the epitaxial structure, dopant, film thickness, and the energization results for the tunnel junction layer of comparative example 1. The SIMS impurity concentrations [cm -３ ] is a transcription of the impurity concentration (peak value) measured by SIMS in Test 2 described later, not in the performance verification element 10.

[0101] *The resistance value [Ω] was calculated by averaging the resistance value when the voltage Vr was in the range of 0.2 V to 0.5 V. **The voltage drop start voltage [V] is the voltage at the start of the negative resistance region where the current is at its maximum, and the voltage drop end voltage [V] is the voltage at the end of the negative resistance region where the current is at its minimum.

[0102] As can be seen from FIG. 9 and Table 2, in Comparative Example 1, the maximum tunnel current (maximum value of current) was as large as several tens of mA, as is the case with a general tunnel junction layer, and tunnel junction characteristics with negative resistance were obtained. On the other hand, in Examples 1 to 3, the starting point of the negative resistance region (the point where the current becomes maximum) in the I-V curve was between 0.02 and 0.2 V, and the maximum tunnel current (maximum value of current) was 7 mA or less, confirming a phenomenon different from behavior that has conventionally been considered.

[0103] [Test 2] In Test 2, the output characteristics of the double-stack semiconductor light-emitting device 200 fabricated in Examples 1 to 4 and Comparative Example 1 and the single-stack semiconductor light-emitting device fabricated in Comparative Examples 2 and 3 were measured. Furthermore, Examples 1 to 3 and Comparative Examples 1 and 2 were subjected to SIMS analysis to measure the impurity concentrations. Table 3 shows the light-emitting output Po [mW] and forward voltage Vf [V] when currents of 30 mA, 100 mA, and 1 A were applied to the double-stack semiconductor light-emitting device 200 fabricated in Examples 1 to 4 and Comparative Example 1 and the single-stack semiconductor light-emitting device fabricated in Comparative Examples 2 and 3, as well as the leakage current Ir [A] when voltages of 5 V and 10 V were applied, and the reverse voltage Vr [V] when currents of 0.1 μA and 1 μA were applied. FIG. 10 is a graph showing the current-light-emitting output characteristics of Examples 1 to 3 and Comparative Examples 1 and 2 (devices with a target wavelength band of 1500 nm).

[0104]

[0105] As can be seen from Table 3 and FIG. 10 , when a current of 1 A was applied, the light output of Examples 1 to 3, in which the dopant of the n-type pseudo tunnel junction layer 2472 was Si, was 1.8 to 1.9 times that of the single-stack type Comparative Example 2, and when the current was 100 mA, it was 1.6 to 1.7 times. In contrast, when a current of 1 A was applied, the light output of Comparative Example 1, in which the dopant of the n-type pseudo tunnel junction layer 2472 was Te, was approximately 1.5 times that of the single-stack type Comparative Example 2, and when the current was 100 mA, it was approximately 1.4 times. The greater the current applied, the greater the effect of improving the light output of this example. This example also has the effect of suppressing output reduction due to heat generation when a large current is applied. It is believed that the pseudo tunnel junction layer 247 of the present invention is able to diffuse current in the in-plane direction more easily than a normal tunnel junction layer, thereby suppressing heat generation due to current concentration. Furthermore, when a reverse voltage of 5 V was applied to Examples 1 to 3, the leakage current Ir was 1.0×10 -１０ A, and 6.5 × 10 -９ A significant reduction in leakage current was also observed. The leakage current Ir when a reverse voltage of 10 V was applied to Examples 1 to 3 was also reduced compared to Comparative Example 1 and the single-stack type Comparative Example 2. Furthermore, the reverse voltage Vr when 0.1 μA or 1 μA was applied to Examples 1 to 3 was approximately 30 V, and a significant increase in reverse voltage was also observed compared to Comparative Example 1 or the single-stack type Comparative Example 2. These effects of improved light output, reduced leakage current, and increased reverse voltage were also observed in a comparison between Example 4, which has a different wavelength, and the single-stack type Comparative Example 3.

[0106] 11 to 14 show the results of SIMS analysis for Examples 1 to 3 and Comparative Example 1, respectively. In these figures, the horizontal axis range was set so that the entire regions of the second active layer 249 and the first active layer 244 were included in the range, so that the extent of n-type dopant diffusion could be seen. Table 4 also shows the average impurity concentrations of the second active layer 249, the first active layer 244, and the n-type InP layer, the maximum (peak) impurity concentration of the pseudo tunnel junction layer 247 (TJ), and the maximum (peak) impurity concentration of the n-type dopant on the TJ side of the second active layer 249 for Examples 1 to 3, as determined from the results of these SIMS analyses. Table 4 also shows the average impurity concentrations of the second active layer 249, the first active layer 244, and the n-type InP layer, the maximum (peak) impurity concentration of the tunnel junction layer (TJ), and the maximum (peak) impurity concentration of the n-type dopant on the TJ side of the second active layer 249 for Comparative Example 1.

[0107] The method for defining the boundary line between the second active layer 249 (i-InGaAlAs) and the spacer layer (i-InP), which is shown by a dashed line in the SIMS profiles of Figures 11 to 14, is described below. The boundary line was positioned at the center of the difference that fluctuates at the point where the As profile drops sharply. Based on the As profile, the region from the center of the second active layer 249 in the thickness direction to the boundary with another layer (spacer layer) that contacts the n-type pseudo tunnel junction layer 2472 side of the second active layer 249 was defined as the TJ side of the second active layer 249.

[0108]

[0109] The impurity concentration of Si mixed in the second active layer 249 in Examples 1 to 3 is 1.0×10 at the maximum value (peak value) on the n-type pseudo tunnel junction layer 2472 side. １６ atoms / cm ３ or less, and the average value in the entire second active layer 249 is 5.0×10 １５ atoms / cm ３ On the other hand, the impurity concentration of Te mixed in the second active layer 249 of Comparative Example 1 is 1.0×10 or less in most of the second active layer 249. １６ atoms / cm ３Furthermore, in Comparative Example 1, the Te concentration in the barrier layer on the TJ side of the second active layer 249 is 3.3×10 １７ atoms / cm ３ The peak value of the impurity concentration (Si) in the n-type pseudo tunnel junction layer 2472 in Examples 1 to 3 is 1.65 to 1.83×10 １９ cm －３ The peak value of the impurity concentration (Te) in the n-type tunnel junction layer of Comparative Example 1 was 1.48×10 １９ cm －３ The peak value of the impurity concentration in the n-type tunnel junction layer of Comparative Example 1 is lower than the peak value of the impurity concentration in the n-type pseudo tunnel junction layer 2472 of Examples 1 to 3. This is presumably because Te in Comparative Example 1 has migrated toward the second active layer.

[0110] From the results of these SIMS analyses and the measurement results of the output characteristics shown in Table 3, it is believed that when Te is used as the n-type dopant in the tunnel junction layer, the impurity Te diffuses into the second active layer 249, causing a decrease in output. In contrast, when Si is used as the n-type dopant, although the results of Test 1 show that a pseudo-tunnel junction layer behaves differently from a normal tunnel junction, Si does not easily diffuse into the second active layer 249, and therefore a decrease in output is unlikely to occur.

[0111] As described above, by satisfying the conditions of the present invention, it is possible to provide a double-stack semiconductor light-emitting device that has good output characteristics, is capable of reducing leakage current, and is capable of increasing reverse voltage. The pseudo-tunnel junction layer of the present invention behaves in a manner that is clearly different from that of conventional tunnel junction layers.

[0112]

[0113] 100 Double stack type semiconductor light emitting element 105 Growth substrate 120 Semiconductor laminate 140 First n-type semiconductor layer 141 N-type contact layer 142 First n-type cladding layer 144 First active layer 144b Barrier layer of first active layer 144w Well layer of first active layer 145 First electron blocking layer 146 First p-type semiconductor layer 147 Pseudo tunnel junction layer 1471 P-type pseudo tunnel junction layer 1472 N-type pseudo tunnel junction layer 148 Second n-type semiconductor layer 149 Second active layer 149b Barrier layer of second active layer 149w Well layer of second active layer 150 Second p-type semiconductor layer 151 Second electron blocking layer 152 Second p-type cladding layer 153 P-type contact layer 163 P-type contact portion 191 Upper electrode 195 Back electrode 200 Double-stacked semiconductor light-emitting element 205 Growth substrate 220 Semiconductor laminate 240 First n-type semiconductor layer 241 N-type contact layer 242 First n-type cladding layer 244 First active layer 244b Barrier layer of first active layer 244w Well layer of first active layer 245 First electron blocking layer 246 First p-type semiconductor layer 247 Pseudo tunnel junction layer 2471 P-type pseudo tunnel junction layer 2472 N-type pseudo tunnel junction layer 248 Second n-type semiconductor layer 249 Second active layer 249b Barrier layer of second active layer 249w Well layer of second active layer 250 Second p-type semiconductor layer 251 Second electron blocking layer 252 Second p-type cladding layer 253 P-type contact layer 230 Protective film 260 Intermediate electrode layer 261 Dielectric section 263 p-type contact portion 265 electrode portion 270 bonding layer 271 metal reflective layer 279 metal bonding layer 280 support substrate 291 upper electrode 295 back electrode

Claims

1. A semiconductor device comprising, in this order: a first n-type semiconductor layer; an undoped first active layer; a p-type pseudo tunnel junction layer having a p-type dopant; an n-type pseudo tunnel junction layer having an n-type dopant provided in contact with the p-type pseudo tunnel junction layer; an undoped second active layer; and a second p-type semiconductor layer, wherein the maximum impurity concentration of the n-type dopant contained in the second active layer on the n-type pseudo tunnel junction layer side is 1.0×10 １６ atoms / cm ３ A double-stack type semiconductor light-emitting device, characterized in that:

2. A silicon impurity concentration of 5.0×10 is formed between the n-type pseudo tunnel junction layer and the second active layer. １７ atoms / cm ３ Above 5.0 x 10 １８ atoms / cm ３ The double-stack type semiconductor light-emitting device according to claim 1 , further comprising a second n-type semiconductor layer having a thickness of:

3. The average impurity concentration of the n-type dopant contained in the first active layer and the second active layer is 5.0 × 10 １５ atoms / cm ３ The double-stack type semiconductor light-emitting device according to claim 1 , wherein:

4. The double-stack type semiconductor light-emitting device according to claim 1, wherein the n-type dopant doped into the n-type pseudo tunnel junction layer is Si.

5. The double-stack type semiconductor light-emitting device according to claim 1, wherein the p-type dopant doped into the p-type pseudo tunnel junction layer is C.

6. The impurity concentration of the n-type dopant in the n-type pseudo tunnel junction layer is 1.5×10 １９ atoms / cm ３ The double-stack type semiconductor light-emitting device according to claim 1 , wherein:

7. The impurity concentration of the p-type dopant in the p-type pseudo tunnel junction layer is 1.0×10 １９ atoms / cm ３ The double-stack type semiconductor light-emitting device according to claim 1 , wherein:

8. The double-stack semiconductor light-emitting device according to claim 1, wherein the first active layer, the second active layer, and the p-type pseudo tunnel junction layer and the n-type pseudo tunnel junction layer contain AlGaInAs or InGaAsP.

9. The double-stack semiconductor light-emitting device according to claim 1, wherein a current-voltage curve when a current is passed through the p-type pseudo tunnel junction layer and the n-type pseudo tunnel junction layer without passing through the first active layer and the second active layer shows a point where the current reaches a maximum in the range of 0.02 V or more and 0.2 V or less.

10. The double-stack semiconductor light-emitting device according to claim 1, wherein a current-voltage curve when a current is passed through the p-type pseudo tunnel junction layer and the n-type pseudo tunnel junction layer without passing through the first active layer and the second active layer shows a maximum current value of 7 mA or less.

11. A method for fabricating a semiconductor device comprising the steps of: forming a first n-type semiconductor layer on a substrate; forming an undoped first active layer on the first n-type semiconductor layer; forming a p-type pseudo tunnel junction layer having a p-type dopant on the first active layer; directly forming an n-type pseudo tunnel junction layer having an n-type dopant on the p-type pseudo tunnel junction layer; forming an undoped second active layer on the n-type pseudo tunnel junction layer; and forming a second p-type semiconductor layer on the second active layer, wherein the maximum impurity concentration of the n-type dopant contained on the n-type pseudo tunnel junction layer side of the second active layer is 1.0×10 １６ atoms / cm ３ The following describes a method for manufacturing a double-stack semiconductor light-emitting device.

12. A semiconductor device comprising: a support substrate; a junction layer provided on the support substrate; an intermediate electrode layer provided on the junction layer, in which a dielectric portion and an electrode portion are arranged in parallel; a second p-type semiconductor layer provided on the intermediate electrode layer; an undoped second active layer provided on the second p-type semiconductor layer; an n-type pseudo tunnel junction layer having an n-type dopant provided on the second active layer; a p-type pseudo tunnel junction layer having a p-type dopant provided on and in contact with the n-type pseudo tunnel junction layer; an undoped first active layer provided on the p-type pseudo tunnel layer; a first n-type semiconductor layer provided on the first active layer; and an upper electrode provided on the first n-type semiconductor layer, wherein the maximum impurity concentration of the n-type dopant contained on the n-type pseudo tunnel junction layer side of the second active layer is 1.0 x 10 １６ atoms / cm ３ The following is a double-stack type semiconductor light-emitting element.

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