Image sensor, imaging device, and method for controlling image sensor

Abstract

The present invention reduces power consumption while suppressing deterioration in image quality in an image sensor of a column-based analog-to-digital converter (ADC) system.　This image sensor comprises: a determination circuit; a sample holding circuit; and an analog-to-digital converter. The determination circuit determines whether the illuminance of incident light on a pixel is not less than a prescribed threshold value. The sample holding circuit holds a pixel signal generated by the pixel, and attenuates and outputs the held pixel signal when the illuminance is not less than the threshold value. The analog-to-digital converter converts the outputted pixel signal into a digital signal.

Description

Image sensor, imaging device, and method for controlling image sensor

[0001] The present technology relates to an image sensor, and more particularly to an image sensor in which an ADC (Analog to Digital Converter) is arranged for each column, an imaging device, and a method for controlling the image sensor.

[0002] Conventionally, in image sensors and the like, in order to miniaturize pixels, a column ADC system has been used in which an ADC is arranged for each column outside a pixel array unit and pixel signals are read out sequentially, row by row. In this column ADC system, an image sensor has been proposed in which a sample-and-hold circuit for holding pixel signals is provided in front of the ADC for each column (see, for example, Patent Document 1). In this image sensor, the sample-and-hold of reset levels and signal levels and the readout by the ADC are performed in a pipelined manner.

[0003] JP 2009-253930 A

[0004] In the above-described conventional technology, sample-hold and readout are performed in a pipelined manner, thereby increasing the readout speed compared to a system without a sample-hold circuit. However, in the above-described conventional technology, if the power supply voltage of the ADC is reduced to reduce power consumption, the dynamic range and signal-to-noise (SN) ratio may deteriorate, resulting in a degradation of image quality. For this reason, it is difficult to reduce power consumption while suppressing degradation of image quality.

[0005] This technology was developed in light of these circumstances, and aims to reduce power consumption while suppressing degradation in image quality in column ADC type image sensors.

[0006] The present technology has been made to solve the above-mentioned problems, and a first aspect thereof is an image sensor including a determination circuit that determines whether or not the illuminance of light incident on a pixel is below a predetermined threshold, a sample-and-hold circuit that holds a pixel signal generated by the pixel and, if the illuminance is above the threshold, attenuates the held pixel signal and outputs it, and an analog-to-digital converter that converts the output pixel signal into a digital signal, and a control method thereof, which has the effect of reducing power consumption.

[0007] In addition, in this first aspect, the level of the pixel signal includes a reset level when the pixel is initialized and a signal level when a signal charge is transferred within the pixel, the sample-and-hold circuit may include a first capacitive element that holds the reset level, a second capacitive element that holds the signal level, a first input transistor that opens and closes a path between a vertical signal line that transmits the pixel signal and the first capacitive element, a second input transistor that opens and closes a path between the vertical signal line and the second capacitive element, a first output transistor that opens and closes a path between the analog-to-digital converter and the first capacitive element, and a second output transistor that opens and closes a path between the analog-to-digital converter and the second capacitive element, and when the illuminance is higher than the threshold, the determination circuit may control the first output transistor to an on state for a predetermined pulse period by a predetermined control signal within a readout period for reading out the signal level. This results in the effect of connecting the first and second capacitive elements in parallel and attenuating the pixel signal.

[0008] In the first aspect, the capacitance value of the first capacitive element may be different from the capacitance value of the second capacitive element, thereby providing an effect that the pixel signal is attenuated at an attenuation rate according to the ratio of the capacitance values.

[0009] In addition, in this first aspect, the determination circuit may include a first comparator that compares the level of the pixel signal with a predetermined reference level and outputs a comparison result, a latch circuit that holds the comparison result from the first comparator when a readout period of the reset level ends, and a logic gate that generates the control signal based on the comparison result held in the latch circuit. This provides the effect of increasing the readout speed compared to when a comparator in an ADC is used to determine illuminance.

[0010] In this first aspect, the analog-to-digital converter may further include a second comparator that compares the pixel signal output by the sample-and-hold circuit with a predetermined ramp signal and outputs a comparison result, and a counter that counts a count value over a period until the comparison result is inverted, thereby achieving the effect of converting the pixel signal into a digital signal by a single-slope ADC.

[0011] In this first aspect, the determination circuit may further include a latch circuit that holds the comparison result from the second comparator at the end of the reset level read period, and a logic gate that generates the control signal based on the comparison result held in the latch circuit, thereby reducing the number of comparators in the determination circuit.

[0012] In addition, in the first aspect, the image sensor may further include an amplifier that amplifies the pixel signal and outputs the amplified signal to the sample-and-hold circuit, thereby providing an effect of reducing noise.

[0013] In the first aspect, the analog-to-digital converter may be a SAR ADC (Successive Approximation Register Analog to Digital Converter), thereby providing an effect of converting pixel signals into digital signals by a successive approximation method.

[0014] According to a second aspect of the present technology, there is provided an imaging device including: a determination circuit that determines whether or not illuminance of light incident on a pixel falls below a predetermined threshold; a sample-and-hold circuit that holds a pixel signal generated by the pixel and, if the illuminance is not below the threshold, attenuates the held pixel signal and outputs the attenuated pixel signal; an analog-to-digital converter that converts the output pixel signal into a digital signal; and a digital signal processing unit that performs predetermined signal processing on the digital signal, thereby reducing power consumption of the imaging device.

[0015] 1 is a block diagram showing an example of a configuration of an imaging device according to a first embodiment of the present technology. FIG. 2 is a block diagram showing an example of a configuration of an image sensor according to the first embodiment of the present technology. FIG. 3 is a circuit diagram showing an example of a configuration of a pixel according to the first embodiment of the present technology. FIG. 4 is a block diagram showing an example of a configuration of a load MOS (Metal-Oxide-Semiconductor) circuit block and a column signal processing circuit according to the first embodiment of the present technology. FIG. 5 is a circuit diagram showing an example of a configuration of a column signal processing circuit according to the first embodiment of the present technology. FIG. 6 is a circuit diagram showing an example of a configuration of a comparator according to the first embodiment of the present technology. FIG. 7 is a circuit diagram showing an example of a comparator with reduced power consumption according to the first embodiment of the present technology. FIG. 8 is a circuit diagram showing another example of a comparator with reduced power consumption according to the first embodiment of the present technology. FIG. 9 is a timing chart showing an example of a readout operation of an image sensor according to the first embodiment of the present technology. FIG. 10 is a timing chart showing an example of a readout operation of an image sensor in a comparative example. FIG. 11 is a timing chart showing an example of a readout operation at high illuminance according to the first embodiment of the present technology. FIG. 12 is a timing chart showing an example of a readout operation at low illuminance according to the first embodiment of the present technology. FIG. 13 is a diagram for explaining digital correction according to the first embodiment of the present technology. 10 is a flowchart showing an example of operation of an image sensor according to a first embodiment of the present technology. FIG. 11 is a circuit diagram showing an example configuration of a column signal processing circuit according to a second embodiment of the present technology. FIG. 12 is a timing chart showing an example of a readout operation during high illuminance according to the second embodiment of the present technology. FIG. 13 is a timing chart showing an example of a readout operation during low illuminance according to the second embodiment of the present technology. FIG. 14 is a block diagram showing an example configuration of a load MOS circuit block and a column signal processing circuit according to a third embodiment of the present technology. FIG. 15 is a block diagram showing an example configuration of a load MOS circuit block and a column signal processing circuit according to a fourth embodiment of the present technology. FIG. 16 is a circuit diagram showing an example configuration of a sample and hold circuit according to a fifth embodiment of the present technology. FIG. 17 is a block diagram showing an example of a schematic configuration of a vehicle control system. FIG. 18 is an explanatory diagram showing an example of installation positions of an outside-vehicle information detection unit and an imaging unit.

[0016] Hereinafter, modes for implementing the present technology (hereinafter referred to as embodiments) will be described. The description will be made in the following order: 1. First embodiment (an example in which a sample-and-hold circuit attenuates a pixel signal when the illuminance is high) 2. Second embodiment (an example in which a comparator in an ADC is used to determine the illuminance, and the sample-and-hold circuit attenuates a pixel signal when the illuminance is high) 3. Third embodiment (an example in which an amplifier is added, and the sample-and-hold circuit attenuates a pixel signal when the illuminance is high) 4. Fourth embodiment (an example in which a SAR ADC is provided, and the sample-and-hold circuit attenuates a pixel signal when the illuminance is high) 5. Fifth embodiment (an example in which the sample-and-hold circuit attenuates a pixel signal when the illuminance is high, and the ratio of capacitance values ​​in the sample-and-hold circuit is adjusted) 6. Application example to a moving body

[0017] 1 is a block diagram showing an example of the configuration of an imaging device 100 according to a first embodiment of the present technology. The imaging device 100 is a device that captures image data, and includes an imaging lens 110, an image sensor 200, a recording unit 120, and an imaging control unit 130. The imaging device 100 may be a digital camera such as an IoT camera, or an electronic device with an imaging function (such as a smartphone or a personal computer).

[0018] The image sensor 200 captures image data under the control of the imaging control unit 130. The image sensor 200 supplies the image data to the recording unit 120 via a signal line 209.

[0019] The imaging lens 110 focuses light and guides it to the image sensor 200. The imaging control unit 130 controls the image sensor 200 to capture image data. The imaging control unit 130 supplies an imaging control signal including, for example, a vertical synchronization signal VSYNC to the image sensor 200 via a signal line 139. The recording unit 120 records the image data.

[0020] Here, the vertical synchronization signal VSYNC is a signal that indicates the timing of imaging, and a periodic signal with a fixed frequency (such as 60 Hz) is used as the vertical synchronization signal VSYNC.

[0021] It should be noted that although the imaging device 100 records image data, the image data may be transmitted to an external device. In this case, an external interface for transmitting the image data is further provided. Alternatively, the imaging device 100 may further display the image data. In this case, a display unit is further provided.

[0022] 2 is a block diagram showing a configuration example of an image sensor 200 according to the first embodiment of the present technology. The image sensor 200 includes a vertical drive unit 211, a pixel array unit 220, a timing control circuit 212, a DAC (Digital to Analog Converter) 213, a load MOS circuit block 250, and a column signal processing circuit 300. In the pixel array unit 220, a plurality of pixels 230 are arranged in a two-dimensional lattice pattern.

[0023] Hereinafter, a group of pixels 230 arranged in the horizontal direction will be referred to as a "row," and a group of pixels 230 arranged in a direction perpendicular to the rows will be referred to as a "column."

[0024] The timing control circuit 212 controls the operation timing of the vertical drive unit 211 , the DAC 213 , and the column signal processing circuit 300 in synchronization with a vertical synchronization signal VSYNC from the imaging control unit 130 .

[0025] The DAC 213 generates an analog reference signal that varies over time by digital-to-analog (DA) conversion. For example, a sawtooth ramp signal is used as the reference signal. The DAC 213 supplies the generated ramp signal to the column signal processing circuit 300.

[0026] The vertical drive unit 211 sequentially selects and drives rows to output analog pixel signals. The pixels 230 photoelectrically convert incident light to generate analog pixel signals. The pixels 230 supply pixel signals to the column signal processing circuit 300 via the load MOS circuit block 250.

[0027] In the load MOS circuit block 250, a load MOS circuit that supplies a constant current is provided for each column.

[0028] The column signal processing circuit 300 performs signal processing such as AD (Analog to Digital) conversion processing on pixel signals for each column. The column signal processing circuit 300 supplies image data in which the processed signals are arranged to the recording unit 120.

[0029] 3 is a circuit diagram showing an example of the configuration of a pixel 230 according to the first embodiment of the present technology. The pixel 230 includes a photodiode 231, a transfer transistor 232, a reset transistor 233, a floating diffusion layer 234, an amplification transistor 235, and a selection transistor 236. Each transistor in the pixel 230 is, for example, an nMOS (n-channel Metal Oxide Semiconductor) transistor.

[0030] The photodiode 231 photoelectrically converts incident light to generate electric charges. The transfer transistor 232 transfers electric charges from the photodiode 231 to the floating diffusion layer 234 in accordance with a transfer signal TRG from the vertical drive unit 211. The reset transistor 233 initializes the amount of electric charge in the floating diffusion layer 234 in accordance with a reset signal RST from the vertical drive unit 211. The floating diffusion layer 234 accumulates electric charges and generates a voltage according to the amount of electric charge.

[0031] The amplification transistor 235 forms a source follower circuit and outputs a signal at a level corresponding to the voltage of the floating diffusion layer 234. The selection transistor 236 outputs the signal from the amplification transistor 235 as a pixel signal to the load MOS circuit block 250 via the vertical signal line 229 in accordance with a selection signal SEL from the vertical drive unit 211.

[0032] The circuit of the pixel 230 is not limited to the configuration illustrated in the figure, as long as it can generate a pixel signal by photoelectric conversion.

[0033] [Configuration Example of Load MOS Circuit Block and Column Signal Processing Circuit] FIG. 4 is a block diagram showing a configuration example of the load MOS circuit block 250 and the column signal processing circuit 300 according to the first embodiment of the present technology.

[0034] A vertical signal line is wired for each column in the load MOS circuit block 250. If the number of columns is I (I is an integer), then I vertical signal lines 229 are wired. Each vertical signal line 229 is connected to a load MOS circuit 251 that supplies a constant current.

[0035] The column signal processing circuit 300 includes a plurality of determination circuits 310, a plurality of sample-and-hold circuits 320, a plurality of single-slope ADCs 330, and a digital signal processing unit 340. The determination circuits 310, the sample-and-hold circuits 320, and the single-slope ADCs 330 are each provided for each column. The single-slope ADCs 330 are an example of an analog-to-digital converter as defined in the claims.

[0036] The determination circuit 310 determines whether the illuminance of light incident on a pixel falls below a predetermined threshold based on a pixel signal generated by the pixel in the corresponding column. The determination circuit 310 supplies a determination result LO to the digital signal processor 340. The determination circuit 310 also controls the sample-and-hold circuit 320 based on the determination result LO.

[0037] The sample-and-hold circuit 320 holds an analog pixel signal from a corresponding column, and attenuates and outputs the held pixel signal if the illuminance of light incident on that pixel does not fall below a threshold. The voltage input to the sample-and-hold circuit 320 is defined as an input voltage Vi, and the voltage output from the sample-and-hold circuit 320 is defined as an output voltage Vo.

[0038] The single-slope ADC 330 converts the analog pixel signal from the sample-and-hold circuit 320 into a digital signal Do using the ramp signal Rmp from the DAC 213. The single-slope ADC 330 supplies the digital signal Do to the digital signal processing unit 340.

[0039] The digital signal processing unit 340 performs predetermined signal processing on the digital signal Do. This signal processing includes correcting the digital signal based on the determination result LO. The digital signal processing unit 340 supplies image data in which the processed signals are arranged to the recording unit 120.

[0040] 5 is a circuit diagram showing an example of a configuration of the column signal processing circuit 300 according to the first embodiment of the present technology. The determination circuit 310 includes capacitive elements 311 and 312, auto-zero switches 313 and 314, a comparator 315, a latch circuit 316, an AND (logical product) gate 317, and an OR (logical sum) gate 318.

[0041] The sample-and-hold circuit 320 includes input transistors 321 and 322, output transistors 323 and 324, and capacitance elements 325 and 326. The single-slope ADC 330 includes capacitance elements 331 and 332, a comparator 400, and a counter 333. Each transistor in the sample-and-hold circuit 320 is, for example, an nMOS transistor.

[0042] In the determination circuit 310, the comparator 315 compares the level of the pixel signal (i.e., the input voltage Vi) with a predetermined reference level Vref, and outputs the comparison result CO. The reference level Vref is input to a non-inverting input terminal (+) of the comparator 315 via a capacitive element 311. The input voltage Vi is input to an inverting input terminal (-) of the comparator 315 via a capacitive element 312.

[0043] The comparator 315 may have a lower comparison accuracy than the subsequent comparator 400. If the accuracy of the comparator 315 is low, the overhead related to the area and power consumption can be reduced accordingly. Note that the comparator 315 is an example of the first comparator described in the claims.

[0044] Furthermore, if a comparator 315 is used in an existing circuit to determine the presence or absence of sunspots, the comparator 315 can also be used to determine the illuminance, and the only additional circuits required are a latch circuit 316, an AND gate 317, and an OR gate 318.

[0045] The auto-zero switches 313 and 314 short-circuit the input terminal and output terminal of the comparator in accordance with the auto-zero signal az from the timing control circuit 212 .

[0046] The latch circuit 316 holds the comparison result CO in accordance with the enable signal latchen from the timing control circuit 212. When the enable signal latchen is at a high level, the latch circuit 316 updates the held value based on the comparison result CO from the comparator 315. On the other hand, when the enable signal latchen is at a low level, the latch circuit 316 holds its state. The latch circuit 316 also outputs the held value as a determination result LO to the AND gate 317 and the digital signal processing unit 340.

[0047] The AND gate 317 outputs the logical product of the determination result LO and the control signal CAPSHOT from the timing control circuit 212 to the OR gate 318 .

[0048] The OR gate 318 outputs the logical sum of the control signal readp from the timing control circuit 212 and the signal from the AND gate 317 as a control signal read_i to the sample-and-hold circuit 320. This control signal read_i is generated individually for each column. read_i indicates the signal for the i-th column (i is an integer from 1 to I). The AND gate 317 and the OR gate 318 are examples of logic gates defined in the claims.

[0049] In the sample-and-hold circuit 320, the input transistor 321 opens and closes a path between the vertical signal line 229 that transmits a pixel signal and one end of a capacitance element 325 in accordance with a control signal writep from the timing control circuit 212. The other end of the capacitance element 325 is grounded. The input transistor 321 is an example of a first input transistor as defined in the claims.

[0050] The input transistor 322 opens and closes a path between the vertical signal line 229 and one end of the capacitance element 326 in accordance with a control signal written from the timing control circuit 212. The other end of the capacitance element 326 is grounded. The input transistor 322 is an example of a second input transistor as defined in the claims.

[0051] The capacitance element 325 holds a P-phase level, which is the level at which the pixel is initialized. This P-phase level is also called a reset level. The capacitance element 325 is an example of a first capacitance element described in the claims.

[0052] The capacitance element 326 holds a D-phase level, which is the level when the signal charge is transferred within the pixel. This D-phase level is also called a signal level. The capacitance element 326 is an example of a second capacitance element described in the claims.

[0053] The output transistor 323 opens and closes a path between one end of the capacitive element 325 and the input terminal of the single-slope ADC 330 in accordance with a control signal read_i. The output transistor 323 is an example of a first output transistor as defined in the claims.

[0054] The output transistor 324 opens and closes a path between one end of the capacitive element 326 and the input terminal of the single-slope ADC 330 in accordance with a control signal read from the timing control circuit 212. The output transistor 324 is an example of a second output transistor as defined in the claims.

[0055] When the P-phase level (i.e., reset level) is generated, the timing control circuit 212 controls the input transistor 321 to be in the ON state by the control signal writep. As a result, the reset level is sampled and held in the capacitive element 325.

[0056] Then, the timing control circuit 212 controls the D-phase side input transistor 322 to the ON state by the control signal written during the reset level read period, and controls the P-phase side output transistor 323 to the ON state by the control signal readp. As a result, the reset level is read, and the D-phase level (i.e., the signal level) is sampled and held.

[0057] Then, the timing control circuit 212 controls the D-phase side output transistor 324 to be in an ON state using the control signal read within the signal level read period.

[0058] If the illuminance does not fall below the threshold, the determination circuit 310 controls the P-phase output transistor 323 to be in the on state for a predetermined pulse period using the control signal read_i during the signal level read period. At this time, the D-phase output transistor 324 is also in the on state, so one end of each of the capacitive elements 325 and 326 is shorted, and these capacitive elements are connected in parallel to the single-slope ADC 330. This attenuates the pixel signal compared to when only the capacitive element 326 is connected. For example, the capacitance values ​​of the capacitive elements 325 and 326 are the same. In this case, the attenuation rate is 1 / 2.

[0059] On the other hand, when the illuminance is less than the threshold value, the output transistor 323 on the P-phase side is controlled to be in the off state during the signal level readout period.

[0060] Due to the attenuation of pixel signals at high illuminance, it is possible to narrow the input range of the downstream single-slope ADC 330 and the output range of the DAC 213. Therefore, it is possible to lower the voltage of the single-slope ADC 330 and the like, thereby reducing their power consumption.

[0061] If the voltage of an ADC (such as the single-slope ADC 330) were simply lowered without attenuating the pixel signal, the range of the ADC or DAC would be reduced more than necessary, deteriorating the dynamic range and S / N ratio and resulting in a deterioration in image quality. However, in the first embodiment, the pixel signal is attenuated and then the voltage of the ADC or the like is lowered, thereby suppressing the deterioration in image quality.

[0062] In the single-slope ADC 330, the comparator 400 compares the ramp signal Rmp with the pixel signal output by the sample-and-hold circuit 320, and outputs the comparison result Co to the counter 333. The ramp signal Rmp is input to the non-inverting input terminal (+) of the comparator 400 via a capacitance element 331. The output voltage Vo is input to the inverting input terminal (-) of the comparator 400 via a capacitance element 332. In addition, the auto-zero signal AZ from the timing control circuit 212 is input to the comparator 400.

[0063] The counter 333 counts the count value over a period until the comparison result Co is inverted. The counter 333 outputs a digital signal Do indicating the count value to the digital signal processing unit 340.

[0064] For example, the counter 333 counts down during the readout period of the reset level and counts up during the readout period of the signal level. This allows for correlated double sampling (CDS) processing to determine the difference between the reset level and the signal level. Alternatively, the single-slope ADC 330 may perform only AD conversion, and the downstream digital signal processor 340 may perform CDS processing.

[0065] 6 is a circuit diagram showing an example of the configuration of the comparator 400 according to the first embodiment of the present technology. The comparator 400 includes pMOS transistors 411 and 412, auto-zero switches 413 and 414, and nMOS transistors 415, 415, and 417. The circuit configuration of the front-stage comparator 315 used to determine the illuminance is assumed to be the same as that of the comparator 400, for example. Note that the circuit configuration of the comparator 315 may be different from that of the comparator 400.

[0066] The pMOS transistors 411 and 412 are connected in parallel to a power supply voltage. The gate of the pMOS transistor 411 is connected to its own drain and to the gate of the pMOS transistor 412. These transistors function as a current mirror circuit.

[0067] The nMOS transistors 415 and 416 are connected in parallel between the current mirror circuit and the nMOS transistor 417. The ramp signal Rmp is input to the gate of the nMOS transistor 415 via a capacitance element 331. The output voltage Vo is input to the gate of the nMOS transistor 416 via a capacitance element 332.

[0068] Furthermore, the level of the ramp signal Rmp gradually decreases during the readout period of the reset level and the signal level.

[0069] The auto-zero switch 413 short-circuits the connection point between the pMOS transistor 411 and the nMOS transistor 415 and the gate of the nMOS transistor 415 in accordance with the auto-zero signal AZ.

[0070] The auto-zero switch 414 short-circuits the connection point between the pMOS transistor 412 and the nMOS transistor 416 and the gate of the nMOS transistor 416 in accordance with the auto-zero signal AZ.

[0071] A predetermined bias voltage Vbias is applied to the gate of the nMOS transistor 417. This nMOS transistor 417 functions as a tail current source.

[0072] The voltage at the connection point between the pMOS transistor 412 and the nMOS transistor 416 is output to the counter 333 as the comparison result Co.

[0073] The circuit configuration of the comparator 400 is not limited to the circuit shown in the figure, as long as it can compare the ramp signal Rmp with the output voltage Vo.

[0074] 7, in the comparator 400, one end of each of the capacitance elements 331 and 332 can be commonly connected to the gate of the nMOS transistor 415. In this case, the gate of the nMOS transistor 416 is connected to the capacitance element 418, and a constant voltage is applied to it. In the circuit configuration shown in the figure, a ramp signal Rmp having a waveform whose level gradually rises during the readout period of the reset level or signal level is input.

[0075] 8, an LDO (Low Dropout) 420, an nMOS transistor 431, and a current source 432 can be arranged in a comparator 400. The LDO 420 includes an nMOS transistor 421 and a capacitance element 422.

[0076] The nMOS transistor 421 and the nMOS transistor 431 are connected in series between a power supply voltage and a current source 432. The capacitance element 422 is connected to the gate of the nMOS transistor 421.

[0077] One end of each of the capacitance elements 331 and 332 is commonly connected to the gate of the nMOS transistor 431. The voltage at the connection point between the nMOS transistor 431 and the current source 432 is output to the counter 333 as the comparison result Co.

[0078] In the circuit illustrated in the figure, a ramp signal Rmp having a waveform whose level gradually rises during the readout period of the reset level or signal level is also input.

[0079] The circuit configurations shown in FIGS. 7 and 8 can reduce the power supply voltage compared to the general differential amplifier circuit shown in FIG.

[0080] 9 is a timing chart showing an example of a readout operation of the image sensor 200 according to the first embodiment of the present technology. Here, exposure control of the image sensor 200 is performed by, for example, a rolling shutter method. Note that exposure control by a global shutter method can also be performed by adding an analog memory within the pixel.

[0081] During the period from timing T1 to T2, pixels in row j (j is an integer) are initialized and a reset level is generated. During the period from timing T3 to timing T4 after the settling period has elapsed, the sample and hold circuit 320 samples and holds the reset level. In the figure, "rst" indicates pixel initialization, and "spl" indicates sample and hold by the sample and hold circuit 320.

[0082] The timing control circuit 212 sets the control signals writep and read to high level during the period from timing T1 to T4. During this period, the reset level of the jth row is sampled and held, and the signal level of the (j-1)th row is read out.

[0083] During the period from timing T4 to timing T5 when exposure of row j is completed, signal charges are transferred within the pixels of that row, and a signal level is generated. "tx" in the figure indicates the transfer of signal charges. During the period from timing T6 to timing T7 after the settling period has elapsed, the sample-and-hold circuit 320 samples and holds the signal level.

[0084] The single-slope ADC 330 starts auto-zeroing at timing T4 and reads out the P-phase level (reset level) during the period from timing T5 to T6. In the figure, "AZ" indicates the auto-zero operation of the comparator 400 in the single-slope ADC 330, and "P-count" indicates the AD conversion (i.e., reading) of the reset level. The level of the ramp signal Rmp gradually decreases over the period in which the reset level is read out.

[0085] The timing control circuit 212 also sets the control signals writep and read to low level at timing T4, and sets the control signals readp and written to high level during the period from immediately after timing T4 to timing T7. During this period, the reset level of row j is read out, and the signal level of row j is sampled and held.

[0086] Then, during the period from timing T7 to timing T8, the pixels in the next (j+1)th row are initialized and a reset level is generated. During the period from timing T9 to timing T10 after the settling period has elapsed, the sample-and-hold circuit 320 samples and holds the reset level.

[0087] The single-slope ADC 330 also reads out the D-phase level (signal level) during the period from timing T8 to T10. "D-count" in the figure indicates the reading of the signal level. The level of the ramp signal Rmp gradually decreases over the signal level reading period.

[0088] The timing control circuit 212 also sets the control signals readp and written to low level at timing T7, and sets the control signal writep to high level during the period from timing T7 to timing T10. The timing control circuit 212 also sets the control signal read to high level during the period from immediately after timing T7 to immediately after timing T10. During this period, the signal level of row j is read out, and the reset level of row (j+1) is sampled and held.

[0089] Then, the reset level of the (j+1)th row is read out, and the signal level of the (j+1)th row is sampled and held.

[0090] As shown in the figure, the sample and hold of the reset level of row j and the readout of the signal level of row (j-1) are executed in parallel, and the readout of the reset level of row j and the sample and hold of the signal level of row j are executed in parallel. Then, the readout of the signal level of row j and the sample and hold of the reset level of row (j+1) are executed in parallel. In this way, the readout of the reset level and signal level, and the sample and hold are executed in a pipelined manner. For example, the period from timing T4 to timing T10 corresponds to the AD period for one row.

[0091] Here, a configuration in which the sample-and-hold circuit 320 is not provided will be considered as a comparative example.

[0092] 10 is a timing chart showing an example of a readout operation of an image sensor in a comparative example. In this comparative example, the pixels in row j are initialized and a reset level is generated during the period from timing T1 to T2. The single-slope ADC 330 performs auto-zero during the period from timing T2 to T3, and reads out the P-phase level (reset level) of row j during the period from timing T4 to T5 after the settling period has elapsed.

[0093] Then, during the period from timing T5 to timing T6 when exposure ends, the signal charges are transferred within the pixels of row j, and a signal level is generated. The single-slope ADC 330 reads out the D-phase level (signal level) of row j during the period from timing T7 to timing T8 after the settling period has elapsed.

[0094] As illustrated in the figure, in the comparative example without the sample-and-hold circuit 320, the reset level and signal level of the jth row are read out in order, and then the reset level and signal level of the (j+1)th row are read out in order.

[0095] 9 and 10, in FIG. 10, which does not include the sample-and-hold circuit 320, the D-phase level is read after a settling period has elapsed after the P-phase level has been read. In contrast, in FIG. 9, which uses a pipelined system including the sample-and-hold circuit 320, the single-slope ADC 330 can read the D-phase level within the settling period. In this way, the pipelined system can improve the readout speed.

[0096] Next, the readout operation at high illuminance where the illuminance does not fall below the threshold and at low illuminance where the illuminance is below the threshold will be described with reference to Figures 11 and 12. Figures 11 and 12 show details of the readout operation during the period from timing T1 to T10 in Figure 9.

[0097] FIG. 11 is a timing chart showing an example of a readout operation under high illuminance in the first embodiment of the present technology.

[0098] As shown in the figure, during the period from timing T1 to t11, the timing control circuit 212 supplies a high-level auto-zero signal az. The front-stage comparator 315 for determining the illuminance performs auto-zero in accordance with the auto-zero signal az.

[0099] During the period from timing T1 to T4, the timing control circuit 212 sets the control signals writep and read to high level, and the reset level is sampled and held during this period.

[0100] At timing t12, immediately after timing T4, the signal charge is transferred, and the input voltage Vi of the vertical signal line 229 decreases. The input voltage Vi before the decrease indicates the reset level, and the input voltage Vi after the decrease indicates the signal level. The difference ΔVvsl between the reset level and the signal level (in other words, the amplitude) indicates the value of the net pixel signal after CDS.

[0101] Furthermore, the reference level Vref also decreases after timing t12. ΔVref, which is the difference between the initial level of the reference level Vref and the level after the decrease, is a value according to the threshold value used to determine the illuminance. If Δvsl is equal to or greater than ΔVref, the illuminance is determined to be high illuminance that does not fall below the threshold value.

[0102] In the case of high illuminance, the comparator 315 outputs a high level comparison result CO after timing t12. The gray areas in the figure indicate that the value of the comparison result CO is irrelevant.

[0103] The timing control circuit 212 outputs a high-level enable signal latchen during the period from timing t13 to T7, thereby updating the value held in the latch circuit 316 with the comparison result CO, and after timing T7, the latch circuit 316 outputs a high-level determination result LO.

[0104] Furthermore, the timing control circuit 212 sets the control signals writep and read to low level at timing T4. During the period from timing t12 to T7, the timing control circuit 212 sets the control signal readp to high level, and the determination circuit 310 for the i-th column sets the control signal readp_i to high level. During this period, the reset level is read out.

[0105] During the period from immediately after timing t12 to immediately before timing T7, the timing control circuit 212 sets the control signal written to high level, and the signal level is sampled and held during this period.

[0106] Then, during the period from timing T7 to T10, the timing control circuit 212 sets the control signal writep to high level.

[0107] Furthermore, the timing control circuit 212 supplies a high-level control signal "capshot" from timing t14 throughout the pulse period. Based on this control signal and the determination result "LO," the determination circuit 310 for column i outputs a high-level control signal "readp_i" from timing t14 throughout the pulse period. This control signal shorts one end of each of the capacitance elements 325 and 326, connecting these capacitance elements in parallel. This attenuates the amplitude of the output voltage "Vo" from the sample-and-hold circuit 320 (in other words, the pixel signal "Δvsl"). This narrows the range of the single-slope ADC 330 and the DAC 213, making it possible to reduce power consumption while suppressing degradation in image quality.

[0108] After the pulse period has elapsed, the control signal readp_i returns to a low level, releasing one end of the capacitive element 331 for the next reset level sample.

[0109] Furthermore, the timing control circuit 212 sets the control signal readp to low level at timing T7, and sets the control signal readd to high level during the period from timing T7 to timing T10, during which the signal level is read out.

[0110] 12 is a timing chart showing an example of a read operation at low illuminance according to the first embodiment of the present technology. Differences from the read operation at high illuminance will be described.

[0111] In the case of low illuminance, the comparator 315 outputs a low-level comparison result CO after timing t12, and then outputs a low-level determination result LO from the latch circuit 316 after timing T7.

[0112] Furthermore, from timing t14 throughout the pulse period, the timing control circuit 212 supplies a high-level control signal CAPSHOT. Based on this control signal and the low-level determination result LO, the determination circuit 310 for column i keeps the control signal READP_I at a low level after timing t14. As a result, only the D-phase side capacitive element 326 is connected to the single-slope ADC 330, so the amplitude of the output voltage VO (pixel signal ΔVS1) is not attenuated and is output as is. Therefore, it is possible to maintain noise characteristics at low illuminance levels equivalent to those of the comparative example.

[0113] Fig. 13 is a diagram for explaining digital correction according to the first embodiment of the present technology. The vertical axis in the figure indicates an output value, which is a digital signal value, converted into LSB (Least Significant Bit). The horizontal axis in the figure indicates a signal amount indicated by an analog pixel signal. Furthermore, thin diagonal lines indicate characteristics of a digital signal in the case of low illuminance. A thick line indicates characteristics of a digital signal before correction in the case of high illuminance. A rough dotted line indicates characteristics of a digital signal after correction in the case of high illuminance.

[0114] As illustrated in the figure, in the case of high illuminance, the analog pixel signal is attenuated, so the slope of the output value relative to the signal amount is smaller than in the case of low illuminance. Therefore, the digital signal processing unit 340 determines whether the illuminance is high for each column based on the determination result LO of the determination circuit 310, and in the case of high illuminance, it is necessary to perform correction by multiplying the output value by a digital gain corresponding to the attenuation rate. When multiplied by the digital gain, the quantization noise of the comparator 400, DAC 213, and counter 333 is amplified, but in the case of high illuminance, optical shot noise is dominant. Therefore, even if the quantization noise generated by the circuit increases, its impact on the overall noise is negligible.

[0115] 14 is a flowchart showing an example of the operation of the image sensor 200 according to the first embodiment of the present technology. This operation is started, for example, when a predetermined application for capturing image data is executed.

[0116] The vertical driver 211 in the image sensor 200 selects a row and starts exposure of the selected row (step S901). Then, just before the end of exposure, the single-slope ADC 330 reads the reset level (step S902). The determination circuit 310 for the i-th column determines whether the illuminance is high enough not to fall below a threshold (step S903).

[0117] If the illuminance is high (step S903: Yes), the sample-and-hold circuit 320 of the i-th column attenuates the signal level (step S904). On the other hand, if the illuminance is low (step S903: No), the signal level is not attenuated. Then, the single-slope ADC 330 reads the signal level (step S905). Note that steps S903 and S904 are performed in parallel for each column.

[0118] Based on the determination result for each column, the digital signal processor 340 performs correction using a digital gain on the digital signals of the columns with high illuminance (step S906).

[0119] The image sensor 200 determines whether or not the readout of all rows has been completed (step S907). If the readout of all rows has not been completed (step S907: No), the image sensor 200 repeatedly executes step S901 and subsequent steps. If the readout of all rows has been completed (step S907: Yes), the image sensor 200 ends the operation for image capture.

[0120] When data for a plurality of images is to be read out successively, steps S901 to S907 are repeatedly executed in synchronization with the vertical synchronization signal VSYNC.

[0121] As described above, according to the first embodiment of the present technology, the determination circuit 310 determines whether or not the illuminance is high, and when the illuminance is high, the sample-and-hold circuit 320 attenuates the pixel signal, thereby narrowing the input range of the single-slope ADC 330. This allows the single-slope ADC 330 to operate at a lower voltage, thereby reducing its power consumption.

[0122] 2. Second Embodiment In the first embodiment described above, the comparator 315 for determining illuminance is provided before the comparator 400 in the single-slope ADC 330. However, it is preferable to further reduce the circuit size. The image sensor 200 in this second embodiment differs from the first embodiment in that it determines illuminance based on the comparison result of the comparator 400 in the single-slope ADC 330.

[0123] 15 is a circuit diagram showing a configuration example of a column signal processing circuit 300 according to a second embodiment of the present technology. The column signal processing circuit 300 according to the second embodiment differs from the first embodiment in that the capacitive elements 311 and 312, the auto-zero switches 313 and 324, and the comparator 315 are eliminated.

[0124] The comparator 400 in the single-slope ADC 330 of the second embodiment outputs the comparison result Co to the counter 333 and the latch circuit 316 .

[0125] As shown in the figure, the determination circuit 310 determines whether or not the illuminance is high based on the comparison result Co of the comparator 400 in the single-slope ADC 330, so that the comparator 315 and the like can be eliminated.

[0126] 16 is a timing chart showing an example of a readout operation under high illuminance conditions according to the second embodiment of the present technology. During the period from timing t11 to timing t12 immediately after timing T4, the timing control circuit 212 supplies a high-level auto-zero signal AZ. The comparator 400 in the single-slope ADC 330 performs auto-zeroing in accordance with the auto-zero signal AZ.

[0127] When Δvsl is a high illuminance equal to or greater than ΔVref, the comparator 400 outputs a high-level comparison result Co. In the second embodiment, the difference between the level of the ramp signal Rmp during auto-zero and the level at the time of illuminance determination corresponds to ΔVref. Note that the level at the time of determination can be set to any value and is not limited to the level at the end of reading the P-phase level.

[0128] Then, the timing control circuit 212 outputs a high-level enable signal latchen during the period from timing t13 to t14. The decision circuit 310 holds the comparison result Co in accordance with the enable signal, and outputs a high-level decision result LO after timing t14.

[0129] From timing t15 through the pulse period, the timing control circuit 212 supplies a high-level control signal, "capshot." Based on this control signal and the determination result, "LO," the determination circuit 310 for the i-th column outputs a high-level control signal, "readp_i," from timing t15 through the pulse period. This control signal attenuates the amplitude of the output voltage, "Vo." Then, AD conversion (in other words, reading) of the signal level is performed.

[0130] 17 is a timing chart showing an example of a read operation at low illuminance according to the second embodiment of the present technology. In the case of low illuminance, the comparator 400 outputs a comparison result Co at a low level.

[0131] The timing control circuit 212 then outputs a high-level enable signal latchen during the period from timing t13 to t14. The decision circuit 310 holds the comparison result Co in accordance with the enable signal, and outputs a low-level decision result LO after timing t14.

[0132] From timing t15 through the pulse period, the timing control circuit 212 supplies a high-level control signal CAPSHOT. Based on this control signal and the determination result LO, the determination circuit 310 for the i-th column keeps the control signal READP_I at a low level after timing t15. This prevents the amplitude of the output voltage VO from being attenuated and outputs it as is. Then, AD conversion (reading) of the signal level is performed.

[0133] 15, in the second embodiment, it is possible to eliminate the comparator 315. However, it should be noted that the column signal processing circuit 300 of the second embodiment needs to sequentially perform the determination of illuminance and the AD conversion of the signal level as shown in FIGS. 16 and 17, and therefore the AD conversion time is slightly longer than in the first embodiment.

[0134] As described above, according to the second embodiment of the present technology, the determination circuit 310 determines whether or not the illuminance is high based on the comparison result of the comparator 400 in the single-slope ADC 330, so that the comparator 315 can be eliminated.

[0135] 3. Third Embodiment In the first embodiment described above, the sample-and-hold circuit 320 samples the pixel signals as they are, but it is preferable to further reduce noise. The image sensor 200 in this third embodiment differs from the first embodiment in that an amplifier is added that amplifies the pixel signals and outputs them to the sample-and-hold circuit 320.

[0136] 18 is a block diagram showing a configuration example of a load MOS circuit block 250 and a column signal processing circuit 300 according to the third embodiment of the present technology. The column signal processing circuit 300 according to the third embodiment differs from the first embodiment in that an amplifier 350 is further provided for each column.

[0137] The amplifier 350 amplifies the pixel signal from the vertical signal line 229 and outputs it to the sample-and-hold circuit 320 and the determination circuit 310. This amplification reduces the input-equivalent value of noise generated in subsequent circuits, thereby enabling further noise reduction.

[0138] The second embodiment can be applied to the third embodiment.

[0139] As described above, according to the third embodiment of the present technology, the amplifier 350 that amplifies the pixel signal and outputs the amplified pixel signal to the sample-and-hold circuit 320 is added, so that noise can be further reduced.

[0140] 4. Fourth Embodiment In the first embodiment described above, the single-slope ADC 330 is used for AD conversion, but other types of ADCs can also be used. The image sensor 200 in this fourth embodiment differs from the first embodiment in that it uses a SAR ADC instead of the single-slope ADC 330.

[0141] 19 is a block diagram showing a configuration example of a load MOS circuit block 250 and a column signal processing circuit 300 according to a fourth embodiment of the present technology. The column signal processing circuit 300 according to the fourth embodiment differs from the first embodiment in that a SAR ADC 335 is arranged for each column instead of the single-slope ADC 330.

[0142] It should be noted that an ADC other than the single slope ADC 330 or the SAR ADC 335, such as a ΔΣ ADC, can also be used as long as it is capable of performing AD conversion.

[0143] Moreover, the third embodiment can also be applied to the fourth embodiment.

[0144] As described above, according to the fourth embodiment of the present technology, the SAR ADC 335 is arranged instead of the single-slope ADC 330, and therefore AD conversion can be performed by the successive approximation method.

[0145] 5. Fifth Embodiment In the first embodiment described above, the capacitance values ​​of the capacitance elements 325 and 326 in the sample-and-hold circuit 320 are the same, but these capacitance values ​​can also be adjusted according to the attenuation rate. Image sensor 200 in this fifth embodiment differs from the first embodiment in that the capacitance value of capacitance element 325 is different from that of capacitance element 326.

[0146] 20 is a circuit diagram showing a configuration example of a sample-and-hold circuit 320 according to a fifth embodiment of the present technology. The sample-and-hold circuit 320 according to the fifth embodiment differs from the first embodiment in that the capacitance value of the capacitive element 325 is different from that of the capacitive element 326.

[0147] For example, the capacitance value of the capacitance element 325 on the P-phase side is set to G (G is a real number greater than 1) times that of the capacitance element 326 on the D-phase side. In this case, the attenuation factor at high illuminance is 1 / (1+G). In this way, the ratio of the capacitance values ​​of the capacitance elements 325 and 326 is adjusted according to the attenuation factor to be set.

[0148] It should be noted that the second, third, and fourth embodiments can each be applied to the fifth embodiment.

[0149] As described above, according to the fifth embodiment of the present technology, since the capacitance value of the capacitive element 325 is different from that of the capacitive element 326, the sample-and-hold circuit 320 can attenuate the pixel signal at an attenuation rate according to the ratio between them.

[0150] 6. Application Examples to Mobile Bodies The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may be realized as a device mounted on any type of mobile body, such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, personal mobility, an airplane, a drone, a ship, or a robot.

[0151] FIG. 21 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile object control system to which the technology according to the present disclosure can be applied.

[0152] The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. In the example shown in Fig. 21 , the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside-vehicle information detection unit 12030, an inside-vehicle information detection unit 12040, and an integrated control unit 12050. Also shown as functional components of the integrated control unit 12050 are a microcomputer 12051, an audio / video output unit 12052, and an in-vehicle network I / F (Interface) 12053.

[0153] The drivetrain control unit 12010 controls the operation of devices related to the drivetrain of the vehicle in accordance with various programs. For example, the drivetrain control unit 12010 functions as a control device for a drive force generating device for generating a drive force of the vehicle, such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating a braking force of the vehicle.

[0154] The body system control unit 12020 controls the operation of various devices equipped in the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as headlamps, backup lamps, brake lamps, turn signals, and fog lamps. In this case, radio waves transmitted from a portable device that serves as a key or signals from various switches can be input to the body system control unit 12020. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door lock device, power window device, lamps, etc.

[0155] The outside-vehicle information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the outside-vehicle information detection unit 12030. The outside-vehicle information detection unit 12030 causes the imaging unit 12031 to capture images outside the vehicle and receives the captured images. The outside-vehicle information detection unit 12030 may perform object detection processing or distance detection processing for people, cars, obstacles, signs, characters on the road surface, etc. based on the received images.

[0156] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0157] The in-vehicle information detection unit 12040 detects information inside the vehicle. For example, a driver state detection unit 12041 that detects the state of the driver is connected to the in-vehicle information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 may calculate the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041, or may determine whether the driver is dozing off.

[0158] The microcomputer 12051 can calculate control target values ​​for the driving force generating device, steering mechanism, or braking device based on the information inside and outside the vehicle acquired by the outside-vehicle information detection unit 12030 or the inside-vehicle information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing the functions of an ADAS (Advanced Driver Assistance System), including vehicle collision avoidance or impact mitigation, following driving based on the distance between vehicles, maintaining vehicle speed, vehicle collision warning, vehicle lane departure warning, etc.

[0159] In addition, the microcomputer 12051 can perform cooperative control for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on driver operation, by controlling the driving force generating device, steering mechanism, braking device, etc. based on information about the surroundings of the vehicle obtained by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040.

[0160] Furthermore, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information outside the vehicle acquired by the outside information detection unit 12030. For example, the microcomputer 12051 can control the headlamps according to the position of a preceding vehicle or an oncoming vehicle detected by the outside information detection unit 12030, and perform cooperative control aimed at preventing glare, such as switching from high beams to low beams.

[0161] The audio / video output unit 12052 transmits at least one of audio and video output signals to an output device capable of visually or audibly notifying the passengers of the vehicle or the outside of the vehicle of information. In the example of Fig. 21, the output devices are exemplified by an audio speaker 12061, a display unit 12062, and an instrument panel 12063. The display unit 12062 may include, for example, at least one of an on-board display and a head-up display.

[0162] FIG. 22 is a diagram showing an example of the installation position of the imaging unit 12031.

[0163] In FIG. 22, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.

[0164] The imaging units 12101, 12102, 12103, 12104, and 12105 are provided, for example, at positions such as the front nose, side mirrors, rear bumper, back door, and the top of the windshield inside the vehicle cabin of the vehicle 12100. The imaging unit 12101 provided on the front nose and the imaging unit 12105 provided on the top of the windshield inside the vehicle cabin mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 provided on the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 provided on the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The imaging unit 12105 provided on the top of the windshield inside the vehicle cabin is mainly used to detect preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, etc.

[0165] 22 shows an example of the imaging ranges of the imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of the imaging unit 12104 provided on the rear bumper or back door. For example, by overlaying the image data captured by the imaging units 12101 to 12104, an overhead image of the vehicle 12100 viewed from above can be obtained.

[0166] At least one of the image capturing units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the image capturing units 12101 to 12104 may be a stereo camera made up of multiple image capturing elements, or may be an image capturing element having pixels for phase difference detection.

[0167] For example, based on the distance information obtained from the imaging units 12101 to 12104, the microcomputer 12051 can calculate the distance to each three-dimensional object within the imaging ranges 12111 to 12114 and the change in this distance over time (relative speed with respect to the vehicle 12100), thereby extracting as a preceding vehicle, in particular, the three-dimensional object that is the closest three-dimensional object on the path of the vehicle 12100 and traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (e.g., 0 km / h or higher). Furthermore, the microcomputer 12051 can set a vehicle-to-vehicle distance to be maintained in advance in front of the preceding vehicle, and perform automatic braking control (including follow-up stop control), automatic acceleration control (including follow-up start control), etc. In this way, cooperative control can be performed for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on driver operation.

[0168] For example, the microcomputer 12051 classifies and extracts three-dimensional object data regarding three-dimensional objects into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on distance information obtained from the imaging units 12101 to 12104, and can use the data for automatic obstacle avoidance. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. The microcomputer 12051 then determines a collision risk that indicates the risk of collision with each obstacle, and when the collision risk is equal to or greater than a set value and a collision is possible, the microcomputer 12051 can provide driving assistance for collision avoidance by outputting an alarm to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or avoidance steering via the drive system control unit 12010.

[0169] At least one of the image capturing units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether a pedestrian is present in the images captured by the image capturing units 12101 to 12104. Such pedestrian recognition is performed, for example, by extracting feature points from the images captured by the image capturing units 12101 to 12104 as infrared cameras and performing pattern matching on a series of feature points that indicate the outline of an object to determine whether the object is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the images captured by the image capturing units 12101 to 12104 and recognizes the pedestrian, the audio / image output unit 12052 controls the display unit 12062 to superimpose a rectangular outline on the recognized pedestrian for emphasis. The audio / image output unit 12052 may also control the display unit 12062 to display an icon or the like indicating the pedestrian at a desired position.

[0170] An example of a vehicle control system to which the technology according to the present disclosure can be applied has been described above. The technology according to the present disclosure can be applied to, for example, the image capturing unit 12031 of the above-described configuration. Specifically, the image capturing device 100 of FIG. 1 can be applied to the image capturing unit 12031. By applying the technology according to the present disclosure to the image capturing unit 12031, it is possible to reduce the power consumption of the system while suppressing degradation in image quality.

[0171] Note that the above-described embodiment shows an example for realizing the present technology, and the matters in the embodiment and the matters specifying the invention in the claims correspond to each other. Similarly, the matters specifying the invention in the claims and the matters in the embodiment of the present technology having the same name correspond to each other. However, the present technology is not limited to the embodiment, and can be realized by applying various modifications to the embodiment within the scope of the gist thereof.

[0172] The effects described in this specification are merely examples and are not limiting, and other effects may also be obtained.

[0173] The present technology can also be configured as follows: (1) An image sensor including: a determination circuit that determines whether or not the illuminance of light incident on a pixel is below a predetermined threshold, a sample-and-hold circuit that holds a pixel signal generated by the pixel and, if the illuminance is above the threshold, attenuates the held pixel signal and outputs it, and an analog-to-digital converter that converts the output pixel signal into a digital signal. (2) The image sensor according to (1), wherein the level of the pixel signal includes a reset level when the pixel is initialized and a signal level when a signal charge is transferred within the pixel, and the sample-and-hold circuit comprises: a first capacitive element that holds the reset level, a second capacitive element that holds the signal level, a first input transistor that opens and closes a path between a vertical signal line that transmits the pixel signal and the first capacitive element, a second input transistor that opens and closes a path between the vertical signal line and the second capacitive element, a first output transistor that opens and closes a path between the analog-to-digital converter and the first capacitive element, and a second output transistor that opens and closes a path between the analog-to-digital converter and the second capacitive element, and when the illuminance is higher than the threshold, the determination circuit controls the first output transistor to an on state for a predetermined pulse period by a predetermined control signal within a readout period for reading out the signal level. (3) The image sensor according to (2), wherein the capacitance value of the first capacitive element is different from that of the second capacitive element. (4) The image sensor according to (2) or (3), wherein the determination circuit comprises: a first comparator that compares the level of the pixel signal with a predetermined reference level and outputs a comparison result; a latch circuit that holds the comparison result from the first comparator at the end of the readout period of the reset level; and a logic gate that generates the control signal based on the comparison result held in the latch circuit.(5) The image sensor according to (2), wherein the analog-to-digital converter comprises: a second comparator that compares the pixel signal output by the sample-and-hold circuit with a predetermined ramp signal and outputs a comparison result; and a counter that counts a count value over a period until the comparison result is inverted. (6) The image sensor according to (5), wherein the determination circuit comprises: a latch circuit that holds the comparison result from the second comparator at the end of a readout period of the reset level; and a logic gate that generates the control signal based on the comparison result held in the latch circuit. (7) The image sensor according to any one of (1) to (6), further comprising an amplifier that amplifies the pixel signal and outputs it to the sample-and-hold circuit. (8) The image sensor according to (1), wherein the analog-to-digital converter is a SAR ADC (Successive Approximation Register Analog to Digital Converter). (9) An imaging device comprising: a determination circuit that determines whether the illuminance of light incident on a pixel is below a predetermined threshold, a sample-and-hold circuit that holds a pixel signal generated by the pixel and, if the illuminance is below the threshold, attenuates the held pixel signal before outputting it, an analog-to-digital converter that converts the output pixel signal into a digital signal, and a digital signal processing unit that performs predetermined signal processing on the digital signal. (10) A control method for an image sensor, comprising: a determination procedure that determines whether the illuminance of light incident on a pixel is below a predetermined threshold, a sample-and-hold procedure that holds the pixel signal generated by the pixel by a sample-and-hold circuit, and, if the illuminance is above the threshold, attenuates the held pixel signal before outputting it, and an analog-to-digital conversion procedure that converts the output pixel signal into a digital signal.

[0174] 100 Imaging device 110 Imaging lens 120 Storage unit 130 Imaging control unit 200 Image sensor 211 Vertical drive unit 212 Timing control circuit 213 DAC 220 Pixel array unit 230 Pixel 231 Photodiode 232 Transfer transistor 233 Reset transistor 234 Floating diffusion layer 235 Amplification transistor 236 Selection transistor 250 Load MOS circuit block 251 Load MOS circuit 300 Column signal processing circuit 310 Determination circuit 311, 312, 325, 326, 331, 332, 418, 422 Capacitance element 313, 314, 413, 414 Auto-zero switch 315, 400 Comparator 316 Latch circuit 317 AND gate 318 OR gate 320 Sample and hold circuit 321, 322 Input transistor 323, 324 Output transistor 330 Single slope ADC 333 Counter 335 SAR ADC 340 Digital signal processing unit 350 Amplifier 411, 412 PMOS transistor 415, 416, 417, 421, 431 NMOS transistor 420 LDO 432 Current source 12031 Imaging unit

Claims

1. An image sensor comprising: a determination circuit that determines whether the illuminance of light incident on a pixel is above a predetermined threshold; a sample-and-hold circuit that holds a pixel signal generated by the pixel and, if the illuminance is above the threshold, attenuates the held pixel signal and outputs it; and an analog-to-digital converter that converts the output pixel signal into a digital signal.

2. The image sensor according to claim 1, wherein the level of the pixel signal includes a reset level when the pixel is initialized and a signal level when signal charge is transferred within the pixel, and the sample-and-hold circuit comprises: a first capacitive element that holds the reset level; a second capacitive element that holds the signal level; a first input transistor that opens and closes a path between a vertical signal line that transmits the pixel signal and the first capacitive element; a second input transistor that opens and closes a path between the vertical signal line and the second capacitive element; a first output transistor that opens and closes a path between the analog-to-digital converter and the first capacitive element; and a second output transistor that opens and closes a path between the analog-to-digital converter and the second capacitive element, and when the illuminance is higher than the threshold, the determination circuit controls the first output transistor to an on state for a predetermined pulse period using a predetermined control signal within a readout period for reading out the signal level.

3. The image sensor according to claim 2, wherein the capacitance value of the first capacitance element is different from the capacitance value of the second capacitance element.

4. An image sensor as described in claim 2, wherein the determination circuit comprises: a first comparator that compares the level of the pixel signal with a predetermined reference level and outputs a comparison result; a latch circuit that holds the comparison result from the first comparator at the end of the readout period of the reset level; and a logic gate that generates the control signal based on the comparison result held in the latch circuit.

5. The image sensor according to claim 2, wherein the analog-to-digital converter comprises: a second comparator that compares the pixel signal output by the sample-and-hold circuit with a predetermined ramp signal and outputs the comparison result; and a counter that counts a count value over a period until the comparison result is inverted.

6. An image sensor according to claim 5, wherein the determination circuit comprises: a latch circuit that holds the comparison result from the second comparator at the end of the readout period of the reset level; and a logic gate that generates the control signal based on the comparison result held in the latch circuit.

7. The image sensor according to claim 1, further comprising an amplifier that amplifies the pixel signal and outputs the amplified signal to the sample-and-hold circuit.

8. The image sensor according to claim 1, wherein the analog-to-digital converter is a SAR ADC (Successive Approximation Register Analog to Digital Converter).

9. An imaging device comprising: a determination circuit that determines whether the illuminance of light incident on a pixel is below a predetermined threshold; a sample-and-hold circuit that holds a pixel signal generated by the pixel and, if the illuminance is above the threshold, attenuates the held pixel signal and outputs it; an analog-to-digital converter that converts the output pixel signal into a digital signal; and a digital signal processing unit that performs predetermined signal processing on the digital signal.

10. A method for controlling an image sensor comprising: a determination step of determining whether the illuminance of light incident on a pixel is above a predetermined threshold; a sample and hold step of a sample and hold circuit holding the pixel signal generated by the pixel, and if the illuminance is above the threshold, attenuating and outputting the held pixel signal; and an analog-to-digital conversion step of converting the output pixel signal into a digital signal.

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