Nitride semiconductor device and method for manufacturing nitride semiconductor device

Abstract

This nitride semiconductor device comprises: a conductive substrate having a first substrate surface and a second substrate surface opposite to the first substrate surface; a high resistance layer provided on the first substrate surface and having a resistance higher than that of the conductive substrate; a nitride semiconductor layer provided on the high resistance layer; a source electrode as a first electrode formed on the nitride semiconductor layer; and a via electrically connected to the source electrode and penetrating through the nitride semiconductor layer and the high resistance layer and in contact with the conductive substrate. The high resistance layer is composed of GaN and is in contact with the first substrate surface.

Description

NITRIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING NITRIDE SEMICONDUCTOR DEVICE

[0001] The present disclosure relates to a nitride semiconductor device and a method for manufacturing a nitride semiconductor device.

[0002] Currently, high electron mobility transistors (HEMTs) using group III nitride semiconductors (hereinafter sometimes simply referred to as "nitride semiconductors") such as gallium nitride (GaN) are being commercialized. HEMTs use two-dimensional electron gas (2DEG) formed near the interface of a semiconductor heterojunction as a conductive path (channel). Power devices using HEMTs are recognized as devices that enable lower on-resistance and higher speed / frequency operation compared to typical silicon (Si) power devices.

[0003] For example, a nitride semiconductor device described in Patent Document 1 includes a substrate, a buffer layer formed on the substrate, an electron transit layer formed on the buffer layer, and an electron supply layer formed on the electron transit layer, and a 2DEG is formed during electron transit near the heterojunction interface between the electron transit layer and the electron supply layer.

[0004] JP 2023-10193 A

[0005] [Summary] A nitride semiconductor device may further include a source electrode formed on an electron supply layer, a backside electrode formed on the underside of a silicon substrate, and a via that penetrates the silicon substrate and connects the source electrode and the backside electrode. In this case, it is desired to reduce the cost required for manufacturing the nitride semiconductor having the via.

[0006] A nitride semiconductor device according to one aspect of the present disclosure includes a conductive substrate having a first substrate surface and a second substrate surface opposite to the first substrate surface, a high-resistance layer provided on the first substrate surface and having a resistance higher than that of the conductive substrate, a nitride semiconductor layer provided on the high-resistance layer, a first electrode formed on the nitride semiconductor layer, and a via electrically connected to the first electrode, passing through the nitride semiconductor layer and the high-resistance layer and in contact with the conductive substrate, wherein the high-resistance layer is made of GaN and in contact with the first substrate surface.

[0007] FIG. 1 is a schematic plan view of an example of an exemplary nitride semiconductor device according to a first embodiment. FIG. 2 is a schematic cross-sectional view of the nitride semiconductor device taken along line F2-F2 in FIG. 1. FIG. 3 is a schematic plan view of an example of an exemplary nitride semiconductor device according to a second embodiment. FIG. 4 is a schematic cross-sectional view of the nitride semiconductor device taken along line F4-F4 in FIG. 3. FIG. 5 is a schematic plan view of a nitride semiconductor chip in the nitride semiconductor device of FIG. 3. FIG. 6 is a schematic plan view of gate wiring, source wiring, drain wiring, and their periphery in the nitride semiconductor chip of FIG. 5. FIG. 7 is a schematic plan view of gate electrodes, source electrodes, drain electrodes, and their periphery in the nitride semiconductor chip of FIG. 5. FIG. 8 is a schematic plan view enlarging a portion of FIG. 7. FIG. 9 is a schematic cross-sectional view of the nitride semiconductor device taken along line F9-F9 in FIG. 8. FIG. 10 is a schematic cross-sectional view of a high-resistance layer and an electron transit layer in the nitride semiconductor device. FIG. 11 is a schematic cross-sectional view enlarging the interface between the high-resistance layer and the electron transit layer in FIG. 10. FIG. 12 is a schematic cross-sectional view showing an example of a manufacturing process of an illustrative nitride semiconductor device according to the second embodiment. FIG. 13 is a schematic cross-sectional view of a process subsequent to the process shown in FIG. 12. FIG. 14 is a schematic cross-sectional view of a process subsequent to the process shown in FIG. 13. FIG. 15 is a schematic cross-sectional view of a process subsequent to the process shown in FIG. 14. FIG. 16 is a schematic cross-sectional view of a process subsequent to the process shown in FIG. 15. FIG. 17 is a schematic cross-sectional view of a process subsequent to the process shown in FIG. 16. FIG. 18 is a schematic cross-sectional view of a process subsequent to the process shown in FIG. 17. FIG. 19 is a schematic cross-sectional view of a process subsequent to the process shown in FIG. 18. FIG. 20 is a schematic cross-sectional view of a process subsequent to the process shown in FIG. 19. FIG. 21 is a schematic cross-sectional view of a nitride semiconductor device according to a third embodiment. FIG. 22 is a schematic cross-sectional view showing an enlarged view of a recess in a conductive substrate and its periphery in the nitride semiconductor device of FIG. 21. FIG. 23 is a schematic cross-sectional view showing an enlarged view of an end of a recess in a conductive substrate and its periphery in the nitride semiconductor device of FIG. 21. FIG. 24 is a schematic cross-sectional view of a nitride semiconductor device according to a modified example. FIG. 25 is a schematic plan view of a nitride semiconductor device according to a modified example. FIG. 26 is a schematic cross-sectional view of a nitride semiconductor device according to a modified example.

[0008] DETAILED DESCRIPTION Hereinafter, several embodiments of nitride semiconductor devices according to the present disclosure will be described with reference to the accompanying drawings. Note that for simplicity and clarity of description, components shown in the drawings are not necessarily drawn to scale. Also, hatching lines may be omitted in cross-sectional views to facilitate understanding. The accompanying drawings are merely illustrative of embodiments of the present disclosure and should not be considered to limit the present disclosure.

[0009] The following detailed description includes devices, systems, and methods embodying exemplary embodiments of the present disclosure. This detailed description is merely illustrative in nature and is not intended to limit the embodiments of the present disclosure or the application and uses of such embodiments.

[0010] The phrase "at least one" as used in this disclosure means "one or more" of the desired options. As an example, the phrase "at least one" as used in this disclosure means "only one option" or "both of two options" when the number of options is two. As another example, the phrase "at least one" as used in this disclosure means "only one option" or "any combination of two or more options" when the number of options is three or more.

[0011] As used in this disclosure, "the dimensions (width, length) of A are equal to the dimensions (width, length) of B" or "the dimensions (width, length) of A and the dimensions (width, length) of B are equal to each other" also includes a relationship in which the difference between the dimensions (width, length) of A and the dimensions (width, length) of B is, for example, within 10% of the dimensions (width, length) of A.

[0012] 1 shows a schematic planar structure of an exemplary nitride semiconductor device 10 according to a first embodiment. The nitride semiconductor device 10 may include an insulating layer 102, and a source wiring 104 and a drain wiring 106 provided on the insulating layer 102. The Z direction is a direction orthogonal to a first substrate surface 112A (see FIG. 2 ) of a SiC substrate 112 described later.

[0013] The insulating layer 102 can be made of any insulating material that can insulate the source wiring 104 from the drain wiring 106. For example, the insulating layer 102 can be made of SiO ２ , SiN, SiON, Al ２ O ３ , AlN, AlON, HfO, HfN, HfON, HfSiON, AlON, or any combination thereof.

[0014] The source wiring 104 and the drain wiring 106 can be composed of one or more conductive materials, for example, the source wiring 104 and the drain wiring 106 can each include Au, Ti, TiN, Pt, Cu, Al, AlSiCu, AlCu, or any combination thereof.

[0015] As shown in FIG. 1 , the source wiring 104 may include a base portion 104A and a plurality of source fingers 104B connected to the base portion 104A. In the illustrated example, the base portion 104A extends in the X direction, and the plurality of source fingers 104B extend in the Y direction. Similarly, the drain wiring 106 may include a base portion 106A and a plurality of drain fingers 106B connected to the base portion 106A. In the illustrated example, the base portion 106A extends in the X direction, and the plurality of drain fingers 106B extend in the Y direction. The plurality of source fingers 104B and the plurality of drain fingers 106B may be spaced apart from each other in the X direction and alternately arranged. In the illustrated example, the plurality of source fingers 104B and the plurality of drain fingers 106B are arranged alternately in the X direction.

[0016] The nitride semiconductor device 10 may further include a gate interconnect 108 and a plurality of gate electrodes 110 connected to the gate interconnect 108. The gate interconnect 108 and the plurality of gate electrodes 110 may be arranged below the source interconnect 104 and the drain interconnect 106 and may be covered by the insulating layer 102. In the illustrated example, the gate interconnect 108 extends in the X direction, and the plurality of gate electrodes 110 extend in the Y direction. Each gate electrode 110 may be arranged between one of the plurality of source fingers 104B and one of the plurality of drain fingers 106B in a plan view. In the illustrated example, each gate electrode 110 is arranged between the source finger 104B and the drain finger 106B that face each other in the X direction in a plan view. The gate interconnect 108 may extend between the base portion 104A of the source interconnect 104 and the plurality of drain fingers 106B in a plan view. In another example, the gate wiring 108 may extend between the base portion 106A of the drain wiring 106 and the plurality of source fingers 104B in a plan view. Further details of the gate electrode 110 will be described later with reference to FIG.

[0017] (Cross-Sectional Structure of Nitride Semiconductor Device) FIG. 2 shows a schematic cross-sectional structure of the nitride semiconductor device 10 taken along line F2-F2 in FIG. 1 . The nitride semiconductor device 10 includes a hexagonal SiC substrate 112 having a first substrate surface 112A, a high-resistance layer 114 provided on the first substrate surface 112A of the SiC substrate 112, and a nitride semiconductor layer 116 provided on the high-resistance layer 114. The SiC substrate 112 also has a second substrate surface 112B opposite the first substrate surface 112A. Note that in the first embodiment, the term "first substrate surface" refers to the surface of the SiC substrate 112 on which the high-resistance layer 114 is placed. The first substrate surface 112A is parallel to a first direction DA (X direction) and a second direction DB (Y direction) that is perpendicular to the first direction DA in a plan view. In the first embodiment, the SiC substrate 112 is an example of a "conductive substrate."

[0018] The SiC substrate 112 is a SiC substrate having an off-axis angle. The first substrate surface 112A is inclined at a predetermined off-axis angle in a specific crystal direction with respect to the c-plane. This off-axis angle may be 2° or more and 6° or less. More preferably, the off-axis angle may be 3° or more and 5° or less, and even more preferably, 3.5° or more and 4.5° or less. In this disclosure, the term "c-plane" is used to refer to the (0001) plane of a hexagonal SiC crystal.

[0019] In the first embodiment, the specific crystal direction may be the [11-20] direction. That is, the first substrate surface 112A may be inclined in the [11-20] direction with an off-angle of 2° to 6° relative to the c-plane. Note that in the indicators representing crystal directions and planes in the present disclosure, a number preceded by a minus sign (e.g., "2" for the [11-20] direction) means the number with a bar above it.

[0020] The SiC substrate 112 may be a 4H—SiC substrate. Here, “4H” represents the polytype of SiC crystal. The SiC substrate 112 may be conductive. The resistivity of the SiC substrate 112 may be, for example, 0.01 Ω·cm (1 Ω·m) or more and 0.03 Ω·cm (3 Ω·m) or less. In the first embodiment, the resistivity of the SiC substrate 112 may be approximately 0.02 Ω·cm (2 Ω·m). Furthermore, the thickness TP of the SiC substrate 112 may be, for example, 30 μm or more and 300 μm or less. The thickness TP of the SiC substrate 112 is, for example, 50 μm or more. The thickness TP of the SiC substrate 112 is, for example, 200 μm or less. In the first embodiment, the SiC substrate 112 may have a thickness of 150 μm. Here, the thickness TP of the SiC substrate 112 can be defined as the distance between the first substrate surface 112A and the second substrate surface 112B in the Z direction.

[0021] In the first embodiment, the SiC substrate 112 is used as the conductive substrate, but this is not limiting. For example, a Si substrate may be used as the conductive substrate, or a semiconductor substrate other than a substrate containing Si, such as a GaN substrate or a sapphire substrate, may be used. Even in this case, the conductive substrate may be doped with impurities or may be polycrystalline. The conductive substrate may also be a metal layer. The metal layer may be composed of a plated layer or a sputtered film. The conductive substrate may also be composed of a metal plate.

[0022] The high-resistance layer 114 includes a first surface 114A and a second surface 114B opposite to the first surface 114A. In one example, the second surface 114B is in contact with the first substrate surface 112A of the SiC substrate 112. A part of the nitride transistor TN is provided in the nitride semiconductor layer 116. The detailed configuration of the high-resistance layer 114 will be described later.

[0023] The nitride semiconductor layer 116 includes an electron transit layer 118 and an electron supply layer 120 provided on the electron transit layer 118. The electron transit layer 118 may be provided on the high-resistivity layer 114. The electron transit layer 118 is in contact with the first surface 114A of the high-resistivity layer 114. The electron transit layer 118 is made of a nitride semiconductor. The electron transit layer 118 may be made of GaN. In the first embodiment, the electron transit layer 118 may be an n-type GaN layer doped with donor impurities. In another example, the electron transit layer 118 may be an undoped GaN layer. The thickness of the electron transit layer 118 may be not less than 0.05 μm and not more than 1 μm. In the first embodiment, the electron transit layer 118 may have a thickness of approximately 0.2 μm.

[0024] The electron supply layer 120 is made of a nitride semiconductor having a band gap larger than that of the electron transit layer 118. In the first embodiment, the electron supply layer 120 is made of Al ｘ Ga １－ｘThe electron supply layer 120 may be composed of N, where 0<x≦1, and more preferably 0.1<x<0.3. The band gap of AlGaN increases as the Al composition increases. In the first embodiment, x=0.2. The thickness of the electron supply layer 120 may be 1 nm or more and 100 nm or less. In the first embodiment, the electron supply layer 120 may have a thickness of approximately 20 nm.

[0025] The electron transit layer 118 and the electron supply layer 120 are composed of nitride semiconductors with different lattice constants. Therefore, the nitride semiconductor (e.g., GaN) constituting the electron transit layer 118 and the nitride semiconductor (e.g., AlGaN) constituting the electron supply layer 120 form a lattice-mismatched heterojunction. Due to spontaneous polarization in the electron transit layer 118 and the electron supply layer 120 and piezoelectric polarization caused by stress on the electron supply layer 120 near the heterojunction interface, the energy level of the conduction band of the electron transit layer 118 near the heterojunction interface is lower than the Fermi level. As a result, a two-dimensional electron gas (2DEG) 122 spreads within the electron transit layer 118 near the heterojunction interface between the electron transit layer 118 and the electron supply layer 120 (e.g., within a range of several nanometers from the interface). The 2DEG 122 in the electron transit layer 118 functions as a channel of the nitride semiconductor device 10. The sheet carrier density of the 2DEG 122 generated in the electron transit layer 118 can be increased by increasing at least one of the Al composition and the thickness of the electron supply layer 120 .

[0026] The nitride semiconductor device 10 may further include a first insulating layer 124 provided on the electron supply layer 120. The first insulating layer 124 has a source contact opening 124A, a drain contact opening 124B, and a gate contact opening 124C that expose the surface of the electron supply layer 120. The source contact opening 124A and the drain contact opening 124B are spaced apart in the X direction. The gate contact opening 124C is located between the source contact opening 124A and the drain contact opening 124B that are spaced apart in the X direction. The first insulating layer 124 is made of SiO ２ , SiN, SiON, Al ２ O３ , AlN, AlON, HfO, HfN, HfON, HfSiON, AlON, or any combination thereof. In the first embodiment, the first insulating layer 124 may be SiN. The thickness of the first insulating layer 124 may be, for example, not less than 10 nm and not more than 200 nm. In the first embodiment, the first insulating layer 124 may have a thickness of approximately 10 nm. The first insulating layer 124 is part of the insulating layer 102.

[0027] The nitride semiconductor device 10 includes a gate electrode 110, a source electrode 126, and a drain electrode 128 disposed on a nitride semiconductor layer 116. The source electrode 126 and the drain electrode 128 are spaced apart in a first direction DA (X direction). The gate electrode 110 is disposed between the source electrode 126 and the drain electrode 128, which are spaced apart in the first direction DA. The source electrode 126, the drain electrode 128, and the gate electrode 110 are disposed to enable electrons to travel in the first direction DA through the 2DEG 122. The source electrode 126 is in contact with the electron supply layer 120 through a source contact opening 124A. The drain electrode 128 is in contact with the electron supply layer 120 through a drain contact opening 124B. The gate electrode 110 is in contact with the electron supply layer 120 through a gate contact opening 124C.

[0028] The source electrode 126 and the drain electrode 128 may be made of any material capable of forming an ohmic contact with the nitride semiconductor layer 116. In the first embodiment, the source electrode 126 and the drain electrode 128 may include a Ti layer and an Al layer. In this case, the Ti layer may be located between the first insulating layer 124 and the Al layer. In one example, the Ti layer may have a thickness of approximately 20 nm, and the Al layer may have a thickness of approximately 300 nm. In another example, the source electrode 126 and the drain electrode 128 may include a Ta layer and an Al layer. In yet another example, the source electrode 126 and the drain electrode 128 may include a Ti layer, an Al layer, a Ni layer, and an Au layer, in this order from the bottom.

[0029] The source electrode 126 includes a source contact 126A that includes a portion that contacts the upper surface of the electron supply layer 120 through the source contact opening 124A. The source contact 126A fills the source contact opening 124A. The source contact 126A has a strip shape that extends in the Y direction in plan view.

[0030] The gate electrode 110 may be made of any material capable of forming a Schottky junction with the nitride semiconductor layer 116. In the first embodiment, the gate electrode 110 may include a Ni layer and an Au layer. In this case, the Ni layer may be located between the first insulating layer 124 and the Au layer. In one example, the Ni layer may have a thickness of 10 nm, and the Au layer may have a thickness of 600 nm.

[0031] 1 , the gate electrode 110 extends in the second direction DB (Y direction). The source electrode 126 and the drain electrode 128 also extend in the second direction DB. That is, the source electrode 126, the gate electrode 110, and the drain electrode 128, which extend in the second direction DB, are aligned in this order in the first direction DA. Therefore, electrons can travel in the first direction DA between the source electrode 126 and the drain electrode 128 via the 2DEG 122 in the electron transit layer 118.

[0032] 2, the nitride semiconductor device 10 may further include a second insulating layer 130 provided on the first insulating layer 124. The second insulating layer 130 has a first opening 130A that exposes the surface of the source electrode 126 and a second opening 130B that exposes the surface of the drain electrode 128. The second insulating layer 130 is made of SiO ２ , SiN, SiON, Al ２ O ３ , AlN, AlON, HfO, HfN, HfON, HfSiON, AlON, or any combination thereof. ２ The second insulating layer 130 may have a thickness of about 500 nm. The second insulating layer 130 is part of the insulating layer 102. It can also be said that the insulating layer 102 includes the first insulating layer 124 and the second insulating layer 130.

[0033] The source wiring 104 and the drain wiring 106 are provided on the second insulating layer 130. The source finger 104B of the source wiring 104 is connected to the source electrode 126 through the first opening 130A. The drain finger 106B of the drain wiring 106 is connected to the drain electrode 128 through the second opening 130B.

[0034] While the above description with reference to FIG. 2 focuses on one source electrode 126, one drain electrode 128, and the gate electrode 110 disposed therebetween, the nitride semiconductor device 10 may include multiple gate electrodes 110, multiple source electrodes 126, and multiple drain electrodes 128 disposed on the nitride semiconductor layer 116. Each of the multiple source electrodes 126 may be connected to one of the multiple source fingers 104B through a first opening 130A. Similarly, each of the multiple drain electrodes 128 may be connected to one of the multiple drain fingers 106B through a second opening 130B. The multiple source electrodes 126 and the multiple drain electrodes 128 may be alternately disposed in a first direction DA (X direction). Furthermore, each of the multiple gate electrodes 110 may be disposed between one of the multiple source electrodes 126 and one of the multiple drain electrodes 128.

[0035] (High Resistance Layer) The high resistance layer 114 is provided on the first substrate surface 112A of the SiC substrate 112. More specifically, the high resistance layer 114 is in contact with the first substrate surface 112A. The high resistance layer 114 is a layer for insulating between the SiC substrate 112 and the nitride semiconductor layer 116. Therefore, the high resistance layer 114 is configured to have a higher resistance value than the SiC substrate 112. The high resistance layer 114 is also configured to have a higher resistance value than the electron transit layer 118. The resistance value of the high resistance layer 114 is, for example, 1×10 ５ The high resistance layer 114 may be irradiated with an electron beam in order to achieve high resistance.

[0036] The high-resistance layer 114 is made of GaN. The high-resistance layer 114 may be, for example, single crystal. That is, the high-resistance layer 114 may be a single-crystal GaN layer. The high-resistance layer 114 may be doped with impurities or may not be doped with impurities. In the first embodiment, the high-resistance layer 114 is doped with impurities. The impurities may be, for example, transition metal elements such as iron (Fe) or zinc (Zn), or at least one of magnesium (Mg), boron (B), and C. That is, the high-resistance layer 114 may contain at least one of the transition metal elements Mg, B, and C as impurities. In one example, the high-resistance layer 114 may contain a transition metal element. In one example, the high-resistance layer 114 may contain Mg. In one example, the high-resistance layer 114 may contain B. In one example, the high-resistance layer 114 may contain C.

[0037] In one example, the impurity concentration of the high resistance layer 114 is 1×10 １６ cm －３ In one example, the impurity concentration of the high resistance layer 114 is 1×10 ２０ cm －３ 2 , the thickness TQ of the high-resistance layer 114 is thinner than the thickness TP of the SiC substrate 112. The thickness TQ of the high-resistance layer 114 is thicker than the thickness TS of the electron supply layer 120 of the nitride semiconductor layer 116. The thickness TQ of the high-resistance layer 114 is thinner than the thickness TR of the electron transit layer 118 of the nitride semiconductor layer 116. The thickness TQ of the high-resistance layer 114 is thinner than the thickness TT of the nitride semiconductor layer 116. In one example, the thickness TQ of the high-resistance layer 114 is 3 μm or more. In one example, the thickness TQ of the high-resistance layer 114 is 20 μm or less. Here, the thickness TQ of the high-resistance layer 114 can be defined as the distance between the first surface 114A and the second surface 114B in the Z direction.

[0038] The thickness TQ of the high-resistance layer 114 can be changed as desired. For example, the thickness TQ of the high-resistance layer 114 may be equal to or greater than the thickness TP of the SiC substrate 112. For example, the thickness TQ of the high-resistance layer 114 may be equal to or greater than the thickness TR of the electron transit layer 118. For example, the thickness TQ of the high-resistance layer 114 may be equal to or greater than the thickness TT of the nitride semiconductor layer 116. For example, the thickness TQ of the high-resistance layer 114 may be equal to or less than the thickness TR of the electron transit layer 118. The thickness TQ of the high-resistance layer 114 may be greater than 20 μm. The thickness TQ of the high-resistance layer 114 may be greater than 20 μm and equal to or less than 100 μm.

[0039] (Via) The nitride semiconductor device 10 includes a via 140 that electrically connects the source electrode 126 and the SiC substrate 112 .

[0040] 2 , the via 140 is in contact with the source electrode 126 and also in contact with the SiC substrate 112. In the first embodiment, the via 140 is in contact with the first substrate surface 112A of the SiC substrate 112. In this manner, the via 140 is electrically connected to both the source electrode 126 and the SiC substrate 112. Therefore, a source voltage is applied to the SiC substrate 112 through the source electrode 126 and the via 140.

[0041] The via 140 penetrates in the Z direction through the layers interposed between the source electrode 126 and the SiC substrate 112. More specifically, the via 140 penetrates in the Z direction through the nitride semiconductor layer 116 and the high-resistance layer 114. Therefore, the length LU of the via 140 is equal to the total thickness of the layers interposed between the source electrode 126 and the SiC substrate 112.

[0042] The total thickness (TQ+TT) of the thickness TT of the nitride semiconductor layer 116 and the thickness TQ of the high-resistivity layer 114 can be made thinner than the thickness TP of the SiC substrate 112. Therefore, the length LU of the via 140 can be made shorter than the thickness TP of the SiC substrate 112. In one example, the length LU of the via 140 may be 100 μm or less. In one example, the length LU of the via 140 may be 50 μm or less.

[0043] 1, the via 140 extends in the Y direction in plan view together with the source contact 126A of the source electrode 126. In the example shown in Fig. 1, a plurality of vias 140 (two in the first embodiment) are provided spaced apart in the Y direction in plan view.

[0044] 2 , the via 140 includes a first end face 141 in contact with the source contact 126A, a second end face 142 in contact with the SiC substrate 112, and a side face 143 connecting the first end face 141 and the second end face 142. The side face 143 is in contact with the high-resistance layer 114 and the nitride semiconductor layer 116.

[0045] 1, a plurality of vias 140 are provided corresponding to a plurality of source electrodes 126. Therefore, it can be said that the plurality of vias 140 are dispersed and arranged over substantially the entire surface of the SiC substrate 112 in a plan view.

[0046] The via 140 may be made of one or more conductive materials. The conductive material may be, for example, a metal material including one or more appropriately selected from Ti, TiN, Au, Ag, Cu, Al, and W. In one example, the via 140 is made of the same material as the source electrode 126. In this case, the via 140 and the source electrode 126 may be integrally formed. In other words, the via 140 and the source electrode 126 may not have a joint surface between them.

[0047] [Operation of First Embodiment] The operation of the nitride semiconductor device 10 of the first embodiment will be described. In the nitride semiconductor device 10, the SiC substrate 112 has a low resistance value and can therefore function as a back electrode to which a source voltage is applied through the source electrode 126 and the via 140. The high-resistance layer 114 can function as an insulating layer that insulates the SiC substrate 112 from the nitride semiconductor layer 116. That is, the high-resistance layer 114 can function as an insulating layer that insulates the SiC substrate 112 from a HEMT formed using the nitride semiconductor layer 116. In this case, the via 140 does not need to have a shape that penetrates the SiC substrate 112 in the Z direction, but only needs to have a shape that contacts the SiC substrate 112. On the other hand, in a configuration in which a back electrode is provided on the lower surface of the semiconductor substrate, the via needs to penetrate the semiconductor substrate to connect to the back electrode. Therefore, compared to a configuration in which a back surface electrode is provided on the lower surface of a semiconductor substrate, the nitride semiconductor device 10 of the first embodiment can shorten the length LU of the via 140 by the thickness T1 of the SiC substrate 112. As a result of the shortened length LU of the via 140, it is possible to reduce costs, such as the amount of work required to form the via 140 (such as the work of penetrating the SiC substrate 112) and time.

[0048] [Effects of First Embodiment] The nitride semiconductor device 10 of the first embodiment has the following effects. (1-1) The nitride semiconductor device 10 includes a SiC substrate 112 having a first substrate surface 112A and a second substrate surface 112B opposite to the first substrate surface 112A, a high-resistance layer 114 provided on the first substrate surface 112A and having a resistance value higher than that of the SiC substrate 112, a nitride semiconductor layer 116 provided on the high-resistance layer 114, a source electrode 126 serving as a first electrode formed on the nitride semiconductor layer 116, and a via 140 electrically connected to the source electrode 126, penetrating the nitride semiconductor layer 116 and the high-resistance layer 114, and in contact with the SiC substrate 112. The high-resistance layer 114 is made of GaN and in contact with the first substrate surface 112A.

[0049] According to this configuration, compared to a configuration in which a back surface electrode is provided on the lower surface of a semiconductor substrate, the length LU of the via 140 can be shortened by the thickness TP of the SiC substrate 112. This reduces costs, such as the amount of work and time required to form the via 140. In addition, by shortening the length LU of the via 140, the inductance caused by the length LU of the via 140 can be reduced.

[0050] Furthermore, because the high-resistance layer 114 is in contact with the SiC substrate 112, the length LU of the via 140 can be made shorter than in a configuration in which a buffer layer is provided between the high-resistance layer 114 and the SiC substrate 112. Therefore, the inductance caused by the length LU of the via 140 can be reduced.

[0051] (1-2) The high-resistance layer 114 is in contact with the nitride semiconductor layer 116. With this configuration, the length LU of the via 140 can be made shorter than in a configuration in which another layer (for example, a buffer layer) is interposed between the high-resistance layer 114 and the nitride semiconductor layer 116. Therefore, the inductance caused by the length LU of the via 140 can be reduced.

[0052] (1-3) The thickness TQ of the high-resistance layer 114 is thinner than the thickness TP of the SiC substrate 112. With this configuration, the length LU of the via 140 can be made shorter than when the thickness TQ of the high-resistance layer 114 is equal to or greater than the thickness TP of the SiC substrate 112. Therefore, the inductance caused by the length LU of the via 140 can be reduced.

[0053] (1-4) The thickness TQ of the high-resistance layer 114 is 3 μm or more. With this configuration, the high-resistance layer 114 can ensure insulation between the nitride semiconductor layer 116 and the SiC substrate 112.

[0054] (1-5) The thickness TQ of the high resistance layer 114 is 20 μm or less. With this configuration, the length LU of the via 140 can be shortened, and therefore the inductance caused by the length LU of the via 140 can be reduced.

[0055] (1-6) The source electrode 126 and the via 140 are made of the same material. This configuration allows for good connection between the source electrode 126 and the via 140. Therefore, an increase in electrical resistance between the source electrode 126 and the via 140 can be suppressed.

[0056] (1-7) The resistance value of the SiC substrate 112 is 2×10 －２ According to this configuration, the source electrode 126 can function as a backside electrode to which a source voltage is applied through the source electrode 126 and the via 140.

[0057] (1-8) The resistance value of the high resistance layer 114 is 1×10 ５ This configuration can improve the insulation between the nitride semiconductor layer 116 and the SiC substrate 112.

[0058] (1-9) The nitride semiconductor layer 116 includes an electron transit layer 118 and an electron supply layer 120 provided on the electron transit layer 118. According to this configuration, the electron transit layer 118 and the high-resistance layer 114 are provided separately. Therefore, the resistance value of the high-resistance layer 114 can be increased, while the resistance value of the electron transit layer 118 can be reduced due to the generation of 2DEG 122.

[0059] (1-10) The thickness TQ of the high-resistance layer 114 is greater than the thickness TR of the electron transit layer 118. With this configuration, the insulation between the electron transit layer 118 and the SiC substrate 112 can be improved.

[0060] (1-11) The source electrode 126 includes a source contact 126A that contacts the electron supply layer 120. The via 140 contacts the source contact 126A. With this configuration, the length LU of the via 140 can be shortened, thereby reducing the inductance caused by the length LU of the via 140.

[0061] (1-12) A plurality of gate electrodes 110, a plurality of source electrodes 126, and a plurality of drain electrodes 128 are provided. A plurality of vias 140 are provided corresponding to the plurality of source electrodes 126. This configuration can suppress variation in source voltage depending on the location on the SiC substrate 112.

[0062] Second Embodiment [Overall Configuration of Nitride Semiconductor Device] The overall configuration of a nitride semiconductor device 10 according to a second embodiment will be described with reference to Figures 3 and 4. Figure 3 schematically shows the internal planar structure of the nitride semiconductor device 10. Figure 4 schematically shows the cross-sectional structure of the nitride semiconductor device 10 taken along line F4-F4 in Figure 3. Note that Figure 3 shows a see-through view of a sealing resin 16, which will be described later, so that the interior of the nitride semiconductor device 10 can be seen.

[0063] 3 and 4, the nitride semiconductor device 10 has a flat plate shape with its thickness direction aligned in the Z direction. In one example, the nitride semiconductor device 10 has a rectangular shape having long and short sides when viewed from the Z direction. In the example shown in FIG. 3, the nitride semiconductor device 10 is arranged so that its long sides extend along the X direction and its short sides extend along the Y direction. Hereinafter, viewing the nitride semiconductor device 10 from the Z direction will be referred to as a "planar view."

[0064] The nitride semiconductor device 10 includes a nitride semiconductor chip 11, a die pad 12, a gate terminal 13, a source terminal 14, a drain terminal 15, and a sealing resin 16. The nitride semiconductor device 10 also includes a gate wire 17, a source clip 18, and a drain clip 19. Here, the gate terminal 13, the source terminal 14, and the drain terminal 15 are examples of "terminals."

[0065] The sealing resin 16 forms the exterior of the nitride semiconductor device 10. For this reason, the sealing resin 16 has a rectangular plate shape. The sealing resin 16 seals the nitride semiconductor chip 11, the gate wire 17, the source clip 18, and the drain clip 19. The sealing resin 16 seals the die pad 12, the gate terminal 13, the source terminal 14, and the drain terminal 15, leaving them partially exposed. The sealing resin 16 is made of a material containing an insulating material. In one example, the sealing resin 16 is made of a material containing a black epoxy resin.

[0066] The sealing resin 16 includes a first sealing surface 16S, a second sealing surface 16R opposite to the first sealing surface 16S, and first to fourth sealing side surfaces 16A to 16D as four side surfaces connecting the first sealing surface 16S and the second sealing surface 16R. The first sealing side surface 16A and the second sealing side surface 16B constitute both end surfaces of the sealing resin 16 in the X direction. The third sealing side surface 16C and the fourth sealing side surface 16D constitute both end surfaces of the sealing resin 16 in the Y direction.

[0067] The nitride semiconductor chip 11 is a semiconductor chip provided with a nitride transistor TN (see FIG. 7 ). The nitride semiconductor chip 11 has a flat plate shape with its thickness direction aligned in the Z direction. In one example, the nitride semiconductor chip 11 has a rectangular shape with long and short sides in a plan view. In the example shown in FIG. 3 , the nitride semiconductor chip 11 is arranged so that its long sides extend along the X direction and its short sides extend along the Y direction.

[0068] The nitride semiconductor chip 11 includes a first chip surface 11S, a second chip surface 11R opposite the first chip surface 11S, and first to fourth chip side surfaces 11A to 11D as four side surfaces connecting the first chip surface 11S and the second chip surface 11R. The first chip side surface 11A and the second chip side surface 11B constitute both end surfaces of the nitride semiconductor chip 11 in the X direction, and the third chip side surface 11C and the fourth chip side surface 11D constitute both end surfaces of the nitride semiconductor chip 11 in the Y direction. The first chip surface 11S is provided with a gate pad 21, a plurality of (two in the second embodiment) source pads 22, and a plurality of (three in the second embodiment) drain pads 23. The detailed configuration of the nitride semiconductor chip 11 will be described later.

[0069] The nitride semiconductor chip 11 is mounted on a die pad 12. In one example, the nitride semiconductor chip 11 is bonded to the die pad 12 by a conductive bonding material SD. For example, solder paste or silver (Ag) paste may be used as the conductive bonding material SD. The die pad 12 is flat and has a thickness direction in the Z direction. The die pad 12 is rectangular in shape having long and short sides in a plan view. In the example shown in FIG. 3 , the die pad 12 is arranged so that the long sides extend along the X direction and the short sides extend along the Y direction. Note that the nitride semiconductor chip 11 may also be bonded to the die pad 12 by an insulating bonding material.

[0070] The drain terminal 15 is disposed closer to the third sealing side surface 16C than the die pad 12. The drain terminal 15 is disposed apart from the die pad 12 in the Y direction. The drain terminal 15 is provided in a strip shape extending in the X direction in a plan view.

[0071] The source terminal 14 and the gate terminal 13 are arranged closer to the fourth sealing side surface 16D with respect to the die pad 12. In other words, the source terminal 14 and the gate terminal 13 are arranged on the opposite side of the die pad 12 from the drain terminal 15. The source terminal 14 and the gate terminal 13 are arranged spaced apart from the die pad 12 in the Y direction. The source terminal 14 and the gate terminal 13 are arranged at the same position as each other in the Y direction and spaced apart from each other in the X direction. The gate terminal 13 is arranged closer to the second sealing side surface 16B than the source terminal 14.

[0072] The source terminal 14 is provided in a strip shape extending in the X direction in a plan view. The dimension of the source terminal 14 in the X direction is shorter than the dimension of the drain terminal 15 in the X direction. The gate terminal 13 is provided in a rectangular shape in a plan view. The dimension of the gate terminal 13 in the X direction is shorter than the dimension of the source terminal 14 in the X direction.

[0073] The die pad 12, gate terminal 13, source terminal 14, and drain terminal 15 are exposed from the second sealing surface 16R. Therefore, the gate terminal 13, source terminal 14, and drain terminal 15 constitute external electrode terminals that are electrically connected to wiring on a circuit board (not shown) when the nitride semiconductor device 10 is mounted on the circuit board. As described above, the nitride semiconductor device 10 has a surface-mount package structure. Note that the package structure of the nitride semiconductor device 10 can be changed as desired.

[0074] The die pad 12, the gate terminal 13, the source terminal 14, and the drain terminal 15 are made of a conductive material such as aluminum (Al), copper (Cu), etc. The die pad 12, the gate terminal 13, the source terminal 14, and the drain terminal 15 are made of a material containing Cu, for example.

[0075] The nitride semiconductor chip 11 is connected to the gate terminal 13, source terminal 14, and drain terminal 15 using a gate wire 17, a source clip 18, and a drain clip 19, respectively. The source clip 18 and the drain clip 19 are conductive. The source clip 18 and the drain clip 19 are formed by bending a metal plate made of, for example, Al, Cu, or the like. The gate wire 17 is made of a conductive material such as Al, Cu, silver (Ag), or gold (Au). The gate wire 17 is, for example, a bonding wire. The drain clip 19 is bonded to the drain pad 23 by a conductive bonding material SD. The source clip 18 is bonded to the source pad 22 by a conductive bonding material SD (not shown).

[0076] The nitride semiconductor chip 11 and the gate terminal 13 are connected by the gate wire 17, so that the gate of the nitride transistor TN is electrically connected to the gate terminal 13. The nitride semiconductor chip 11 and the source terminal 14 are connected by the source clip 18, so that the source of the nitride transistor TN is electrically connected to the source terminal 14. The nitride semiconductor chip 11 and the drain terminal 15 are connected by the drain clip 19, so that the drain of the nitride transistor TN is electrically connected to the drain terminal 15.

[0077] [Detailed Configuration of Nitride Semiconductor Chip] Next, the detailed configuration of the nitride semiconductor chip 11 will be described with reference to FIGS. 5 to 9. FIG. 5 schematically shows the planar structure of the nitride semiconductor chip 11. FIG. 6 schematically shows an example of the internal planar structure of the nitride semiconductor chip 11. FIG. 7 schematically shows an example of the planar structure of the nitride transistor TN in the nitride semiconductor chip 11. FIG. 8 schematically shows an enlarged planar structure of a portion of the nitride transistor TN. FIG. 9 schematically shows an example of a cross-sectional structure of the nitride semiconductor chip 11 taken along line F9-F9 in FIG. 8. For convenience, in FIG. 8, gate wiring 41, source wiring 42B, and drain wiring 43B, which will be described later, are indicated by dashed dotted lines.

[0078] 5 , the nitride semiconductor chip 11 includes a gate pad 21, a plurality of (two in the second embodiment) source pads 22, and a plurality of (three in the second embodiment) drain pads 23. The gate pad 21, the source pad 22, and the drain pad 23 are used as external electrode terminals of the nitride semiconductor chip 11.

[0079] The source pads 22 and the drain pads 23 are arranged alternately in the X direction. In plan view, each source pad 22 and each drain pad 23 extends in a direction (Y direction) perpendicular to the arrangement direction (X direction) of the source pads 22 and the drain pads 23. In plan view, each source pad 22 and each drain pad 23 has a rectangular shape with its long side extending in the Y direction and its short side extending in the X direction.

[0080] The gate pad 21 is disposed in a corner portion of the nitride semiconductor chip 11 that is closer to the second chip side surface 11B and the fourth chip side surface 11D. The gate pad 21 is rectangular in plan view. In one example, the gate pad 21 may be square in plan view. Note that the arrangement and shape of the gate pad 21 in plan view can both be changed as desired.

[0081] The gate pad 21 is disposed adjacent to one of the plurality of drain pads 23 in the Y direction. Here, the drain pad 23 adjacent to the gate pad 21 among the plurality of drain pads 23 is referred to as an "end drain pad 23E." The dimension in the Y direction of the end drain pad 23E is shorter than the dimension in the Y direction of the other drain pads 23. In addition, the gate pad 21 is disposed adjacent to one of the plurality of source pads 22 in the X direction.

[0082] 7, the nitride semiconductor chip 11 includes a nitride transistor TN. In one example, the nitride transistor TN is configured as a high electron mobility transistor (HEMT) using a nitride semiconductor.

[0083] The nitride transistor TN of the nitride semiconductor chip 11 includes a plurality of first transistor cells TA, a plurality of second transistor cells TB, and a plurality of third transistor cells TC. The plurality of first transistor cells TA are arranged along the X direction. The plurality of second transistor cells TB are arranged along the X direction. The plurality of second transistor cells TB are arranged adjacent to the plurality of first transistor cells TA in the Y direction. The plurality of third transistor cells TC are arranged along the X direction. The plurality of third transistor cells TC are arranged on the opposite side of the plurality of second transistor cells TB from the plurality of first transistor cells TA in the Y direction. In other words, the plurality of second transistor cells TB are arranged between the plurality of first transistor cells TA and the plurality of third transistor cells TC in the Y direction.

[0084] Corner regions RC, in which no transistor cells are formed, are provided adjacent to both the second transistor cell TB and the third transistor cell TC. The corner regions RC can also be said to be provided in corner portions of the nitride semiconductor chip 11 that are closer to the second chip side surface 11B and the fourth chip side surface 11D. The corner regions RC are regions where gate pads 21 (see FIG. 5 ) are provided in a plan view.

[0085] Each of the first to third transistor cells TA, TB, and TC includes a gate electrode 31, a source electrode 32, and a drain electrode 33. Both the source electrode 32 and the drain electrode 33 may have a strip shape extending in the Y direction in a plan view. The gate electrode 31 may include a ring shape surrounding the drain electrode 33 in a plan view.

[0086] The source electrodes 32 and drain electrodes 33 of the plurality of first transistor cells TA are alternately arranged one by one and spaced apart from each other in the X direction. The annular gate electrode 31 of each of the plurality of first transistor cells TA includes a portion that is arranged between the source electrode 32 and drain electrode 33 of each of the plurality of first transistor cells TA in the X direction.

[0087] The arrangement of the gate electrodes 31, source electrodes 32, and drain electrodes 33 of the second transistor cells TB is the same as that of the first transistor cells TA. The gate electrodes 31, source electrodes 32, and drain electrodes 33 of the second transistor cells TB are arranged at the same positions in the X direction as the gate electrodes 31, source electrodes 32, and gate electrodes 31 of the first transistor cells TA adjacent to them in the Y direction. The gate electrodes 31 of the second transistor cells TB are integrated with the gate electrodes 31 of the first transistor cells TA adjacent to them in the Y direction.

[0088] The arrangement of the gate electrodes 31, source electrodes 32, and drain electrodes 33 of the multiple third transistor cells TC is similar to that of the multiple second transistor cells TB. The gate electrodes 31, source electrodes 32, and drain electrodes 33 of the multiple third transistor cells TC are arranged at the same positions in the X direction as the gate electrodes 31, source electrodes 32, and drain electrodes 33 of the second transistor cells TB adjacent to them in the Y direction. The gate electrodes 31 of the multiple third transistor cells TC are integrated with the gate electrodes 31 of the second transistor cells TB adjacent to them in the Y direction.

[0089] 6, the nitride semiconductor device 10 includes a gate wiring 41, a plurality of (three in the second embodiment) source wirings 42A to 42C, and a plurality of (three in the second embodiment) drain wirings 43A to 43C. The gate wiring 41, the source wirings 42A to 42C, and the drain wirings 43A to 43C are provided on a second insulating layer 82 (described later) that covers the nitride transistor TN.

[0090] The multiple drain wirings 43A to 43C are arranged spaced apart from one another in the Y direction. Each of the drain wirings 43A to 43C has a strip shape extending in the X direction in a plan view. The drain wiring 43A is a wiring that electrically connects the drain electrode 33 (see FIG. 7) of each first transistor cell TA to the drain pad 23 (see FIG. 5). The drain wiring 43A is arranged in a position that overlaps the first transistor cell TA in a plan view. The drain wiring 43A is arranged so as to overlap both the drain electrode 33 and the source electrode 32 (see FIG. 7) of the multiple first transistor cells TA in a plan view. The drain wiring 43A extends across the entire multiple first transistor cells TA in the X direction in a plan view. The drain wiring 43A is electrically connected to the drain electrodes 33 of the multiple first transistor cells TA by multiple drain vias 46 (see FIG. 8).

[0091] The drain wiring 43B is a wiring that electrically connects the drain electrode 33 of each second transistor cell TB to the drain pad 23. The drain wiring 43B is arranged at a position that overlaps the second transistor cell TB in a planar view. The drain wiring 43B is arranged so as to overlap both the drain electrode 33 and the source electrode 32 of the second transistor cells TB in a planar view. The drain wiring 43B extends over the entire X-direction of the second transistor cells TB in a planar view. The dimension of the drain wiring 43B in the X-direction is equal to the dimension of the drain wiring 43A in the X-direction. The drain wiring 43B is electrically connected to the drain electrodes 33 of the second transistor cells TB by a plurality of drain vias 46.

[0092] The drain wiring 43C is a wiring that electrically connects the drain electrode 33 of each third transistor cell TC to the drain pad 23. The drain wiring 43C is arranged at a position that overlaps the third transistor cell TC in a plan view. The drain wiring 43C is arranged so as to overlap both the drain electrode 33 and the source electrode 32 of the multiple third transistor cells TC in a plan view. The drain wiring 43C extends over the entire X-direction of the multiple third transistor cells TC in a plan view. The dimension of the drain wiring 43C in the X-direction is smaller than the dimension of the drain wiring 43A in the X-direction. The drain wiring 43C is electrically connected to the drain electrodes 33 of the multiple third transistor cells TC by multiple drain vias 46.

[0093] The multiple source wirings 42A to 42C are arranged spaced apart from one another in the Y direction. Each of the source wirings 42A to 42C has a strip shape extending in the X direction in a plan view. The source wiring 42A is a wiring that electrically connects the source electrode 32 of each first transistor cell TA to the source pad 22 (see FIG. 5). The source wiring 42A is arranged in a position overlapping the first transistor cell TA in a plan view. The source wiring 42A is arranged so as to overlap both the drain electrode 33 and the source electrode 32 of the multiple first transistor cells TA in a plan view. The source wiring 42A is arranged in a position adjacent to the drain wiring 43A in the Y direction. The source wiring 42A extends across the entirety of the multiple first transistor cells TA in the X direction in a plan view. The source wiring 42A is electrically connected to the source electrodes 32 of the multiple first transistor cells TA by multiple source vias 45 (see FIG. 8).

[0094] The source wiring 42B is a wiring that electrically connects the source electrode 32 of each second transistor cell TB to the source pad 22. The source wiring 42B is arranged in a position that overlaps the second transistor cell TB in a planar view. The source wiring 42B is arranged so as to overlap both the drain electrode 33 and the source electrode 32 of the multiple second transistor cells TB in a planar view. The source wiring 42B is arranged in a position adjacent to the drain wiring 43B in the Y direction. The source wiring 42B extends over the entire multiple second transistor cells TB in the X direction in a planar view. The dimension of the source wiring 42B in the X direction is equal to the dimension of the source wiring 42A in the X direction. The source wiring 42B is electrically connected to the source electrodes 32 of the multiple second transistor cells TB by multiple source vias 45.

[0095] The source wiring 42C is a wiring that electrically connects the source electrode 32 of each third transistor cell TC to the source pad 22. The source wiring 42C is arranged in a position that overlaps the third transistor cell TC in a planar view. The source wiring 42C is arranged so as to overlap both the drain electrode 33 and the source electrode 32 of the multiple third transistor cells TC in a planar view. The source wiring 42C is arranged in a position adjacent to the drain wiring 43C in the Y direction. The source wiring 42C extends over the entire multiple third transistor cells TC in the X direction in a planar view. The dimension of the source wiring 42C in the X direction is smaller than the dimension of the source wiring 42A in the X direction. The source wiring 42C is electrically connected to the source electrodes 32 of the multiple third transistor cells TC by multiple source vias 45.

[0096] The gate wiring 41 is a wiring electrically connected to the gate pad 21 (see FIG. 5). The gate wiring 41 includes a peripheral gate wiring 41A and an intermediate gate wiring 41B. The peripheral gate wiring 41A is provided on the periphery of the nitride semiconductor chip 11 in a plan view. The peripheral gate wiring 41A is a wiring that surrounds the first to third transistor cells TA, TB, and TC. The peripheral gate wiring 41A includes a pad connection portion 41C and a peripheral wiring portion 41D. The pad connection portion 41C is provided in a corner region RC. The peripheral wiring portion 41D is connected to the pad connection portion 41C and is provided in a ring shape that surrounds the first to third transistor cells TA, TB, and TC, the drain wirings 43A to 43C, and the source wirings 42A to 42C.

[0097] The intermediate gate wiring 41B is disposed between the first transistor cell TA and the second transistor cell TB in the Y direction, and between the second transistor cell TB and the third transistor cell TC in the Y direction. The intermediate gate wiring 41B is disposed in a position that does not overlap with the drain wiring 43A-43C and the source wiring 42A-42C in a plan view. The intermediate gate wiring 41B is strip-shaped extending in the X direction in a plan view. In one example, the width of the intermediate gate wiring 41B is smaller than the width of the drain wiring 43A-43C and the width of the source wiring 42A-42C. The intermediate gate wiring 41B is connected to the peripheral wiring portion 41D of the peripheral gate wiring 41A. The intermediate gate wiring 41B, disposed between the second transistor cell TB and the third transistor cell TC in the Y direction, is connected to the pad connection portion 41C. The intermediate gate wiring 41B is electrically connected to the gate electrodes 31 of the first to third transistor cells TA, TB, and TC by a plurality of gate vias 44 (see FIG. 8 ).

[0098] (Schematic Cross-Sectional Structure of Nitride Semiconductor Chip) As shown in FIG. 9 , the nitride semiconductor chip 11 includes a conductive substrate 50, a high-resistance layer 60, and a nitride semiconductor layer 70. The high-resistance layer 60 is provided on the conductive substrate 50. The high-resistance layer 60 includes a first surface 61 and a second surface 62 opposite to the first surface 61. In one example, the second surface 62 is in contact with the first substrate surface 51 of the conductive substrate 50. A part of the nitride transistor TN is provided in the nitride semiconductor layer 70. The detailed configurations of the conductive substrate 50 and the high-resistance layer 60 will be described later.

[0099] The nitride semiconductor layer 70 is provided on the high-resistance layer 60. The nitride semiconductor layer 70 is epitaxially grown on the first surface 61 of the high-resistance layer 60. Therefore, the nitride semiconductor layer 70 is in contact with the high-resistance layer 60. In other words, the high-resistance layer 60 is in contact with the nitride semiconductor layer 70.

[0100] The nitride semiconductor layer 70 includes an electron transit layer 71 provided on the first surface 61 of the high resistance layer 60, and an electron supply layer 72 provided on the electron transit layer 71. The electron transit layer 71 is in contact with the first surface 61 of the high resistance layer 60.

[0101] The electron transit layer 71 is in contact with the first surface 61 of the high-resistance layer 60. The electron transit layer 71 is made of a nitride semiconductor. The electron transit layer 71 is made of GaN. In other words, the electron transit layer 71 can be said to be a GaN layer. The thickness of the electron transit layer 71 can be set to, for example, 0.5 μm or more and 2 μm or less. Note that, in order to suppress leakage current in the electron transit layer 71, impurities may be introduced into a portion of the electron transit layer 71 to make the electron transit layer 71 semi-insulating except for the surface region. In this case, the impurity is, for example, carbon (C), and the peak concentration of the impurity in the electron transit layer 71 is, for example, 1×10 １９ cm －３ It can be more than that.

[0102] The electron supply layer 72 is made of a nitride semiconductor having a larger band gap than the electron transit layer 71. The electron supply layer 72 is, for example, an aluminum gallium nitride (AlGaN) layer. In this case, the band gap increases as the Al composition increases, so the electron supply layer 72, which is an AlGaN layer, has a larger band gap than the electron transit layer 71, which is a GaN layer. In one example, the electron supply layer 72 is made of Al ｘ Ga １－ｘ The electron supply layer 72 is made of N, where x is 0.1<x<0.4, and more preferably 0.2<x<0.3. The thickness of the electron supply layer 72 can be set to, for example, 5 nm or more and 20 nm or less.

[0103] The electron transit layer 71 and the electron supply layer 72 are made of nitride semiconductors with different lattice constants. Therefore, the GaN constituting the electron transit layer 71 and the nitride semiconductor (e.g., AlGaN) constituting the electron supply layer 72 form a lattice-mismatched heterojunction. Due to spontaneous polarization in the electron transit layer 71 and the electron supply layer 72 and piezoelectric polarization caused by stress applied to the electron supply layer 72 near the heterojunction interface, the energy level of the conduction band of the electron transit layer 71 near the heterojunction interface is lower than the Fermi level. As a result, a two-dimensional electron gas (2DEG) 73 spreads within the electron transit layer 71 near the heterojunction interface between the electron transit layer 71 and the electron supply layer 72 (e.g., within a range of several nanometers from the interface).

[0104] The nitride semiconductor chip 11 further includes a gate layer 74 provided on the electron supply layer 72, a gate electrode 31 provided on the gate layer 74, and a first insulating layer 81. The gate layer 74 is located between a source opening 81A and a drain opening 81B (described later) of the first insulating layer 81. The gate layer 74 is disposed apart from both the source opening 81A and the drain opening 81B. In one example, the gate layer 74 is located closer to the source opening 81A than to the drain opening 81B.

[0105] The gate layer 74 is made of a nitride semiconductor. In one example, the gate layer 74 is made of a nitride semiconductor having a band gap smaller than that of the electron supply layer 72 and containing acceptor-type impurities. In one example, the gate layer 74 is GaN doped with acceptor-type impurities (a p-type GaN layer). The acceptor-type impurities may be at least one of magnesium (Mg), zinc (Zn), and C. The maximum concentration of the acceptor-type impurities in the gate layer 74 is, for example, 7×10 １８ cm －３ 1x10 or more ２０ cm －３ It can be as follows:

[0106] The gate electrode 31 provided on the gate layer 74 includes one or more metal layers. In one example, the gate electrode 31 may be a titanium nitride (TiN) layer. In another example, the gate electrode 31 may be composed of a first metal layer made of Ti and a second metal layer made of TiN provided on the first metal layer. The gate electrode 31 may be composed of, for example, a material that forms a Schottky junction with the gate layer 74. One example of such a material is TiN. The thickness of the gate electrode 31 may be, for example, 50 nm or more and 200 nm or less.

[0107] The first insulating layer 81 is provided on the electron supply layer 72, the gate layer 74, and the gate electrode 31, and includes a source opening 81A and a drain opening 81B. Both the source opening 81A and the drain opening 81B expose the upper surface 72A of the electron supply layer 72. The nitride semiconductor chip 11 includes a source electrode 32 in contact with the upper surface 72A of the electron supply layer 72 through the source opening 81A, a drain electrode 33 in contact with the upper surface 72A of the electron supply layer 72 through the drain opening 81B, and a via 90 electrically connecting the source electrode 32 and the conductive substrate 50. Here, the source electrode 32 is an example of a "first electrode." The detailed configuration of the via 90 will be described later.

[0108] The first insulating layer 81 is made of, for example, silicon dioxide (SiO ２ ), silicon nitride (SiN), silicon oxynitride (SiON), alumina (Al ２ O ３ The first insulating layer 81 may be made of one or any combination of aluminum oxynitride (AlON), AlN, and aluminum oxynitride (AlON). The thickness of the first insulating layer 81 may be, for example, 50 nm to 200 nm, preferably 80 nm to 150 nm.

[0109] The source electrode 32 is provided on the nitride semiconductor layer 70. The source electrode 32 includes a source contact 32A including a portion that contacts the upper surface 72A of the electron supply layer 72 through the source opening 81A. The source contact 32A of the source electrode 32 fills the source opening 81A. The source contact 32A is in ohmic contact with the 2DEG 73 directly below the electron supply layer 72 through the source opening 81A. The source contact 32A has a strip shape that extends in the Y direction in a plan view. Here, the Y direction is an example of the "first direction."

[0110] The drain electrode 33 includes a drain contact 33A that contacts the upper surface 72A of the electron supply layer 72 through the drain opening 81B. The drain contact 33A of the drain electrode 33 fills the drain opening 81B. The drain contact 33A is in ohmic contact with the 2DEG 73 directly below the electron supply layer 72 through the drain opening 81B.

[0111] The source electrode 32 and the drain electrode 33 include one or more metal layers. In one example, the source electrode 32 and the drain electrode 33 may be composed of one or any combination of Ti, TiN, Al, aluminum silicon copper (AlSiCu), and aluminum copper (AlCu). In one example, the source electrode 32 and the drain electrode 33 are composed of a first metal layer in contact with the upper surface 72A of the electron supply layer 72, a second metal layer stacked on the second metal layer, a third metal layer stacked on the second metal layer, and a fourth metal layer stacked on the third metal layer. The first metal layer is, for example, a Ti layer, the second metal layer is, for example, an Al layer, the third metal layer is, for example, a Ti layer, and the fourth metal layer is, for example, a TiN layer.

[0112] In a structure in which the gate layer 74 is formed of a nitride semiconductor containing acceptor-type impurities, the conduction path (channel) is blocked by depletion of the 2DEG 73 in the region directly below the gate layer 74 at zero bias when no voltage is applied to the gate electrode 31. This realizes a normally-off HEMT in which the gate threshold voltage is a positive value.

[0113] In the example shown in FIG. 9 , the gate layer 74 includes a ridge portion 74A and a source-side extension portion 74B and a drain-side extension portion 74C that are thinner than the ridge portion 74A. The ridge portion 74A corresponds to a relatively thick portion of the gate layer 74. The gate electrode 31 is in contact with the ridge portion 74A. The ridge portion 74A may have a rectangular or trapezoidal shape in a cross section along the XZ plane. The thickness of the ridge portion 74A may be, for example, 100 nm or more and 200 nm or less. The thickness of the ridge portion 74A can be defined by the distance in the Z direction between an upper surface 74AA of the ridge portion 74A and an upper surface 72A of the electron supply layer 72. The thickness of the ridge portion 74A is determined taking into consideration various parameters such as gate breakdown voltage.

[0114] The source-side extension portion 74B and the drain-side extension portion 74C extend in opposite directions relative to the ridge portion 74A. More specifically, the source-side extension portion 74B extends from the ridge portion 74A toward the source opening 81A in the first insulating layer 81. The source-side extension portion 74B can also be said to extend from the ridge portion 74A toward the source electrode 32. The drain-side extension portion 74C extends from the ridge portion 74A toward the drain opening 81B in the first insulating layer 81. The drain-side extension portion 74C can also be said to extend from the ridge portion 74A toward the drain electrode 33.

[0115] The thickness of the source side extension 74B may be, for example, 60 nm or less. The thickness of the source side extension 74B may be, for example, 30 nm or less, 25 nm or less, 20 nm or less, or 15 nm or less. The thickness of the source side extension 74B may be, for example, 10 nm or more. The thickness of the drain side extension 74C may be, for example, 30 nm or less, 25 nm or less, 20 nm or less, or 15 nm or less. The thickness of the drain side extension 74C may be, for example, 10 nm or more. In one example, the thickness of the source side extension 74B and the thickness of the drain side extension 74C are equal to each other. Here, the thickness of the source side extension 74B can be defined by the distance in the Z direction between the upper surface 74BA of the source side extension 74B and the upper surface 72A of the electron supply layer 72. The thickness of the drain-side extension portion 74C can be defined by the distance in the Z direction between an upper surface 74CA of the drain-side extension portion 74C and an upper surface 72A of the electron supply layer 72. At least one of the source-side extension portion 74B and the drain-side extension portion 74C may be omitted from the gate layer 74.

[0116] The nitride semiconductor chip 11 includes a field plate electrode 34 provided on the first insulating layer 81. The field plate electrode 34 is electrically connected to the source electrode 32. In the example shown in FIG. 9 , the field plate electrode 34 is formed integrally with the source electrode 32. That is, a portion of the source electrode 32 is provided as the field plate electrode 34. Therefore, a voltage having the same potential as that of the source electrode 32 is applied to the field plate electrode 34. The field plate electrode 34 is also called a source field plate. The field plate electrode 34 covers the entire gate layer 74 in a plan view. The field plate electrode 34 may be provided separately from the source electrode 32. In this case, the field plate electrode 34 may be disposed apart from the source electrode 32.

[0117] The nitride semiconductor chip 11 includes a second insulating layer 82 provided on a first insulating layer 81. The second insulating layer 82 covers the source electrode 32, the drain electrode 33, and the field plate electrode 34. The second insulating layer 82 is made of, for example, SiO ２ , SiN, SiON, Al ２ O ３ , AlN, and AlON. In one example, the second insulating layer 82 is made of SiO ２ The device is made of a material containing:

[0118] Gate wiring 41, source wiring 42A to 42C, and drain wiring 43A to 43C (see FIG. 6 for all) are provided on the second insulating layer 82. Gate via 44, source via 45, and drain via 46 (see FIG. 8 for all) are provided so as to penetrate the second insulating layer 82 in the Z direction.

[0119] Although not shown, the nitride semiconductor chip 11 includes a third insulating layer provided on the second insulating layer 82. The third insulating layer covers the gate wiring 41, the source wirings 42A to 42C, and the drain wirings 43A to 43C. The third insulating layer is made of, for example, SiO ２ , SiN, SiON, Al ２ O ３, AlN, and AlON, or any combination thereof. A gate pad 21, a plurality of source pads 22, and a plurality of drain pads 23 (all of which are shown in FIG. 5) are provided on the third insulating layer.

[0120] (Conductive Substrate and High-Resistance Layer) The configurations of the conductive substrate 50 and the high-resistance layer 60 will be described with reference to Fig. 9 to Fig. 11. Fig. 10 schematically shows dislocation lines 63 in the high-resistance layer 60 and the nitride semiconductor layer 70. Fig. 11 schematically shows the bending of the dislocation lines 63 at the interface between the high-resistance layer 60 and the electron transit layer 71. Fig. 11 shows an enlarged view of the interface between the high-resistance layer 60 and the electron transit layer 71.

[0121] As shown in Fig. 9, the conductive substrate 50 is configured to have conductivity by, for example, introducing impurities into a semiconductor substrate. The conductive substrate 50 is configured from a material containing, for example, silicon (Si) or silicon carbide (SiC) as a semiconductor substrate. In one example, the conductive substrate 50 uses a SiC substrate as the semiconductor substrate. The conductive substrate 50 may be doped with, for example, nitrogen (N) as an impurity. It is preferable that the conductive substrate 50 is polycrystalline, that is, a polycrystalline SiC substrate is used. The resistance value of the conductive substrate 50 is, for example, 2 x 10 －２ It is Ωcm or less.

[0122] It should be noted that a Si substrate may be used as the conductive substrate 50 instead of a SiC substrate. Furthermore, instead of a SiC substrate or a Si substrate, a semiconductor substrate other than a substrate containing Si, such as a GaN substrate or a sapphire substrate, may be used as the conductive substrate 50. Even in this case, the conductive substrate 50 may be doped with impurities or may be polycrystalline. Furthermore, the conductive substrate 50 may be a metal layer. The metal layer may be formed of a plated layer or a sputtered film. Furthermore, the conductive substrate 50 may be formed of a metal plate.

[0123] The conductive substrate 50 has a first substrate surface 51 and a second substrate surface 52 opposite to the first substrate surface 51. In one example, the second substrate surface 52 constitutes the second chip surface 11R of the nitride semiconductor chip 11. The thickness T1 of the conductive substrate 50 is, for example, 50 μm or more. The thickness T1 of the conductive substrate 50 is, for example, 200 μm or less. In one example, the thickness T1 of the conductive substrate 50 is 100 μm. Here, the thickness T1 of the conductive substrate 50 can be defined as the distance between the first substrate surface 51 and the second substrate surface 52 in the Z direction.

[0124] The high-resistance layer 60 is provided on the first substrate surface 51 of the conductive substrate 50. More specifically, the high-resistance layer 60 is in contact with the first substrate surface 51. The high-resistance layer 60 is a layer for insulating between the conductive substrate 50 and the nitride semiconductor layer 70. Therefore, the high-resistance layer 60 is configured to have a higher resistance value than the conductive substrate 50. The high-resistance layer 60 is also configured to have a higher resistance value than the electron transit layer 71. The resistance value of the high-resistance layer 60 is, for example, 1×10 ５ The high resistance layer 60 may be irradiated with an electron beam in order to achieve high resistance.

[0125] The high-resistance layer 60 is made of GaN. The high-resistance layer 60 may be, for example, single crystal. That is, the high-resistance layer 60 may be a single-crystal GaN layer. The high-resistance layer 60 may be doped with impurities or may not be doped with impurities. In the second embodiment, the high-resistance layer 60 is doped with impurities. The impurities may be, for example, transition metal elements such as iron (Fe) or zinc (Zn), or at least one of magnesium (Mg), boron (B), and C. That is, the high-resistance layer 60 may contain at least one of the transition metal elements Mg, B, and C as impurities. In one example, the high-resistance layer 60 may contain a transition metal element. In one example, the high-resistance layer 60 may contain Mg. In one example, the high-resistance layer 60 may contain B. In one example, the high-resistance layer 60 may contain C.

[0126] The impurity concentration of the high resistance layer 60 is higher than, for example, the impurity concentration of the gate layer 74. In one example, the impurity concentration of the high resistance layer 60 is 1×10 １６ cm －３ In one example, the impurity concentration of the high resistance layer 60 is 1×10 ２０ cm －３ The following is the result.

[0127] 9 , the thickness T2 of the high-resistance layer 60 is thinner than the thickness T1 of the conductive substrate 50. The thickness T2 of the high-resistance layer 60 is thicker than the thickness T4 of the electron supply layer 72 of the nitride semiconductor layer 70. The thickness T2 of the high-resistance layer 60 is thicker than the thickness T3 of the electron transit layer 71 of the nitride semiconductor layer 70. The thickness T2 of the high-resistance layer 60 is thicker than the thickness T5 of the nitride semiconductor layer 70. In one example, the thickness T2 of the high-resistance layer 60 is 3 μm or more. In another example, the thickness T2 of the high-resistance layer 60 is 20 μm or less. Here, the thickness T2 of the high-resistance layer 60 can be defined by the distance between the first surface 61 and the second surface 62 in the Z direction.

[0128] The thickness T2 of the high-resistance layer 60 can be changed as desired. For example, the thickness T2 of the high-resistance layer 60 may be equal to or greater than the thickness T1 of the conductive substrate 50. For example, the thickness T2 of the high-resistance layer 60 may be equal to or less than the thickness T5 of the nitride semiconductor layer 70. For example, the thickness T2 of the high-resistance layer 60 may be equal to or less than the thickness T3 of the electron transit layer 71. The thickness T2 of the high-resistance layer 60 may be greater than 20 μm ... and equal to or less than 100 μm.

[0129] 10 , the high-resistance layer 60 includes dislocations (dislocation lines 63), which are a type of linear lattice defect. The dislocations in the high-resistance layer 60 may be threading dislocations that penetrate the high-resistance layer 60 in the Z direction. The dislocation lines 63 can be visually recognized by observing a cross section of the nitride semiconductor device 10 using transmission electron microscopy (TEM). The dislocation density of the high-resistance layer 60 is, for example, 1×10 ５ cm －２At least some of the multiple dislocation lines 63 may extend continuously through both the high-resistance layer 60 and the nitride semiconductor layer 70. Note that, for the sake of explanation, all of the dislocation lines 63 in the high-resistance layer 60 are depicted as being bent in FIG. 10 , but the present invention is not limited to this.

[0130] In the nitride semiconductor layer 70, the number of dislocation lines 63 passing through the interface between the electron transit layer 71 and the electron supply layer 72 (see FIG. 9 ) is smaller than the number of dislocation lines 63 passing through the interface (first surface 61) between the high-resistivity layer 60 and the electron transit layer 71. In one example, at least some of the dislocation lines 63 are bent at the interface (first surface 61) between the high-resistivity layer 60 and the electron transit layer 71, so that the bent dislocation lines 63 are bonded to each other in the electron transit layer 71. As a result, the number of dislocation lines 63 passing through the interface between the electron transit layer 71 and the electron supply layer 72 is smaller than the number of dislocation lines 63 passing through the interface (first surface 61) between the high-resistivity layer 60 and the electron transit layer 71. Therefore, the dislocation density of the nitride semiconductor layer 70 is smaller than the dislocation density of the high-resistivity layer 60. Here, the number of dislocation lines 63 passing through the interface between the electron transit layer 71 and the electron supply layer 72 and the number of dislocation lines 63 passing through the interface (first surface 61) between the high-resistance layer 60 and the electron transit layer 71 can be compared using values ​​counted in multiple cross sections at different positions on the nitride semiconductor device 10, for example.

[0131] As shown in FIG. 11 , the impurity-doped high-resistance layer 60 can be obtained by controlling the growth temperature and growth rate of the GaN layer. For example, the first surface 61 of the high-resistance layer 60 obtained by relatively lowering the growth temperature and increasing the growth rate of the GaN layer has unevenness. The growth direction of the electron transit layer 71 provided on the first surface 61 of the high-resistance layer 60 can be changed from the growth direction of the high-resistance layer 60 (e.g., the Z direction) due to such unevenness. Therefore, the propagation direction of the dislocation lines 63 can also be changed at the interface (first surface 61) between the high-resistance layer 60 and the electron transit layer 71. In the example shown in FIG. 11 , the dislocation lines 63 extend in direction D1 (e.g., the Z direction) in the high-resistance layer 60. However, in the electron transit layer 71, they extend in direction D2 (e.g., a direction perpendicular to the first surface 61) different from direction D1. If two dislocation lines 63 extending substantially parallel to each other are present in the high-resistivity layer 60, the two dislocation lines 63 will extend in different directions in the electron transit layer 71. As a result, the two dislocation lines 63 may bond with each other above the interface (first surface 61) between the high-resistivity layer 60 and the electron transit layer 71. Therefore, the number of dislocation lines 63 decreases in the electron transit layer 71 at a position closer to the electron supply layer 72.

[0132] (Via) The configuration of the via 90 will be described with reference to FIGS. 6 to 9. As shown in FIG. 9, the via 90 is in contact with the source contact 32A of the source electrode 32 and also in contact with the conductive substrate 50. In the second embodiment, the via 90 is in contact with the first substrate surface 51 of the conductive substrate 50. In this manner, the via 90 is electrically connected to both the source electrode 32 and the conductive substrate 50. Therefore, a source voltage is applied to the conductive substrate 50 through the source electrode 32 and the via 90.

[0133] The via 90 penetrates in the Z direction through the layers interposed between the source electrode 32 and the conductive substrate 50. More specifically, the via 90 penetrates in the Z direction through the nitride semiconductor layer 70 and the high-resistance layer 60. Therefore, the length LV of the via 90 is equal to the total thickness of the layers interposed between the source electrode 32 and the conductive substrate 50.

[0134] The total thickness (T2+T5) of the thickness T5 of the nitride semiconductor layer 70 and the thickness T2 of the high-resistance layer 60 can be made thinner than the thickness T1 of the conductive substrate 50. Therefore, the length LV of the via 90 can be made shorter than the thickness T1 of the conductive substrate 50. In one example, the length LV of the via 90 may be 100 μm or less. In one example, the length LV of the via 90 may be 50 μm or less.

[0135] 8, the via 90 extends in the Y direction together with the source contact 32A in a plan view. In the example shown in Fig. 8, the via 90 is slightly smaller than the source contact 32A in a plan view.

[0136] 9 , the via 90 includes a first end face 91 in contact with the source contact 32A, a second end face 92 in contact with the conductive substrate 50, and a side face 93 connecting the first end face 91 and the second end face 92. The side face 93 is in contact with the high-resistance layer 60 and the nitride semiconductor layer 70.

[0137] 6 and 7 , the nitride semiconductor device 10 is provided with a plurality of gate electrodes 31, a plurality of source electrodes 32, and a plurality of drain electrodes 33. The vias 90 are provided in correspondence with the plurality of source electrodes 32. Therefore, it can be said that the plurality of vias 90 are distributed over substantially the entire surface of the conductive substrate 50 in a plan view.

[0138] The via 90 may be made of one or more conductive materials. The conductive material may be, for example, a metal material including one or more appropriately selected from Ti, TiN, Au, Ag, Cu, Al, and W. In one example, the via 90 is made of the same material as the source electrode 32. In this case, the via 90 and the source electrode 32 may be integrally formed. In other words, the via 90 and the source electrode 32 may not have a joint surface between them.

[0139] [Method for Manufacturing Nitride Semiconductor Device] An exemplary method for manufacturing the nitride semiconductor device 10 will be described with reference to Figures 12 to 20. Figures 12 to 20 schematically show the cross-sectional structure taken along line F9-F9 in Figure 8.

[0140] As shown in FIG. 12 , the manufacturing method of the nitride semiconductor device 10 includes forming a high-resistance layer 60. In this step, a GaN substrate 800 is first prepared. The GaN substrate 800 includes a first substrate surface 801 and a second substrate surface 802 opposite to the first substrate surface 801. A release layer 810 is provided on the first substrate surface 801. The release layer 810 is made of a two-dimensional material. For example, graphene may be used as the two-dimensional material. Next, the high-resistance layer 60 is formed on the release layer 810.

[0141] The high-resistance layer 60 is formed by epitaxial growth on the GaN substrate 800 using, for example, metal organic chemical vapor deposition (MOCVD). Therefore, the high-resistance layer 60 can be made of GaN. A doping gas may be introduced into the growth chamber during the epitaxial growth of the high-resistance layer 60. This allows the high-resistance layer 60 to be doped with impurities. Here, the impurity may be, for example, at least one of a transition metal element, Mg, B, and C.

[0142] 13 , the method for manufacturing the nitride semiconductor device 10 includes forming a nitride semiconductor layer 70. This process includes forming an electron transit layer 71 and forming an electron supply layer 72 on the electron transit layer 71. Both the electron transit layer 71 and the electron supply layer 72 are formed by epitaxial growth on the high-resistance layer 60 using the MOCVD method. Because the high-resistance layer 60, the electron transit layer 71, and the electron supply layer 72 are made of nitride semiconductors with relatively similar lattice constants, they can be epitaxially grown successively.

[0143] A doping gas may be introduced into the growth chamber during the epitaxial growth of each of the electron transit layer 71 and the electron supply layer 72. This allows the desired layers to be doped with impurities. In one example, Si is doped as an n-type impurity during the epitaxial growth of the electron supply layer 72. This allows the electron supply layer 72 to be formed containing n-type impurities.

[0144] 14 , the manufacturing method of the nitride semiconductor device 10 includes peeling off the high-resistance layer 60 and the nitride semiconductor layer 70 from the GaN substrate 800. In this step, first, a holding member 820 is attached to the electron supply layer 72 of the nitride semiconductor layer 70. Next, the holding member 820 is moved to peel off the high-resistance layer 60 from the peeling layer 810 and the GaN substrate 800. In this case, if the peeling layer 810 provided on the first substrate surface 801 of the GaN substrate 800 is made of, for example, graphene, the peeling layer 810 and the high-resistance layer 60 can be easily peeled off.

[0145] As shown in FIG. 15 , the manufacturing method for the nitride semiconductor device 10 includes forming a conductive substrate 50. In one example, the conductive substrate 50 can be formed by bonding a semiconductor substrate that will become the conductive substrate 50 to the second surface 62 of the high-resistivity layer 60. The conductive substrate 50 can be, for example, a polycrystalline SiC substrate. In one example, the high-resistivity layer 60 and the nitride semiconductor layer 70 are placed on the conductive substrate 50 using a holding member 820 (see FIG. 14 ). The holding member 820 is then removed. For example, the bonding method involves irradiating the second surface 62 of the high-resistivity layer 60 with a specific impurity in a vacuum, and irradiating the surface of the semiconductor substrate that will become the conductive substrate 50 with the specific impurity in a vacuum. Then, in the vacuum where the specific impurity has been irradiated, the second surface 62 of the high-resistivity layer 60 and the surface of the semiconductor substrate (the first substrate surface 51 of the conductive substrate 50) are bonded together, followed by heat treatment. The specific impurity is an inert impurity that does not generate carriers in the high-resistivity layer 60 or the semiconductor substrate. The temperature of the heat treatment can be set depending on the materials constituting the semiconductor substrate that will become the high resistance layer 60 and the conductive substrate 50 .

[0146] In another example, the conductive substrate 50 can be formed on the second surface 62 of the high-resistivity layer 60 using a CVD method. In yet another example, the conductive substrate 50 can be formed on the second surface 62 of the high-resistivity layer 60 by electrolytic plating or electroless plating. In yet another example, the conductive substrate 50 can be a metal plate. In this case, the conductive substrate 50 is bonded to the high-resistivity layer 60.

[0147] 16 and 17 , the method for manufacturing the nitride semiconductor device 10 includes forming a via 90 in the nitride semiconductor layer 70 and the high-resistance layer 60. Forming the via 90 includes forming a through-hole 94 that penetrates the nitride semiconductor layer 70 and the high-resistance layer 60, and filling the through-hole 94 with a conductive material.

[0148] As shown in FIG. 16 , the through-hole 94 penetrates both the nitride semiconductor layer 70 and the high-resistance layer 60. Therefore, the through-hole 94 exposes the first substrate surface 51 of the conductive substrate 50. In one example, the through-hole 94 is formed by selectively removing portions of the nitride semiconductor layer 70 and the high-resistance layer 60 by lithography and etching. Here, plasma etching, for example, may be used as the etching. In another example, the through-hole 94 is formed by grinding the nitride semiconductor layer 70 and the high-resistance layer 60. Subsequently, as shown in FIG. 17 , a via 90 is formed by filling the through-hole 94 with a conductive material. A first end surface 91 of the via 90 is flush with, for example, the upper surface 72A of the electron supply layer 72.

[0149] As shown in FIG. 18 , the method for manufacturing the nitride semiconductor device 10 includes forming a gate layer 74. The gate layer 74 is formed by selectively removing a nitride semiconductor layer (not shown) formed on the electron supply layer 72 using lithography and etching. The nitride semiconductor layer can be epitaxially grown on the electron supply layer 72 using an MOCVD method. A doping gas is introduced into a growth chamber during the epitaxial growth of the nitride semiconductor layer. In one example, Mg is doped as an acceptor-type impurity during the epitaxial growth of the nitride semiconductor layer. This forms the gate layer 74 containing the acceptor-type impurity.

[0150] 19 , the method for manufacturing the nitride semiconductor device 10 includes forming a gate electrode 31 on a gate layer 74. The gate electrode 31 is formed on an upper surface 74AA of a ridge portion 74A of the gate layer 74. In one example, the gate electrode 31 is formed by selectively removing a metal layer (not shown) formed on the nitride semiconductor layer 70 and the gate layer 74 by lithography and etching.

[0151] 20 , the method for manufacturing the nitride semiconductor device 10 includes forming a first insulating layer 81, forming a source electrode 32, and forming a drain electrode 33. The method for manufacturing the nitride semiconductor device 10 also includes forming a field plate electrode 34.

[0152] In the step of forming the first insulating layer 81, an insulating layer (not shown) is first formed on the electron supply layer 72, the gate layer 74, and the gate electrode 31. This insulating layer is formed so as to cover a part of the electron supply layer 72, the gate layer 74, and the gate electrode 31. In one example, the insulating layer can be formed by using a low-pressure chemical vapor deposition (LPCVD) method.

[0153] Next, a source opening 81A exposing the electron supply layer 72 and the via 90 and a drain opening 81B exposing the electron supply layer 72 are formed in the insulating layer. The source opening 81A and the drain opening 81B are formed so that the gate layer 74 is located between the source opening 81A and the drain opening 81B. The source opening 81A and the drain opening 81B are formed by selectively removing a portion of the insulating layer using lithography and etching. This forms the first insulating layer 81.

[0154] In the step of forming the source electrode 32 , the source electrode 32 is formed so as to contact the upper surface 72 A of the electron supply layer 72 exposed from the source opening 81 A of the first insulating layer 81 and the first end surface 91 of the via 90 .

[0155] In the process of forming the field plate electrode 34, the field plate electrode 34 is formed integrally with the source electrode 32 on the first insulating layer 81. In the process of forming the drain electrode 33, the drain electrode 33 is formed so as to contact the upper surface 72A of the electron supply layer 72 exposed from the drain opening 81B of the first insulating layer 81. In one example, the source electrode 32, the drain electrode 33, and the field plate electrode 34 are formed by selectively removing a metal layer (not shown) formed to cover the first insulating layer 81 using lithography and etching. That is, the source electrode 32, the drain electrode 33, and the field plate electrode 34 are formed in a common process. The source contact 32A is formed by embedding the metal layer in the source opening 81A. The source contact 32A contacts the entire first end surface 91 of the via 90. The source contact 32A contacts the entire region of the upper surface 72A of the electron supply layer 72 exposed from the source opening 81A. Through the above processes, the nitride semiconductor device 10 is manufactured.

[0156] [Operation of Second Embodiment] The operation of the nitride semiconductor device 10 of the second embodiment will be described. In the nitride semiconductor device 10, the conductive substrate 50 has a low resistance value and can function as a back electrode to which a source voltage is applied through the source electrode 32 and the via 90. The high-resistance layer 60 can function as an insulating layer that insulates the conductive substrate 50 from the nitride semiconductor layer 70. That is, the high-resistance layer 60 can function as an insulating layer that insulates the conductive substrate 50 from the HEMT formed using the nitride semiconductor layer 70. In this case, the via 90 does not need to have a shape that penetrates the conductive substrate 50 in the Z direction, but only needs to have a shape that contacts the conductive substrate 50. On the other hand, in a configuration in which a back electrode is provided on the underside of the semiconductor substrate, the via needs to penetrate the semiconductor substrate to connect to the back electrode. Therefore, in the nitride semiconductor device 10 of the second embodiment, the length LV of the via 90 can be shortened by the thickness T1 of the conductive substrate 50, compared to a configuration in which a back electrode is provided on the underside of the semiconductor substrate. Furthermore, as a result of the shortening of the length LV of the via 90, the amount of work required to form the via 90 (such as the work of penetrating the conductive substrate 50) and costs such as time can be reduced.

[0157] [Effects of Second Embodiment] The nitride semiconductor device 10 of the second embodiment has the following effects. (2-1) The nitride semiconductor device 10 includes a conductive substrate 50 having a first substrate surface 51 and a second substrate surface 52 opposite to the first substrate surface 51, a high-resistance layer 60 provided on the first substrate surface 51 and having a resistance value higher than that of the conductive substrate 50, a nitride semiconductor layer 70 provided on the high-resistance layer 60, a source electrode 32 serving as a first electrode formed on the nitride semiconductor layer 70, and a via 90 electrically connected to the source electrode 32, penetrating the nitride semiconductor layer 70 and the high-resistance layer 60, and in contact with the conductive substrate 50. The high-resistance layer 60 is made of GaN and in contact with the first substrate surface 51.

[0158] According to this configuration, the length LV of the via 90 can be shortened by the thickness T1 of the conductive substrate 50, compared to a configuration in which a back surface electrode is provided on the lower surface of the semiconductor substrate. This reduces the cost, such as the amount of work and time required to form the via 90. In addition, the shortening of the length LV of the via 90 reduces the inductance caused by the length LV of the via 90.

[0159] Furthermore, because the high-resistance layer 60 is in contact with the conductive substrate 50, the length LV of the via 90 can be made shorter than in a configuration in which a buffer layer is provided between the high-resistance layer 60 and the conductive substrate 50. Therefore, the inductance caused by the length LV of the via 90 can be reduced.

[0160] (2-2) The high-resistance layer 60 is in contact with the nitride semiconductor layer 70. With this configuration, the length LV of the via 90 can be made shorter than in a configuration in which another layer (for example, a buffer layer) is interposed between the high-resistance layer 60 and the nitride semiconductor layer 70. Therefore, the inductance caused by the length LV of the via 90 can be reduced.

[0161] (2-3) The thickness T2 of the high-resistance layer 60 is thinner than the thickness T1 of the conductive substrate 50. With this configuration, the length LV of the via 90 can be made shorter than when the thickness T2 of the high-resistance layer 60 is equal to or greater than the thickness T1 of the conductive substrate 50. Therefore, the inductance caused by the length LV of the via 90 can be reduced.

[0162] (2-4) The thickness T2 of the high-resistance layer 60 is 3 μm or more. With this configuration, the high-resistance layer 60 can ensure insulation between the nitride semiconductor layer 70 and the conductive substrate 50.

[0163] (2-5) The thickness T2 of the high resistance layer 60 is 20 μm or less. With this configuration, the length LV of the via 90 can be shortened, and therefore the inductance caused by the length LV of the via 90 can be reduced.

[0164] (2-6) The dislocation density of the high resistance layer 60 is 1×10 ５ cm －２According to this configuration, the low dislocation density of the high-resistance layer 60 can suppress the conduction of leakage current between the first surface 61 and the second surface 62 of the high-resistance layer 60. Therefore, the leakage current of the nitride semiconductor device 10 can be reduced.

[0165] (2-7) The dislocation density of the nitride semiconductor layer 70 is lower than the dislocation density of the high-resistance layer 60. With this configuration, the low dislocation density of the nitride semiconductor layer 70 can suppress the conduction of leakage current that passes through the nitride semiconductor layer 70. Therefore, the leakage current of the nitride semiconductor device 10 can be further reduced.

[0166] (2-8) The high-resistance layer 60 contains at least one of a transition metal element, Mg, B, and C as an impurity. This configuration can increase the resistance value of the high-resistance layer 60. Therefore, the insulation between the nitride semiconductor layer 70 and the conductive substrate 50 can be improved.

[0167] (2-9) The source electrode 32 and the via 90 are made of the same material. This configuration allows for good connection between the source electrode 32 and the via 90. Therefore, an increase in electrical resistance between the source electrode 32 and the via 90 can be suppressed.

[0168] (2-10) The resistance value of the conductive substrate 50 is 2×10 －２ According to this configuration, the source electrode 32 can function as a back electrode to which a source voltage is applied through the source electrode 32 and the via 90.

[0169] (2-11) The resistance value of the high resistance layer 60 is 1×10 ５ With this configuration, the insulation between the nitride semiconductor layer 70 and the conductive substrate 50 can be improved.

[0170] (2-12) The nitride semiconductor layer 70 includes an electron transit layer 71 and an electron supply layer 72 provided on the electron transit layer 71. According to this configuration, the electron transit layer 71 and the high-resistance layer 60 are provided separately. Therefore, the resistance value of the high-resistance layer 60 can be increased, while the resistance value of the electron transit layer 71 can be reduced due to the generation of 2DEG 73.

[0171] (2-13) The thickness T2 of the high-resistance layer 60 is greater than the thickness T3 of the electron transit layer 71. This configuration can improve the insulation between the electron transit layer 71 and the conductive substrate 50.

[0172] (2-14) The source electrode 32 includes a source contact 32A that contacts the electron supply layer 72. The via 90 contacts the source contact 32A. With this configuration, the length LV of the via 90 can be shortened, and therefore, the inductance caused by the length LV of the via 90 can be reduced.

[0173] (2-15) A plurality of gate electrodes 31, source electrodes 32, and drain electrodes 33 are provided. A plurality of vias 90 are provided corresponding to the plurality of source electrodes 32. This configuration can suppress variation in source voltage depending on the location on the conductive substrate 50.

[0174] (2-16) The impurity concentration of the high-resistance layer 60 is higher than the impurity concentration of the gate layer 74. This configuration can increase the resistance value of the high-resistance layer 60. Therefore, the insulation between the nitride semiconductor layer 70 and the conductive substrate 50 can be improved.

[0175] (2-17) A method for manufacturing a nitride semiconductor device 10 includes forming a high-resistance layer 60 and a nitride semiconductor layer 70 containing GaN on a GaN substrate 800 provided with a separation layer 810, via the separation layer 810, peeling the high-resistance layer 60 and the nitride semiconductor layer 70 from the GaN substrate 800 via the separation layer 810, forming a conductive substrate 50 such that the high-resistance layer 60 is in contact with a first substrate surface 51 of the conductive substrate 50, forming a via 90 that penetrates the nitride semiconductor layer 70 and the high-resistance layer 60 and is in contact with the conductive substrate 50, and forming a source electrode 32 as a first electrode on the nitride semiconductor layer 70 so as to be in contact with the via 90. The high-resistance layer 60 is made of GaN.

[0176] According to this configuration, the length LV of the via 90 can be shortened by the thickness T1 of the conductive substrate 50, compared to a configuration in which a back surface electrode is provided on the lower surface of the semiconductor substrate. This reduces the cost, such as the amount of work and time required to form the via 90. In addition, the shortening of the length LV of the via 90 reduces the inductance caused by the length LV of the via 90.

[0177] Here, when forming the high-resistance layer 60 using a SiC substrate instead of the GaN substrate 800, it is necessary to first form a buffer layer made of AlGaN on the SiC substrate, and then form the high-resistance layer 60 on the buffer layer. The distance between the source electrode 32 and the conductive substrate 50 in the Z direction increases by the thickness of this buffer layer. As a result, the length LV of the via 90 increases.

[0178] In this regard, in the method for manufacturing the nitride semiconductor device 10 according to the second embodiment, the high-resistance layer 60 is formed using the GaN substrate 800, and therefore the high-resistance layer 60 made of GaN can be formed without forming a buffer layer. Therefore, the distance between the source electrode 32 as the first electrode and the conductive substrate 50 can be shortened, and the length LV of the via 90 can be shortened.

[0179] Furthermore, by using the GaN substrate 800 that has been peeled off from the high-resistance layer 60 and the nitride semiconductor layer 70 again to form the high-resistance layer 60 and the nitride semiconductor layer 70, in other words, by reusing the GaN substrate 800, it is possible to reduce the manufacturing cost of the nitride semiconductor device 10.

[0180] (2-18) In the method for manufacturing the nitride semiconductor device 10, forming the high-resistance layer 60 includes implanting at least one of a transition metal element, Mg, B, and C as an impurity into the high-resistance layer 60. This configuration can increase the resistance value of the high-resistance layer 60. Therefore, the insulation between the nitride semiconductor layer 70 and the conductive substrate 50 can be improved.

[0181] (2-19) In the method for manufacturing the nitride semiconductor device 10, forming the nitride semiconductor layer 70 includes forming an electron transit layer 71 and forming an electron supply layer 72 on the electron transit layer 71. The electron transit layer 71 is formed to be thinner than the high-resistance layer 60.

[0182] According to this configuration, the high resistance layer 60 can be formed thicker than the electron transit layer 71 without forming a buffer layer, thereby improving the insulation between the nitride semiconductor layer 70 and the conductive substrate 50.

[0183] (2-20) In the manufacturing method of the nitride semiconductor device 10, a SiC substrate is used as the conductive substrate 50. When forming a GaN layer (high-resistance layer) on a SiC substrate, the GaN layer cannot be formed directly on the SiC substrate; instead, a buffer layer made of AlGaN is formed first, and the GaN layer (high-resistance layer) is then formed on the buffer layer. However, in the manufacturing method of the nitride semiconductor device 10 of the second embodiment, the high-resistance layer 60 is formed using a GaN substrate 800, and then the high-resistance layer 60 is peeled off from the GaN substrate 800 and bonded to, for example, the conductive substrate 50. Therefore, the high-resistance layer 60 is formed on the conductive substrate 50 of the SiC substrate without forming a buffer layer. The time required to form the buffer layer is longer than the total time required to form the high-resistance layer 60 on the GaN substrate 800, the time required to peel off the high-resistance layer 60 from the GaN substrate 800, and the time required to bond the high-resistance layer 60 to the conductive substrate 50. This shortens the manufacturing time of the nitride semiconductor device 10, thereby reducing the manufacturing cost of the nitride semiconductor device 10. Furthermore, by using a SiC substrate as the conductive substrate 50, the cost of the conductive substrate 50 can be reduced compared to when a GaN substrate is used as the conductive substrate 50. Note that the same effect can be obtained when a Si substrate is used as the conductive substrate 50.

[0184] In addition, when a GaN layer (high resistance layer) is formed after forming a buffer layer on a SiC substrate, the dislocation density of the GaN layer (high resistance layer) is 1×10 ６ cm －２ or more or 1 x 10 cm －２ In this regard, in the method for manufacturing the nitride semiconductor device 10 according to the second embodiment, the high-resistance layer 60 is formed using the GaN substrate 800, and therefore the dislocation density of the high-resistance layer 60 is reduced. Specifically, the dislocation density of the high-resistance layer 60 is reduced to 1×10 ５ cm －２ As a result, the effect of (1-6) above can be obtained.

[0185] 21 to 23, a nitride semiconductor device 10 according to a third embodiment will be described. The nitride semiconductor device 10 according to the third embodiment differs from the nitride semiconductor device 10 according to the second embodiment mainly in the configurations of the conductive substrate 50 and the vias 90. In the following, components common to the second embodiment will be denoted by the same reference numerals, and their description may be omitted.

[0186] Fig. 21 schematically shows a cross-sectional structure of a portion of the nitride semiconductor device 10 of the third embodiment. Fig. 21 schematically shows a cross-sectional structure of the nitride semiconductor device 10 of the third embodiment taken along line F9-F9 in Fig. 8. Fig. 22 schematically shows an enlarged cross-sectional structure of the connection portion between the conductive substrate 50 and the via 90 in Fig. 21. Fig. 23 schematically shows a cross-sectional structure of the connection portion between the conductive substrate 50 and the via 90 taken along the YZ plane.

[0187] 21 , the conductive substrate 50 includes a recess 53 recessed from the first substrate surface 51 toward the second substrate surface 52. The recess 53 has a strip shape extending in the Y direction in a plan view. The recess 53 is provided to face the source contact 32A of the source electrode 32 in the Z direction. A via 90 is embedded in the recess 53. Therefore, the length LV of the via 90 is longer than the sum (T5 + T2) of the thickness T5 of the nitride semiconductor layer 70 and the thickness T2 of the high-resistance layer 60. Meanwhile, the length LV of the via 90 is shorter than the thickness T1 of the conductive substrate 50.

[0188] 22 , the recess 53 includes a bottom surface 53A, a side surface 53B, and a corner surface 53C connecting the bottom surface 53A and the side surface 53B in the X direction. The corner surface 53C is curved. A corner surface 95 that contacts the corner surface 53C is provided between a second end surface 92 of the via 90 embedded in the recess 53, the second end surface 92 contacting the bottom surface 53A, and a side surface 93 contacting the side surface 53B of the recess 53, in the X direction. The corner surface 95 has a shape that follows the corner surface 53C of the recess 53.

[0189] 23 , at the Y-direction end of the recess 53, the recess 53 includes a corner surface 53D that connects the bottom surface 53A and the side surface 53B in the Y direction. Of the vias 90 embedded in the recess 53, a corner surface 96 that contacts the corner surface 53D is provided between the Y-direction end of the second end surface 92 and the side surface 93. The corner surface 96 has a shape that follows the corner surface 53D of the recess 53.

[0190] 21 to 23 , the depth HR of the recess 53 is shallower than the thickness T2 of the high-resistance layer 60. The depth HR of the recess 53 is deeper than the thickness T4 of the electron supply layer 72. The depth HR of the recess 53 may be equal to or greater than the thickness T3 of the electron transit layer 71. The ratio (HR / T1) of the depth HR of the recess 53 to the thickness T1 of the conductive substrate 50 may be, for example, 1 / 200 or greater and 3 / 50 or less. In one example, the depth HR of the recess 53 is 3 μm or less.

[0191] In one example, the length of the recess 53 in the X direction is longer than the depth HR of the recess 53. Also, the length of the recess 53 in the Y direction is longer than the depth HR of the recess 53. As a result, the width dimension (length in the X direction) of the via 90 is longer than the length in the Z direction of the portion of the via 90 that is embedded in the conductive substrate 50. The length dimension (length in the Y direction) of the via 90 is longer than the length in the Z direction of the portion of the via 90 that is embedded in the conductive substrate 50.

[0192] [Method of Manufacturing Nitride Semiconductor Device] The method of manufacturing the nitride semiconductor device 10 of the third embodiment differs mainly in the step of forming the via 90. Forming the via 90 includes forming a through hole 94 in the nitride semiconductor layer 70 and the high-resistance layer 60, forming a recess 53 in the conductive substrate 50, and filling the through hole 94 and the recess 53 with a conductive material.

[0193] To form the through-hole 94 in the nitride semiconductor layer 70 and the high-resistance layer 60, the region where the source contact 32A of the source electrode 32 is to be formed is selectively removed by lithography and the first plasma etching. As a result, the through-hole 94 is formed.

[0194] To form the recess 53 in the conductive substrate 50, the region of the first substrate surface 51 of the conductive substrate 50 exposed by the through hole 94 is selectively removed by lithography and second plasma etching. This forms the recess 53. The etching gas used in the process of forming the recess 53 may be different from the etching gas used in the process of forming the through hole 94. That is, the etching gas used in the process of forming the through hole 94 may be a type that easily removes GaN-based materials. The etching gas used in the process of forming the recess 53 may be a type that easily removes Si-based materials. Subsequently, a conductive material is filled in the through hole 94 and the recess 53, thereby forming the via 90. The second end surface 92 of the via 90 is in contact with the bottom surface 53A of the recess 53. Note that the processes before and after the process of forming the via 90 are the same as those in the second embodiment.

[0195] Effects of the Third Embodiment The nitride semiconductor device 10 of the third embodiment has the following effects: (3-1) The conductive substrate 50 includes a recess 53 recessed from the first substrate surface 51 toward the second substrate surface 52. The via 90 is embedded in the recess 53.

[0196] According to this configuration, the via 90 comes into contact with the recess 53, thereby increasing the contact area between the via 90 and the conductive substrate 50. Therefore, the electrical connection between the via 90 and the conductive substrate 50 becomes more stable.

[0197] (3-2) Forming the via 90 includes forming a through-hole 94 that penetrates the nitride semiconductor layer 70 and the high-resistance layer 60 using a first plasma etching, and forming a recess 53 in the conductive substrate 50 using a second plasma etching. The etching gases used in the first plasma etching and the second plasma etching are different from each other.

[0198] According to this configuration, it is possible to individually select an etching gas suitable for forming the through-hole 94 and an etching gas suitable for forming the recess 53. Therefore, it is possible to suitably form each of the through-hole 94 and the recess 53.

[0199] <Application Examples of Each Embodiment> The nitride semiconductor device 10 of each embodiment can be applied to electronic devices with high frequencies (e.g., several hundred MHz or more) and large currents (e.g., several tens of A or more). Examples of electronic devices include an inverter device for driving an in-vehicle traction motor and an inverter device for driving a compressor in an air conditioner.

[0200] <Modifications> The above-described embodiments can be modified as follows: Furthermore, the above-described embodiments and the following modifications can be combined with each other to the extent that no technical contradiction occurs.

[0201] The dislocation density of the high resistance layer 60 of the second embodiment can be applied to the first embodiment. That is, in the first embodiment, the dislocation density of the high resistance layer 114 is 1×10 ５ cm －２ The dislocation density of the nitride semiconductor layer 116 may be lower than the dislocation density of the high resistance layer 114. The high resistance layer 114 may contain at least one of a transition metal element, Mg, B, and C as an impurity.

[0202] The first embodiment and the third embodiment may be combined. That is, similar to the third embodiment, the SiC substrate 112 may include a recess 53 recessed from the first substrate surface 112A toward the second substrate surface 112B. The via 140 may be embedded in the recess 53 of the SiC substrate 112.

[0203] In the second and third embodiments, the impurity concentration of the high resistance layer 60 can be changed as desired. For example, the impurity concentration of the high resistance layer 60 may be equal to or lower than the impurity concentration of the gate layer 74.

[0204] In each embodiment, the material of the high resistance layer 60, 114 is not limited to GaN and can be changed as desired. In this case, the dislocation density of the high resistance layer 60, 114 is 1×10 ５ cm －２ Preferably, the high resistance layers 60 and 114 are made of SiC.

[0205] In each embodiment, the dislocation density of the high-resistance layers 60 and 114 may be any value. For example, the dislocation density of the high-resistance layers 60 and 114 may be equal to or lower than the dislocation density of the electron transit layers 71 and 118.

[0206] In each embodiment, if the dislocation density of the electron transit layer 71, 118 is lower than the dislocation density of the high resistance layer 60, 114, the dislocation density of the high resistance layer 60, 114 is 1×10 ５ cm －２ The material forming the high resistance layers 60 and 114 is not limited to GaN.

[0207] In each embodiment, the material constituting the conductive substrate 50 (SiC substrate 112) can be changed as desired. In one example, the conductive substrate 50 (SiC substrate 112) may be made of the same material as the high-resistance layers 60, 114. In other words, if the high-resistance layers 60, 114 are made of GaN, a GaN substrate may be used as the conductive substrate 50 (SiC substrate 112).

[0208] In each embodiment, another layer may be provided between the high-resistance layer 60, 114 and the electron transit layer 71, 118. In other words, the high-resistance layer 60, 114 does not need to be in contact with the electron transit layer 71, 118.

[0209] In the second and third embodiments, as shown in Fig. 24, the high resistance layer 60 and the electron transit layer 71 may be made of the same GaN. That is, the high resistance layer 60 does not need to be doped with impurities. In this case, the nitride semiconductor layer 70 includes an electron supply layer 72. The high resistance layer 60 includes an electron transit layer 71. The first embodiment can also be modified in a similar manner.

[0210] In the second and third embodiments, as shown in Fig. 25, a plurality of vias 90 (three in Fig. 25) may be provided for one source electrode 32. The plurality of vias 90 are arranged at the same position in the X direction and spaced apart from one another in the Y direction. In one example, the plurality of vias 90 contact the source contacts 32A of the source electrode 32. Note that in the third embodiment, although not shown, a plurality of recesses 53 are provided in the conductive substrate 50 corresponding to the number of vias 90. Furthermore, in the first embodiment, a single via 140 may be provided.

[0211] In the second and third embodiments, the via 90 may be in contact with a portion of the source electrode 32 that is different from the source contact 32A. In each embodiment, the shape of the vias 90 and 140 in a plan view can be changed as desired. For example, the vias 90 and 140 may be circular in a plan view.

[0212] In the third embodiment, the shape and size of the recess 53 of the conductive substrate 50 can be changed as desired. For example, the depth HR of the recess 53 may be shallower than the thickness T3 of the electron transit layer 71. For example, the length of the recess 53 in the X direction may be equal to the depth HR of the recess 53. As a result, the width dimension (length in the X direction) of the via 90 may be equal to the length in the Z direction of the portion of the via 90 embedded in the recess 53. For example, the length of the recess 53 in the X direction may be shorter than the depth HR of the recess 53. As a result, the width dimension (length in the X direction) of the via 90 may be shorter than the length in the Z direction of the portion of the via 90 embedded in the recess 53.

[0213] In each embodiment, the source electrodes 32, 126 and the vias 90, 140 may be made of different materials. In one example, the source electrodes 32, 126 may be made of a material containing Al, and the vias 90, 140 may be made of a material containing Ti or W.

[0214] In the second and third embodiments, the configuration of the gate layer 74 can be changed as desired. In one example, at least one of the source-side extension 74B and the drain-side extension 74C may be omitted from the gate layer 74. Figure 26 shows a configuration in which both the source-side extension 74B and the drain-side extension 74C are omitted from the gate layer 74. In other words, the gate layer 74 may be formed of a ridge portion 74A.

[0215] In the second and third embodiments, the sealing resin 16 may be omitted from the nitride semiconductor device 10. In the second and third embodiments, a source wire may be used instead of the source clip 18. A drain wire may be used instead of the drain clip 19.

[0216] In the second and third embodiments, the arrangement of the gate pad 21, source pad 22, and drain pad 23 of the nitride semiconductor chip 11 can be changed as desired. In the method for manufacturing the nitride semiconductor device 10 of the third embodiment, the same type of etching gas may be used for the first plasma etching and the second plasma etching. Furthermore, the step of forming the through hole 94 and the step of forming the recess 53 may be performed as a common step. That is, for example, the through hole 94 and the recess 53 may be formed consecutively by plasma etching. In this case, the input power for the plasma etching is greater than the input power for the first plasma etching.

[0217] In the manufacturing method of the nitride semiconductor device 10 according to the second and third embodiments, the formation of the via 90 and the formation of the source electrode 32 may be performed in the same step. In other words, the via 90 and the source electrode 32 may be formed integrally.

[0218] In the first embodiment, the method for manufacturing the nitride semiconductor device 10 may be the same as the method for manufacturing the nitride semiconductor device 10 of the second embodiment. Furthermore, in the method for manufacturing the nitride semiconductor device 10, the formation of the via 140 and the formation of the source electrode 126 may be performed in the same step. In other words, the via 140 and the source electrode 126 may be formed integrally.

[0219] One or more of the various examples described in this disclosure can be combined to the extent that they are not technically inconsistent. The term "on" used in this disclosure includes the meanings of "on" and "above," unless the context clearly indicates otherwise. Thus, for example, the expression "a first element is disposed on a second element" means that in some embodiments, the first element may be in contact with the second element and disposed directly on the second element, but in other embodiments, the first element may be disposed above the second element without contacting the second element. In other words, the term "on" does not exclude a structure in which another element is formed between the first element and the second element.

[0220] The Z-axis direction used in this disclosure does not necessarily have to be the vertical direction, nor does it have to completely coincide with the vertical direction. Therefore, various structures according to this disclosure are not limited to the "up" and "down" in the Z direction described in this disclosure being "up" and "down" in the vertical direction. For example, the X direction may be the vertical direction, or the Y direction may be the vertical direction.

[0221] <Supplementary Notes> The technical ideas that can be understood from this disclosure are described below. Note that, for the purpose of aiding understanding and not intending to be limiting, the components described in the supplementary notes are given the reference numerals of the corresponding components in the above embodiment. The reference numerals are shown as examples to aid understanding, and the components described in each supplementary note should not be limited to the components indicated by the reference numerals.

[0222] [Supplementary Note 1] A conductive substrate (50 / 112) having a first substrate surface (51 / 112A) and a second substrate surface (52 / 112B) opposite to the first substrate surface (51 / 112A), a high-resistance layer (60 / 114) provided on the first substrate surface (51 / 112A) and having a resistance value higher than that of the conductive substrate (50 / 112), a nitride semiconductor layer (70 / 116) provided on the high-resistance layer (60 / 114), a first electrode (32 / 126) formed on the nitride semiconductor layer (70 / 116), and a via (90 / 140) electrically connected to the first electrode (32 / 126), passing through the nitride semiconductor layer (70 / 116) and the high-resistance layer (60 / 114) and in contact with the conductive substrate (50 / 112), The high-resistance layer (60 / 114) is made of GaN and is in contact with the first substrate surface (51 / 112A).

[0223] [Supplementary Note 2] The nitride semiconductor device according to Supplementary Note 1, wherein the high resistance layer (60 / 114) is in contact with the nitride semiconductor layer (70 / 116).

[0224] [Supplementary Note 3] The nitride semiconductor device according to Supplementary Note 1 or 2, wherein a thickness (T2 / TQ) of the high resistance layer (60 / 114) is smaller than a thickness (T1 / TP) of the conductive substrate (50 / 112).

[0225] [Supplementary Note 4] The nitride semiconductor device according to any one of Supplementary Notes 1 to 3, wherein the high resistance layer (60 / 114) has a thickness (T2 / TQ) of 3 μm or more.

[0226] [Supplementary Note 5] The nitride semiconductor device according to Supplementary Note 4, wherein the high resistance layer (60 / 114) has a thickness (T2 / TQ) of 20 μm or less.

[0227] [Note 6] The dislocation density of the high resistance layer (60 / 114) is 1×10 ５ cm －２ The nitride semiconductor device according to any one of appendices 1 to 5, wherein:

[0228] [Supplementary Note 7] The nitride semiconductor device according to any one of Supplementary Notes 1 to 6, wherein the dislocation density of the nitride semiconductor layer (70 / 116) is lower than the dislocation density of the high-resistance layer (60 / 114).

[0229] [Supplementary Note 8] The nitride semiconductor device according to any one of Supplementary Notes 1 to 7, wherein the high resistance layer (60 / 114) contains at least one of a transition metal element, Mg, B, and C as an impurity.

[0230] [Appendix 9] The nitride semiconductor device according to any one of Appendices 1 to 8, wherein the conductive substrate (50 / 112) includes a recess (53) recessed from the first substrate surface (51 / 112A) toward the second substrate surface (52 / 112B), and the via (90 / 140) is embedded in the recess (53).

[0231] [Supplementary Note 10] The nitride semiconductor device according to Supplementary Note 9, wherein the recess (53) has a depth (HR) of 3 μm or less.

[0232] [Supplementary Note 11] The nitride semiconductor device according to Supplementary Note 10, wherein the conductive substrate (50 / 112) has a thickness (T1 / TP) of 50 μm or more and 200 μm or less.

[0233] [Supplementary Note 12] The nitride semiconductor device according to any one of Supplementary Notes 1 to 11, wherein the first electrode (32 / 126) and the via (90 / 140) are made of the same material.

[0234] [Supplementary Note 13] The nitride semiconductor device according to any one of Supplementary Notes 1 to 11, wherein the first electrode (32 / 126) and the via (90 / 140) are made of different materials.

[0235] [Supplementary Note 14] The resistance value of the conductive substrate (50 / 112) is 2×10 －２ 14. The nitride semiconductor device according to any one of claims 1 to 13, wherein the resistivity is Ωcm or less.

[0236] [Supplementary Note 15] The resistance value of the high resistance layer (60 / 114) is 1×10 ５ The nitride semiconductor device according to any one of appendices 1 to 14, wherein the resistivity is Ωcm or more.

[0237] [Supplementary Note 16] The nitride semiconductor device according to any one of Supplementary Notes 1 to 15, wherein the nitride semiconductor layer (70 / 116) includes: an electron transit layer (71 / 118); and an electron supply layer (72 / 120) provided on the electron transit layer (71 / 118).

[0238] [Supplementary Note 17] The nitride semiconductor device according to Supplementary Note 16, wherein a thickness (T2 / TQ) of the high resistance layer (60 / 114) is greater than a thickness (T3 / TR) of the electron transit layer (71 / 118).

[0239] [Supplementary Note 18] The nitride semiconductor device according to Supplementary Note 16 or 17, wherein the electron transit layer (71 / 118) is made of the same material as the high resistance layer (60 / 114).

[0240] [Supplementary Note 19] The nitride semiconductor device according to any one of Supplementary Notes 16 to 18, wherein a gate electrode (31 / 110), a source electrode (32 / 126) as the first electrode, and a drain electrode (33 / 128) are provided on the electron supply layer (72 / 120), the source electrode (32 / 126) includes a source contact (32A) in contact with the electron supply layer (72 / 120), and the via (90 / 140) is in contact with the source contact (32A).

[0241] [Supplementary Note 20] The nitride semiconductor device according to any one of Supplementary Notes 1 to 19, wherein a plurality of the vias (90 / 140) are provided for the first electrode (32 / 126).

[0242] [Supplementary Note 21] The nitride semiconductor device according to any one of Supplementary Notes 1 to 20, wherein a plurality of the first electrodes (32 / 126) are provided, and a plurality of the vias (90 / 140) are provided corresponding to the plurality of first electrodes (32 / 126).

[0243] [Supplementary Note 22] The nitride semiconductor device according to Supplementary Note 19, wherein a plurality of the source electrodes (32 / 126) are provided, and a plurality of the vias (90 / 140) are in contact with the source contacts (32A) of the plurality of the source electrodes (32 / 126).

[0244] [Supplementary Note 23] The nitride semiconductor device according to Supplementary Note 22, wherein the source contact (32A) has a strip shape extending in a first direction (Y) in a plan view, and the plurality of vias (90 / 140) are arranged spaced apart in the first direction (Y).

[0245] [Supplementary Note 24] The nitride semiconductor device according to Supplementary Note 22, wherein the source contact (32A) has a strip shape extending in a first direction (Y) in a plan view, and the via (90 / 140) extends in the first direction (Y) in a plan view.

[0246] [Supplementary Note 25] The nitride semiconductor device according to any one of Supplementary Notes 1 to 24, wherein the high resistance layer (60 / 114) is made of a material different from that of the conductive substrate (50 / 112).

[0247] [Supplementary Note 26] A conductive substrate (50 / 112) having a first substrate surface (51 / 112A) and a second substrate surface (52 / 112B) opposite to the first substrate surface (51 / 112A), a high-resistance layer (60 / 114) provided on the first substrate surface (51 / 112A) and having a resistance value higher than that of the conductive substrate (50 / 112), a nitride semiconductor layer (70 / 116) provided on the high-resistance layer (60 / 114), a first electrode (32 / 126) formed on the nitride semiconductor layer (70 / 116), and a via (90 / 140) electrically connected to the first electrode (32 / 126), passing through the nitride semiconductor layer (70 / 116) and the high-resistance layer (60 / 114) and in contact with the conductive substrate (50 / 112), The conductive substrate (50 / 112) includes a recess (53) recessed from the first substrate surface (51 / 112A) toward the second substrate surface (52 / 112B), and the via (90 / 140) is embedded in the recess (53).

[0248] [Supplementary Note 27] The nitride semiconductor device according to Supplementary Note 26, wherein the depth (HR) of the recess (53) is 3 μm or less.

[0249] [Supplementary Note 28] The nitride semiconductor device according to Supplementary Note 27, wherein the conductive substrate (50 / 112) has a thickness (T1 / TP) of 50 μm or more and 200 μm or less.

[0250] [Supplementary Note 29] The nitride semiconductor device according to any one of Supplementary Notes 26 to 28, wherein the first electrode (32 / 126) and the via (90 / 140) are made of the same material.

[0251] [Supplementary Note 30] The nitride semiconductor device according to any one of Supplementary Notes 26 to 28, wherein the first electrode (32 / 126) and the via (90 / 140) are made of different materials.

[0252] [Supplementary Note 31] A conductive substrate (50 / 112) having a first substrate surface (51 / 112A) and a second substrate surface (52 / 112B) opposite to the first substrate surface (51 / 112A), a high-resistance layer (60 / 114) provided on the first substrate surface (51 / 112A) and having a resistance value higher than that of the conductive substrate (50 / 112), a nitride semiconductor layer (70 / 116) provided on the high-resistance layer (60 / 114), a first electrode (32 / 126) formed on the nitride semiconductor layer (70 / 116), and a via (90 / 140) electrically connected to the first electrode (32 / 126), passing through the nitride semiconductor layer (70 / 116) and the high-resistance layer (60 / 114) and in contact with the conductive substrate (50 / 112), The high resistance layer (60 / 114) contains at least one of a transition metal element, Mg, B, and C as an impurity.

[0253] [Supplementary Note 32] A conductive substrate (50 / 112) having a first substrate surface (51 / 112A) and a second substrate surface (52 / 112B) opposite to the first substrate surface (51 / 112A), a high-resistance layer (60 / 114) provided on the first substrate surface (51 / 112A) and having a resistance value higher than that of the conductive substrate (50 / 112), a nitride semiconductor layer (70 / 116) provided on the high-resistance layer (60 / 114), a first electrode (32 / 126) formed on the nitride semiconductor layer (70 / 116), and a via (90 / 140) electrically connected to the first electrode (32 / 126), passing through the nitride semiconductor layer (70 / 116) and the high-resistance layer (60 / 114) and in contact with the conductive substrate (50 / 112), The dislocation density of the high resistance layer (60 / 114) is 1×10 ５ cm －２ The following is a nitride semiconductor device (10).

[0254] [Supplementary Note 33] The nitride semiconductor device according to Supplementary Note 32, wherein the dislocation density of the nitride semiconductor layer (70 / 116) is lower than the dislocation density of the high resistance layer (60 / 114).

[0255] [Supplementary Note 34] A conductive substrate (50 / 112) having a first substrate surface (51 / 112A) and a second substrate surface (52 / 112B) opposite to the first substrate surface (51 / 112A), a high-resistance layer (60 / 114) provided on the first substrate surface (51 / 112A) and having a resistance value higher than that of the conductive substrate (50 / 112), a nitride semiconductor layer (70 / 116) provided on the high-resistance layer (60 / 114), a first electrode (32 / 126) formed on the nitride semiconductor layer (70 / 116), and a via (90 / 140) electrically connected to the first electrode (32 / 126), passing through the nitride semiconductor layer (70 / 116) and the high-resistance layer (60 / 114) and in contact with the conductive substrate (50 / 112), The nitride semiconductor layer (70 / 116) has a dislocation density lower than the dislocation density of the high-resistance layer (60 / 114).

[0256] [Supplementary Note 35] The nitride semiconductor device according to any one of Supplementary Notes 31 to 34, wherein the high resistance layer (60 / 114) is in contact with the nitride semiconductor layer (70 / 116).

[0257] [Supplementary Note 36] The nitride semiconductor device according to any one of Supplementary Notes 31 to 35, wherein the high resistance layer (60 / 114) has a thickness (T2 / TQ) of 3 μm or more.

[0258] [Supplementary Note 37] The nitride semiconductor device according to Supplementary Note 36, wherein the high resistance layer (60 / 114) has a thickness (T2 / TQ) of 20 μm or less.

[0259] [Supplementary Note 38] The nitride semiconductor device according to any one of Supplementary Notes 31 to 37, wherein the nitride semiconductor layer (70 / 116) includes: an electron transit layer (71 / 118); and an electron supply layer (72 / 120) provided on the electron transit layer (71 / 118), wherein a gate electrode (31 / 110), a source electrode (32 / 126) serving as the first electrode, and a drain electrode (33 / 128) are provided on the electron supply layer (72 / 120), and the via (90 / 140) is electrically connected to the source electrode (32 / 126).

[0260] [Supplementary Note 39] The nitride semiconductor device according to Supplementary Note 38, wherein a thickness (T2 / TQ) of the high resistance layer (60 / 114) is greater than a thickness (T3 / TR) of the electron transit layer (71 / 118).

[0261] [Supplementary Note 40] The nitride semiconductor device according to Supplementary Note 38 or 39, wherein the electron transit layer (71 / 118) is made of the same material as the high resistance layer (60 / 114).

[0262] [Supplementary Note 41] The nitride semiconductor device according to any one of Supplementary Notes 31 to 40, wherein the high resistance layer (60 / 114) is made of a material different from that of the conductive substrate (50 / 112).

[0263] [Appendix 42] The nitride semiconductor device according to any one of Appendices 1 to 41, comprising: a nitride semiconductor chip (11) including the conductive substrate (50), the high-resistance layer (60), the nitride semiconductor layer (70), and the via (90); a die pad (12) on which the nitride semiconductor chip (11) is mounted; terminals (13 / 14 / 15) electrically connected to the nitride semiconductor chip (11); and a sealing resin (16) that seals the nitride semiconductor chip (11) and also seals a portion of each of the die pad (12) and the terminals (13 / 14 / 15).

[0264] [Appendix 43] The nitride semiconductor device according to Appendix 42, wherein the sealing resin (16) includes a first sealing surface (16S) and a second sealing surface (16R) opposite the first sealing surface (16S), and each of the die pad (12) and the terminals (13 / 14 / 15) is exposed from the second sealing surface (16R).

[0265] [Supplementary Note 44] The nitride semiconductor device according to Supplementary Note 19, further comprising: a gate layer (74) provided on the electron supply layer (72), having a band gap smaller than that of the electron supply layer (72), and containing an acceptor-type impurity; the gate electrode (31) provided on the gate layer (74); the high-resistance layer (60) containing at least one of a transition metal element, Mg, B, and C as an impurity; and an impurity concentration of the high-resistance layer (60) higher than an impurity concentration of the gate layer (74).

[0266] [Appendix 45] A method for manufacturing a nitride semiconductor device (10), comprising: forming a high-resistance layer (60) and a nitride semiconductor layer (70) containing GaN on a GaN substrate (800) provided with a release layer (810) via the release layer (810); peeling the high-resistance layer (60) and the nitride semiconductor layer (70) from the release layer (810) and the GaN substrate (800); forming a conductive substrate (50) so as to be in contact with the high-resistance layer (60); forming a via (90) that penetrates the nitride semiconductor layer (70) and the high-resistance layer (60) and is in contact with the conductive substrate (50); and forming a first electrode (32) on the nitride semiconductor layer (70) so as to be in contact with the via (90), wherein the high-resistance layer (60) is made of GaN.

[0267] [Appendix 46] The method for manufacturing a nitride semiconductor device according to appendix 45, wherein forming the high resistance layer (60) includes implanting at least one of a transition metal element, Mg, B, and C as an impurity into the high resistance layer (60).

[0268] [Supplementary Note 47] The method for manufacturing a nitride semiconductor device according to Supplementary Note 45 or 46, wherein forming the nitride semiconductor layer (70) includes forming an electron transit layer (71); and forming an electron supply layer (72) on the electron transit layer (71), wherein the electron transit layer (71) is formed to be thinner than the high-resistance layer (60).

[0269] [Supplementary Note 48] The method for manufacturing a nitride semiconductor device according to Supplementary Note 45, wherein forming the via (90) and forming the first electrode (32) are carried out in the same step.

[0270] [Appendix 49] The method for manufacturing a nitride semiconductor device according to any one of Appendices 45 to 48, wherein forming the via (90) includes: forming a through hole (94) that penetrates the nitride semiconductor layer (70) and the high-resistance layer (60) and exposes the conductive substrate (50); and filling the through hole (94) with a metal material.

[0271] [Supplementary Note 50] The method for manufacturing a nitride semiconductor device according to Supplementary Note 49, wherein forming the via (90) includes forming a recess (53) in the conductive substrate (50) that communicates with the through hole (94), and embedding the metal material in the through hole (94) includes embedding the metal material in the recess (53).

[0272] [Appendix 51] The method for manufacturing a nitride semiconductor device according to Appendix 50, wherein forming the via (90) includes: forming the through hole (94) penetrating the nitride semiconductor layer (70) and the high-resistance layer (60) using a first plasma etching; and forming the recess (53) in the conductive substrate (50) using a second plasma etching, wherein the etching gas used in the first plasma etching and the etching gas used in the second plasma etching are different from each other.

[0273] The above description is merely illustrative. Those skilled in the art will recognize that many more possible combinations and permutations are possible other than the components and methods (manufacturing processes) listed for the purpose of illustrating the technology of the present disclosure. The present disclosure is intended to embrace all alternatives, modifications, and variations that fall within the scope of the present disclosure, including the claims.

[0274] DESCRIPTION OF SYMBOLS 10...Nitride semiconductor device 11...Nitride semiconductor chip 11S...First chip surface 11R...Second chip surface 11A to 11D...First to fourth chip side surfaces 12...Die pad 13...Gate terminal 14...Source terminal 15...Drain terminal 16...Sealing resin 16S...First sealing surface 16R...Second sealing surface 16A to 16D...First to fourth sealing side surfaces 17...Gate wire 18...Source clip 19...Drain clip 21...Gate pad 22...Source pad 23...Drain pad 23E...End drain pad 31...Gate electrode 32...Source electrode 32A...Source contact 33...Drain electrode 33A...Drain contact 34...Field plate electrode 41...Gate wiring 41A...Peripheral gate wiring 41B...Intermediate gate wiring 41C...Pad connection portion 41D...Peripheral wiring portion 42A to 42C...Source wiring 43A to 43C...Drain wiring 44...Gate via 45...Source via 46...Drain via 50...Conductive substrate 51...First substrate surface 52...Second substrate surface 53...Recess 53A...Bottom surface 53B...Side surface 53C, 53D...Corner surface 60...High resistance layer 61...First surface 62...Second surface 63...Dislocation line 70...Nitride semiconductor layer 71...Electron transit layer 72...Electron supply layer 72A...Upper surface 73...Two-dimensional electron gas (2DEG) 74...Gate layer 74A...Ridge portion 74AA...Upper surface 74B...Source side extension portion 74BA...Upper surface 74C...Drain side extension portion 74CA...Upper surface 81...First insulating layer 81A...Source opening 81B...Drain opening 82...Second insulating layer 90...Via 91...First end surface 92...Second end surface 93...Side surface 94...Through hole 95,96...Corner surface 102...Insulating layer 104...Source wiring 104A...Base portion 104B...Source finger 106...Drain wiring 106A...Base portion 106B...Drain finger 108...Gate wiring 110...Gate electrode 112...SiC substrate 112A...First substrate surface 112B...Second substrate surface 114...High resistance layer 114A...First surface 114B...Second surface 116...Nitride semiconductor layer 118...Electron transit layer 120...Electron supply layer 122...Two-dimensional electron gas (2DEG) 124...First insulating layer 124A...Source contact opening 124B...Drain contact opening 124C...Gate contact opening 126...Source electrode 126A...Source contact 128...Drain electrode 130...Second insulating layer 130A...First opening 130B...second opening 140...via 141...first end face 142...second end face 143...side face 800...GaN substrate 801...first substrate surface 802...second substrate surface 810...peeling layer (two-dimensional material) 820...holding member TN...nitride transistor TA...first transistor cell TB...second transistor cell TC...third transistor cell SD...conductive bonding material RC...corner region T1...thickness of conductive substrate T2...thickness of high resistance layer T3...thickness of electron transit layer T4...thickness of electron supply layer T5...thickness of nitride semiconductor layer TP...thickness of SiC substrate TQ...thickness of high resistance layer TR...thickness of electron transit layer TS...thickness of electron supply layer TT...thickness of nitride semiconductor layer D1, D2...direction DA...first direction DB...second direction LV...length of via LU...length of via HR: depth of recess,

Claims

1. A nitride semiconductor device comprising: a conductive substrate having a first substrate surface and a second substrate surface opposite to the first substrate surface; a high-resistivity layer provided on the first substrate surface and having a resistance higher than that of the conductive substrate; a nitride semiconductor layer provided on the high-resistivity layer; a first electrode formed on the nitride semiconductor layer; and a via electrically connected to the first electrode, passing through the nitride semiconductor layer and the high-resistivity layer and in contact with the conductive substrate, wherein the high-resistivity layer is made of GaN and in contact with the first substrate surface.

2. The nitride semiconductor device according to claim 1, wherein the high resistance layer is in contact with the nitride semiconductor layer.

3. The nitride semiconductor device according to claim 1 or 2, wherein the thickness of said high resistance layer is thinner than the thickness of said conductive substrate.

4. The nitride semiconductor device according to any one of claims 1 to 3, wherein the high resistance layer has a thickness of 3 μm or more.

5. The nitride semiconductor device according to claim 4, wherein the high resistance layer has a thickness of 20 μm or less.

6. The dislocation density of the high resistance layer is 1×10 ５ cm －２ The nitride semiconductor device according to any one of claims 1 to 5, wherein:

7. The nitride semiconductor device according to any one of claims 1 to 6, wherein the dislocation density of said nitride semiconductor layer is lower than the dislocation density of said high resistance layer.

8. The nitride semiconductor device according to any one of claims 1 to 7, wherein the high resistance layer contains at least one of a transition metal element, Mg, B, and C as an impurity.

9. The nitride semiconductor device according to any one of claims 1 to 8, wherein the conductive substrate includes a recess recessed from the first substrate surface toward the second substrate surface, and the via is embedded in the recess.

10. The nitride semiconductor device according to claim 9, wherein the depth of the recess is 3 μm or less.

11. The nitride semiconductor device according to claim 10, wherein the conductive substrate has a thickness of 50 μm or more and 200 μm or less.

12. The nitride semiconductor device according to any one of claims 1 to 11, wherein the first electrode and the via are made of the same material.

13. The nitride semiconductor device according to any one of claims 1 to 11, wherein the first electrode and the via are made of different materials.

14. The resistance of the conductive substrate is 2 x 10 －２ The nitride semiconductor device according to any one of claims 1 to 13, wherein the resistivity is Ωcm or less.

15. The resistance value of the high resistance layer is 1×10 ５ The nitride semiconductor device according to any one of claims 1 to 14, wherein the resistivity is Ωcm or more.

16. The nitride semiconductor device according to any one of claims 1 to 15, wherein the nitride semiconductor layer includes: an electron transit layer; and an electron supply layer provided on the electron transit layer.

17. The nitride semiconductor device according to claim 16, wherein the high resistance layer is thicker than the electron transit layer.

18. The nitride semiconductor device according to claim 16 or 17, wherein the electron transit layer is made of the same material as the high resistance layer.

19. The nitride semiconductor device according to any one of claims 16 to 18, wherein a gate electrode, a source electrode as the first electrode, and a drain electrode are provided on the electron supply layer, the source electrode includes a source contact in contact with the electron supply layer, and the via is in contact with the source contact.

20. A method for manufacturing a nitride semiconductor device, comprising: forming a high-resistance layer containing GaN and a nitride semiconductor layer on a GaN substrate having a release layer provided thereon, via the release layer; peeling the high-resistance layer and the nitride semiconductor layer from the release layer and the GaN substrate; forming a conductive substrate so as to be in contact with the high-resistance layer; forming a via that penetrates the nitride semiconductor layer and the high-resistance layer and is in contact with the conductive substrate; and forming a first electrode on the nitride semiconductor layer so as to be in contact with the via, wherein the high-resistance layer is composed of GaN.

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