Substrate with built-in capacitor and multi-terminal capacitor

Abstract

Provided is a substrate with a built-in capacitor having an improved noise reduction effect. A substrate 100A with a built-in capacitor has an IC mounted thereon, and comprises a multi-terminal capacitor 1A that has a first internal electrode layer 21 and a second internal electrode layer that are embedded in the substrate and face each other, and has at least five terminals 41, 42, wherein the multi-terminal capacitor 1A is connected to the IC so that at least a portion of a DC electric current of an electric power supply of the IC flows through the first internal electrode layer 21 of the multi-terminal capacitor 1A.

Description

Capacitor-embedded board and multi-terminal capacitor

[0001] The present invention relates to a capacitor-embedded substrate and a multi-terminal capacitor.

[0002] Patent Document 1 discloses a via array type capacitor and a wiring board having a built-in via array type capacitor. This via array type capacitor includes: a laminate formed by stacking a plurality of dielectric layers; a first internal electrode layer and a second internal electrode layer disposed inside the laminate and facing each other with the dielectric layer sandwiched therebetween; a plurality of first conductor vias disposed inside the laminate, extending in the stacking direction, and electrically connected to the first internal electrode layer; a plurality of second conductor vias disposed inside the laminate, extending in the stacking direction, and electrically connected to the second internal electrode layer; a plurality of first external electrodes disposed on a first main surface and a second main surface of the laminate, and connected to the plurality of first conductor vias, respectively; and a plurality of second external electrodes disposed on the first main surface and a second main surface of the laminate, and connected to the plurality of second conductor vias, respectively.

[0003] In a wiring board incorporating this via array type capacitor, the via array type capacitor is used as a decoupling capacitor for the power supply of an IC mounted on the first main surface side of the wiring board, the power supply wiring on the motherboard side is connected to the first external electrode and second external electrode on the second main surface, and the power supply wiring on the IC side is connected to the first external electrode and second external electrode on the first main surface.

[0004] Furthermore, Patent Document 2 discloses a bridge die including a silicon capacitor and a substrate incorporating the bridge die including the silicon capacitor. In this capacitor-embedded substrate, the silicon capacitor is used as a capacitor for decoupling the power supplies of two ICs that the bridge die spans.

[0005] Japanese Patent No. 5,139,171 U.S. Patent No. 10,886,228

[0006] In the via array capacitor disclosed in Patent Document 1, the DC current of the IC's power supply flows through the conductive vias, resulting in a low noise reduction effect. For example, noise generated in the IC is transmitted to the motherboard and radiated outside the IC package. Furthermore, noise from the motherboard may be transmitted to the IC, causing the IC to malfunction.

[0007] Furthermore, in the capacitor-embedded substrate disclosed in Patent Document 2, noise generated in one IC may propagate through the power supply wiring and be transmitted to the other IC, causing the other IC to malfunction.

[0008] An object of the present invention is to provide a capacitor-embedded substrate and a multi-terminal capacitor that have an improved noise reduction effect.

[0009] After extensive research, the present inventors have discovered a new method for connecting a multi-terminal capacitor to a power supply wiring to reduce noise. Specifically, the inventors discovered that noise can be reduced by connecting the internal electrode layers of the multi-terminal capacitor in series between the power supply wiring and allowing the DC current of the power supply to flow through the internal electrode layers of the multi-terminal capacitor. Therefore, a new configuration for a multi-terminal capacitor that achieves this type of multi-terminal capacitor connection and a substrate incorporating such a multi-terminal capacitor are devised below. Note that the invention of the following multi-terminal capacitor-embedded substrate also includes the invention of a new connection structure for a conventional multi-terminal capacitor, such as that described in Patent Document 1.

[0010] The capacitor-embedded substrate of the present invention is a substrate on which an IC is mounted, and is equipped with a multi-terminal capacitor embedded therein, having first and second internal electrode layers facing each other, and having at least five terminals, and the multi-terminal capacitor is connected to the IC so that at least a portion of the DC current of the power supply of the IC flows through the first internal electrode layer of the multi-terminal capacitor.

[0011] A multi-terminal capacitor according to the present invention comprises: a laminate formed by stacking a plurality of dielectric layers and having a first main surface and a second main surface opposing each other in a stacking direction; a first internal electrode layer and a second internal electrode layer disposed inside the laminate and opposing each other in the stacking direction with at least one dielectric layer of the plurality of dielectric layers sandwiched therebetween; a plurality of first conductor vias disposed inside the laminate, extending in the stacking direction, electrically connected to the first internal electrode layers, and electrically insulated from the second internal electrode layers; a plurality of second conductor vias disposed inside the laminate, extending in the stacking direction, electrically insulated from the first internal electrode layers, and electrically connected to the second internal electrode layers; a plurality of first external electrodes disposed on at least one of the first main surface and the second main surface, and connected to the plurality of first conductor vias, respectively; and a plurality of second external electrodes disposed on at least one of the first main surface and the second main surface, and connected to the plurality of second conductor vias, respectively, wherein the plurality of first conductor vias are a first-main-surface unconnected conductor via that does not extend to the first main surface and is not connected to one of the plurality of first external electrodes at the first main surface, and extends to the second main surface and is connected to one of the plurality of first external electrodes at the second main surface; and a second-main-surface unconnected conductor via that extends to the first main surface and is connected to one of the plurality of first external electrodes at the first main surface, does not extend to the second main surface, and is not connected to one of the plurality of first external electrodes at the second main surface, wherein each of the plurality of second conductor vias extends from the first main surface to the second main surface and is connected to one of the plurality of second external electrodes at the first main surface and the second main surface.

[0012] Another multi-terminal capacitor according to the present invention comprises: a laminate formed by stacking a plurality of dielectric layers and having a first main surface and a second main surface opposing each other in a stacking direction; a first internal electrode layer and a second internal electrode layer disposed inside the laminate and opposing each other in the stacking direction with at least one dielectric layer of the plurality of dielectric layers sandwiched therebetween; a plurality of first conductor vias disposed inside the laminate, extending in the stacking direction, electrically connected to the first internal electrode layers, and electrically insulated from the second internal electrode layers; a plurality of second conductor vias disposed inside the laminate, extending in the stacking direction, electrically insulated from the first internal electrode layers, and electrically connected to the second internal electrode layers; a plurality of first external electrodes disposed on at least one of the first main surface and the second main surface, and connected to the plurality of first conductor vias, respectively; and a plurality of second external electrodes disposed on at least one of the first main surface and the second main surface, and connected to the plurality of second conductor vias, respectively, wherein the plurality of first conductor vias are The semiconductor device includes: conductor vias that extend from the first main surface to the second main surface and are connected to one of the plurality of first external electrodes on the first main surface and the second main surface; and second main surface unconnected conductor vias that extend to the first main surface and are connected to one of the plurality of first external electrodes on the first main surface, but do not extend to the second main surface and are not connected to one of the plurality of first external electrodes on the second main surface, wherein each of the plurality of second conductor vias extends from the first main surface to the second main surface and is connected to one of the plurality of second external electrodes on the first main surface and the second main surface.

[0013] Furthermore, as a result of extensive research, the inventors of the present invention have discovered a new method for connecting a multi-terminal capacitor to a power supply wiring to reduce noise. Specifically, the inventors have discovered that noise can be reduced by connecting the internal electrode layers of the multi-terminal capacitor in series between the power supply wiring so that the AC current of the power supply flows through the internal electrode layers of the multi-terminal capacitor. Therefore, the following is a devised circuit board incorporating a multi-terminal capacitor that realizes such a multi-terminal capacitor connection.

[0014] The capacitor-embedded substrate of the present invention is a substrate on which two ICs are mounted, and is equipped with a multi-terminal capacitor embedded therein, having first and second internal electrode layers facing each other, and having at least five terminals, and the multi-terminal capacitor is connected to the two ICs so that at least a portion of the AC current of a power supply propagating between the two ICs flows through the first internal electrode layer of the multi-terminal capacitor.

[0015] Another capacitor-embedded substrate according to the present invention is a bridge-type substrate placed across two ICs, having first and second internal electrode layers facing each other and including a multi-terminal capacitor having at least five terminals, the multi-terminal capacitor being connected to the two ICs so that at least a portion of the AC current of a power supply propagating between the two ICs flows through the first internal electrode layer of the multi-terminal capacitor.

[0016] According to the present invention, it is possible to enhance the noise reduction effect in IC packaging technology.

[0017] FIG. 1B is a cross-sectional view of a multi-terminal capacitor according to a first embodiment; FIG. 1C is a cross-sectional view of a multi-terminal capacitor according to a second embodiment; FIG. 1D is a cross-sectional view of a conventional multi-terminal capacitor; FIG. 1E is a plan view of a first internal electrode layer in the multi-terminal capacitor shown in FIG. 1A; FIG. 1F is a plan view of a second internal electrode layer in the multi-terminal capacitor shown in FIG. 1A; FIG. 1G is a cross-sectional view of a multi-terminal capacitor according to a first embodiment; FIG. 1H is a cross-sectional view of a multi-terminal capacitor according to a second embodiment; FIG. 1H is a cross-sectional view of a multi-terminal capacitor according to a first embodiment; FIG. 1I is a cross-sectional view of a multi-terminal capacitor according to a first embodiment; FIG. 1I is a cross-sectional view of a multi-terminal capacitor according to a second embodiment; FIG. 4A is a cross-sectional view of a multi-terminal capacitor according to a first embodiment; FIG. 4B is a cross-sectional view of a multi-terminal capacitor according to a first embodiment; FIG. 4B is a cross-sectional view of a multi-terminal capacitor according to a second embodiment; FIG. 4A is a cross-sectional view of a multi-terminal capacitor according to a first embodiment; 1B is a schematic diagram showing the current at each part of the multi-terminal capacitor of the present invention in FIG. 1B with the connection structure shown in FIG. 4B. FIG. 4D is a schematic diagram showing the current at each part of the multi-terminal capacitor of the present invention in FIG. 1B with the connection structure shown in FIG. 4D. FIG. 4G is a schematic diagram showing the current at each part of the conventional multi-terminal capacitor in FIG. 1C with the connection structure shown in FIG. 4G. FIG. 4G is a simulation result of the power passing characteristic S21 of the multi-terminal capacitor of the first embodiment, the second embodiment described later, and the conventional multi-terminal capacitor. FIG. 4G is a simulation result of the impedance characteristic Z11 as viewed from the IC side of the multi-terminal capacitor of the first embodiment, the second embodiment described later, and the conventional multi-terminal capacitor. FIG. 4G is a schematic cross-sectional view of the capacitor-embedded substrate of the first embodiment. FIG. 4G is a schematic cross-sectional view of the capacitor-embedded substrate of the second embodiment. FIG. 4G is a schematic cross-sectional view of the multi-terminal capacitor according to the modified example. FIG. 4G is a schematic cross-sectional view of the capacitor-embedded substrate of the modified example.

[0018] An example of an embodiment of the present invention will be described below with reference to the accompanying drawings, in which the same or equivalent parts are designated by the same reference numerals.

[0019] [Multi-Terminal Capacitor] (First Embodiment) FIG. 1A is a cross-sectional schematic diagram of a multi-terminal capacitor according to a first embodiment. FIG. 2 is a plan view of a first internal electrode layer in the multi-terminal capacitor shown in FIG. 1A, and FIG. 3 is a plan view of a second internal electrode layer in the multi-terminal capacitor shown in FIG. 1A. Note that the cross-sectional schematic diagram of FIG. 1A is a cross-sectional schematic diagram along line IA-IA shown in FIGS. 2 and 3, and the number of first conductive vias and second conductive vias is omitted. Furthermore, the number of first conductive vias and second conductive vias is not limited to this in FIGS. 2 and 3. As shown in FIG. 1A, the multi-terminal capacitor 1A of the first embodiment includes a laminate 10, a plurality of first internal electrode layers 21 and a plurality of second internal electrode layers 22, a plurality of first conductive vias 31 and a plurality of second conductive vias 32, a plurality of first external electrodes (terminals) 41 and a plurality of second external electrodes (terminals) 42. The multi-terminal capacitor 1A has at least five terminals.

[0020] The laminate 10 has a substantially rectangular parallelepiped shape and has a first main surface S1 and a second main surface S2 that face each other in a stacking direction T. The laminate 10 has a plurality of dielectric layers 12 stacked in the stacking direction T.

[0021] The material of the dielectric layer 12 is not particularly limited, but may be, for example, BaTiO ３ , CaTiO ３ , SrTiO ３ , or CaZrO ３ A dielectric ceramic containing, as a main component, a Mn compound, an Fe compound, a Cr compound, a Co compound, a Ni compound, or the like may be added as a secondary component to the material of the dielectric layer 12.

[0022] The first internal electrode layers 21 and the second internal electrode layers 22 are arranged inside the laminate 10. The first internal electrode layers 21 and the second internal electrode layers 22 are arranged alternately in the stacking direction T of the laminate 10, and face each other with at least one dielectric layer 12 sandwiched between them. The shapes of the first internal electrode layers 21 and the second internal electrode layers 22 are not particularly limited, but may be, for example, substantially rectangular. The first internal electrode layers 21 and the second internal electrode layers 22 generate electrostatic capacitance and essentially function as capacitors.

[0023] As shown in Fig. 2, the first internal electrode layer 21 has a plurality of through holes 21A. Also, as shown in Fig. 3, the second internal electrode layer 22 has a plurality of through holes 22A. In a plan view along the first main surface S1 and the second main surface S2, the through holes 21A and the through holes 22A are arranged at approximately equal intervals, and the through holes 21A and the through holes 22A do not overlap.

[0024] The first internal electrode layer 21 and the second internal electrode layer 22 are not particularly limited, but may contain, for example, metal Ni as a main component. Furthermore, the first internal electrode layer 21 and the second internal electrode layer 22 may contain, for example, at least one selected from metals such as Cu, Ag, Pd, or Au, or alloys containing at least one of these metals, such as an Ag-Pd alloy, as a main component, or may contain the metal as a component other than the main component. In this specification, the metal of the main component is defined as the metal component with the highest weight percentage.

[0025] The first conductor via 31 and the second conductor via 32 are disposed inside the laminate 10 and extend in the stacking direction T of the laminate 10. The first conductor via 31 is electrically connected to the first internal electrode layer 21 and is electrically insulated from the second internal electrode layer 22 at the through hole 22A. The second conductor via 32 is electrically insulated from the first internal electrode layer 21 at the through hole 21A and is electrically connected to the second internal electrode layer 22.

[0026] The first conductive vias 31 include a first-surface unconnected conductive via 31A and a second-surface unconnected conductive via 31B. The first-surface unconnected conductive via 31A extends to the second main surface S2, is exposed on the second main surface S2, and is connected to the first external electrode 41 on the second main surface S2. On the other hand, the first-surface unconnected conductive via 31A does not extend to the first main surface S1, is not exposed on the first main surface S1, and is not connected to the first external electrode 41 on the first main surface S1.

[0027] The second-main-surface unconnected conductive via 31B extends to the first main surface S1, is exposed on the first main surface S1, and is connected to the first external electrode 41 on the first main surface S1. On the other hand, the second-main-surface unconnected conductive via 31B does not extend to the second main surface S2, is not exposed on the second main surface S2, and is not connected to the first external electrode 41 on the second main surface S2.

[0028] On the other hand, the second conductor via 32 extends from the first main surface S1 to the second main surface S2, is exposed on the first main surface S1 and the second main surface S2, and is connected to the second external electrode 42 on the first main surface S1 and the second main surface S2. This makes it possible to stabilize the GND potential.

[0029] The first conductor vias 31 and the second conductor vias 32 are arranged adjacent to each other in an alternating manner, and the direction of the current flowing through the first conductor via 31 is opposite to the direction of the current flowing through the adjacent second conductor via 32, so that the magnetic field generated by the current flowing through the first conductor via 31 and the magnetic field generated by the current flowing through the adjacent second conductor via 32 cancel each other out, thereby reducing the equivalent series inductance ESL.

[0030] The first conductor via 31 and the second conductor via 32 are not particularly limited, but may contain, for example, metal Ni as a main component, similar to the first internal electrode layer 21 and the second internal electrode layer 22. Furthermore, the first conductor via 31 and the second conductor via 32 may contain, for example, at least one selected from metals such as Cu, Ag, Pd, or Au, or alloys containing at least one of these metals, such as an Ag—Pd alloy, as a main component, or may contain this as a component other than the main component.

[0031] 1A, 2, 3, and the drawings described later are schematic diagrams, and the numbers of first conductive vias 31 and second conductive vias 32 are not limited to those shown.

[0032] The first external electrode (terminal) 41 is disposed at the position of the first-main-surface unconnected conductor via 31A on the second main surface S2, and is connected to the first-main-surface unconnected conductor via 31A of the first conductor via 31. The first external electrode 41 is disposed at the position of the second-main-surface unconnected conductor via 31B on the first main surface S1, and is connected to the second-main-surface unconnected conductor via 31B of the first conductor via 31. The second external electrode (terminal) 42 is disposed at the position of the second conductor via 32 on the first and second main surfaces S and S2, and is connected to the second conductor via 32.

[0033] The number of first external electrodes 41 on the first main surface S1 may be different from the number of first external electrodes 41 on the second main surface S2. Furthermore, the first external electrodes 41 may be embedded in the first main surface S1 and the second main surface S2, and the second external electrodes 42 may be embedded in the first main surface S1 and the second main surface S2.

[0034] The first external electrode 41 and the second external electrode 42 are not particularly limited, but may contain, for example, metal Cu as a main component. The first external electrode 41 and the second external electrode 42 may contain, as a main component, or as a component other than the main component, at least one selected from metals such as Ni, Ag, Pd, or Au, or alloys such as Ag-Pd alloys. The first external electrode 41 and the second external electrode 42 are conductor pads formed from a fired film, a vapor-deposited film, or a plated film. The first external electrode 41 and the second external electrode 42 may include conductor bumps formed on the conductor pads.

[0035] Here, a conventional multi-terminal capacitor as disclosed in Patent Document 1 will be described. Fig. 1C is a schematic cross-sectional view of the conventional multi-terminal capacitor. The conventional multi-terminal capacitor 1X shown in Fig. 1C differs from the multi-terminal capacitor 1A of the first embodiment shown in Fig. 1A in that it includes first conductor vias 31X instead of the first conductor vias 31, i.e., the first main surface unconnected conductor vias 31A and the second main surface unconnected conductor vias 31B. The first conductor vias 31X extend from the first main surface S1 to the second main surface S2, are exposed on the first main surface S1 and the second main surface S2, and are connected to first external electrodes 41 on the first main surface S1 and the second main surface S2.

[0036] 4G is a cross-sectional view showing an example of a connection structure of the conventional multi-terminal capacitor of FIG. 1C in a conventional capacitor-embedded substrate. As shown in FIG. 4G, the first conductive vias 31X and the second conductive vias 32 on the second main surface S2 of the multi-terminal capacitor 1X are connected to the power supply wiring VDD and VSS on the motherboard side, and the first conductive vias 31X and the second conductive vias 32 on the first main surface S1 of the multi-terminal capacitor 1X are connected to the power supply wiring VDD and VSS on the IC side. At this time, a current flows through the multi-terminal capacitor 1X as shown by the arrows.

[0037] Fig. 5D is a schematic diagram showing currents in the respective portions (1) to (3) of the conventional multi-terminal capacitor of Fig. 1C having the connection structure shown in Fig. 4G. Note that Fig. 5D is a schematic diagram, and the number of first conductive vias 31 and second conductive vias 32 has been omitted. As shown in Fig. 4D, the respective portions (1) to (3) are (1) the vicinity of the second main surface S2 of the first conductive via 31 of the multi-terminal capacitor 1X, (2) the first internal electrode layer 21 of the multi-terminal capacitor 1X, and (3) the vicinity of the first main surface S1 of the first conductive via 31 of the multi-terminal capacitor 1X. Figure 5D shows (1) a DC current flowing near the second main surface S2 of the first conductor via 31 of the multi-terminal capacitor 1X, (2) a DC current flowing in the first internal electrode layer 21 of the multi-terminal capacitor 1X, (3) an AC current from the IC side flowing in the first internal electrode layer 21 of the multi-terminal capacitor 1X, and (3) a DC current flowing near the first main surface S1 of the first conductor via 31 of the multi-terminal capacitor 1X.

[0038] As shown in (1) of Figure 5D, in the multi-terminal capacitor 1X, current is input to all of the first conductor vias 31, and as shown in (3) of Figure 5D, in the multi-terminal capacitor 1X, current is output from all of the first conductor vias 31.

[0039] As shown in (2) AC current from the IC side in the multi-terminal capacitor 1X, the AC current from the IC side flows through the first internal electrode layer 21 from the first conductive via 31 toward the adjacent second conductive via 32. This provides a noise reduction effect. On the other hand, as shown in (2) DC current in the multi-terminal capacitor 1X, the DC current passes only through the first conductive via 31 and does not flow through the first internal electrode layer 21.

[0040] In this conventional multi-terminal capacitor 1X, DC current flows only through the first conductive vias 31X, resulting in a low noise reduction effect. For example, noise generated in the IC is transmitted to the motherboard and radiated outside the IC package. Furthermore, noise from the motherboard may be transmitted to the IC, causing the IC to malfunction.

[0041] 4A is a cross-sectional schematic diagram showing an example of a connection structure of the multi-terminal capacitor of FIG. 1A in a capacitor-embedded substrate of the present invention. As shown in FIG. 4A, first-main-surface unconnected conductive vias 31A and second conductor vias 32 of first conductor vias 31 on second main surface S2 of multi-terminal capacitor 1A are connected to power supply wiring VDD and VSS of the motherboard, and second-main-surface unconnected conductive vias 31B and second conductor vias 32 of first conductor vias 31 on first main surface S1 of multi-terminal capacitor 1A are connected to power supply wiring VDD and VSS of the IC. At this time, current flows through multi-terminal capacitor 1A as shown by the arrows.

[0042] Fig. 5A is a schematic diagram showing currents in the respective portions (1) to (3) of the multi-terminal capacitor of the first embodiment of the connection structure shown in Fig. 4A. Note that Fig. 5A is a schematic diagram, and the numbers of the first conductive vias 31 and the second conductive vias 32 are omitted. As shown in Fig. 4A, the respective portions (1) to (3) are: (1) the vicinity of the second main surface S2 of the first-main-surface unconnected conductive via 31A of the first conductive via 31 of the multi-terminal capacitor 1A; (2) the first internal electrode layer 21 of the multi-terminal capacitor 1A; and (3) the vicinity of the first main surface S1 of the second-main-surface unconnected conductive via 31B of the first conductive via 31 of the multi-terminal capacitor 1A. Figure 5A shows (1) a DC current flowing near the second main surface S2 of the first main surface unconnected conductor via 31A of the first conductor via 31 of the multi-terminal capacitor 1A, (2) a DC current flowing in the first internal electrode layer 21 of the multi-terminal capacitor 1A, (3) an AC current from the IC side flowing in the first internal electrode layer 21 of the multi-terminal capacitor 1A, and (3) a DC current flowing near the first main surface S1 of the second main surface unconnected conductor via 31B of the first conductor via 31 of the multi-terminal capacitor 1A.

[0043] As shown in (1) of Fig. 5A, in the multi-terminal capacitor 1A, current is input to the first main surface unconnected conductive vias 31A of the first conductive vias 31, and as shown in (3) of Fig. 5A, in the multi-terminal capacitor 1A, current is output from the second main surface unconnected conductive vias 31B of the first conductive vias 31. Note that in the multi-terminal capacitor 1A of the first embodiment, the number of input first conductive vias 31 on the second main surface S2 side is reduced, and the number of output first conductive vias 31 on the first main surface S1 side is reduced, compared to the conventional multi-terminal capacitor 1X.

[0044] As shown in (2) AC Current from the IC Side in Fig. 5A, in the multi-terminal capacitor 1A, the AC current from the IC side flows through the first internal electrode layer 21 from the first conductive via 31 toward the adjacent second conductive via 32. This provides a noise reduction effect. For example, noise generated in the IC and noise from the motherboard are reduced. Note that in the multi-terminal capacitor 1A of the first embodiment, the number of AC current paths is reduced compared to the conventional multi-terminal capacitor 1X.

[0045] 5A (2) DC current, in the multi-terminal capacitor 1A, DC current flows through the first internal electrode layer 21 from the first main surface unconnected conductive via 31A of the first conductive via 31 to the second main surface unconnected conductive via 31B. This enhances the noise reduction effect. For example, noise generated in the IC and noise from the motherboard are reduced.

[0046] As described above, according to the multi-terminal capacitor 1A of the first embodiment, the first internal electrode layers 21 are interposed in series between the power supply wirings, and the DC current of the power supply flows through the first internal electrode layers 21. This enhances the noise reduction effect. For example, it is possible to prevent noise generated in the IC from being transmitted to the motherboard and radiated outside the IC package. It is also possible to prevent noise from being transmitted from the motherboard to the IC, causing the IC to malfunction.

[0047] The effects described above will be considered below through simulations. Fig. 6A shows the results of simulations of the power passing characteristics S21 of the first embodiment, the second embodiment (described later), and the conventional multi-terminal capacitor, and Fig. 6B shows the results of simulations of the impedance characteristics Z11 as viewed from the IC side of the first embodiment, the second embodiment (described later), and the conventional multi-terminal capacitor.

[0048] In the simulation, a three-dimensional electromagnetic field analysis tool, Ansys HFSS, was used to obtain the power passing characteristic S21 and the impedance characteristic Z11 seen from the IC side. The materials used in the simulation were as follows: Dielectric layer: BaTiO ３ First internal electrode layer and second internal electrode layer: Ni First conductor via and second conductor via: Ni First external electrode and second external electrode: Ni

[0049] 6A, the power passing characteristic S21 of the multi-terminal capacitor 1A of the first embodiment is lower on the high frequency side than that of the conventional multi-terminal capacitor 1X. This shows that the multi-terminal capacitor 1A of the first embodiment has a higher noise reduction effect (noise filtering effect) than the conventional multi-terminal capacitor 1X.

[0050] 6B, the impedance characteristic Z11 and equivalent series resistance ESR of the multi-terminal capacitor 1A of the first embodiment as viewed from the IC side are higher on the high frequency side compared to the conventional multi-terminal capacitor 1X. This shows that the power supply decoupling effect (impedance reduction, power supply stabilization) of the multi-terminal capacitor 1A of the first embodiment is lower compared to the conventional multi-terminal capacitor 1X. In other words, the multi-terminal capacitor 1A of the first embodiment has a lower power supply decoupling effect in exchange for an improved noise filtering effect.

[0051] Second Embodiment Fig. 1B is a cross-sectional schematic diagram of a multi-terminal capacitor according to a second embodiment. The multi-terminal capacitor 1B of the second embodiment shown in Fig. 1B differs from the multi-terminal capacitor 1A of the first embodiment shown in Fig. 1A in that it includes a conductor via 31C instead of the first-main-surface unconnected conductor via 31A of the first conductor via 31. The conductor via 31C extends from the first main surface S1 to the second main surface S2, is exposed on the first main surface S1 and the second main surface S2, and is connected to the first external electrode 41 on the first main surface S1 and the second main surface S2.

[0052] In this way, the first conductor via 31 may be a combination of the second main surface unconnected conductor via 31B of the first conductor via 31 of the multi-terminal capacitor 1A of the first embodiment and a conductor via 31C corresponding to the first conductor via 31X of the conventional multi-terminal capacitor 1X.

[0053] 4B is a cross-sectional view showing an example of a connection structure of the multi-terminal capacitor of FIG. 1B in a capacitor-embedded substrate of the present invention. As shown in FIG. 4B, conductor via 31C of first conductor via 31 on second main surface S2 of multi-terminal capacitor 1B and second conductor via 32 are connected to the power supply wiring VDD and VSS of the motherboard, and second-main-surface unconnected conductor via 31B and conductor via 31C of first conductor via 31 on first main surface S1 of multi-terminal capacitor 1B, as well as second conductor via 32, are connected to the power supply wiring VDD and VSS of the IC. At this time, current flows through multi-terminal capacitor 1B as shown by the arrows.

[0054] Fig. 5B is a schematic diagram showing currents in portions (1) to (3) of a multi-terminal capacitor according to a second embodiment of the connection structure shown in Fig. 4B. Note that Fig. 5B is a schematic diagram, and the number of first conductive vias 31 and second conductive vias 32 has been omitted. As shown in Fig. 4B, the portions (1) to (3) are (1) the vicinity of the second main surface S2 of the conductor via 31C of the first conductor via 31 of the multi-terminal capacitor 1B, (2) the first internal electrode layer 21 of the multi-terminal capacitor 1B, and (3) the vicinity of the first main surface S1 of the second main surface unconnected conductor via 31B and the conductor via 31C of the first conductor via 31 of the multi-terminal capacitor 1B. Figure 5B shows (1) a DC current flowing near the second main surface S2 of the conductor via 31C of the first conductor via 31 of the multi-terminal capacitor 1B, (2) a DC current flowing in the first internal electrode layer 21 of the multi-terminal capacitor 1B, (3) an AC current from the IC side flowing in the first internal electrode layer 21 of the multi-terminal capacitor 1B, and (3) a DC current flowing near the first main surface S1 of the second main surface unconnected conductor via 31B and conductor via 31C of the first conductor via 31 of the multi-terminal capacitor 1B.

[0055] 5B (1), in the multi-terminal capacitor 1B, current is input to the conductor via 31C in the first conductor via 31, and as shown in Fig. 5B (3), in the multi-terminal capacitor 1B, current is output from the second main surface unconnected conductor via 31B and the conductor via 31C in the first conductor via 31. Note that in the multi-terminal capacitor 1B of the first embodiment, the number of first conductor vias 31 at the input on the second main surface S2 side is the same as in the multi-terminal capacitor 1A of the first embodiment, and the number of first conductor vias 31 at the output on the first main surface S1 side is increased.

[0056] As shown in (2) AC Current from the IC Side in Fig. 5B, in the multi-terminal capacitor 1B, the AC current from the IC side flows through the first internal electrode layer 21 from the first conductive via 31 toward the adjacent second conductive via 32. This provides a noise reduction effect. For example, noise generated in the IC and noise from the motherboard are reduced. Note that in the multi-terminal capacitor 1B of the second embodiment, the number of AC current paths is increased compared to the multi-terminal capacitor 1A of the first embodiment.

[0057] On the other hand, as shown in (2) DC current in FIG. 5B , in the multi-terminal capacitor 1B, the DC current passes through the conductor via 31C of the first conductor via 31 and flows through the first internal electrode layer 21 from the conductor via 31C of the first conductor via 31 toward the second-main-surface unconnected conductor via 31B. This enhances the noise reduction effect. For example, noise generated in the IC and noise from the motherboard are reduced. Note that the multi-terminal capacitor 1B of the second embodiment has fewer DC current paths than the multi-terminal capacitor 1A of the first embodiment.

[0058] In the multi-terminal capacitor 1B of the second embodiment, the first internal electrode layers 21 are also interposed in series between the power supply wirings, so that the DC current of the power supply flows through the first internal electrode layers 21. This enhances the noise reduction effect. For example, it is possible to prevent noise generated in the IC from being transmitted to the motherboard and radiated outside the IC package. It is also possible to prevent noise from being transmitted from the motherboard to the IC, causing the IC to malfunction.

[0059] The above-mentioned effects will be considered below through simulations. As shown in Fig. 6A, the power passing characteristics S21 of the multi-terminal capacitor 1B of the second embodiment are lower on the high frequency side compared to the conventional multi-terminal capacitor 1X. This shows that the multi-terminal capacitor 1B of the second embodiment has a higher noise reduction effect (noise filtering effect) compared to the conventional multi-terminal capacitor 1X.

[0060] 6B , the impedance characteristic Z11 and equivalent series resistance ESR seen from the IC side of the multi-terminal capacitor 1B of the second embodiment are equivalent to those of the conventional multi-terminal capacitor 1X on the high frequency side, which shows that the power supply decoupling effect (impedance reduction, power supply stabilization) of the multi-terminal capacitor 1B of the second embodiment is equivalent to that of the conventional multi-terminal capacitor 1X.

[0061] Furthermore, compared to the multi-terminal capacitor 1A of the first embodiment, the impedance characteristic Z11 and equivalent series resistance ESR of the multi-terminal capacitor 1B of the second embodiment as viewed from the IC side are lower on the high-frequency side. This shows that the power supply decoupling effect (impedance reduction, power supply stabilization) of the multi-terminal capacitor 1B of the second embodiment is higher than that of the multi-terminal capacitor 1A of the first embodiment. That is, in the multi-terminal capacitor 1B of the second embodiment, the first conductive vias 31 are combined with the second-main-surface unconnected conductive vias 31B of the first conductive vias 31 of the multi-terminal capacitor 1A of the first embodiment and the conductor vias 31C corresponding to the first conductive vias 31X of the conventional multi-terminal capacitor 1X. This improves the noise filtering effect without reducing the impedance characteristic Z11 and equivalent series resistance ESR as viewed from the IC side.

[0062] (Variation of the Second Embodiment) Fig. 4D is a cross-sectional schematic diagram showing an example of a connection structure of the multi-terminal capacitor of Fig. 1B in a capacitor-embedded substrate of the present invention. As shown in Fig. 4D, second-main-surface unconnected conductor vias 31B and a portion of conductor vias 31C of first conductor vias 31 on first main surface S1 of multi-terminal capacitor 1B may be connected to one power supply wiring VDD, and conductor vias 31C of first conductor vias 31 on first main surface S1 of multi-terminal capacitor 1B that are not connected to one power supply wiring VDD may be connected to the other power supply wiring VDD. In this case, a current flows through multi-terminal capacitor 1B as shown by the arrows.

[0063] Fig. 5C is a schematic diagram showing currents in portions (1) to (3) of a multi-terminal capacitor according to a second embodiment of the connection structure shown in Fig. 4D. Note that Fig. 5C is a schematic diagram, and the number of first conductive vias 31 and second conductive vias 32 has been omitted. As shown in Fig. 4D, the portions (1) to (3) are (1) the vicinity of the second main surface S2 of the conductor via 31C of the first conductor via 31 of the multi-terminal capacitor 1B, (2) the first internal electrode layer 21 of the multi-terminal capacitor 1B, and (3) the vicinity of the first main surface S1 of the second main surface non-connected conductor via 31B and the conductor via 31C of the first conductor via 31 of the multi-terminal capacitor 1B. Figure 5C shows (1) a DC current flowing near the second main surface S2 of the conductor via 31C of the first conductor via 31 of the multi-terminal capacitor 1B, (2) a DC current flowing in the first internal electrode layer 21 of the multi-terminal capacitor 1B, (3) an AC current from the IC side flowing in the first internal electrode layer 21 of the multi-terminal capacitor 1B, and (3) a DC current flowing near the first main surface S1 of the second main surface unconnected conductor via 31B and conductor via 31C of the first conductor via 31 of the multi-terminal capacitor 1B.

[0064] According to (3) of Figure 5C, in the multi-terminal capacitor 1B, current is input to a part of the first conductor via 31 on the first main surface S1, and current is output from another part of the first conductor via 31 on the first main surface S1.

[0065] As shown in (2) AC Current from the IC Side in Fig. 5C, in the multi-terminal capacitor 1B, the AC current from the IC side flows through the first internal electrode layer 21 from the first conductive via 31 to the adjacent second conductive via 32. This provides a noise reduction effect. For example, noise generated in the IC and noise from the motherboard are reduced.

[0066] On the other hand, as shown in (2) DC current in Fig. 5C, in the multi-terminal capacitor 1B, the DC current flows through the first internal electrode layer 21 from one part of the first conductive via 31 to another part. This enhances the noise reduction effect. For example, noise generated in the IC and noise from the motherboard are reduced.

[0067] In the multi-terminal capacitor 1B having the connection structure according to this modified example of the second embodiment, the first internal electrode layers 21 are also interposed in series between the power supply wirings, so that the DC current of the power supply flows through the first internal electrode layers 21. This enhances the noise reduction effect. For example, it is possible to prevent noise generated in the IC from being transmitted to the motherboard and radiated outside the IC package. It is also possible to prevent noise from the motherboard from being transmitted to the IC and causing the IC to malfunction.

[0068] [Substrate with built-in capacitors] Chiplet technology is attracting attention as an IC packaging technology. Chiplet technology is a technology in which, instead of integrating a large-scale integrated circuit (IC) onto a single chip, the large-scale integrated circuit (IC) is separated into multiple small chips (chiplets), and these chips are mounted and combined on a substrate (package substrate, interposer, etc.) to form a single IC package.

[0069] In chiplet technology, the power supply voltages for multiple processors (ICs) are different, which makes the power wiring on the board complex. To address this issue, it is possible to install voltage regulators (ICs) near the processors (ICs) on the board and unify the power supply voltages supplied to the voltage regulators. In this case, capacitors for decoupling and switching noise filtering are required near the voltage regulators and processors. Therefore, we devised a capacitor-embedded board with capacitors embedded inside.

[0070] First Embodiment A capacitor-embedded substrate according to a first embodiment will be described with reference to Fig. 7A and Fig. 4A to Fig. 4F. Fig. 7A is a schematic diagram of the capacitor-embedded substrate according to the first embodiment.

[0071] The capacitor-embedded substrate 100A shown in Fig. 7A is a package substrate used in an IC package. ICs such as a voltage regulator VR and a processor are mounted on the capacitor-embedded substrate 100A via conductor bumps. The IC package is mounted on a motherboard, and thus the motherboard (not shown) is placed on the side of the capacitor-embedded substrate 100A opposite the IC-mounted surface.

[0072] An inductor L and multi-terminal capacitors 1 and 2 that constitute a voltage regulator VR are embedded inside the capacitor-embedded substrate 100A. The multi-terminal capacitors 1A and 1B of the present invention described above are applied to the multi-terminal capacitor 1. The conventional multi-terminal capacitor 1X described above may also be applied to the multi-terminal capacitor 1. On the other hand, the multi-terminal capacitor 1B of the present invention described above is applied to the multi-terminal capacitor 2. The conventional multi-terminal capacitor 1X and multi-terminal capacitor 1Y described above may also be applied to the multi-terminal capacitor 2. The multi-terminal capacitors 1 and 2 have at least five terminals.

[0073] The multi-terminal capacitor 1 is disposed in a position overlapping the voltage regulator VR, i.e., directly below the voltage regulator VR, in a plan view along the main surface of the capacitor-embedded substrate 100A. The external electrode on the second main surface of the multi-terminal capacitor 1 is connected to the power supply wiring of the motherboard, and the external electrode on the first main surface of the multi-terminal capacitor 1 is connected to the power supply wiring for the input of the voltage regulator VR. This enhances the noise reduction effect. For example, switching noise generated by the voltage regulator VR is suppressed near the noise source, preventing the switching noise from being transmitted to the motherboard and radiated outside the IC package.

[0074] On the other hand, the multi-terminal capacitor 2 is arranged in a position overlapping the processor, i.e., directly below the processor, in a plan view along the main surface of the capacitor-embedded substrate 100A. An external electrode on the first main surface of the multi-terminal capacitor 2 is connected to the power supply wiring for the output of the voltage regulator VR, and an external electrode on the first main surface of the multi-terminal capacitor 2 is connected to the power supply wiring for the processor's power supply. This enhances the noise reduction effect. For example, switching noise generated by the voltage regulator VR is suppressed, preventing the switching noise from being transmitted to the processor and causing it to malfunction.

[0075] 4A, the capacitor-embedded substrate 100A has a core substrate 101 and a wiring layer 102. In the vicinity of the multi-terminal capacitor 1 of the capacitor-embedded substrate 100A, power supply wiring VDD and VSS (GND) are arranged on the wiring layer 102 on the motherboard side, and power supply wiring VDD and VSS (GND) are arranged on the wiring layer 102 on the voltage regulator VR (IC) side.

[0076] When the above-described multi-terminal capacitor 1A of the present invention is applied as the multi-terminal capacitor 1, the power supply wiring VDD on the motherboard side is connected via the first external electrode 41 and the conductor via to the first-main-surface unconnected conductor via 31A of the first conductor vias 31 on the second main surface S2 of the multi-terminal capacitor 1. The power supply wiring VSS on the motherboard side is connected to the second conductor via 32 on the second main surface S2 of the multi-terminal capacitor 1 via the second external electrode 42 and the conductor via.

[0077] The power supply wiring VDD on the voltage regulator VR(IC) side is connected via a first external electrode 41 and a conductor via to a second main surface unconnected conductor via 31B of the first conductor via 31 on the first main surface S1 of the multi-terminal capacitor 1. The power supply wiring VSS on the voltage regulator VR(IC) side is connected to a second conductor via 32 on the first main surface S1 of the multi-terminal capacitor 1 via a second external electrode 42 and a conductor via.

[0078] This causes a portion of the first internal electrode layer 21 of the multi-terminal capacitor 1 to be interposed in series between the power supply wiring VDD on the motherboard side and the power supply wiring VDD on the voltage regulator VR (IC) side. As a result, as shown by the arrow, at least a portion of the DC current of the power supply input to the voltage regulator VR (IC) flows through the first internal electrode layer 21 of the multi-terminal capacitor 1. This enhances the noise reduction effect. For example, switching noise generated in the voltage regulator VR is suppressed near the noise source, preventing the switching noise from being transmitted to the motherboard and radiated outside the IC package.

[0079] In a plan view along the first main surface S1 and the second main surface S2, the positions of the first external electrodes 41 on the first main surface S1 connected to the power supply wiring VDD are offset from the positions of the first external electrodes 41 on the second main surface S2 connected to the power supply wiring VDD. Furthermore, the number of first external electrodes 41 on the first main surface S1 connected to the power supply wiring VDD is different from the number of first external electrodes 41 on the second main surface S2 connected to the power supply wiring VDD. Furthermore, the total number of first external electrodes 41 and second external electrodes 42 arranged on the first main surface S1 is greater than the total number of first external electrodes 41 and second external electrodes 42 arranged on the second main surface S2.

[0080] Examples of materials for the core substrate 101 include known materials such as glass epoxy, and examples of materials for the wiring layer 102 include known materials such as epoxy resin. The power supply wiring VDD, VSS is composed of conductor patterns and conductor vias formed on the wiring layer 102. Examples of materials for the conductor patterns and conductor vias include known metal materials such as Cu.

[0081] 4B , when the multi-terminal capacitor 1B of the present invention described above is used as the multi-terminal capacitor 1, the power supply wiring VDD on the motherboard side is connected to the conductor via 31C of the first conductor via 31 on the second main surface S2 of the multi-terminal capacitor 1 via the first external electrode 41 and the conductor via. The power supply wiring VSS on the motherboard side is connected to the second conductor via 32 on the second main surface S2 of the multi-terminal capacitor 1 via the second external electrode 42 and the conductor via.

[0082] The power supply wiring VDD on the voltage regulator VR(IC) side is connected via a first external electrode 41 and a conductor via to a second main surface unconnected conductor via 31B of the first conductor via 31 on the first main surface S1 of the multi-terminal capacitor 1. The power supply wiring VSS on the voltage regulator VR(IC) side is connected to a second conductor via 32 on the first main surface S1 of the multi-terminal capacitor 1 via a second external electrode 42 and a conductor via.

[0083] This causes a portion of the first internal electrode layer 21 of the multi-terminal capacitor 1 to be interposed in series between the power supply wiring VDD on the motherboard side and the power supply wiring VDD on the voltage regulator VR (IC) side. As a result, as shown by the arrow, at least a portion of the DC current of the power supply of the voltage regulator VR (IC) flows through the first internal electrode layer 21 of the multi-terminal capacitor 1. This enhances the noise reduction effect. For example, switching noise generated in the voltage regulator VR is suppressed near the noise source, preventing the switching noise from being transmitted to the motherboard and radiated outside the IC package.

[0084] In a plan view along the first main surface S1 and the second main surface S2, the positions of the first external electrodes 41 on the first main surface S1 connected to the power supply wiring VDD are offset from the positions of the first external electrodes 41 on the second main surface S2 connected to the power supply wiring VDD. Furthermore, the number of first external electrodes 41 on the first main surface S1 connected to the power supply wiring VDD is different from the number of first external electrodes 41 on the second main surface S2 connected to the power supply wiring VDD. Furthermore, the total number of first external electrodes 41 and second external electrodes 42 arranged on the first main surface S1 is greater than the total number of first external electrodes 41 and second external electrodes 42 arranged on the second main surface S2.

[0085] 4C , when the above-described conventional multi-terminal capacitor 1X is used as the multi-terminal capacitor 1, the power supply wiring VDD on the motherboard side is connected via a first external electrode 41X and a conductor via to a part of the first conductor via 31X on the second main surface S2 of the multi-terminal capacitor 1. The power supply wiring VSS on the motherboard side is connected to the second conductor via 32 on the second main surface S2 of the multi-terminal capacitor 1 via a second external electrode 42 and a conductor via.

[0086] The power supply wiring VDD on the voltage regulator VR(IC) side is connected, via a first external electrode 41 and a conductor via, to a first conductor via 31X on the first main surface S1 of the multi-terminal capacitor 1 that is not connected to the power supply wiring VDD on the motherboard side on the second main surface S2. The power supply wiring VSS on the voltage regulator VR(IC) side is connected to a second conductor via 32 on the first main surface S1 of the multi-terminal capacitor 1, via a second external electrode 42 and a conductor via.

[0087] This causes a portion of the first internal electrode layer 21 of the multi-terminal capacitor 1 to be interposed in series between the power supply wiring VDD on the motherboard side and the power supply wiring VDD on the voltage regulator VR (IC) side. As a result, as shown by the arrow, at least a portion of the DC current of the power supply of the voltage regulator VR (IC) flows through the first internal electrode layer 21 of the multi-terminal capacitor 1. This enhances the noise reduction effect. For example, switching noise generated in the voltage regulator VR is suppressed near the noise source, preventing the switching noise from being transmitted to the motherboard and radiated outside the IC package.

[0088] On the other hand, as shown in FIG. 4D , in the vicinity of the multi-terminal capacitor 2 of the capacitor-embedded substrate 100A, the wiring layer 102 on the voltage regulator VR and processor (IC) side has the power supply wiring VDD, VSS (GND) on the voltage regulator VR side and the power supply wiring VDD, VSS (GND) on the processor side, and only the power supply wiring VSS (GND) is arranged on the wiring layer 102 on the motherboard side.

[0089] When the multi-terminal capacitor 1B of the present invention described above is used as the multi-terminal capacitor 2, the power supply wiring VDD on the voltage regulator VR side is connected to first-main-surface unconnected conductor vias 31A and a portion of conductor vias 31C of the first conductor vias 31 on the first main surface S1 of the multi-terminal capacitor 2 via a first external electrode 41 and a conductor via. The power supply wiring VDD on the processor side is connected to conductor vias 31C of the first conductor vias 31 on the first main surface S1 of the multi-terminal capacitor 2 that are not connected to the power supply wiring VDD on the voltage regulator VR side via a first external electrode 41 and a conductor via. The power supply wiring VSS on the voltage regulator VR and processor side is connected to second conductor vias 32 on the first main surface S1 of the multi-terminal capacitor 2 via a second external electrode 42 and a conductor via. The power supply wiring VSS on the motherboard side is connected to second conductor vias 32 on the second main surface S2 of the multi-terminal capacitor 2 via a second external electrode 42 and a conductor via.

[0090] As a result, a portion of the first internal electrode layer 21 of the multi-terminal capacitor 2 is interposed in series between the power supply wiring VDD on the voltage regulator (IC) side and the power supply wiring VDD on the processor (IC) side. As a result, as shown by the arrow, at least a portion of the DC current of the power supply of the processor (IC) flows through the first internal electrode layer 21 of the multi-terminal capacitor 2. This can enhance the noise reduction effect. For example, switching noise generated in the voltage regulator VR can be suppressed, and the switching noise can be prevented from being transmitted to the processor, causing the processor to malfunction.

[0091] 4E , when the conventional multi-terminal capacitor 1X described above is used as the multi-terminal capacitor 2, the power supply wiring VDD on the voltage regulator VR side is connected to a portion of the first conductive vias 31X on the first main surface S1 of the multi-terminal capacitor 2 via a first external electrode 41 and a conductive via. The power supply wiring VDD on the processor side is connected to the first conductive vias 31X on the first main surface S1 of the multi-terminal capacitor 2 that are not connected to the power supply wiring VDD on the voltage regulator VR side via a first external electrode 41 and a conductive via. The power supply wiring VSS on the voltage regulator VR and processor side is connected to the second conductive vias 32 on the first main surface S1 of the multi-terminal capacitor 2 via a second external electrode 42 and a conductive via. The power supply wiring VSS on the motherboard side is connected to the second conductive vias 32 on the second main surface S2 of the multi-terminal capacitor 2 via a second external electrode 42 and a conductive via.

[0092] This causes a portion of the first internal electrode layer 21 of the multi-terminal capacitor 2 to be interposed in series between the power supply wiring VDD on the voltage regulator (IC) side and the power supply wiring VDD on the processor (IC) side. As a result, as shown by the arrow, at least a portion of the DC current of the power supply for the processor (IC) flows through the first internal electrode layer 21 of the multi-terminal capacitor 2. This enhances the noise reduction effect. For example, switching noise generated in the voltage regulator VR is suppressed, and it is possible to prevent the switching noise from being transmitted to the processor and causing it to malfunction.

[0093] 4F, the multi-terminal capacitor 2 in FIG. 4E may be a multi-terminal capacitor 1Y instead of the multi-terminal capacitor 1X. The multi-terminal capacitor 1Y includes a first conductive via 31Y instead of the first conductive via 31X in the multi-terminal capacitor 1X. The first conductive via 31Y differs from the first conductive via 31X in that it does not extend to the second main surface S2, is not exposed on the second main surface S2, and is not connected to the first external electrode 41 on the second main surface S2.

[0094] 4F , when a multi-terminal capacitor 1Y is used as the multi-terminal capacitor 2, the power supply wiring VDD on the voltage regulator VR side is connected to a portion of the first conductive via 31Y on the first main surface S1 of the multi-terminal capacitor 2 via a first external electrode 41 and a conductive via. The power supply wiring VDD on the processor side is connected to a portion of the first conductive via 31Y on the first main surface S1 of the multi-terminal capacitor 2 that is not connected to the power supply wiring VDD on the voltage regulator VR side via a first external electrode 41 and a conductive via. The power supply wiring VSS on the voltage regulator VR and processor side is connected to a second conductive via 32 on the first main surface S1 of the multi-terminal capacitor 2 via a second external electrode 42 and a conductive via. The power supply wiring VSS on the motherboard side is connected to a second conductive via 32 on the second main surface S2 of the multi-terminal capacitor 2 via a second external electrode 42 and a conductive via.

[0095] This causes a portion of the first internal electrode layer 21 of the multi-terminal capacitor 2 to be interposed in series between the power supply wiring VDD on the voltage regulator (IC) side and the power supply wiring VDD on the processor (IC) side. As a result, as shown by the arrow, at least a portion of the DC current of the power supply for the processor (IC) flows through the first internal electrode layer 21 of the multi-terminal capacitor 2. This enhances the noise reduction effect. For example, switching noise generated in the voltage regulator VR is suppressed, and it is possible to prevent the switching noise from being transmitted to the processor and causing it to malfunction.

[0096] Second Embodiment Next, a capacitor-embedded substrate according to a second embodiment will be described with reference to Fig. 7B and Fig. 4A to Fig. 4C. Fig. 7B is a schematic diagram of the capacitor-embedded substrate according to the second embodiment.

[0097] The capacitor-embedded substrate 100B shown in Figure 7B is an interposer used in an IC package. The capacitor-embedded substrate 100B is disposed between a package substrate 110 and an IC such as a voltage regulator VR and a processor. The capacitor-embedded substrate 100B is connected to the package substrate 110 via conductor bumps, and is also connected to the voltage regulator VR and the IC such as a processor via conductor bumps. The IC package is mounted on a motherboard, and thus the motherboard is disposed on the side of the package substrate 110 opposite the IC-mounted surface (not shown).

[0098] An inductor L constituting a voltage regulator VR is embedded inside the package substrate 110. Multi-terminal capacitors 1 and 3 are embedded inside the capacitor-embedded substrate 100B. The multi-terminal capacitors 1 and 3 may be the multi-terminal capacitors 1A and 1B of the present invention described above. Alternatively, the multi-terminal capacitors 1 and 3 may be the conventional multi-terminal capacitor 1X described above. The multi-terminal capacitors 1 and 3 have at least five terminals.

[0099] The multi-terminal capacitor 1 is disposed in a position overlapping the voltage regulator VR, i.e., directly below the voltage regulator VR, in a plan view along the main surface of the capacitor-embedded substrate 100B. The external electrode on the second main surface of the multi-terminal capacitor 1 is connected to the power supply wiring of the motherboard, and the external electrode on the first main surface of the multi-terminal capacitor 1 is connected to the power supply wiring for the input of the voltage regulator VR. This enhances the noise reduction effect. For example, switching noise generated by the voltage regulator VR is suppressed near the noise source, preventing the switching noise from being transmitted to the motherboard and radiated outside the IC package.

[0100] On the other hand, the multi-terminal capacitor 3 is disposed in a position overlapping the processor, i.e., directly below the processor, in a plan view along the main surface of the capacitor-embedded substrate 100B. Furthermore, the multi-terminal capacitor 3 is disposed in a position overlapping the inductor L, i.e., directly above the inductor, in a plan view along the main surface of the capacitor-embedded substrate 100B. The external electrode on the second main surface of the multi-terminal capacitor 3 is connected to the power supply wiring for the output of the voltage regulator VR, and the external electrode on the first main surface of the multi-terminal capacitor 3 is connected to the power supply wiring for the processor's power supply. This enhances the noise reduction effect. For example, switching noise generated by the voltage regulator VR is suppressed, and noise generated by the inductor L is suppressed near the noise source, preventing these noises from being transmitted to the processor and causing it to malfunction.

[0101] 4A, the capacitor-embedded substrate 100B has a core substrate 101 and a wiring layer 102. In the vicinity of the multi-terminal capacitor 1 of the capacitor-embedded substrate 100B, power supply wiring VDD and VSS (GND) are arranged on the wiring layer 102 on the motherboard side, and power supply wiring VDD and VSS (GND) are arranged on the wiring layer 102 on the voltage regulator VR (IC) side.

[0102] When the above-described multi-terminal capacitor 1A of the present invention is applied as the multi-terminal capacitor 1, the power supply wiring VDD on the motherboard side is connected via the first external electrode 41 and the conductor via to the first-main-surface unconnected conductor via 31A of the first conductor vias 31 on the second main surface S2 of the multi-terminal capacitor 1. The power supply wiring VSS on the motherboard side is connected to the second conductor via 32 on the second main surface S2 of the multi-terminal capacitor 1 via the second external electrode 42 and the conductor via.

[0103] The power supply wiring VDD on the voltage regulator VR(IC) side is connected via a first external electrode 41 and a conductor via to a second main surface unconnected conductor via 31B of the first conductor via 31 on the first main surface S1 of the multi-terminal capacitor 1. The power supply wiring VSS on the voltage regulator VR(IC) side is connected to a second conductor via 32 on the first main surface S1 of the multi-terminal capacitor 1 via a second external electrode 42 and a conductor via.

[0104] This causes a portion of the first internal electrode layer 21 of the multi-terminal capacitor 1 to be interposed in series between the power supply wiring VDD on the motherboard side and the power supply wiring VDD on the voltage regulator VR (IC) side. As a result, as shown by the arrow, at least a portion of the DC current of the power supply input to the voltage regulator VR (IC) flows through the first internal electrode layer 21 of the multi-terminal capacitor 1. This enhances the noise reduction effect. For example, switching noise generated in the voltage regulator VR is suppressed near the noise source, preventing the switching noise from being transmitted to the motherboard and radiated outside the IC package.

[0105] In a plan view along the first main surface S1 and the second main surface S2, the positions of the first external electrodes 41 on the first main surface S1 connected to the power supply wiring VDD are offset from the positions of the first external electrodes 41 on the second main surface S2 connected to the power supply wiring VDD. Furthermore, the number of first external electrodes 41 on the first main surface S1 connected to the power supply wiring VDD is different from the number of first external electrodes 41 on the second main surface S2 connected to the power supply wiring VDD. Furthermore, the total number of first external electrodes 41 and second external electrodes 42 arranged on the first main surface S1 is greater than the total number of first external electrodes 41 and second external electrodes 42 arranged on the second main surface S2.

[0106] The core substrate 101 may be made of a known material such as epoxy resin, and the wiring layer 102 may be made of a known material such as epoxy resin. The power supply wiring VDD, VSS is composed of a conductor pattern and conductor vias formed on the wiring layer 102. The conductor pattern and conductor vias may be made of a known metal material such as Cu.

[0107] 4B , when the multi-terminal capacitor 1B of the present invention described above is used as the multi-terminal capacitor 1, the power supply wiring VDD on the motherboard side is connected to the conductor via 31C of the first conductor via 31 on the second main surface S2 of the multi-terminal capacitor 1 via the first external electrode 41 and the conductor via. The power supply wiring VSS on the motherboard side is connected to the second conductor via 32 on the second main surface S2 of the multi-terminal capacitor 1 via the second external electrode 42 and the conductor via.

[0108] The power supply wiring VDD on the voltage regulator VR(IC) side is connected via a first external electrode 41 and a conductor via to a second main surface unconnected conductor via 31B of the first conductor via 31 on the first main surface S1 of the multi-terminal capacitor 1. The power supply wiring VSS on the voltage regulator VR(IC) side is connected to a second conductor via 32 on the first main surface S1 of the multi-terminal capacitor 1 via a second external electrode 42 and a conductor via.

[0109] This causes a portion of the first internal electrode layer 21 of the multi-terminal capacitor 1 to be interposed in series between the power supply wiring VDD on the motherboard side and the power supply wiring VDD on the voltage regulator VR (IC) side. As a result, as shown by the arrow, at least a portion of the DC current of the power supply of the voltage regulator VR (IC) flows through the first internal electrode layer 21 of the multi-terminal capacitor 1. This enhances the noise reduction effect. For example, switching noise generated in the voltage regulator VR is suppressed near the noise source, preventing the switching noise from being transmitted to the motherboard and radiated outside the IC package.

[0110] In a plan view along the first main surface S1 and the second main surface S2, the positions of the first external electrodes 41 on the first main surface S1 connected to the power supply wiring VDD are offset from the positions of the first external electrodes 41 on the second main surface S2 connected to the power supply wiring VDD. Furthermore, the number of first external electrodes 41 on the first main surface S1 connected to the power supply wiring VDD is different from the number of first external electrodes 41 on the second main surface S2 connected to the power supply wiring VDD. Furthermore, the total number of first external electrodes 41 and second external electrodes 42 arranged on the first main surface S1 is greater than the total number of first external electrodes 41 and second external electrodes 42 arranged on the second main surface S2.

[0111] 4C , when the above-described conventional multi-terminal capacitor 1X is used as the multi-terminal capacitor 1, the power supply wiring VDD on the motherboard side is connected via a first external electrode 41X and a conductor via to a part of the first conductor via 31X on the second main surface S2 of the multi-terminal capacitor 1. The power supply wiring VSS on the motherboard side is connected to the second conductor via 32 on the second main surface S2 of the multi-terminal capacitor 1 via a second external electrode 42 and a conductor via.

[0112] The power supply wiring VDD on the voltage regulator VR(IC) side is connected, via a first external electrode 41 and a conductor via, to a first conductor via 31X on the first main surface S1 of the multi-terminal capacitor 1 that is not connected to the power supply wiring VDD on the motherboard side on the second main surface S2. The power supply wiring VSS on the voltage regulator VR(IC) side is connected to a second conductor via 32 on the first main surface S1 of the multi-terminal capacitor 1, via a second external electrode 42 and a conductor via.

[0113] This causes a portion of the first internal electrode layer 21 of the multi-terminal capacitor 1 to be interposed in series between the power supply wiring VDD on the motherboard side and the power supply wiring VDD on the voltage regulator VR (IC) side. As a result, as shown by the arrow, at least a portion of the DC current of the power supply of the voltage regulator VR (IC) flows through the first internal electrode layer 21 of the multi-terminal capacitor 1. This enhances the noise reduction effect. For example, switching noise generated in the voltage regulator VR is suppressed near the noise source, preventing the switching noise from being transmitted to the motherboard and radiated outside the IC package.

[0114] On the other hand, as shown in FIG. 4A, in the vicinity of the multi-terminal capacitor 3 of the capacitor-embedded substrate 100B, the power supply wiring VDD and VSS (GND) are arranged on the wiring layer 102 on the voltage regulator VR (IC) side, and the power supply wiring VDD and VSS (GND) are arranged on the wiring layer 102 on the processor (IC) side.

[0115] When the above-described multi-terminal capacitor 1A of the present invention is applied as the multi-terminal capacitor 3, the power supply wiring VDD on the voltage regulator VR(IC) side is connected to the first-main-surface unconnected conductive via 31A of the first conductive vias 31 on the second main surface S2 of the multi-terminal capacitor 3 via the first external electrode 41 and the conductive via. The power supply wiring VSS on the voltage regulator VR(IC) side is connected to the second conductive via 32 on the second main surface S2 of the multi-terminal capacitor 3 via the second external electrode 42 and the conductive via.

[0116] The power supply wiring VDD on the processor (IC) side is connected to the second main surface unconnected conductive via 31B of the first conductive via 31 on the first main surface S1 of the multi-terminal capacitor 3 via the first external electrode 41 and a conductive via. The power supply wiring VSS on the processor side is connected to the second conductive via 32 on the first main surface S1 of the multi-terminal capacitor 1 via the second external electrode 42 and a conductive via.

[0117] As a result, a portion of the first internal electrode layer 21 of the multi-terminal capacitor 3 is interposed in series between the power supply wiring VDD on the voltage regulator (IC) side and the power supply wiring VDD on the processor (IC) side. As a result, as shown by the arrow, at least a portion of the DC current of the power supply of the processor (IC) flows through the first internal electrode layer 21 of the multi-terminal capacitor 3. This can enhance the noise reduction effect. For example, switching noise generated in the voltage regulator VR can be suppressed, and the switching noise can be prevented from being transmitted to the processor, causing the processor to malfunction.

[0118] 4B , when the multi-terminal capacitor 1B of the present invention described above is used as the multi-terminal capacitor 3, the power supply wiring VDD on the voltage regulator VR(IC) side is connected to the conductor via 31C of the first conductor via 31 on the second main surface S2 of the multi-terminal capacitor 3 via the first external electrode 41 and the conductor via. The power supply wiring VSS on the voltage regulator VR(IC) side is connected to the second conductor via 32 on the second main surface S2 of the multi-terminal capacitor 1 via the second external electrode 42 and the conductor via.

[0119] The power supply wiring VDD on the processor (IC) side is connected to the second main surface unconnected conductive via 31B of the first conductive via 31 on the first main surface S1 of the multi-terminal capacitor 3 via the first external electrode 41 and a conductive via. The power supply wiring VSS on the processor side is connected to the second conductive via 32 on the first main surface S1 of the multi-terminal capacitor 1 via the second external electrode 42 and a conductive via.

[0120] As a result, a portion of the first internal electrode layer 21 of the multi-terminal capacitor 3 is interposed in series between the power supply wiring VDD on the voltage regulator (IC) side and the power supply wiring VDD on the processor (IC) side. As a result, as shown by the arrow, at least a portion of the DC current of the power supply of the processor (IC) flows through the first internal electrode layer 21 of the multi-terminal capacitor 3. This can enhance the noise reduction effect. For example, switching noise generated in the voltage regulator VR can be suppressed, and the switching noise can be prevented from being transmitted to the processor, causing the processor to malfunction.

[0121] 4C , when the above-described conventional multi-terminal capacitor 1X is used as the multi-terminal capacitor 3, the power supply wiring VDD on the voltage regulator VR(IC) side is connected to a part of the first conductive via 31X on the second main surface S2 of the multi-terminal capacitor 3 via a first external electrode 41 and a conductive via. The power supply wiring VSS on the voltage regulator VR(IC) side is connected to the second conductive via 32 on the second main surface S2 of the multi-terminal capacitor 1 via a second external electrode 42 and a conductive via.

[0122] The power supply wiring VDD on the processor (IC) side is connected, via a first external electrode 41 and a conductor via, to a first conductor via 31X on the first main surface S1 of the multi-terminal capacitor 3 that is not connected to the power supply wiring VDD on the voltage regulator VR (IC) side on the second main surface S2. The power supply wiring VSS on the processor (IC) side is connected to a second conductor via 32 on the first main surface S1 of the multi-terminal capacitor 1, via a second external electrode 42 and a conductor via.

[0123] As a result, a portion of the first internal electrode layer 21 of the multi-terminal capacitor 3 is interposed in series between the power supply wiring VDD on the voltage regulator (IC) side and the power supply wiring VDD on the processor (IC) side. As a result, as shown by the arrow, at least a portion of the DC current of the power supply of the processor (IC) flows through the first internal electrode layer 21 of the multi-terminal capacitor 3. This can enhance the noise reduction effect. For example, switching noise generated in the voltage regulator VR can be suppressed, and the switching noise can be prevented from being transmitted to the processor, causing the processor to malfunction.

[0124] Although the embodiments of the present invention have been described above, the present invention is not limited to the above-described embodiments and various modifications and variations are possible. For example, the above-described embodiments illustrate connection structures in substrates incorporating multilayer ceramic capacitors in which dielectric layers and internal electrode layers are stacked. However, the features of the present invention are not limited to these. For example, the present invention can be applied to connection structures in substrates incorporating silicon capacitors that are three-dimensionally fabricated using semiconductor processes to significantly increase the electrode surface and increase the capacitance per unit area of ​​the substrate, and can also be applied to connection structures in substrates incorporating polymer capacitors that use conductive polymers (conductive polymers) for the cathodes.

[0125] [Modification of Multi-Terminal Capacitor] Below, a silicon capacitor will be exemplified as a modification of the multi-terminal capacitor. Fig. 8 is a schematic cross-sectional view of a multi-terminal capacitor according to the modification. As shown in Fig. 8, the multi-terminal capacitor 1C of the modification includes a silicon substrate 10A, first internal electrode layers 21 and second internal electrode layers 22, a plurality of first external electrodes (terminals) 41, and a plurality of second external electrodes (terminals) 42. The multi-terminal capacitor 1C has at least five terminals.

[0126] The silicon substrate 10A has a substantially rectangular parallelepiped shape and has a first main surface S1 and a second main surface S2.

[0127] The first internal electrode layer 21 and the second internal electrode layer 22 are disposed on the first main surface S1 of the silicon substrate 10A. The first internal electrode layer 21 and the second internal electrode layer 22 face each other with the dielectric layer 12 sandwiched therebetween. The shapes of the first internal electrode layer 21 and the second internal electrode layer 22 are not particularly limited, but may be, for example, a trench structure or a flat plate structure. The first internal electrode layer 21 and the second internal electrode layer 22 generate electrostatic capacitance and essentially function as a capacitor.

[0128] The material of the first internal electrode layer 21 and the second internal electrode layer 22 is not particularly limited, but may be, for example, a semiconductor such as polysilicon, or a conductor such as metal.

[0129] The multi-terminal capacitor 1C may include a plurality of first conductive vias 31 and a plurality of second conductive vias 32. The first conductive vias 31 and the second conductive vias 32 are disposed inside the silicon substrate 10A. The first conductive vias 31 extend from the first main surface S1 to the second main surface S2, are exposed at the first main surface S1 and the second main surface S2, and are connected to the first external electrode 41 at the first main surface S1 and the second main surface S2. The second conductive vias 32 extend from the first main surface S1 to the second main surface S2, are exposed at the first main surface S1 and the second main surface S2, and are connected to the second external electrode 42 at the first main surface S1 and the second main surface S2.

[0130] The first conductor vias 31 and the second conductor vias 32 are arranged adjacent to each other in an alternating manner, and the direction of the current flowing through the first conductor via 31 is opposite to the direction of the current flowing through the adjacent second conductor via 32, so that the magnetic field generated by the current flowing through the first conductor via 31 and the magnetic field generated by the current flowing through the adjacent second conductor via 32 cancel each other out, thereby reducing the equivalent series inductance ESL.

[0131] The first external electrodes (terminals) 41 are arranged at a plurality of positions on the first internal electrode layers 21 on the first main surface S1, and are connected to the first internal electrode layers 21. The first external electrodes 41 are also arranged at the positions of the first conductor vias 31 on the first main surface S and the second main surface S2, and are connected to the first conductor vias 31.

[0132] The second external electrodes (terminals) 42 are arranged at a plurality of positions on the second internal electrode layers 22 on the first main surface S1, and are connected to the second internal electrode layers 22 via, for example, conductive vias (not shown). The second external electrodes (terminals) 42 are also arranged at the positions of the second conductive vias 32 on the first main surface S and the second main surface S2, and are connected to the second conductive vias 32.

[0133] [Variations of Capacitor-Embedded Substrate] In the chiplet technology of the IC package technology described above, there is a technology in which chips with the same power supply voltage, such as two processors (IC) or one processor (IC) and a memory (IC) such as an HBM (High Bandwidth Memory), are mounted and combined on a substrate (package substrate, interposer, etc.) and housed in a single IC package.

[0134] For example, it is known that a bridge die having a redistribution layer (RDL) disposed on a silicon substrate is used to transmit and receive high-frequency signals between processors (IC) or between a processor (IC) and a memory (IC).

[0135] In this case, capacitors for decoupling and noise filtering are required near the processor and memory. Therefore, we devised a capacitor-embedded substrate in which a bridge die consisting of a silicon capacitor and a rewiring layer is embedded.

[0136] Fig. 9A is a schematic cross-sectional view of a capacitor-embedded substrate according to a modified example. The capacitor-embedded substrate 100C shown in Fig. 9A is a package substrate or interposer used in an IC package. ICs such as processors and memories are mounted on the capacitor-embedded substrate 100C via, for example, conductor bumps (not shown). The IC package is mounted on a motherboard, and thus a motherboard (not shown) is disposed on the side of the capacitor-embedded substrate 100C opposite the IC-mounted surface.

[0137] Embedded inside the capacitor-embedded substrate 100C are the multi-terminal capacitor 1C made up of the above-described silicon capacitor and a bridge die made up of a rewiring layer 102. The bridge die is disposed across the processor and memory.

[0138] In the rewiring layer 102, signal wirings that connect the processor (IC) and the memory (IC) and power supply wirings VDD and VSS (GND) are arranged.

[0139] The power supply wiring VDD on the motherboard side is connected to the first conductive via 31 on the second main surface S2 of the multi-terminal capacitor 1C via the first external electrode 41 and a conductive via. The power supply wiring VSS on the motherboard side is connected to the second conductive via 32 on the second main surface S2 of the multi-terminal capacitor 1C via the second external electrode 42 and a conductive via.

[0140] The power supply wiring VDD of the processor (IC) is connected to the first conductive via 31 and a part of the first internal electrode layer 21 on the first main surface S1 of the multi-terminal capacitor 1C via the first external electrode 41 and the conductive via. The power supply wiring VSS of the processor (IC) is connected to the second conductive via 32 and a part of the second internal electrode layer 22 on the first main surface S1 of the multi-terminal capacitor 1C via the second external electrode 42 and the conductive via.

[0141] The power supply wiring VDD of the memory (IC) is connected to the first conductive via 31 and another part of the first internal electrode layer 21 on the first main surface S1 of the multi-terminal capacitor 1C via the first external electrode 41 and the conductive via. The power supply wiring VSS of the memory (IC) is connected to the second conductive via 32 and another part of the second internal electrode layer 22 on the first main surface S1 of the multi-terminal capacitor 1C via the second external electrode 42 and the conductive via.

[0142] The power supply wiring VDD of the processor (IC) and the power supply wiring VDD of the memory (IC) are disconnected at a portion on the first internal electrode layer 21 of the multi-terminal capacitor 1C, so that a portion of the first internal electrode layer 21 of the multi-terminal capacitor 1C is interposed in series between the power supply wiring VDD of the processor (IC) and the power supply wiring VDD of the memory (IC).

[0143] As a result, at least a portion of the AC current (noise) of the power supply propagating between the processor (IC) and the memory (IC) flows through the first internal electrode layer 21 of the multi-terminal capacitor 1C. For example, as shown by the arrows, an AC current caused by noise generated in the processor (IC) and propagating to the memory (IC) flows through a portion of the first internal electrode layer 21 of the multi-terminal capacitor 1C. Alternatively, an AC current caused by noise generated in the memory (IC) and propagating to the processor (IC) flows through a portion of the first internal electrode layer 21 of the multi-terminal capacitor 1C. As a result, the conducted noise propagated from the processor to the memory and the conducted noise propagated from the memory to the processor are reduced.

[0144] In reality, a certain degree of potential difference may occur between the power supply voltage of the processor (IC) and the power supply voltage of the memory (IC). In this case, at least a portion of the DC current of the power supply input to the processor (IC) flows through the first internal electrode layer 21 of the multi-terminal capacitor 1. Alternatively, at least a portion of the DC current of the power supply input to the memory (IC) flows through the first internal electrode layer 21 of the multi-terminal capacitor 1. This reduces the conducted noise transmitted from the processor to the memory and the conducted noise transmitted from the memory to the processor.

[0145] The above-described capacitor-embedded substrate 100C has a configuration in which a bridge die made up of a multi-terminal capacitor 1C made up of a silicon capacitor and a rewiring layer 102 is embedded in a substrate (package substrate, interposer, etc.). Note that, as shown in Fig. 9B, the capacitor-embedded substrate 100C may have a bridge die alone made up of a multi-terminal capacitor 1C made up of a silicon capacitor and a rewiring layer 102, without the bridge die being embedded in the substrate.

[0146] 1, 1A, 1B, 1C, 1X, 1Y, 2, 3 Multi-terminal capacitor 10 Laminated body 10A Silicon substrate 12 Dielectric layer 21 First internal electrode layer 21A, 22A Through hole 22 Second internal electrode layer 31, 31X First conductive via 31A First principal surface non-connected conductor via 31B Second principal surface non-connected conductor via 31C Conductor via 32 Second conductor via 41 First external electrode (terminal) 42 Second external electrode (terminal) 100A, 100B, 100C Capacitor-embedded substrate 101 Core substrate 102 Wiring layer, rewiring layer L Inductor S1 First principal surface S2 Second principal surface T Stacking direction VDD, VSS Power supply wiring

Claims

1. A substrate on which an IC is mounted, the substrate comprising: a multi-terminal capacitor embedded therein, having first and second internal electrode layers facing each other, and having at least five terminals; the multi-terminal capacitor being connected to the IC so that at least a portion of the DC current of the power supply for the IC flows through the first internal electrode layer of the multi-terminal capacitor.

2. The capacitor-embedded substrate according to claim 1, further comprising a power supply wiring for supplying power to the IC, wherein the multi-terminal capacitor is a capacitor for decoupling the power supply of the IC, and the multi-terminal capacitor is connected in series to the power supply wiring such that a portion of the first internal electrode layer of the multi-terminal capacitor is interposed between the power supply wiring and the multi-terminal capacitor.

3. The capacitor-embedded substrate according to claim 2, wherein the multi-terminal capacitor has: a first main surface and a second main surface opposing each other in the stacking direction of the first internal electrode layers and the second internal electrode layers; a plurality of first conductor vias extending in the stacking direction, electrically connected to the first internal electrode layers, and electrically insulated from the second internal electrode layers; a plurality of second conductor vias extending in the stacking direction, electrically insulated from the first internal electrode layers, and electrically connected to the second internal electrode layers; a plurality of first external electrodes arranged on at least one of the first main surface and the second main surface, and connected to each of the plurality of first conductor vias; and a plurality of second external electrodes arranged on at least one of the first main surface and the second main surface, and connected to each of the plurality of second conductor vias.

4. A capacitor-embedded substrate according to claim 3, wherein some of the plurality of first external electrodes are arranged on the first main surface, and another portion of the plurality of first external electrodes are arranged on the second main surface, and the first external electrodes on the first main surface and the first external electrodes on the second main surface are connected to the power supply wiring in series with the power supply wiring so that part of the first internal electrode layer of the multi-terminal capacitor is interposed therebetween.

5. A capacitor-embedded substrate as described in claim 3 or 4, wherein, in a plan view along the first principal surface and the second principal surface, the position of the first external electrode on the first principal surface connected to the power supply wiring is offset from the position of the first external electrode on the second principal surface connected to the power supply wiring.

6. A capacitor-embedded substrate according to claim 3 or 4, wherein the number of first external electrodes on the first main surface connected to the power supply wiring is different from the number of first external electrodes on the second main surface connected to the power supply wiring.

7. A capacitor-embedded substrate according to claim 3 or 4, wherein the total number of first external electrodes and second external electrodes arranged on the first main surface is greater than the total number of first external electrodes and second external electrodes arranged on the second main surface.

8. The capacitor-embedded substrate according to any one of claims 2 to 7, wherein the IC includes a processor and a voltage regulator, and the multi-terminal capacitor is connected to the power supply wiring leading to the input of the voltage regulator.

9. The capacitor-embedded substrate according to claim 8, wherein the multi-terminal capacitor is connected to the power supply wiring from the output of the voltage regulator to the power supply of the processor.

10. The capacitor-embedded substrate according to any one of claims 1 to 9, which is a package substrate or interposer used in an IC package.

11. The capacitor-embedded substrate according to any one of claims 1 to 10, wherein the multi-terminal capacitor is a multilayer ceramic capacitor, a silicon capacitor, or a polymer capacitor.

12. A capacitor-embedded substrate according to claim 8 or 9, wherein the multi-terminal capacitor is arranged in a position overlapping the IC, the voltage regulator, the processor, or an inductor constituting the voltage regulator, in a plan view along the main surface of the capacitor-embedded substrate.

13. A capacitor-embedded substrate, comprising a substrate on which two ICs are mounted, the substrate comprising a multi-terminal capacitor embedded therein, having first and second internal electrode layers facing each other, and having at least five terminals, the multi-terminal capacitor being connected to the two ICs so that at least a portion of the AC current of a power supply propagating between the two ICs flows through the first internal electrode layer of the multi-terminal capacitor.

14. A capacitor-embedded substrate, which is a bridge-type substrate placed across two ICs, and which has first and second internal electrode layers facing each other and a multi-terminal capacitor with at least five terminals, and which is connected to the two ICs so that at least a portion of the AC current of a power supply propagating between the two ICs flows through the first internal electrode layer of the multi-terminal capacitor.

15. A capacitor-embedded substrate as described in claim 13 or 14, comprising power supply wiring for supplying power to the two ICs and connecting the two ICs, the multi-terminal capacitor being a capacitor for decoupling the power supplies of the two ICs, and the multi-terminal capacitor being connected to the power supply wiring in series with the power supply wiring so that a portion of the first internal electrode layer of the multi-terminal capacitor is interposed therebetween.

16. The capacitor-embedded substrate according to claim 15, wherein the power supply voltages of the two ICs are the same, the multi-terminal capacitor is a silicon capacitor, and a portion of the power supply wiring is cut so that a portion of the first internal electrode layer of the multi-terminal capacitor is interposed in series with the power supply wiring.

17. A laminate comprising a plurality of dielectric layers stacked one on top of the other, the laminate having a first main surface and a second main surface opposing each other in the stacking direction; a first internal electrode layer and a second internal electrode layer disposed inside the laminate and opposing each other in the stacking direction with at least one of the plurality of dielectric layers sandwiched therebetween; a plurality of first conductor vias disposed inside the laminate, extending in the stacking direction, electrically connected to the first internal electrode layers, and electrically insulated from the second internal electrode layers; a plurality of second conductor vias disposed inside the laminate, extending in the stacking direction, electrically insulated from the first internal electrode layers, and electrically connected to the second internal electrode layers; a plurality of first external electrodes disposed on at least one of the first main surface and the second main surface, and connected to the plurality of first conductor vias, respectively; and a plurality of second external electrodes disposed on at least one of the first main surface and the second main surface, and connected to the plurality of second conductor vias, respectively, wherein the plurality of first conductor vias are a first-main-surface unconnected conductor via that does not extend to the first main surface and is not connected to one of the plurality of first external electrodes at the first main surface, and that extends to the second main surface and is connected to one of the plurality of first external electrodes at the second main surface; and a second-main-surface unconnected conductor via that extends to the first main surface and is connected to one of the plurality of first external electrodes at the first main surface, but does not extend to the second main surface and is not connected to one of the plurality of first external electrodes at the second main surface, wherein each of the plurality of second conductor vias extends from the first main surface to the second main surface and is respectively connected to one of the plurality of second external electrodes at the first main surface and the second main surface.

18. A laminate comprising a plurality of dielectric layers stacked one on top of the other, the laminate having a first main surface and a second main surface opposing each other in the stacking direction; a first internal electrode layer and a second internal electrode layer disposed inside the laminate and opposing each other in the stacking direction with at least one of the plurality of dielectric layers sandwiched therebetween; a plurality of first conductor vias disposed inside the laminate, extending in the stacking direction, electrically connected to the first internal electrode layers, and electrically insulated from the second internal electrode layers; a plurality of second conductor vias disposed inside the laminate, extending in the stacking direction, electrically insulated from the first internal electrode layers, and electrically connected to the second internal electrode layers; a plurality of first external electrodes disposed on at least one of the first main surface and the second main surface, and connected to the plurality of first conductor vias, respectively; and a plurality of second external electrodes disposed on at least one of the first main surface and the second main surface, and connected to the plurality of second conductor vias, respectively, wherein the plurality of first conductor vias are a second-main-surface unconnected conductor via extending to the first main surface and connected to one of the plurality of first external electrodes at the first main surface and the second main surface, the second-main-surface unconnected conductor via extending to the first main surface and connected to one of the plurality of first external electrodes at the first main surface, but not extending to the second main surface and not connected to one of the plurality of first external electrodes at the second main surface, wherein each of the plurality of second conductor vias extends from the first main surface to the second main surface and is connected to one of the plurality of second external electrodes at the first main surface and the second main surface.

19. A multi-terminal capacitor according to claim 17 or 18, wherein the number of first external electrodes on the first main surface is different from the number of first external electrodes on the second main surface.

20. A multi-terminal capacitor according to claim 17 or 18, wherein each of the first external electrode and the second external electrode is a conductive pad or a conductive bump.

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