Signal isolation circuit with improved common mode transient tolerance

Abstract

Disclosed is a signal isolation circuit with improved common mode transient tolerance. According to one aspect disclosed herein, provided is a signal isolation circuit for signal transmission between electrically isolated domains, the signal isolation circuit comprising: a transmitter configured to generate a second signal by modulating a first signal on a first domain; an insulating core configured to transfer the second signal from the first domain to a second domain; a receiver configured to generate a third signal by demodulating the second signal on the second domain; a quasi-receiver provided between the transmitter and the insulating core and configured to demodulate the second signal into a fourth signal on the first domain; and a current boost circuit configured to selectively increase, on the basis of the first signal and the fourth signal, an input current supplied to the transmitter or an output current output by the transmitter.

Description

Signal isolation circuit with improved common-mode transient immunity

[0001] The present disclosure relates to a signal isolation circuit with improved common mode transient immunity.

[0002] The content described below merely provides background information related to the present embodiment and does not constitute prior art.

[0003] Galvanic isolated drive circuits for driving wide bandgap switch devices (e.g., SiC MOSFETs or GaN FETs) mainly use magnetic coupling or capacitive coupling to transmit signals between input and output. To prevent malfunction of the isolated drive circuit, a circuit with robust noise immunity against common-mode transients that occur during signal transmission is required. This common-mode transient immunity (CMTI) is one of the important characteristics of the drive circuit. CMTI refers to the ability of the output signal to maintain its state (high or low) during the transient voltage section that occurs between different ground potentials of the isolated drive circuit. During the operation of the isolated drive circuit, the common-mode transient voltage can reach 1.5 kV, and CMTI can be expressed in units of V / ns (or kV / μs).

[0004] The present disclosure aims to provide a circuit and a signal isolation circuit including the same that can prevent malfunctions caused by common mode transients or similar malfunctions caused by various other causes such as temperature, process, and supply voltage changes.

[0005] The problems to be solved by the present invention are not limited to the problems mentioned above, and other problems not mentioned will be clearly understood by those skilled in the art from the description below.

[0006] According to one aspect of the present disclosure, a signal isolation circuit for signal transmission between electrically isolated domains is provided, comprising: a transmitter configured to modulate a first signal on a first domain to generate a second signal; an insulation core configured to transmit the second signal from the first domain to a second domain; a receiver configured to demodulate the second signal on the second domain to generate a third signal; a quasi-receiver provided between the transmitter and the insulation core, the quasi-receiver demodulating the second signal on the first domain into a fourth signal; and a current boost circuit configured to selectively increase an input current supplied to the transmitter or an output current output from the transmitter based on the first signal and the fourth signal.

[0007] According to another aspect of the present disclosure, a transmitting circuit for transmitting a signal to a different domain is provided, comprising: a transmitter configured to modulate a first signal on a first domain to generate a second signal; a quasi-receiver configured to demodulate the second signal into a fourth signal on the first domain; and a current boost circuit configured to selectively increase an input current supplied to the transmitter or an output current output from the transmitter based on the first signal and the fourth signal.

[0008] According to another aspect of the present disclosure, a circuit is provided on the transmitter side to prevent malfunction of a signal isolation circuit, the circuit comprising: a quasi-receiver that demodulates a second signal output by the transmitter into a fourth signal; and a current boost circuit configured to selectively increase an input current supplied to the transmitter or an output current output by the transmitter based on a first signal and the fourth signal, which are modulated signals of the second signal.

[0009] In some examples, the transmitter may be configured to output the second signal that selectively oscillates based on the level of the first signal. The transmitter may output the second signal that oscillates based on whether the first signal has a first logic level. The quasi-receiver may be configured to output the fourth signal that has a different level depending on whether the second signal is oscillated.

[0010] In some examples, the current boost circuit may be configured to output a fifth signal that triggers an increase in the input current or the output current based on a level of the first signal and a level of the fourth signal.

[0011] In some examples, the current boost circuit may include a comparison circuit that compares a level of the first signal with a level of the fourth signal. When the fourth signal transitions to have a different level from the first signal, a level of an output signal of the comparison circuit may transition. The comparison circuit may be activated based on the first signal having the first logic level. A level of the output signal of the comparison circuit may transition from the second logic level to the first logic level when a level of the fourth signal transitions from the first logic level to the second logic level.

[0012] In some examples, the current boost circuit may further include a one-shot trigger circuit configured to generate a sixth signal having a predetermined pulse width based on a level transition of the output signal of the comparison circuit.

[0013] In some examples, the receiver and the quasi-receiver may have identical circuit configurations. The receiver and the quasi-receiver may each include a first circuit configuration for demodulating the second signal. The receiver may further include a second circuit configuration for preventing glitches in the third signal. The first circuit configuration may include a low noise amplifier and an envelope detector, and the second circuit configuration may include a low-pass filter.

[0014] In some examples, the transmitter may include a cross-coupled LC oscillator configured to generate a signal oscillating at a predetermined frequency; and a first switching element selectively conducting or blocking a path of a first tail current of the cross-coupled LC oscillator based on a level of the first signal; and a second switching element selectively conducting or blocking a path of a second tail current of the cross-coupled LC oscillator based on an output of the current boost circuit.

[0015] In some examples, the transmitter may include a modulation circuit that selectively outputs the first signal and an output signal of the oscillator circuit based on a level of the first signal; and a buffer circuit that outputs the second signal based on an output of the modulation circuit. The buffer circuit may include a plurality of inverters; and a switching element that selectively connects some of the plurality of inverters to the remaining inverters based on an output of the current boost circuit.

[0016] According to embodiments of the present disclosure, malfunctions caused by common-mode transients during the operation of a signal isolation circuit can be prevented. Accordingly, the CMTI of the signal isolation circuit can be improved. Furthermore, similar malfunctions caused by various other factors, such as temperature, process, and supply voltage variations, can also be resolved.

[0017] The malfunction prevention circuit according to the embodiment of the present disclosure can be applied to transmitters of various types of signal isolation circuits (e.g., a galvanic isolation type signal isolation circuit based on magnetic coupling and a galvanic isolation type signal isolation circuit based on capacitive coupling) without substantial technical changes, and thus has high usability.

[0018] According to an embodiment of the present disclosure, by connecting a quasi-receiver having a structure similar to that of a receiver to the transmitter, the current of the transmitter can be adaptively increased, thereby improving power consumption efficiency. For example, the buffer current of the transmitter can be adaptively adjusted whenever a malfunction occurs. In another example, the tail current of an oscillator can be adaptively adjusted whenever a malfunction occurs. This method consumes less power than a method of maintaining oscillation by increasing the tail current of the oscillator for a certain period of time. In addition, since a single malfunction prevention circuit can respond to conditions of a wide time-varying ratio (e.g., ~300 V / ns level), there is an advantage in that the area and power consumption for additional circuit configuration are not required.

[0019] The effects of the present disclosure are not limited to the effects mentioned above, and other effects not mentioned will be clearly understood by those skilled in the art from the description below.

[0020] FIG. 1 is a schematic diagram of a signal insulation circuit according to one embodiment of the present disclosure.

[0021] FIG. 2 is an exemplary waveform diagram referenced to explain the on-off keying signal transmission protocol.

[0022] Figure 3 is an exemplary waveform diagram referenced to explain malfunction due to common mode transient.

[0023] FIG. 4 is a waveform diagram referenced to explain the operation of a malfunction prevention circuit according to one embodiment of the present disclosure.

[0024] FIG. 5 is a schematic diagram of a receiver according to one embodiment of the present disclosure.

[0025] FIG. 6 is a schematic diagram of a quasi-receiver according to one embodiment of the present disclosure.

[0026] FIG. 7 and FIG. 8 are circuit diagrams schematically illustrating a current boost circuit according to various embodiments of the present disclosure.

[0027] FIG. 9 and FIG. 10 are exemplary circuit diagrams for reference to explain an example in which a malfunction prevention circuit according to one embodiment of the present disclosure is applied to a magnetic coupling-based galvanic isolation type signal isolation circuit.

[0028] FIG. 11 and FIG. 12 are exemplary circuit diagrams for reference to explain an example in which a malfunction prevention circuit according to one embodiment of the present disclosure is applied to a galvanic isolation type signal isolation circuit based on capacitive coupling.

[0029] FIG. 13 is an exemplary circuit diagram for reference to explain another example in which a malfunction prevention circuit according to one embodiment of the present disclosure is applied to a magnetic coupling-based galvanic isolation type signal isolation circuit.

[0030] FIG. 14 is an exemplary waveform diagram referenced to explain signal transmission malfunction that may occur as the signal strength of on-off keying modulation decreases.

[0031] FIG. 15 is a waveform diagram referenced to explain the operation of a malfunction prevention circuit according to one embodiment of the present disclosure.

[0032] Hereinafter, some embodiments of the present disclosure will be described in detail using exemplary drawings. When designating components in each drawing, it should be noted that, where possible, identical components are given the same reference numerals, even if they appear in different drawings. Furthermore, when describing the present disclosure, detailed descriptions of related known structures or functions will be omitted if they are deemed to obscure the gist of the present disclosure.

[0033] In describing components of embodiments according to the present disclosure, symbols such as first, second, i), ii), a), b) may be used. These symbols are only for distinguishing the components from other components, and the nature, order, or sequence of the components are not limited by the symbols. When a part in the specification is said to "include" or "have" a component, this does not mean that other components are excluded, but rather that other components may be included, unless explicitly stated otherwise.

[0034] The detailed description set forth below, together with the accompanying drawings, is intended to explain exemplary embodiments of the present disclosure and is not intended to represent the only embodiments in which the present disclosure may be practiced.

[0035] FIG. 1 is a schematic diagram of a signal insulation circuit according to one embodiment of the present disclosure.

[0036] A signal isolation circuit (10) is a device that electrically isolates multiple domains while simultaneously enabling the transmission of specific digital signals between the multiple domains. The signal isolation circuit (10) may include, for example, a digital isolator. The multiple domains may have different power levels or may have separate power supplies.

[0037] As illustrated in FIG. 1, a signal insulation circuit (10) according to one embodiment of the present disclosure may include all or part of a transmitter (100), an insulation core (120), a receiver (140), and a malfunction prevention circuit (160). The components illustrated in FIG. 1 represent functionally distinct elements, and at least one of the components may be implemented in a form in which they are integrated with each other in an actual physical environment.

[0038] Input signal (V) of signal insulation circuit (10) IN ) is modulated by a transmitter (100) located in a first domain, and then transmitted to a second domain through an insulating core (120), and restored through demodulation in a receiver (140). The transmitter (100) and the receiver (140) can modulate or demodulate a signal based on an On-Off Keying (OOK) topology. As an insulating channel (or insulating barrier) applied to the insulating core (120), a micro transformer, a capacitor, a magneto-resistor (giant magneto-resistor), or an opto-electric device may be used, but is not limited to these examples, and the present disclosure does not limit this in a specific manner.

[0039] FIG. 2 is an exemplary waveform diagram referenced to explain the on-off keying signal transmission protocol. FIG. 3 is an exemplary waveform diagram referenced to explain malfunction due to common mode transients.

[0040] As shown in Figure 2, OOK is a method of representing a digital signal depending on the presence or absence of a carrier wave. For example, an input signal (V IN ) is high, the input signal (V IN ) is a high frequency signal (V OSCP and V OSCN) is transmitted through an isolated channel and then demodulated to produce an output signal (V) with a high level again. OUT ) is restored.

[0041] Meanwhile, a common mode transient voltage (V) is generated between the ground of the first domain and the ground of the second domain. CM ) occurs, a common mode transient current (I) is generated by the capacitor component of the insulating core (120) (especially, parasitic capacitance that inevitably exists due to the insulating structure). CMTI+ and I CMTI- ) is derived. The size of the parasitic capacitance is C par When this is said, the common mode transient current (I CMTI+ and I CMTI- ) can be expressed as in mathematical expression 1.

[0042]

[0043] Common mode transient current (I CMTI+ and I CMTI- ) is the common mode transient voltage (V CM ) can flow in different directions in the rising and falling sections. For example, referring to Fig. 1, the common mode transient voltage (V CM ) rising section (T + ) is a common mode transient current (I) flowing from the receiver (140) side to the transmitter (100) side. CMTI+ ) can be induced, and the common mode transient voltage (V CM ) of the descending section (T - ) is a common mode transient current (I) flowing from the transmitter (100) side to the receiver (140) side. CMTI- ) can be derived.

[0044] This common mode transient current (I CMTI+ and I CMTI-) may cause malfunction of the transmitter (100) or receiver (140) for transmitting the on-off keying signal. For example, the transmitter (100) may be provided with an oscillator for generating a high-frequency carrier wave, and the common mode transient voltage (V CM ) rising section (T + ) in the common mode transient current (I CMTI+ ) can stop the oscillation of the oscillator. At this time, depending on the circuit structure of the oscillator, the modulation signal (V) output by the transmitter (100) as shown in Fig. 3 OSCP and V OSCN ) is the supply voltage (V CC ) can be fixed to a voltage greater than that of the on-off keying signal transmission protocol, and the receiver (140) outputs the signal as a low level output signal (V OUT ) is demodulated. That is, the common mode transient voltage (V CM ) rising section (T + ) in the signal isolation circuit (10) output signal (V OUT ) is the input signal (V IN ) may cause malfunctions that are different from those described above.

[0045] Referring again to FIG. 1, a malfunction prevention circuit (160) is introduced to prevent malfunctions caused by the aforementioned common mode transients, or similar malfunctions caused by various other causes such as temperature, process, and supply voltage changes.

[0046] The malfunction prevention circuit (160) detects the modulation signal (V) output by the transmitter (100). OSCP and V OSCN ) based on the input signal (V) of the signal insulation circuit (10) IN ) and output signal (V OUT ) detects a malfunction situation in which the triggering signal (V IBST ) can be output. To this end, the malfunction prevention circuit (160) outputs a modulation signal (V OSCP and V OSCN) and a quasi-demodulated signal (V) demodulated by the quasi-receiver (170). DET ) based on the triggering signal (V IBST ) may include a current boost circuit (190) that generates a current boost current.

[0047] FIG. 4 is a waveform diagram referenced to explain the operation of a malfunction prevention circuit according to one embodiment of the present disclosure.

[0048] Referring to Fig. 4, the malfunction prevention circuit (160) detects the modulation signal (V) oscillating from the transmitter (100). OSCP and V OSCN ) is to be output (e.g., input signal (V IN ) is at a high level), the actual modulation signal (V OSCP and V OSCN ) detects the cessation of the oscillation and triggers the triggering signal (V IBST ) can be generated. The triggering signal (V IBST ) causes an increase in the input current supplied to the transmitter (100) or the output current output by the transmitter (100), thereby generating a modulation signal (V OSCP and V OSCN ) can help to re-oscillate. The malfunction prevention circuit (160) is a modulation signal (V OSCP and V OSCN ) is continuously monitored to detect the modulation signal (V OSCP and V OSCN ) repeatedly triggers the signal (V) whenever the oscillation stops. IBST ) can be generated. That is, the malfunction prevention circuit (160) can generate a common mode overvoltage (V CM ) rising section (T + ) can adaptively respond without additional circuit adjustment even if the length of the common mode transient voltage (V CM ) rising section (T +) is mainly described as an example of preventing malfunction of the transmitter (100), but the present disclosure is not limited thereto. The malfunction prevention circuit (160) is configured to prevent common mode overvoltage (V CM ) of the descending section (T - ) can be applied without any change in the actual technical idea even in the case where the transmitter (100) malfunctions.

[0049] Hereinafter, various configuration examples of a quasi-receiver (170) and a current boost circuit (190) for implementing the above-described operation will be described with reference to FIGS. 5 to 8.

[0050] Fig. 5 is a schematic diagram of a receiver according to one embodiment of the present disclosure. Fig. 6 is a schematic diagram of a quasi-receiver according to one embodiment of the present disclosure.

[0051] Referring to FIGS. 5 and 6, the receiver (140) and the quasi-receiver (170) may have the same or similar circuit configurations. That is, in the present disclosure, the quasi-receiver (170) having the same or similar structure as the receiver (140) is placed on the transmitter (100) side, and the modulation signal (V OSCP and V OSCN ) can detect whether the signal is oscillating. The fact that the receiver (140) and the quasi-receiver (170) have the same or similar structure may mean that they demodulate the signal based on the same demodulation topology. In some examples, the receiver (140) and the quasi-receiver (170) may output voltages having different levels based on whether the input signal is oscillating. For example, the receiver (140) may output a signal (V) transmitted through the insulating core (120). RXP and V RXN ) when the high level output signal (V OUT ) while the quasi-receiver (170) outputs a modulation signal (V OSCP and V OSCN ) does not oscillate, a high-level quasi-demodulation signal (V DET) can be output. As another example, the quasi-receiver (170) can output a modulation signal (V OSCP and V OSCN ) is not oscillating, a low-level quasi-demodulation signal (V DET ) can also be printed.

[0052] The receiver (140) and the quasi-receiver (170) may include a circuit configuration for demodulating the input signal. For example, the receiver (140) may include an envelope detector (520) operating in a second domain, and the quasi-receiver may include an envelope detector (620) operating in a first domain. In some examples, amplifiers (500 and 600) may be provided in front of the envelope detectors (520 and 620). The amplifier (500) of the receiver (140) may amplify a modulation signal (V) transmitted through an insulating core (120). RXP and V RXN ) can be amplified and supplied to the envelope detector (520), and the amplifier (600) of the quasi-receiver (170) can amplify the modulation signal (V) output by the transmitter (100). OSCP and V OSCN ) can be amplified and supplied to the envelope detector (620). Here, the amplifier may be a low noise amplifier (LNA).

[0053] The receiver (140) or quasi-receiver (170) may further include additional circuit configurations for dedicated functions. For example, the receiver (140) may output a signal (V) by a detection delay in the quasi-receiver (170). OUT ) may further include a low-pass filter (540). The filter applied to the receiver (140) has a disadvantage of increasing the propagation delay of the signal isolation circuit (10), and thus needs to be minimized to ensure the data transmission rate, and the output signal (V) that may be generated by the response delay of the quasi-receiver (170) OUT) can be removed through short filters that minimize data rate degradation because the glitches are on the order of a few nanoseconds or less.

[0054] Meanwhile, the receiver (140) and quasi-receiver (170) may employ any type of receiver structure that can be used in the on-off keying protocol. Since the specific structure can be selected in various ways depending on the type of isolation channel and the type of transmitter (100), the present disclosure does not limit it in any particular way.

[0055] FIG. 7 and FIG. 8 are circuit diagrams schematically illustrating a current boost circuit according to various embodiments of the present disclosure.

[0056] Referring to Fig. 7, the current boost circuit (190a) receives the input signal (V) which is the modulated signal. IN ) and the level of the quasi-demodulated signal (V DET ) may include a comparison circuit (700) for comparing the levels of the input and output signals. The comparison circuit (700) may be implemented as a combinational circuit. Meanwhile, in FIG. 7, an example in which the comparison circuit (700) is composed of an inverter and an AND gate is illustrated, but the present invention is not limited thereto and may be composed of various other types of combinational circuits.

[0057] The comparison circuit (700) is an input signal (V IN ) is a high level and a quasi-demodulated signal (V DET ) is at a low level, the output (CMT) is at a high level BST ) can be configured to generate an input signal (V IN ) is at a low level, the comparison circuit (700) is deactivated and the output of the comparison circuit (700) (CMT BST ) is maintained at a low level, and the input signal (V IN ) is at a high level, the comparison circuit (700) is activated and a quasi-demodulation signal (V DET ) by the level of the comparison circuit (700) output (CMT) BST) can be determined. That is, the modulation signal (V OSCP and V OSCN ) is a quasi-demodulation signal (V) indicating a stopped section of the oscillation DET ) is an input signal (V) by a comparison circuit (700). IN ) is synchronized with the input signal (V IN ) can be activated when the level is high.

[0058] Input signal (V IN ) is a quasi-demodulated signal (V) in the time interval where the DET ) transitions from a high level to a low level, the output of the comparison circuit (700) (CMT BST ) can transition from a low level to a high level. The output of the comparison circuit (700) (CMT BST ) is a triggering signal (V) that passes through one or more buffers. IBST ) can be converted into a triggering signal (V IBST ) by modulation signal (V OSCP and V OSCN ) resumes, the quasi-demodulation signal (V DET ) transitions from low level to high level, and the output of the comparison circuit (700) (CMT BST ) and triggering signal (V IBST ) can transition from high level to low level again.

[0059] Referring to Fig. 8, the current boost circuit (190b) may further include a one-shot trigger circuit (800). The one-shot trigger circuit (800) outputs the comparison circuit (CMT BST ) detects the edge of the signal (CMT) with a predetermined pulse width. BSTE ) can be output. For example, the input signal (V IN ) is a quasi-demodulated signal (V) in the time interval where the DET ) transitions from a high level to a low level, the output of the comparison circuit (700) (CMT BST) can transition from a low level to a high level. The one-shot trigger circuit (800) outputs the comparison circuit (700) (CMT BST ) detects the rising edge of the output signal (CMT) BSTE ) can transition from low level to high level. Output signal (CMT BSTE ) is a triggering signal (V) that passes through one or more buffers. IBST ) can be converted into the output signal (CMT) of the one-shot trigger circuit (800). BSTE ) and triggering signal (V IBST ) can transition from a high level to a low level again after a pre-designed time interval has elapsed.

[0060] In this way, the current boost circuit (190b) triggers the triggering signal (V IBST ) can minimize glitches that may occur due to detection delay of the quasi-receiver (170) by increasing the length of the time interval in which the high level is present. Meanwhile, the pulse width increased by the one-shot trigger circuit (800) is at a very small level of several tens of ns, and thus the power consumption can still be maintained at a low level.

[0061] FIG. 9 and FIG. 10 are exemplary circuit diagrams for reference to explain an example in which a malfunction prevention circuit according to one embodiment of the present disclosure is applied to a magnetic coupling-based galvanic isolation type signal isolation circuit.

[0062] Fig. 9 shows an example of a galvanic isolation type signal isolation circuit (10a) based on magnetic coupling including a malfunction prevention circuit (160).

[0063] As illustrated in FIG. 9, a transmitter (100a) of a magnetic coupling-based galvanic isolation type signal isolation circuit (10a) may include a cross-coupled LC oscillator configured to generate a signal oscillating at a predetermined frequency.

[0064] In the cross-coupled LC oscillator, the input signal (V IN ), the first tail current (I) of the cross-coupled LC oscillator is TAIL ) can be connected to a first switching element (SW1) that selectively conducts or blocks the path of the input signal (V IN ) has a high level, the first switch element (SW1) is turned on and the first tail current (I TAIL ) is connected, and this initiates the operation of the cross-coupled LC oscillator, generating a high-frequency modulation signal (V OSCP and V OSCN ) can be created.

[0065] Common mode transient voltage (V CM ) due to the rise of the common mode transient current (I ) of sufficiently large magnitude. CMTI+ ) is introduced into the output side of the cross-coupled LC oscillator, the modulation signal (V OSCP and V OSCN ) stops oscillating. The modulation signal (V OSCP and V OSCN ) is a transistor of a cross-coupled LC oscillator (e.g., a supply voltage (V CC ) side, the body-diode voltage drop of the P-channel MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) connected to the supply voltage (V CC ) can be fixed at a higher voltage.

[0066] In this situation, to increase the tail current of the cross-coupled LC oscillator, a boosting signal (V IBST ), the second tail current (I of the cross-coupled LC oscillator BST ) may be further connected to selectively conduct or block the path of the second switching element (SW2). For example, a triggering signal (V) may be connected by a malfunction prevention circuit (160). IBST) transitions to a high level, the second switch element (SW2) is turned on and the second tail current (I BST ) is connected, and the size of the total tail current of the cross-coupled LC oscillator increases accordingly, resulting in a modulation signal (V OSCP and V OSCN ) may resume rash.

[0067] Figure 10 shows the modulation signal (V) output by the cross-coupled LC oscillator. OSCP and V OSCN ) shows an example of a quasi-receiver (170a) for detecting the onset (or cessation of onset).

[0068] Referring to Fig. 10, the quasi-receiver (170a) receives a high-frequency modulation signal (V) formed by a cross-coupled LC oscillator. OSCP and V OSCN ) may include a capacitor cross-coupled LNA (600a) to amplify the input signal. Meanwhile, in the example of FIG. 10, considering that the cross-coupled LC oscillator outputs a high-level signal when the input signal is at a low level, the capacitor cross-coupled LNA (600a) was designed using a P-channel MOSFET, but the present disclosure is not limited thereto.

[0069] FIG. 11 and FIG. 12 are exemplary circuit diagrams for reference to explain an example in which a malfunction prevention circuit according to one embodiment of the present disclosure is applied to a galvanic isolation type signal isolation circuit based on capacitive coupling.

[0070] Fig. 11 shows an example of a galvanic isolation type signal isolation circuit (10b) based on capacitive coupling including a malfunction prevention circuit (160).

[0071] As shown in Fig. 11, the transmitter (100b) of the galvanic isolation type signal isolation circuit (10b) based on capacitive coupling is configured to output the output signal of the oscillator (OSC) and the input signal (V IN) can be used to perform on-off keying modulation by AND gating. The output of the AND gate (V IN_BFP ) is the input signal (V IN ) based on the level of the input signal (V IN ) and an output signal of the oscillator circuit. The oscillator (OSC) may be, for example, a ring oscillator or a voltage controlled oscillator (VCO). In some examples, the oscillator (OSC) and the AND gate may be collectively referred to as a modulation circuit.

[0072] The high frequency signal (V) output by the modulation circuit IN_BFP ) can be transmitted across the insulation barrier of the insulation core (120), a buffer circuit (BFP and BFN) may be provided between the modulation circuit and the insulation core (120). A signal (V) in single-ended form IN_BFP ) from the differential form modulation signal (V OSCP and V OSCN ) can be used to create multiple buffer circuits (BFP and BFN) and inverters.

[0073] Meanwhile, the common mode transient voltage (V CM ) of the time-varying pressure ratio (dV) CM When / dt) is high, the common mode transient current (I) is larger than the current capacity of the buffer circuit (BFP and BFN). CMTI+ ) can be introduced to the output side of the buffer circuit (BFP and BFN). In this case, the buffer circuit (BFP and BFN) outputs a high-frequency signal (V IN_BFP ) cannot be transmitted normally, and the output voltage of the buffer circuit (BFP and BFN) is lower than the supply voltage (V CC ) or can be fixed to the ground.

[0074] The malfunction prevention circuit (160) prevents the modulation signal (V) caused by such malfunction. OSCP and V OSCN) to detect the oscillation stop and to cause an increase in the output current of the buffer circuit (BFP and BFN). IBST ) can be created.

[0075] Figure 12 shows an example of a buffer circuit (BFP and BFN) that can selectively increase the output current capacity.

[0076] As illustrated in Fig. 12, the buffer circuit (BFP and BFN) may include an inverter chain (1200) in which a plurality of inverters are sequentially connected, at least one additional inverter (1220) for providing additional current capacity, and a switch element (SW) for selectively connecting the inverter chain (1200) and the additional inverter (1220). The switch element (SW) may be configured to receive a triggering signal (V IBST ) can be controlled by a triggering signal (V IBST ) has a high level, the switch element (SW) is turned on so that the last inverter of the inverter chain (1200) and the additional inverter (1220) can be connected in parallel. That is, the additional inverter (1220) receives the modulation signal (V OSCP and V OSCN ) is stopped, the output current of the buffer circuit (BFP and BFN) is increased, thereby increasing the modulation signal (V OSCP and V OSCN ) may help to resume the rash.

[0077] FIG. 13 is an exemplary circuit diagram for reference to explain another example in which a malfunction prevention circuit according to one embodiment of the present disclosure is applied to a magnetic coupling-based galvanic isolation type signal isolation circuit.

[0078] Referring to Fig. 13, the aforementioned transmitter (100b) may also be applied to a galvanic isolation-type signal isolation circuit (10c) based on magnetic coupling. For example, the malfunction prevention circuit (160) can detect a malfunction of the transmitter (100b) in the falling section of the secondary potential through the quasi-receiver (160), thereby preventing the output of the receiver (140) from being erroneously demodulated.

[0079] In the above, common mode transients were assumed as an example of a cause of malfunction of a signal isolation circuit, but the present disclosure can be applied to signal transmission malfunctions due to various other causes without any change in the actual technical idea.

[0080] FIG. 14 is an exemplary waveform diagram used to explain a signal transmission malfunction that may occur as the signal strength of on-off keying modulation decreases. FIG. 15 is a waveform diagram used to explain the operation of a malfunction prevention circuit according to an embodiment of the present disclosure.

[0081] Referring to Fig. 14, the signal strength of the on-off keying modulation may be reduced due to various reasons such as temperature, process, supply voltage change, EMI, etc., and thus, a signal transmission malfunction may occur between the transmitter (100, 100a, or 100b) and the receiver (140). For example, in the time period (T) shown in Fig. 14, the input signal (V) of the transmitter IN ) was high, but the output signal (V) had a low level due to a signal transmission malfunction. OUT ) can be restored.

[0082] Referring to FIG. 15, a malfunction prevention circuit (160) or a signal isolation circuit (10, 10a, 10b or 10c) including the same according to various embodiments of the present disclosure is configured to modulate a modulation signal (V) oscillated by a transmitter (100, 100a or 100b). OSCP and V OSCN ) is to be output (e.g., input signal (VIN ) is at a high level), the actual modulation signal (V OSCP and V OSCN ) detects the cessation of the oscillation and triggers the triggering signal (V IBST ) can be generated. The triggering signal (V IBST ) causes an increase in the input current supplied to the transmitter (100, 100a or 100b) or the output current output by the transmitter (100, 100a or 100b) to generate a modulation signal (V OSCP and V OSCN ) can help to re-oscillate. The malfunction prevention circuit (160) is a modulation signal (V OSCP and V OSCN ) is continuously monitored to detect the modulation signal (V OSCP and V OSCN ) repeatedly triggers the signal (V) whenever the oscillation stops. IBST ) can occur. That is, the malfunction prevention circuit (160) can adaptively respond without additional circuit adjustment even if the length of the time interval (T) in which the signal transmission malfunction occurs changes.

[0083] Each component of the device or method according to the present disclosure may be implemented in hardware, software, or a combination of hardware and software. Furthermore, the functions of each component may be implemented in software, with a microprocessor configured to execute the software functions corresponding to each component.

[0084] Various implementations of the systems and techniques described herein may be implemented as digital electronic circuits, integrated circuits, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), computer hardware, firmware, software, and / or combinations thereof. These various implementations may include implementations of one or more computer programs executable on a programmable system. The programmable system includes at least one programmable processor (which may be a special purpose processor or a general purpose processor) coupled to receive data and instructions from and transmit data and instructions to a storage system, at least one input device, and at least one output device. Computer programs (also known as programs, software, software applications, or code) include instructions for the programmable processor and are stored on a "computer-readable recording medium."

[0085] A computer-readable recording medium includes any type of recording device that stores data that can be read by a computer system. Such a computer-readable recording medium may be a non-volatile or non-transitory medium such as a ROM, CD-ROM, magnetic tape, floppy disk, memory card, hard disk, magneto-optical disk, storage device, and may further include a transitory medium such as a data transmission medium. Furthermore, the computer-readable recording medium may be distributed across network-connected computer systems, so that computer-readable code can be stored and executed in a distributed manner.

[0086] Although the flowchart / timing diagram of this specification describes each process as being executed sequentially, this is merely an illustrative description of the technical idea of ​​one embodiment of the present disclosure. In other words, a person of ordinary skill in the art to which one embodiment of the present disclosure belongs may modify and apply various modifications and variations by changing the order described in the flowchart / timing diagram without departing from the essential characteristics of one embodiment of the present disclosure, or by executing one or more of the processes in parallel. Therefore, the flowchart / timing diagram is not limited to a chronological order.

[0087] The above description is merely an example of the technical idea of ​​the present embodiment, and those skilled in the art will appreciate that various modifications and variations can be made without departing from the essential characteristics of the present embodiment. Therefore, the present embodiments are not intended to limit the technical idea of ​​the present embodiment, but rather to explain it, and the scope of the technical idea of ​​the present embodiment is not limited by these embodiments. The scope of protection of the present embodiment should be interpreted by the claims below, and all technical ideas within a scope equivalent thereto should be interpreted as being included in the scope of rights of the present embodiment.

[0088] (Explanation of symbols)

[0089] 10: Signal isolation circuit

[0090]

[0091]

[0092] CROSS-REFERENCE TO RELATED APPLICATION

[0093] This patent application claims priority to Korean Patent Application No. 10-2024-0073080, filed in Korea on June 4, 2024, and Korean Patent Application No. 10-2024-0093076, filed in Korea on July 15, 2024, the entire contents of which are incorporated herein by reference.

Claims

1. A signal isolation circuit for signal transmission between electrically isolated domains, A transmitter configured to modulate a first signal on a first domain to generate a second signal; An insulating core configured to transmit the second signal from the first domain to the second domain; A receiver configured to demodulate the second signal on the second domain to generate a third signal; A quasi-receiver provided between the transmitter and the insulating core, which demodulates the second signal into a fourth signal on the first domain; and A current boost circuit configured to selectively increase an input current supplied to the transmitter or an output current output by the transmitter based on the first signal and the fourth signal. A signal isolation circuit including:

2. In paragraph 1, The transmitter is configured to output the second signal that selectively oscillates based on the level of the first signal, A signal isolation circuit wherein the above-mentioned quasi-receiver is configured to output the fourth signal having a different level depending on whether the second signal is oscillated.

3. In paragraph 1, A signal isolation circuit, wherein the current boost circuit is configured to output a fifth signal that triggers an increase in the input current or the output current based on the level of the first signal and the level of the fourth signal.

4. In paragraph 1, The above current boost circuit includes a comparison circuit that compares the level of the first signal and the level of the fourth signal, A signal isolation circuit in which the level of the output signal of the comparison circuit transitions when the fourth signal transitions to have a different level from the first signal.

5. In paragraph 4, The transmitter outputs the second signal that oscillates based on the first signal having a first logic level, The above comparison circuit is, The first signal is activated based on having the first logic level, A signal isolation circuit in which, when the level of the fourth signal transitions from the first logic level to the second logic level, the level of the output signal transitions from the second logic level to the first logic level.

6. In paragraph 4, The above current boost circuit, A signal isolation circuit further comprising a one-shot trigger circuit configured to generate a sixth signal having a predetermined pulse width based on an edge of an output signal of the above comparison circuit.

7. In paragraph 1, A signal isolation circuit wherein the receiver and the quasi-receiver have the same circuit configuration.

8. In paragraph 7, The above receiver and the above quasi-receiver each include a first circuit configuration for demodulating the second signal, A signal isolation circuit, wherein the receiver further includes a second circuit configuration for preventing glitches in the third signal.

9. In paragraph 8, The above first circuit configuration includes a low noise amplifier and an envelope detector, The second circuit configuration is a signal isolation circuit including a low-pass filter.

10. In paragraph 1, The above transmitter, A cross-coupled LC oscillator configured to generate a signal oscillating at a predetermined frequency; and A first switching element that selectively conducts or blocks a path of a first tail current of the cross-coupled LC oscillator based on the level of the first signal; and A second switching element that selectively conducts or blocks the path of the second tail current of the cross-coupled LC oscillator based on the output of the current boost circuit. A signal isolation circuit including:

11. In paragraph 1, The above transmitter, A modulation circuit that selectively outputs the first signal and the output signal of the oscillator circuit based on the level of the first signal; and It includes a buffer circuit that outputs the second signal based on the output of the modulation circuit, The above buffer circuit, multiple inverters; and A signal isolation circuit comprising a switching element that selectively connects some of the plurality of inverters to the remaining inverters based on the output of the current boost circuit.

12. As a transmission circuit for signal transmission to different domains, A transmitter configured to modulate a first signal on a first domain to generate a second signal; A quasi-receiver that demodulates the second signal into a fourth signal on the first domain; and A current boost circuit configured to selectively increase an input current supplied to the transmitter or an output current output by the transmitter based on the first signal and the fourth signal. A transmission circuit including:

13. In paragraph 12, The above current boost circuit includes a comparison circuit that compares the level of the first signal and the level of the fourth signal, A transmitting circuit in which the level of the output signal of the comparison circuit transitions when the fourth signal transitions to have a different level from the first signal.

14. In paragraph 13, The transmitter outputs the second signal that oscillates based on the first signal having a first logic level, The above comparison circuit is, The first signal is activated based on having the first logic level, A signal isolation circuit in which, when the level of the fourth signal transitions from the first logic level to the second logic level, the level of the output signal transitions from the second logic level to the first logic level.

15. In paragraph 13, The above current boost circuit, A signal isolation circuit further comprising a one-shot trigger circuit configured to generate a sixth signal having a predetermined pulse width based on an edge of an output signal of the above comparison circuit.

16. In paragraph 12, The above transmitter, A cross-coupled LC oscillator configured to generate a signal oscillating at a predetermined frequency; and A first switching element that selectively conducts or blocks a path of a first tail current of the cross-coupled LC oscillator based on the level of the first signal; and A second switching element that selectively conducts or blocks the path of the second tail current of the cross-coupled LC oscillator based on the output of the current boost circuit. A signal isolation circuit including:

17. In paragraph 12, The above transmitter, A modulation circuit that selectively outputs the first signal and the output signal of the oscillator circuit based on the level of the first signal; and It includes a buffer circuit that outputs the second signal based on the output of the modulation circuit, The above buffer circuit, multiple inverters; and A signal isolation circuit comprising a switching element that selectively connects some of the plurality of inverters to the remaining inverters based on the output of the current boost circuit.

18. A circuit provided on the transmitter side to prevent malfunction of the signal isolation circuit. A quasi-receiver that demodulates the second signal output by the transmitter into a fourth signal; and A current boost circuit configured to selectively increase an input current supplied to the transmitter or an output current output by the transmitter based on a first signal and a fourth signal, which are modulated signals of the second signal. A circuit including.

19. In paragraph 18, The current boost circuit includes a comparison circuit that compares the level of the first signal and the level of the fourth signal, A circuit in which the level of the output signal of the comparison circuit transitions when the fourth signal transitions to have a different level from the first signal.

20. In paragraph 19, The above current boost circuit, A circuit further comprising a one-shot trigger circuit configured to generate a sixth signal having a predetermined pulse width based on an edge of an output signal of the above comparison circuit.

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