Curing method in three-dimensional memory

Abstract

Disclosed is a curing method in a three-dimensional memory. According to one embodiment, the curing method in a three-dimensional memory may comprise a step of performing a UV exposure process together with a low-temperature annealing process at a temperature below a preset temperature value for the three-dimensional memory. By proposing a curing method for performing a UV exposure process together with a low-temperature annealing process at a temperature below a temperature value that begins to cause performance degradation of a three-dimensional memory, a technical effect of solving performance degradation problems of a memory due to a high-temperature annealing process can be achieved.

Description

Curing method in three-dimensional memory

[0001] The examples below describe a curing method in a three-dimensional memory.

[0002] As NAND flash memory and DRAM are implemented in a three-dimensional structure, moving away from the two-dimensional structure, in line with the trend toward high integration to secure storage space, three-dimensional NAND flash memory and three-dimensional DRAM have been proposed.

[0003] A three-dimensional NAND flash memory has a structure including gate electrodes (EL1, EL2, EL3) that are formed horizontally and vertically spaced apart from each other on a substrate (SUB) as illustrated in FIG. 1, interlayer insulating layers (ILD) interposed between the gate electrodes (EL1, EL2, EL3), channel holes (CH) that extend vertically and penetrate the gate electrodes (EL1, EL2, EL3) and the interlayer insulating layers (ILD), and vertical channel structures (VCHS) formed within the channel holes (CH), each of the vertical channel structures (VCHS) including a vertical channel pattern (VCHP) that extends vertically and a data storage pattern (DSP) that is formed in contact with an outer wall of the vertical channel pattern (VCHP).

[0004] In a 3D NAND flash memory of this structure, a high-temperature annealing process of 800 degrees or more is performed to cure the grains of the vertical channel pattern, which may cause problems such as deterioration of the memory performance due to transistor deterioration and substrate deformation.

[0005] Meanwhile, the 3D DRAM has a structure including gate electrodes (EL1, EL2, EL3) that are formed horizontally and vertically spaced apart from each other on a substrate (SUB) as illustrated in FIG. 2, interlayer insulating layers (ILD) interposed between the gate electrodes (EL1, EL2, EL3), holes (H) that extend vertically and penetrate the gate electrodes (EL1, EL2, EL3) and the interlayer insulating layers (ILD), and vertical conductive structures (VCOS) formed within the holes (H), each of the vertical conductive structures (VCOS) including a vertical conductive pattern (VCOP) that extends vertically and a data storage pattern (DSP) that is formed in contact with an outer wall of the vertical conductive pattern (VCOP).

[0006] In 3D DRAMs with this structure, a high-temperature annealing process of over 800 degrees is performed to cure the combination of data storage patterns, which may cause problems such as deterioration of memory performance due to transistor deterioration and substrate deformation.

[0007] Therefore, there is a need to propose a technology to solve the problem of memory performance degradation due to high-temperature annealing process in existing 3D NAND flash memory and 3D DRAM.

[0008]

[0009] One embodiment proposes a curing method that performs a UV exposure process together with a low-temperature annealing process below a temperature value that begins to cause performance degradation of a three-dimensional memory, in order to address the problem of performance degradation of the memory due to a high-temperature annealing process.

[0010] However, the technical problems to be solved by the present invention are not limited to the above problems, and can be expanded in various ways without departing from the technical spirit and scope of the present invention.

[0011] According to one embodiment, a curing method in a three-dimensional NAND flash memory may include performing a UV exposure process together with a low-temperature annealing process below a preset temperature value for a three-dimensional NAND flash memory including vertical channel structures formed vertically extending within channel holes, each of the vertical channel structures including a vertical channel pattern formed vertically extending and a data storage pattern formed in contact with an outer wall of the vertical channel pattern.

[0012] According to one aspect, the step of performing the UV exposure process may include a step of performing curing for at least one of surface modification of the channel holes, grain of the vertical channel pattern, bonding of the data storage pattern, or dangling bonding between the vertical channel pattern and the data storage pattern through the UV exposure process.

[0013] According to another aspect, the step of performing the curing may be characterized by including a step of performing the UV exposure process on one of the sub-vertical channel patterns at a time point immediately after one of the sub-vertical channel patterns is formed and before the other of the sub-vertical channel patterns is formed, so as to perform curing on grains of one of the sub-vertical channel patterns included in the vertical channel pattern when the vertical channel pattern has a dual structure.

[0014] According to another aspect, the step of performing the UV exposure process may be characterized as a step of performing the UV exposure process on the channel holes immediately after the etching process of the channel holes to perform curing for surface modification of the channel holes.

[0015] According to another aspect, the step of performing the UV exposure process may be characterized as a step of performing the UV exposure process on the vertical channel pattern immediately after the forming process of the vertical channel pattern to perform curing on the grain of the vertical channel pattern.

[0016] According to another aspect, the step of performing the UV exposure process may be characterized as a step of performing the UV exposure process on the data storage pattern immediately after the process of forming the data storage pattern to perform curing for bonding the data storage pattern.

[0017] According to another aspect, the step of performing the UV exposure process may be characterized as a step of performing the UV exposure process on the vertical channel pattern and the data storage pattern after the process of forming the data storage pattern and immediately after the process of forming the vertical channel pattern to perform curing for dangling bonds between the vertical channel pattern and the data storage pattern.

[0018] According to another embodiment, a curing method in a three-dimensional DRAM may include performing a UV exposure process together with a low-temperature annealing process below a preset temperature value for a three-dimensional DRAM including vertical conductive structures formed vertically extending within holes, each of the vertical conductive structures including a vertical conductive pattern formed vertically extending and a data storage pattern formed in contact with an outer wall of the vertical conductive pattern.

[0019] According to one aspect, the step of performing the UV exposure process may be characterized by including a step of performing curing for at least one of surface modification of the holes or bonding of the data storage pattern through the UV exposure process.

[0020] According to another aspect, the step of performing the UV exposure process may be characterized as a step of performing the UV exposure process on the holes immediately after the etching process of the holes to perform curing for surface modification of the holes.

[0021] According to another aspect, the step of performing the UV exposure process may be characterized as a step of performing the UV exposure process on the data storage pattern immediately after the process of forming the data storage pattern to perform curing for bonding the data storage pattern.

[0022] According to another embodiment, a curing method in a three-dimensional memory may include performing a UV exposure process together with a low-temperature annealing process below a preset temperature value for the three-dimensional memory.

[0023] One embodiment proposes a curing method that performs a UV exposure process together with a low-temperature annealing process below a temperature value that begins to cause performance degradation of a three-dimensional memory, thereby achieving a technical effect that solves the problem of performance degradation of a memory due to a high-temperature annealing process.

[0024] However, the effects of the present invention are not limited to the above effects, and can be expanded in various ways without departing from the technical spirit and scope of the present invention.

[0025]

[0026] FIG. 1 is a cross-sectional view illustrating a three-dimensional NAND flash memory according to an embodiment.

[0027] FIG. 2 is a cross-sectional view illustrating a three-dimensional DRAM according to an embodiment.

[0028] Figure 3 is a flow chart illustrating a curing method according to an embodiment.

[0029] FIGS. 4 to 8 are drawings for explaining a case where the curing method illustrated in FIG. 3 is performed on a three-dimensional NAND flash memory.

[0030] FIGS. 9 and 10 are drawings for explaining a case where the curing method illustrated in FIG. 3 is performed on a 3D DRAM.

[0031] Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings. However, the present invention is not limited or restricted by these embodiments. In addition, the same reference numerals in each drawing represent the same components.

[0032] In addition, the terminology used in this specification is a term used to appropriately express the preferred embodiments of the present invention, and this may vary depending on the intention of the viewer or operator, or the customs of the field to which the present invention belongs. Therefore, the definition of these terms should be determined based on the contents throughout this specification. For example, in this specification, the singular also includes the plural unless specifically stated in the phrase. In addition, the terms "comprises" and / or "comprising" as used herein do not exclude the presence or addition of one or more other components, steps, operations, and / or elements with respect to the mentioned components, steps, operations, and / or elements. In addition, although the terms first, second, etc. are used in this specification to describe various regions, directions, shapes, etc., these regions, directions, and shapes should not be limited by these terms. These terms are only used to distinguish a certain region, direction, or shape from another region, direction, or shape. Therefore, a part referred to as a first part in one embodiment may be referred to as a second part in another embodiment.

[0033] It should also be understood that the various embodiments of the present invention, while different, are not necessarily mutually exclusive. For example, specific shapes, structures, and characteristics described herein may be implemented in other embodiments without departing from the spirit and scope of the present invention. Furthermore, it should be understood that the location, arrangement, or configuration of individual components within each of the disclosed embodiments may be modified without departing from the spirit and scope of the present invention.

[0034] Hereinafter, with reference to the drawings, a curing method is described in detail, which performs a UV exposure process together with a low-temperature annealing process below a temperature value that begins to cause performance degradation of a 3D memory, in order to solve the problem of performance degradation of a memory due to a high-temperature annealing process.

[0035]

[0036] FIG. 3 is a flow chart illustrating a curing method according to an embodiment, FIGS. 4 to 8 are drawings for explaining a case where the curing method illustrated in FIG. 3 is performed on a three-dimensional NAND flash memory, and FIGS. 9 to 10 are drawings for explaining a case where the curing method illustrated in FIG. 3 is performed on a three-dimensional DRAM.

[0037] The curing method described below is assumed to be performed by a mechanized and automated semiconductor processing system that performs a low-temperature annealing process and a UV exposure process for a three-dimensional memory.

[0038] The three-dimensional memory described below may include conventional three-dimensional NAND flash memory and three-dimensional DRAM. That is, the curing method described below may be performed on three-dimensional memory including three-dimensional NAND flash memory and three-dimensional DRAM.

[0039] Referring to FIG. 3, in step (S310), the semiconductor process processing system can perform a UV exposure process together with a low-temperature annealing process below a preset temperature value for a three-dimensional memory.

[0040] Here, the temperature value at which the low-temperature annealing process is performed can be preset to a temperature (e.g., 600 degrees) that begins to cause performance degradation of the 3D memory.

[0041] Since the low-temperature annealing process is performed in the same manner as the conventional annealing process except for the conditions of the described temperature values, a detailed description thereof will be omitted.

[0042] The UV exposure process is a process of irradiating a target object with UV light in a wavelength range of 214 nm to 276 nm, and the exposure time (irradiation time), number of exposures (irradiation counts), etc. can be adaptively adjusted. For example, the exposure time (irradiation time), number of exposures (irradiation counts), etc. of the UV exposure process can be adjusted to meet the conditions for achieving the curing purpose.

[0043] Since the three-dimensional memory includes three-dimensional NAND flash memory and three-dimensional DRAM, the described step (S310) can be performed on the three-dimensional NAND flash memory or the three-dimensional DRAM. However, the three-dimensional memory is not limited thereto and can include various memories having a three-dimensional structure, and the described step (S310) can be performed on various memories having a three-dimensional structure.

[0044] For example, in step (S310), the semiconductor process processing system can cure components of the 3D NAND flash memory by performing a UV exposure process together with a low-temperature annealing process below a preset temperature value for the 3D NAND flash memory.

[0045] For a more specific example, when step (S310) is performed for a 3D NAND flash memory, the semiconductor process processing system can perform curing for at least one of surface modification of channel holes (CH), bonding of grains of vertical channel patterns (VCHP), data storage patterns (DSP), or dangling bonds between vertical channel patterns (VCHP) and data storage patterns (DSP) through a UV exposure process.

[0046] When performing curing for surface modification of channel holes (CH), the semiconductor process processing system can perform a UV exposure process on the channel holes (CH) immediately after the etching process of the channel holes (CH) to perform curing for surface modification of the channel holes (CH) as illustrated in FIG. 4.

[0047] In this way, the UV exposure process performed on the channel holes (CH) can be performed independently of the low-temperature annealing process. That is, the semiconductor processing system can perform the UV exposure process on the channel holes (CH) immediately after the etching process of the channel holes (CH) to perform curing for surface modification of the channel holes (CH).

[0048] When performing curing on grains of a vertical channel pattern (VCHP), the semiconductor process processing system can perform a UV exposure process on the vertical channel pattern (VCHP) immediately after the formation process of the vertical channel pattern (VCHP) to perform curing on grains of the vertical channel pattern (VCHP) as illustrated in FIG. 5.

[0049] If the vertical channel pattern (VCHP) has a dual structure, the semiconductor process processing system can perform a UV exposure process on one of the sub-vertical channel patterns (SUB-VCHP1) included in the vertical channel pattern (VCHP) immediately after one of the sub-vertical channel patterns (SUB-VCHP1) is formed and before the other sub-vertical channel pattern (SUB-VCHP2) is formed, so as to perform curing on the grains of the sub-vertical channel pattern (SUB-VCHP1) included in the vertical channel pattern (VCHP), as shown in FIG. 6.

[0050] Next, the semiconductor process processing system may perform a UV exposure process on the remaining one sub-vertical channel pattern (SUB-VCHP2) immediately after the remaining one sub-vertical channel pattern (SUB-VCHP2) is formed to perform curing on the grains of the remaining one sub-vertical channel pattern (SUB-VCHP2). However, this may be adaptively omitted.

[0051] When performing curing for the combination of data storage patterns (DSP), the semiconductor process processing system can perform a UV exposure process on the data storage pattern (DSP) immediately after the formation process of the data storage pattern (DSP) to perform curing for the combination of the data storage pattern (DSP) as illustrated in FIG. 7.

[0052] When performing curing for dangling bonds between a vertical channel pattern (VCHP) and a data storage pattern (DSP), the semiconductor process processing system can perform a UV exposure process on the vertical channel pattern (VCHP) and the data storage pattern (DSP) after the formation process of the data storage pattern (DSP) and immediately after the formation process of the vertical channel pattern (VCHP) to perform curing for dangling bonds between the vertical channel pattern (VCHP) and the data storage pattern (DSP), as illustrated in FIG. 8.

[0053] As another example, in step (S310), the semiconductor process processing system can cure components of the 3D DRAM by performing a UV exposure process together with a low-temperature annealing process below a preset temperature value for the 3D DRAM.

[0054] For another more specific example, when step (S310) is performed for a 3D DRAM, the semiconductor process processing system can perform curing for at least one of surface modification of holes (H) or bonding of data storage patterns (DSP) through a UV exposure process.

[0055] When performing curing for surface modification of holes (H), the semiconductor process processing system can perform a UV exposure process on the holes (H) immediately after the etching process of the holes (H) to perform curing for surface modification of the holes (CH) as illustrated in FIG. 9.

[0056] When performing curing for the combination of data storage patterns (DSP), the semiconductor process processing system can perform a UV exposure process on the data storage pattern (DSP) immediately after the formation process of the data storage pattern (DSP) to perform curing for the combination of the data storage pattern (DSP) as illustrated in FIG. 10.

[0057] Although the embodiments described above have been described by way of limited examples and drawings, those skilled in the art will appreciate that various modifications and variations can be made based on the above teachings. For example, appropriate results can still be achieved even if the described techniques are performed in a different order than described, and / or components of the described systems, structures, devices, circuits, etc. are combined or combined in a different manner than described, or are replaced or substituted with other components or equivalents.

[0058] Therefore, other implementations, other embodiments, and equivalents to the claims also fall within the scope of the claims described below.

Claims

1. A step of performing a UV exposure process together with a low-temperature annealing process below a preset temperature value for a 3D NAND flash memory including vertical channel structures formed extending in a vertical direction within channel holes, each of the vertical channel structures including a vertical channel pattern formed extending in the vertical direction and a data storage pattern formed in contact with an outer wall of the vertical channel pattern. A curing method in a three-dimensional NAND flash memory including:

2. In paragraph 1, The step of performing the above UV exposure process is: A step of performing curing for at least one of surface modification of the channel holes, grain of the vertical channel pattern, bonding of the data storage pattern, or dangling bonding between the vertical channel pattern and the data storage pattern through the UV exposure process. A curing method in a three-dimensional NAND flash memory, characterized by including:

3. In paragraph 2, The steps for performing the above curing are: In the case where the vertical channel pattern has a dual structure, a step of performing the UV exposure process on one of the sub-vertical channel patterns immediately after one of the sub-vertical channel patterns is formed and before the other of the sub-vertical channel patterns is formed so as to perform curing on the grain of one of the sub-vertical channel patterns included in the vertical channel pattern. A curing method in a three-dimensional NAND flash memory, characterized by including:

4. In paragraph 2, The step of performing the above UV exposure process is: A curing method in a 3D NAND flash memory, characterized in that the step of performing the UV exposure process on the channel holes immediately after the etching process of the channel holes is performed to perform curing for surface modification of the channel holes.

5. In paragraph 2, The step of performing the above UV exposure process is: A curing method in a 3D NAND flash memory, characterized in that the step of performing the UV exposure process on the vertical channel pattern immediately after the formation process of the vertical channel pattern to perform curing on the grain of the vertical channel pattern.

6. In paragraph 2, The step of performing the above UV exposure process is: A curing method in a 3D NAND flash memory, characterized in that the step of performing the UV exposure process on the data storage pattern immediately after the formation process of the data storage pattern is performed to perform curing for the combination of the data storage pattern.

7. In paragraph 2, The step of performing the above UV exposure process is: A curing method in a 3D NAND flash memory, characterized in that the step of performing the UV exposure process on the vertical channel pattern and the data storage pattern after the formation process of the data storage pattern and immediately after the formation process of the vertical channel pattern to perform curing for dangling bonds between the vertical channel pattern and the data storage pattern.

8. A step of performing a UV exposure process together with a low-temperature annealing process below a preset temperature value for a 3D DRAM including vertical conductive structures formed vertically extending within holes, each of the vertical conductive structures including a vertical conductive pattern formed vertically extending and a data storage pattern formed in contact with an outer wall of the vertical conductive pattern. A curing method in a three-dimensional DRAM including:

9. In paragraph 8, The step of performing the above UV exposure process is: A step of performing curing for at least one of surface modification of the holes or combination of the data storage pattern through the above UV exposure process. A curing method in a three-dimensional DRAM, characterized by including:

10. In paragraph 9, The step of performing the above UV exposure process is: A curing method in a 3D DRAM, characterized in that the step of performing the UV exposure process on the holes immediately after the etching process of the holes is performed to perform curing for surface modification of the holes.

11. In paragraph 9, The step of performing the above UV exposure process is: A curing method in a 3D DRAM, characterized in that the step of performing the UV exposure process on the data storage pattern immediately after the formation process of the data storage pattern is performed to perform curing for the combination of the data storage pattern. Step of performing a UV exposure process together with a low-temperature annealing process below a preset temperature value for 12.3-dimensional memory A curing method in a three-dimensional memory including .

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