Circuit unit for actuating a half-bridge circuit, and circuit arrangement

Abstract

The present invention relates to a circuit unit (5, 7) for actuating a half-bridge circuit and to a circuit arrangement having a multiplicity of such circuit units (5, 7). The circuit arrangement is designed to take a control signal (S1, S2) for complementary switching of a first semiconductor switch (T1) and a second semiconductor switch (T2), which form the half-bridge circuit, as a basis for dynamically adapting a dead time between respective switched-on states of the first semiconductor switch (T1) and the second semiconductor switch (T2), in order to reduce a power loss of the circuit arrangement.

Description

[0001] Description

[0002] Title and

[0003] State of the art

[0004] The present invention relates to a circuit unit for controlling a half-bridge circuit and a circuit arrangement with a plurality of such circuit units.

[0005] Power transistors are known from the prior art and are used, among other things, in power electronic half-bridge circuits. Such power electronic half-bridges are used as switching elements in many different applications, such as electric drives, switched-mode power supplies, chargers, etc. They consist of two power transistors connected in series, which are driven alternately by their respective gate drivers. A DC voltage, for example from a battery or a capacitor, is applied across the two power transistors.

[0006] The gate drivers receive respective control signals for a complementary switching on and off of the two power transistors, usually from a control unit (e.g. a microcontroller), which regulates energy conversion for a load located at a node between the two power transistors.

[0007] Typically, the control signals are provided by the control unit or by the gate drivers with a dead time, which ensures that the two power transistors are never simultaneously in an on state, as this would lead to a short circuit of the half-bridge circuit.

[0008] To reduce switching losses in power transistors, a technique called zero-voltage switching (ZVS), also known as soft switching, can be implemented under certain circumstances. Zero-voltage switching ensures that at least some of the turn-on operations of the respective power transistors occur in a state where essentially no or only a small voltage is applied across the switching path of the power transistor being switched on.

[0009] When switching at zero voltage, it is therefore crucial to ensure that the respective power transistor is only switched on after voltage commutation at zero voltage has been completed. For this reason, the dead time should be chosen so that there is at least a very short period, for example a few nanoseconds, between voltage commutation and the switching on of the respective power transistor.

[0010] During this period, an antiparallel diode (freewheeling diode) of the power transistor conducts a current through the half-bridge circuit. If the switch-on process is started too early, significantly increased losses occur during switch-on because the zero voltage across the power transistor being switched on has not yet been reached.

[0011] If, however, the switching-on process is started later than necessary due to an excessively long dead time, the diode conducts the current for a correspondingly long period and also causes increased conduction losses.

[0012] Furthermore, since the dead time varies depending on various influencing factors such as the current, the value of a gate resistance, temperature, etc., a dynamic adjustment of the dead time is important for efficient operation of such half-back switches in zero-voltage switching operation.

[0013] Prior art methods for dynamically adjusting the dead time depending on such influencing factors are based, for example, on the use of models and / or tables, on the basis of which a pre-control of the dead time is carried out.

[0014] Alternatively, the switch-on time can be determined based on a measurement of the voltage across the power transistors. For this purpose, the respective gate driver typically uses a measuring circuit that detects the voltage across the power transistors. This requires additional components and establishes a connection between the high-voltage potential of the power transistors and the respective gate driver, so appropriate isolation distances must be taken into account.

[0015] Disclosure of the invention

[0016] According to a first aspect of the present invention, a circuit unit for controlling a half-bridge circuit is proposed, which may preferably be formed from a series connection of a first semiconductor switch and a second semiconductor switch and which may be supplied with a DC voltage.

[0017] A half-bridge circuit controlled by means of the circuit unit according to the invention is, for example, a half-bridge used in electric drives, switched-mode power supplies, chargers, etc., which can also be one of several parallel-connected half-bridges (e.g. for a multi-phase load), each of which can be controlled by means of a plurality of circuit units according to the invention.

[0018] A load connectable to a midpoint of the half-bridge circuit preferably has an inductive component, such that, based on this inductive component, a current flow in a load circuit of the half-bridge circuit is at least temporarily maintained during a dead-time phase (i.e., a phase in which both semiconductor switches of the half-bridge circuit are in the off state to prevent a short circuit). The circuit unit according to the invention comprises a logic unit, a gate driver, a current sensor, an integrator, a comparator circuit, and a delay element.

[0019] It should be noted that the logic unit can be a single unit or a distributed logic unit, the overall functionality of which can be realized on the basis of a large number of hardware and / or software components, which in particular can be arranged separately.

[0020] It should also be noted that the gate driver in the following description is essentially described as a pure level converter and / or amplifier, which is configured to convert signals provided by the logic unit into suitable signals for controlling a gate of a semiconductor switch. For this purpose, the gate driver is, for example, designed as a so-called "push-pull" stage.

[0021] This does not explicitly exclude the possibility that the gate driver may contain additional components (e.g., the logic unit or part of a distributed logic unit and / or components that differ from this).

[0022] The gate driver is designed to be connected to a gate terminal of a semiconductor switch of a half-bridge circuit, wherein the semiconductor switch may in particular be a power semiconductor switch and / or a MOSFET, an IGBT, a HEMT, or a semiconductor switch other than the above.

[0023] The current sensor is configured, for example, as a shunt resistor and / or a Hall sensor. Furthermore, the current sensor is designed to measure a gate current in a control circuit for the semiconductor switch, where the control circuit is understood to be a circuit formed by the gate driver and a gate-source path (or a gate-emitter path, depending on the specific design of the semiconductor switch). Preferably, such a circuit additionally includes a commonly used gate resistor. Moreover, it is possible for the current sensor to be configured as a separate component or as part of a component of the circuit unit according to the invention, and in particular as part of the gate driver.

[0024] The integrator, which may be configured as an RC circuit and / or operational amplifier circuit and / or in a different configuration, is designed to integrate the gate current (i.e., the current flowing within the gate circuit) measured by the current sensor over time in order to determine the total charge flowing in the gate circuit.

[0025] Furthermore, the integrator is configured to receive a reset signal from the logic unit and, upon receiving this signal, to set a predefined initial value (preferably zero) for the integration of the gate current. Setting the initial value is achieved, for example, by discharging a capacitor used for the integration.

[0026] The comparison circuit, which is designed as a comparator, for example, is set up to compare the determined charge with a charge threshold and to output a first trigger signal to the logic unit if the determined charge reaches or exceeds the charge threshold.

[0027] Advantageously, the charge threshold is set such that it is reached or exceeded by the measured charge when a semiconductor switch of the half-bridge circuit, which is to be switched on by the circuit unit, is still in an off state after another semiconductor switch of the half-bridge circuit has been switched off, and the resulting current flow during voltage commutation is essentially complete due to capacitive coupling. This case occurs when a load current flowing through the half-bridge circuit, after the other semiconductor switch has been switched off, is directed in such a way that such voltage commutation can take place. As a consequence, a current flows through the gate circuit of the semiconductor switch that is still off and is to be switched on.Preferably, the charge threshold is determined as a function of a voltage applied across the half-bridge circuit, since this voltage has a strong influence on the voltage commutation.

[0028] In this way, by appropriately setting the charge threshold, an optimized or optimal switch-on time for the semiconductor switch can be advantageously determined, which ensures that the voltage commutation is essentially complete, so that a soft switch-on or zero-voltage switching of the semiconductor switch is enabled and at the same time an unwanted current flow via a freewheeling diode of the semiconductor switch, which leads to dead-time losses, is essentially prevented.

[0029] It should be noted that, in the present invention, "soft switching" or "zero-voltage switching" refers not only to switching operations when an actual open-circuit voltage is present, but also to switching operations where a residual voltage is present across the semiconductor switch to be switched on at the time of switching. Such a residual voltage can, for example, correspond to several volts. The crucial point is that at least a partially reduced voltage is present compared to the maximum voltage present across the semiconductor switch to be switched on, in order to at least partially reduce switching losses.

[0030] The circuit unit is set up to receive a control signal to turn the semiconductor switch on and off (e.g. from a control unit).

[0031] The delay element is configured to initiate a time measurement upon receiving the control signal to switch on the semiconductor switch and to output a second trigger signal to the logic unit as soon as a predetermined time period has elapsed since the start of the time measurement. The predetermined time period preferably corresponds to a maximum intended dead time for complementary switching of the semiconductor switches in the half-bridge circuit. By means of the predetermined time period, it can be ensured that, in a case where, due to the magnitude and direction of a current in the load circuit, no or incomplete voltage commutation can occur and thus the charge threshold cannot be reached by the charge flowing in the gate circuit, a switch-on operation requested based on the control signal is executed no later than the elapsed time period.

[0032] In this way, it can be ensured that all intended switching operations are carried out correctly, even if, in the case described above, no or no optimal zero-voltage switching is possible and the semiconductor switch to be switched on may be hard-switched.

[0033] The logic unit is accordingly configured to control the gate driver to turn on the semiconductor switch as soon as the first trigger signal and / or the second trigger signal is received, and to control the gate driver to turn off the semiconductor switch as soon as the control signal to turn off is received.

[0034] The logic unit is further configured to output the reset signal to the integrator as soon as the switch-off control signal is received and / or while the semiconductor switch is in an off state. This ensures that the integration of the current in the gate circuit for each switch-on process starts from a defined initial value and thus produces comparable values.

[0035] The logic unit is configured to terminate the output of the reset signal to the integrator no later than upon receipt of the control signal to switch on the semiconductor switch. This ensures that the integrator is able to begin integrating the current flowing in the gate circuit in a timely manner to determine the appropriate switch-on time for the semiconductor switch.

[0036] It should be generally noted that the units used in the claims and in the description of the present invention, such as the logic unit, the gate driver, the current sensor, etc., are to be understood in principle as functional units which, in a real implementation of the circuit unit according to the invention, can be arbitrarily divided and / or physically combined, as long as the overall functionality according to the invention is given.

[0037] The circuit unit according to the invention offers, among other things, the advantage that the circuit unit can independently reduce or optimize switching and dead time losses during soft switching operations, regardless of current boundary conditions (e.g., temperatures, component tolerances, etc.), by very precisely setting a suitable dead time for each switching operation.

[0038] Furthermore, the circuit unit according to the invention does not require the measurement of a high-voltage potential applied across the half-bridge circuit that is required in the prior art, thus eliminating the need to consider the associated high requirements for insulation distances, etc.

[0039] The dependent claims describe preferred embodiments of the invention.

[0040] In a particularly preferred embodiment of the present invention, the circuit unit is designed as a partially or fully integrated circuit. Since the circuit unit according to the invention is configured to determine a suitably adapted (i.e., optimized) dead time based on the integration of the current within the gate circuit, no isolation distances or similar measures need to be considered, which are required in a voltage measurement across the semiconductor switches of the half-bridge circuit as used in the prior art.

[0041] Accordingly, a particularly efficient integration of individual or all components of the circuit unit according to the invention can be achieved, which allows the size and / or manufacturing costs of the circuit unit to be kept particularly low.

[0042] Preferably, the logic unit is configured to output a feedback signal if, during an ongoing control operation to switch on the semiconductor switch, the second trigger signal is received before the first trigger signal. Since the second trigger signal indicates that the charge threshold was not reached when integrating the current in the gate circuit during the current switch-on process, and thus no soft switching or only a partially soft switching was possible, the control signal for the semiconductor switches can be adjusted accordingly based on the feedback signal. This allows, if possible, the subsequent number of soft switching operations to be increased based on the feedback signal.

[0043] Furthermore, the charge threshold may be a predefined value, which could, for example, be stored in a memory unit that is connected to the logic unit via information technology. Alternatively or additionally, the circuit unit is advantageously configured to determine the charge threshold depending on current boundary conditions.

[0044] In a further advantageous embodiment of the present invention, the circuit unit is configured to determine a maximum charge by ascertaining a maximum value of the charge integrated into the integrator over time and defining it as the maximum charge. For this purpose, the circuit unit includes, for example, a peak value detection circuit which continuously or discretely evaluates the charges currently integrated by the integrator in order to determine a peak value of the integrated charges. Alternatively or additionally, the circuit unit is configured to determine the maximum charge by receiving information representing the end time of a switch-on process of the semiconductor switch (e.g., from the control unit) and defining the integrated charge present in the integrator at that end time as the maximum charge.The circuit unit is further configured to receive information about a gate charge, which represents the charge required to fully recharge the gate-source capacitance of the semiconductor switch during a switch-on operation, to subtract the gate charge from the determined maximum charge, and to define the result of the subtraction as the charge threshold. The gate charge information can be received, for example, from the control unit and / or from a storage unit connected to the logic unit. Alternatively or additionally, the information about the charge required to recharge the gate-source capacitance can also be determined automatically during a calibration process described below.Determining the charge threshold as described above offers the particular advantage that the charge threshold is automatically set in accordance with a DC voltage currently applied to the half-bridge circuit, without having to directly measure the DC voltage and adjust the charge threshold based on such a measurement.

[0045] The circuit unit is further advantageously configured to subtract a predefined tolerance value from the charge threshold and to set the result of the subtraction as the current charge threshold. This can be used to advantage, regardless of whether the charge threshold is a predefined value and / or a value determined as above, to explicitly switch on a semiconductor switch controlled by the circuit unit before the voltage commutation is fully completed. This reduces the period during which the freewheeling diode conducts current, thereby further reducing dead-time losses.

[0046] According to a second aspect of the present invention, a circuit arrangement is proposed comprising a first circuit unit and a second circuit unit according to the first aspect of the invention, a half-bridge circuit consisting of a first semiconductor switch and a second semiconductor switch, a control unit, a DC voltage source, and a load. The first semiconductor switch and the second semiconductor switch are, for example, each configured as power semiconductor switches and / or MOSFETs, IGBTs, HEMTs, or otherwise. The DC voltage source, which is configured, for example, as a battery and / or a capacitor and / or otherwise, is configured to supply the half-bridge circuit with a DC voltage (e.g., an intermediate circuit voltage). The load, which has at least an inductive component, is connected to a node (i.e., a junction box).The first semiconductor switch and the second semiconductor switch are electrically connected at a midpoint of the half-bridge circuit. The first circuit unit is configured to control the first semiconductor switch, while the second circuit unit is configured to control the second semiconductor switch. The control unit, which may be an ASIC, FPGA, processor, digital signal processor, microcontroller, or similar device, is configured to generate a first control signal, which is fed into the first circuit unit to switch the first semiconductor switch on and off, and a second control signal, which is fed into the second circuit unit to switch the second semiconductor switch on and off. It should be noted that the first and second control signals can be the same control signal.In such a case, the control signal fed into the first circuit unit can, for example, be fed in unchanged, while the control signal fed into the second circuit unit can be logically inverted using an inverter (non-gate). Alternatively, it is possible to invert the control signal fed into the first circuit unit and use the control signal fed into the second circuit unit unchanged. Crucially, the first control signal must be inverted with respect to the second control signal to ensure complementary switching of the first and second semiconductor switches. The control unit is further configured to provide an alternating voltage to the load by appropriately defining the first and second control signals based on the DC voltage.The features, combinations of features, and the advantages arising therefrom correspond so clearly to those described in connection with the first-mentioned aspect of the invention that reference is made to the above explanations to avoid repetition. In general, the arrangement consisting of the control unit, the circuit units according to the invention, and the half-bridge circuit can be used particularly advantageously for the implementation of soft-switching power electronic converters.

[0047] In an advantageous embodiment of the circuit arrangement according to the invention, the control unit is configured to execute at least part of the switching-on processes of the first semiconductor switch and / or the second semiconductor switch as soft switching-on processes based on the control by the first control signal and by the second control signal.

[0048] Preferably, the control unit of the circuit arrangement according to the invention is configured to receive the feedback signal and to adjust the control of the semiconductor switches of the half-bridge circuit based on the feedback signal. In an exemplary case, where, based on the feedback signal, a number of hard and / or partially hard switching operations per unit of time exceeds a predefined threshold for a maximum intended number of hard switching operations, the control unit can accordingly adjust the modulation of the control signal to potentially perform a lower number of hard switching operations subsequently and / or reduce the power supplied to the load via the half-bridge circuit. Both measures reduce power loss to prevent potential damage to the semiconductor switches due to excessive heating.

[0049] In a further advantageous embodiment of the present invention, the circuit arrangement is configured to determine the gate charge required to completely recharge the respective gate capacitance of the respective semiconductor switches during a switch-on process of the semiconductor switches in a calibration mode of the circuit arrangement. For this purpose, the circuit arrangement is advantageously configured to activate the calibration mode in a state of the circuit arrangement in which the system is unloaded and / or no voltage is applied across the half-bridge circuit. In this state, the circuit arrangement is advantageously configured to switch one of the semiconductor switches of the half-bridge circuit into a switched-on state in order to measure the amount of charge flowing in the gate circuit during the switch-on process, which is required to charge the gate-source capacitance during the switch-on process.This charge quantity, which can advantageously be determined by means of the integrator of the circuit unit according to the invention, represents the gate charge accordingly, so that a value for the determined gate charge can be stored, for example, in a storage unit and used during a subsequent regular switching operation according to the invention.

[0050] Furthermore, the circuit arrangement can be advantageously configured to adjust the time duration considered in the delay element depending on current boundary conditions (e.g., a current DC link voltage and / or a current temperature). Brief description of the drawings

[0051] Exemplary embodiments of the invention are described in detail below with reference to the accompanying drawings. The drawing shows:

[0052] Figure 1 shows a circuit diagram of an embodiment of a circuit unit according to the invention; and

[0053] Figure 2 shows a circuit diagram of an embodiment of a circuit arrangement according to the invention.

[0054] Embodiments of the invention

[0055] Figure 1 shows a circuit diagram of an embodiment of a circuit unit 5 according to the invention, the components of which are described below are preferably integrated into a single chip, without thereby requiring such integration in connection with the present invention.

[0056] The circuit unit 5 includes a logic unit 10, a gate driver 20 designed as an amplifier, a current sensor 30 designed as a Hall element, an integrator 40 designed as an RC low-pass filter, a comparator circuit 50 designed as a comparator, a delay element 60 and a peak detection circuit 110.

[0057] The gate driver 20 is connected via a gate resistor Rg to a gate terminal of a semiconductor switch T1 of a half-bridge circuit, whereby a second semiconductor switch T2 (see Figure 2) of the half-bridge circuit is not shown here. The first semiconductor switch T1 is implemented here as a power MOSFET with an antiparallel-connected freewheeling diode 130 and has the intrinsic capacitances Cgs (gate-source capacitance), Cm (Miller capacitance) and Cds (drain-source capacitance).

[0058] The current sensor 30 is configured to measure a gate current Ig in a control circuit for the semiconductor switch T1. The integrator 40 is configured to integrate the gate current Ig measured by the current sensor 30 over time in order to determine a charge Qg flowing in the gate circuit (i.e., a total charge) and to receive a reset signal Sr from the logic unit 10 and, in response to this, to set a predefined start value for the integration of the gate current Ig.

[0059] For this purpose, the integrator 40, designed as an RC low-pass filter, has, for example, an (not shown) activatable discharge path for the capacitance of the RC low-pass filter in order to discharge the capacitance when responding to the reception of the reset signal Sr.

[0060] The circuit unit 5 is set up on the basis of the peak value detection circuit 110 to determine a maximum charge Qmax by determining a maximum value of the charge Qg integrated in the integrator 40 over time.

[0061] The circuit unit 5 is further configured to receive information about a gate charge Qgs (e.g., from the control unit and / or from a storage unit in which this information may be stored), which represents a charge required to completely recharge the gate-source capacitance Cgs of the semiconductor switch T1 during a switch-on operation of the semiconductor switch T1, to subtract the gate charge Qgs from the maximum charge Qmax, and to use the result of the subtraction as the charge threshold Qs.

[0062] The comparison circuit 50 is set up to compare the determined charge Qg with the charge threshold Qs and to output a first trigger signal St1 to the logic unit 10 if the determined charge Qg reaches or exceeds the charge threshold Qs.

[0063] The circuit unit 5 is further configured to receive a control signal S1 to switch the semiconductor switch T1 on and off.

[0064] The delay element 60 is configured to begin a timing measurement upon receiving the control signal S1 to switch on the semiconductor switch T1 and to output a second trigger signal St2 to the logic unit 10 as soon as a predetermined time duration Tdmax has elapsed since the start of the timing measurement. The logic unit 10 is configured to control the gate driver 20 by means of a switching signal SL to switch on the semiconductor switch T1 as soon as the first trigger signal St1 and / or the second trigger signal St2 is received.

[0065] The logic unit 10 is further configured to control the gate driver 20 by means of a further switching signal SL to switch off the semiconductor switch T1 as soon as the control signal S1 to switch off is received.

[0066] The logic unit 10 is also configured to output the reset signal Sr to the integrator 40 as soon as the control signal S1 to switch off is received and / or while the semiconductor switch T1 is in an off state. The logic unit 10 is further configured to stop outputting the reset signal Sr to the integrator 40 at the latest upon receipt of the control signal S1 to switch on the semiconductor switch T1.

[0067] Furthermore, the logic unit 10 is configured to output a feedback signal Sf1 if, during a current control operation to switch on the semiconductor switch T1, the second trigger signal St2 is received before the first trigger signal St1.

[0068] Figure 2 shows a circuit diagram of an embodiment of a circuit arrangement according to the invention, which has a first circuit unit 5 according to Figure 1 and a second circuit unit 7 according to Figure 1, a half-bridge circuit consisting of a first semiconductor switch T1 and a second semiconductor switch T2, a control unit 70 designed as a microcontroller, a first gate resistor Rg, a second gate resistor Rg', a DC voltage source 80 and an inductive load 90.

[0069] The semiconductor switches T1, T2 each have the intrinsic capacitances Cm, Cgs, Cds and Cm', Cgs', Cds' respectively and are connected antiparallel to corresponding freewheeling diodes 130, 135.

[0070] The circuit units 5, 7, the control unit 70, the gate resistors Rg, Rg' and the semiconductor switches T1, T2 form an inverter which is set up to supply the load 90, which is electrically connected to a node 100 between the first semiconductor switch T1 and the second semiconductor switch T2, with an alternating voltage on the basis of a DC voltage Ude provided by the DC voltage source 80.

[0071] For this purpose, the first circuit unit 5 is set up to control the first semiconductor switch T1, while the second circuit unit 7 is set up to control the second semiconductor switch T2.

[0072] The control unit 70 is set up to generate a first control signal S1, which is fed into the first circuit unit 5 as the control signal for switching on and off the first semiconductor switch T1.

[0073] The circuit arrangement is also designed to generate a second control signal S2 from the first control signal S1 by means of an inverter 120, which is accordingly inverted with respect to the first control signal S1, and to feed the second control signal S2 into the second circuit unit 7 as the control signal for switching on and off the second semiconductor switch T2.

[0074] Based on the control by the control unit 70, the circuit arrangement is set up to provide the load 90 with the AC voltage described above by means of a suitable determination of the first control signal S1 and the second control signal S2 based on the DC voltage Ude, so that a load current IL can flow through the load 90 to operate the load 90.

Claims

Claims 1. Circuit unit (5) comprising for controlling a half-bridge circuit: - a logic unit (10), - a gate driver (20), - a current sensor (30), - an integrator (40), - a comparison circuit (50), and - a delay element (60), wherein - the gate driver (20) is set up to be connected to a gate terminal of a semiconductor switch (T1, T2) of a half-bridge circuit, - the current sensor (30) is set up to measure a gate current (Ig) in a control circuit for the semiconductor switch (T1 , T2), - the integrator (40) is set up, - to integrate the gate current (Ig) measured by the current sensor (30) over time in order to determine a charge (Qg) flowing in the gate circuit, and - to receive a reset signal (Sr) from the logic unit (10) and, in response to it, to set a predefined start value for the integration of the gate current (Ig), - the comparison circuit (50) is set up to compare the determined charge (Qg) with a charge threshold value (Qs) and to output a first trigger signal (St1) to the logic unit (10) if the determined charge (Qg) reaches or exceeds the charge threshold value (Qs), - the circuit unit (5) is set up to receive a control signal (S1 , S2) to switch on and off the semiconductor switch (T1 , T2), - the delay element (60) is set up, - to start a timing measurement upon receiving the control signal (S1, S2) to switch on the semiconductor switch (T1, T2), and - to output a second trigger signal (St2) to the logic unit (10) as soon as a predetermined time period (Tdmax) has elapsed after the start of the time measurement, - the logic unit (10) is set up, - to control the gate driver (20) to switch on the semiconductor switch (T1, T2) as soon as the first trigger signal (St1) and / or the second trigger signal (St2) is received, and - to control the gate driver (20) to switch off the semiconductor switch (T1, T2) as soon as the control signal (S1, S2) to switch off is received, and - to output the reset signal (Sr) to the integrator (40) as soon as the control signal (S1, S2) to switch off is received and / or while the semiconductor switch (T1, T2) is in an off state, and - to terminate the output of the reset signal (Sr) to the integrator (40) at the latest upon receipt of the control signal (S1 , S2) to switch on the semiconductor switch (T1 , T2).

2. Circuit unit (5) according to claim 2, wherein the circuit unit (5) is designed as a partially or fully integrated circuit.

3. Circuit unit (5) according to one of the preceding claims, wherein the logic unit (10) is configured to output a feedback signal (Sf1 , Sf2) if, during a current control to switch on the semiconductor switch (T1 , T2), the second trigger signal (St2) is received before the first trigger signal (St1).

4. Circuit unit (5) according to one of the preceding claims, wherein - the charge threshold (Qs) is a predefined threshold, and / or - the circuit unit (5) is set up to determine the charge threshold (Qs) depending on current boundary conditions.

5. Circuit unit (5) according to claim 4, wherein the circuit unit (5) is configured, - to determine a maximum charge (Qmax) by determining a maximum value of the charge (Qg) integrated in the integrator (40) over time and / or by receiving information representing an end time of a switching-on process of the semiconductor switch (T1 , T2) and defining the integrated charge present in the integrator (40) at the end time as the maximum charge (Qmax), - to receive information about a gate charge (Qgs) which represents a charge required to fully recharge a gate-source capacitance (Cgs, Cgs') of the semiconductor switch (T1, T2) during a switch-on operation of the semiconductor switch (T1, T2), and - to subtract the gate charge (Qgs) from the maximum charge (Qmax) and define the result of the subtraction as the charge threshold (Qs).

6. Circuit unit (5) according to one of the preceding claims, wherein the circuit unit (5) is configured to subtract a predefined tolerance value from the charge threshold (Qs) and to define the result of the subtraction as the current charge threshold (Qs).

7. comprising circuit arrangement - a first circuit unit (5) and a second circuit unit (7) according to one of the preceding claims, - a half-bridge circuit consisting of a first semiconductor switch (T1) and a second semiconductor switch (T2), - a control unit (70), - a DC voltage source (80), and - a load (90), wherein - the DC voltage source (80) is set up to apply a DC voltage (Ude) to the half-bridge circuit, - the load (90) has at least an inductive component and is electrically connected to a node (100) between the first semiconductor switch (T1) and the second semiconductor switch (T2), - the first circuit unit (5) is set up to control the first semiconductor switch (T1), - the second circuit unit (7) is set up to control the second semiconductor switch (T2), - the control unit (70) is set up, - to generate a first control signal (S1), which is fed into the first circuit unit (5) as the control signal for switching on and off the first semiconductor switch (T1), and - to generate a second control signal (S2), which is fed into the second circuit unit (7) as the control signal for switching on and off the second semiconductor switch (T2), and - to provide an alternating voltage to the load (90) by means of a suitable determination of the first control signal (S1) and the second control signal (S2) based on the DC voltage (Ude), and - the first control signal (S1) is an inverted signal with respect to the second control signal (S2).

8. Circuit arrangement according to claim 7, wherein the control unit (70) is configured to perform at least part of the switching-on operations of the first semiconductor switch (T1) and / or the second semiconductor switch (T2) as soft switching operations based on the control by the first control signal (S1) and the second control signal (S2).

9. Circuit arrangement according to claim 7 or 8, wherein the control unit (70) is configured to receive the feedback signal (Sf1 , Sf2) and to adapt the control of the semiconductor switches (T1 , T2) of the half-bridge circuit based on the feedback signal (Sf1 , Sf2).

10. Circuit arrangement according to one of claims 7 to 9, wherein the The circuit arrangement is set up, the gate charge (Qgs) which is used for to determine in a calibration mode of the circuit arrangement the complete recharging of a respective gate capacitance (Cgs, Cgs') of the respective semiconductor switches (T1 , T2) is required during a switch-on process of the semiconductor switches (T1 , T2).

11. Circuit arrangement according to one of claims 7 to 10, wherein the circuit arrangement is configured to adapt the time duration (Tdmax) taken into account in the delay element (60) depending on current boundary conditions.

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