Field-effect transistor

Abstract

A gate electrode (107) comprises: a leg part (107a); a first head part (107b); a second head part (107c); a first lateral part (107d); and a second lateral part (107e). The first head part (107b) is continuously formed above the leg part (107a), and is longer in length than the leg part (107a) in the gate length direction. The first lateral part (107d) and the second lateral part (107e) are continuously formed at both ends in the gate length direction of the first head part (107b). The second head part (107c) is continuously formed above at least one of the first lateral part (107d) and the second lateral part (107e), and is longer in length than the leg part (107a) in the gate length direction. In this example, the second head part (107c) is continuously formed above both the first lateral part (107d) and the second lateral part (107e).

Description

field-effect transistor

[0001] The present invention relates to a field effect transistor.

[0002] The terahertz frequency band (0.3 to 3.0 THz) is expected to be used in a wide range of applications, including not only next-generation high-speed wireless communications but also non-destructive testing using terahertz wave imaging, security applications using transmission imaging, material analysis using absorption spectra, and obtaining weather-related information using radiometers mounted on satellites. For this reason, attention is being drawn to electronic devices and integrated circuits that can directly handle the terahertz frequency band. Generally, field-effect transistors using compound semiconductors with high electron mobility are used as electronic devices with excellent high-frequency characteristics.

[0003] A high-frequency field-effect transistor generally has a structure in which a buffer layer, a channel layer, and a barrier layer are stacked on a semiconductor substrate, on which an ohmic cap layer and source and drain electrodes serving as ohmic electrodes are formed, and a gate electrode is formed between the source and drain electrodes.

[0004] Within the barrier layer, a carrier supply layer called a delta-doped layer is formed, which is heavily doped with impurities. Carriers, i.e., electrons, generated by the ionization of these impurities are accumulated in the channel layer, which has a smaller band gap than the barrier layer, forming a two-dimensional electron gas. Because the two-dimensional electron gas in the channel layer is spatially separated from the ionized impurities by the barrier layer, it can travel between the source and drain at high speed without suffering mobility degradation due to impurity scattering.

[0005] In addition, the ohmic cap layer may be doped with impurities in the same manner as the carrier supply layer in order to facilitate carrier injection from the ohmic electrode to the channel layer and carrier conduction from the channel layer to the ohmic electrode, i.e., to reduce the source resistance and the drain resistance.

[0006] In the above structure, applying a voltage to the gate electrode modulates the band structure directly below the gate electrode, thereby controlling the two-dimensional electron gas concentration in the channel layer and the amount of current flowing between the source and drain. Therefore, in a configuration where the source electrode is grounded, by inputting a high-frequency signal to be amplified to the gate electrode, the amplified signal can be output from the drain electrode.

[0007] When handling high-frequency signals such as terahertz waves with such field-effect transistors, the skin effect must be taken into consideration. The skin effect is a phenomenon in which current density concentrates on the surface of a conductor when a high-frequency signal propagates through it. It is known that the resistance increases because the effective cross-sectional area of ​​the conductor through which the high-frequency signal propagates becomes smaller.

[0008] Here, the current density J inside the conductor can be expressed as a function of the distance d from the conductor surface by the following equation:

[0009]

[0010] In equation (1), J0 is the current density on the conductor surface, and d is called the skin depth, which is given by the following equation:

[0011]

[0012] In equation (2), ρ is the electrical resistivity of the conductor, ω is the angular frequency of the signal, and μ is the magnetic permeability of a vacuum (1.26 × 10 -6 H / m), μ r is the relative permeability of the conductor. If the frequency of the signal is f, then ω = 2πf, and therefore, from equations (1) and (2), it can be seen that the higher the frequency of the signal, the more the current density concentrates on the surface of the conductor.

[0013] For example, when gold and nickel are used as measurement pads and gate electrodes of field-effect transistors, the skin depths are estimated to be 144 nm and 24 nm at f = 300 GHz, and 45 nm and 7.5 nm at f = 3.0 THz. The electrical resistivity and magnetic permeability of gold are 2.44 × 10 -8W m and 1, and the electrical resistivity and magnetic permeability of nickel are 6.67 × 10 -8 W·m and 100.

[0014] On the other hand, the maximum oscillation frequency f max , minimum noise factor F min is given by the following formula:

[0015]

[0016] In the above formula, f t is the current gain cutoff frequency, R i , R s , R g are the channel resistance, source resistance, and gate resistance, respectively, and g d,int , g m,int are the drain conductance and transconductance of the device intrinsic region, respectively, and C gs , C gd are the gate-source capacitance and gate-drain capacitance, respectively, and K G is a term mainly related to drain noise, and K r is a term mainly related to gate-induced noise.

[0017] f max is an important parameter for amplifier applications of high-frequency field-effect transistors, and for example, when designing a high-frequency front-end IC, a higher F min is an index related to noise generated by the field-effect transistor itself, and it is desirable that it be as low as possible in order to amplify the received signal without degrading the S / N ratio. In order to satisfy these requirements, the gate resistance R g Reducing this is effective.

[0018] Generally, the skin effect g In order to avoid this increase, a T-shaped gate structure is used as shown in FIG. 1A of Patent Document 1 and FIG. 1 of Patent Document 2. By using a T-shaped gate structure, the surface area of ​​the gate electrode increases, the influence of the skin effect is reduced, and the R g It is possible to further reduce R gTo reduce this, a structure such as that shown in Fig. 1 of Non-Patent Document 1 has been proposed in which the head of the T-shaped gate structure is enlarged.

[0019] Patent No. 6713948 Patent No. 6750455

[0020] T. Takahashi, M. Sato, Y. Nakasha, T. Hirose, and N. Hara, “Noise Figure Improvement in InP-Based HEMTs Using Wide Gate Head and Cavity Structure,” IEEE Electron Device Lett., vol. 33, no. 2, pp. 206-208, 2012.

[0021] However, in a typical T-shaped gate, the width of the head is 300 to 1200 nm and the height is 100 to 400 nm, and as mentioned above, the skin depth in the terahertz wave region is less than 100 nm, so the influence of the skin effect cannot be ignored. g To reduce gs , C gd For example, in Non-Patent Document 1, instead of enlarging the head of the T-type gate, gs , C gd In order to prevent the increase of R, a cavity is formed around the gate. In the frequency bands currently considered for devices, the R due to the increased cross-sectional area is g Although the reduction is still effective, considering future terahertz wave applications, the above-mentioned approach is likely to lose its effectiveness due to the influence of the skin effect.

[0022] In addition, it is difficult to increase the gate cross-sectional area from the viewpoint of device scaling. For example, in a device in which the distance between the source electrode and the drain electrode is reduced to the limit, the head portion that is long in the channel length direction (gate length direction) overlaps with the source electrode, the drain electrode, or both, resulting in a C gs , C gd This leads to an increase in

[0023] The present invention has been made to solve the above problems, and has as its object to prevent an increase in gate resistance due to the skin effect.

[0024] a first head portion formed continuously on the leg portion and having a length in the gate length direction longer than the leg portion; a first side portion and a second side portion formed continuously on each end of the first head portion in the gate length direction; and a second head portion formed continuously on at least one of the first side portion and the second side portion and having a length in the gate length direction longer than the leg portion, wherein the first head portion and the second head portion have cross sections perpendicular to the gate width direction that are horizontally elongated in the gate length direction, and the first side portion and the second side portion have cross sections perpendicular to the gate width direction that are vertically elongated in the thickness direction.

[0025] As described above, according to the present invention, the gate electrode is composed of a leg portion, a first head portion formed continuously on the leg portion, a first side portion and a second side portion formed continuously on each of both ends of the first head portion, and a second head portion formed continuously on at least one of the first side portion and the second side portion, thereby preventing an increase in gate resistance due to the skin effect.

[0026] FIG. 1 is a cross-sectional view showing the configuration of a field-effect transistor according to a first embodiment of the present invention. FIG. 2A is a cross-sectional view showing the state of a field-effect transistor in an intermediate step for explaining a method for manufacturing a field-effect transistor according to a first embodiment of the present invention. FIG. 2B is a cross-sectional view showing the state of a field-effect transistor in an intermediate step for explaining a method for manufacturing a field-effect transistor according to a first embodiment of the present invention. FIG. 2C is a cross-sectional view showing the state of a field-effect transistor in an intermediate step for explaining a method for manufacturing a field-effect transistor according to a first embodiment of the present invention. FIG. 2D is a cross-sectional view showing the state of a field-effect transistor in an intermediate step for explaining a method for manufacturing a field-effect transistor according to a first embodiment of the present invention. FIG. 2E is a cross-sectional view showing the state of a field-effect transistor in an intermediate step for explaining a method for manufacturing a field-effect transistor according to a first embodiment of the present invention. FIG. 2F is a cross-sectional view showing the state of a field-effect transistor in an intermediate step for explaining a method for manufacturing a field-effect transistor according to a first embodiment of the present invention. FIG. 2G is a cross-sectional view showing the state of a field-effect transistor in an intermediate step for explaining a method for manufacturing a field-effect transistor according to a first embodiment of the present invention. FIG. 2H is a cross-sectional view showing the state of a field-effect transistor in an intermediate step for explaining a method for manufacturing a field-effect transistor according to a first embodiment of the present invention. FIG. 2I is a plan view showing the state of a field-effect transistor in an intermediate step for explaining a method for manufacturing a field-effect transistor according to a first embodiment of the present invention. Fig. 2J is a plan view showing a state of a field effect transistor in an intermediate step for explaining a manufacturing method of a field effect transistor according to embodiment 1 of the present invention. Fig. 3A is an explanatory diagram for explaining the effect of reducing gate resistance in the gate electrode structure of the field effect transistor according to embodiment 1. Fig. 3B is an explanatory diagram for explaining the effect of reducing gate resistance in the gate electrode structure of the field effect transistor according to embodiment 1. Fig. 4 is a cross-sectional view showing a gate electrode structure of a field effect transistor according to embodiment 2 of the present invention. Fig. 5A is a cross-sectional view showing a state of a gate electrode structure in an intermediate step for explaining a manufacturing method of the gate electrode structure of a field effect transistor according to embodiment 2 of the present invention.FIG. 5B is a cross-sectional view showing a state of a gate electrode structure in an intermediate step for explaining a method for manufacturing a gate electrode structure of a field effect transistor according to Embodiment 2 of the present invention. FIG. 5C is a cross-sectional view showing a state of a gate electrode structure in an intermediate step for explaining a method for manufacturing a gate electrode structure of a field effect transistor according to Embodiment 2 of the present invention. FIG. 5D is a cross-sectional view showing a state of a gate electrode structure in an intermediate step for explaining a method for manufacturing a gate electrode structure of a field effect transistor according to Embodiment 2 of the present invention. FIG. 5E is a cross-sectional view showing a state of a gate electrode structure in an intermediate step for explaining a method for manufacturing a gate electrode structure of a field effect transistor according to Embodiment 2 of the present invention. FIG. 5F is a cross-sectional view showing a state of a gate electrode structure in an intermediate step for explaining a method for manufacturing a gate electrode structure of a field effect transistor according to Embodiment 2 of the present invention. FIG. 5G is a cross-sectional view showing a state of a gate electrode structure in an intermediate step for explaining a method for manufacturing a gate electrode structure of a field effect transistor according to Embodiment 2 of the present invention. FIG. 5H is a plan view showing a state of a gate electrode structure in an intermediate step for explaining a method for manufacturing a gate electrode structure of a field effect transistor according to Embodiment 2 of the present invention. FIG. 5I is a plan view showing a state of a gate electrode structure in an intermediate step for explaining a method for manufacturing a gate electrode structure of a field effect transistor according to Embodiment 2 of the present invention. FIG. 6 is a cross-sectional view showing a gate electrode structure of a field effect transistor according to Embodiment 3 of the present invention. Fig. 7A is a cross-sectional view showing the state of the gate electrode structure in an intermediate step for explaining the method for manufacturing the gate electrode structure of the field effect transistor according to the third embodiment of the present invention. Fig. 7B is a cross-sectional view showing the state of the gate electrode structure in an intermediate step for explaining the method for manufacturing the gate electrode structure of the field effect transistor according to the third embodiment of the present invention. Fig. 7C is a cross-sectional view showing the state of the gate electrode structure in an intermediate step for explaining the method for manufacturing the gate electrode structure of the field effect transistor according to the third embodiment of the present invention. Fig. 8 is a cross-sectional view showing the gate electrode structure of the field effect transistor according to the fourth embodiment of the present invention. Fig. 9A is a cross-sectional view showing the state of the gate electrode structure in an intermediate step for explaining the method for manufacturing the gate electrode structure of the field effect transistor according to the fourth embodiment of the present invention.FIG. 9B is a perspective view showing a state of a gate electrode structure in an intermediate step for explaining a method for manufacturing a gate electrode structure of a field effect transistor according to Embodiment 4 of the present invention. FIG. 9C is a cross-sectional view showing a state of a gate electrode structure in an intermediate step for explaining a method for manufacturing a gate electrode structure of a field effect transistor according to Embodiment 4 of the present invention. FIG. 9D is a cross-sectional view showing a state of a gate electrode structure in an intermediate step for explaining a method for manufacturing a gate electrode structure of a field effect transistor according to Embodiment 4 of the present invention. FIG. 9E is a cross-sectional view showing a state of a gate electrode structure in an intermediate step for explaining a method for manufacturing a gate electrode structure of a field effect transistor according to Embodiment 4 of the present invention. FIG. 9F is a cross-sectional view showing a state of a gate electrode structure in an intermediate step for explaining a method for manufacturing a gate electrode structure of a field effect transistor according to Embodiment 4 of the present invention. FIG. 9G is a cross-sectional view showing a state of a gate electrode structure in an intermediate step for explaining a method for manufacturing a gate electrode structure of a field effect transistor according to Embodiment 4 of the present invention. FIG. 9H is a cross-sectional view showing a state of a gate electrode structure in an intermediate step for explaining a method for manufacturing a gate electrode structure of a field effect transistor according to Embodiment 4 of the present invention. FIG. 9I is a cross-sectional view showing a state of a gate electrode structure in an intermediate step for explaining a method for manufacturing a gate electrode structure of a field effect transistor according to Embodiment 4 of the present invention. FIG. 9J is a cross-sectional view showing a state of a gate electrode structure in an intermediate step for explaining a method for manufacturing a gate electrode structure of a field effect transistor according to Embodiment 4 of the present invention. Fig. 10 is a cross-sectional view showing a gate electrode structure of a field effect transistor according to embodiment 5 of the present invention. Fig. 11 is a cross-sectional view showing a gate electrode structure of another field effect transistor according to embodiment 5 of the present invention. Fig. 12A is a cross-sectional view showing a state of the gate electrode structure in an intermediate step for explaining a manufacturing method of the gate electrode structure of the field effect transistor according to embodiment 5 of the present invention. Fig. 12B is a perspective view showing a state of the gate electrode structure in an intermediate step for explaining a manufacturing method of the gate electrode structure of the field effect transistor according to embodiment 5 of the present invention. Fig. 12C is a cross-sectional view showing a state of the gate electrode structure in an intermediate step for explaining a manufacturing method of the gate electrode structure of the field effect transistor according to embodiment 5 of the present invention.13 and 14 are cross-sectional views showing the gate electrode structure of another field effect transistor according to the fifth embodiment of the present invention.

[0027] Hereinafter, a field effect transistor according to an embodiment of the present invention will be described.

[0028] First Embodiment First, a field-effect transistor according to a first embodiment of the present invention will be described with reference to Fig. 1. Fig. 1 shows a cross section of a plane perpendicular to the gate width direction (parallel to the gate length direction) of the configuration of the element region of the field-effect transistor. This field-effect transistor includes a buffer layer 102, a channel layer 103, a barrier layer 104, and a δ-doped carrier supply layer 105 formed in the barrier layer 104, all of which are formed on a semiconductor substrate 101.

[0029] The field-effect transistor also includes a gate electrode 107 formed on the barrier layer 104, and a source electrode 108 and a drain electrode 109 formed on the barrier layer 104 with the gate electrode 107 sandwiched therebetween. The source electrode 108 and the drain electrode 109 are formed on a cap layer 106 formed between the barrier layer 104 and the source electrode 108 and the drain electrode 109.

[0030] The semiconductor substrate 101 may be made of, for example, semi-insulating InP. The buffer layer 102 may be made of, for example, InAlAs and have a thickness of 100 to 300 nm. The channel layer 103 may be made of, for example, InGaAs and have a thickness of 5 to 20 nm. The barrier layer 104 may be made of, for example, InAlAs and have a thickness of 5 to 20 nm. The carrier supply layer 105 is formed on the barrier layer 104 by, for example, well-known δ-doping. 1×10 Si is used as an impurity. 11 cm -2 ~1 x 10 13 cm -2The barrier layer 104 can be doped to a certain extent. In this example, a stopper layer 110 is provided on the barrier layer 104. The stopper layer 110 can be made of, for example, InP and have a thickness of 2 to 5 nm. Each of these layers can be formed by crystal growth using, for example, metalorganic chemical vapor deposition or molecular beam epitaxy.

[0031] In this example, the recess region 106a is formed by etching the cap layer 106 through an opening in the insulating layer 111 formed between the source electrode 108 and the drain electrode 109 on the cap layer 106. In forming the recess region 106a, the stopper layer 110 can be used as an etching stop layer.

[0032] Here, the gate electrode 107 of the field effect transistor according to the first embodiment includes a leg portion 107a, a first head portion 107b, a second head portion 107c, a first side portion 107d, and a second side portion 107e.

[0033] The first head 107b is formed continuously on the leg 107a and has a longer length in the gate length direction than the leg 107a. The first side 107d and the second side 107e are formed continuously on both ends of the first head 107b in the gate length direction. The second head 107c is formed continuously on at least one of the first side 107d and the second side 107e and has a longer length in the gate length direction than the leg 107a. In this example, the second head 107c is formed continuously on both the first side 107d and the second side 107e.

[0034] Furthermore, the cross-sectional shapes of the first head 107b and the second head 107c in a plane perpendicular to the gate width direction are horizontally elongated (rectangular) in the gate length direction. The cross-sectional shapes of the first side 107d and the second side 107e in a plane perpendicular to the gate width direction are vertically elongated (rectangular) in the thickness direction. In the first embodiment, the cross-sectional shape of the portion of the gate electrode 107 composed of the first head 107b, the second head 107c, the first side 107d, and the second side 107e in a plane perpendicular to the gate width direction is a hollow quadrangle (a rectangular tube extending in the gate width direction). Furthermore, the gate electrode 107 extends beyond the gate width in the gate width direction.

[0035] In this example, an insulating layer 112 is formed within the hollow rectangular shape of the gate electrode 107, and insulating layers 113 are formed on both sides of the gate electrode 107 in the gate length direction. It is generally known that the speed of an electrical signal propagating through a conductor on a dielectric is slower than the speed of an electromagnetic wave propagating through a vacuum (the speed of light). Therefore, in order to propagate terahertz waves at a higher speed, the insulating layer within and around the hollow rectangular shape of the gate electrode 107 can be partially or entirely removed.

[0036] According to the first embodiment, compared to the conventional configuration, C gs , C gd Therefore, the surface area of ​​the gate electrode 107 can be increased without increasing the thickness, and the gate resistance in the terahertz wave band can be reduced. As a result, an increase in the gate resistance due to the skin effect can be prevented.

[0037] Next, a method for manufacturing a field effect transistor according to the first embodiment of the present invention will be described with reference to Figures 2A to 2H, which show cross sections parallel to the gate length direction.

[0038] First, as shown in FIG. 2A, a buffer layer 102, a channel layer 103, a barrier layer 104, a carrier supply layer 105, a stopper layer 110, and a cap layer 106 are formed on a semiconductor substrate 101 (first step).

[0039] For example, a buffer layer 102, a channel layer 103, a barrier layer 104, a stopper layer 110, and a cap layer 106 are sequentially stacked on a semiconductor substrate 101 by crystal growth using metal organic chemical vapor deposition, molecular beam epitaxy, or the like. A carrier supply layer 105 is formed in the barrier layer 104 by δ-doping. Furthermore, for element isolation, element regions that are rectangular in plan view parallel to the plane of the semiconductor substrate 101 are formed by patterning using wet etching or dry etching.

[0040] Next, as shown in FIG. 2B , a source electrode 108 and a drain electrode 109 are formed on the cap layer 106, spaced apart from each other (step 2). The source electrode 108 and the drain electrode 109 are formed on either side of the region where the gate electrode 107 will be formed. For example, a lift-off mask with openings corresponding to the electrode formation regions is formed using a known photolithography technique. Next, a metal layer such as Ni, Ti, Pt, Au, or Mo, or a composite deposition layer of these metals, is formed by electrolytic plating, electroless plating, vacuum deposition, sputtering, or the like. The lift-off mask is then removed (lifted off) to form the source electrode 108 and the drain electrode 109. The source electrode 108 and the drain electrode 109 form ohmic contacts with the cap layer 106.

[0041] 2C , an insulating layer 111 having a penetrating gate opening 111a extending in the gate width direction is formed on the cap layer 106. For example, an insulating material is deposited by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), sputtering, or the like to form the insulating layer 111. The insulating layer 111 can typically be made of SiO, SiN, or a composite deposited layer thereof.

[0042] Next, a resist pattern having an opening with a target gate length in the region where the gate electrode is to be formed is formed by a typical lithography process, and the insulating layer 111 is etched using this resist pattern as a mask to form the gate opening 111a. The insulating layer 111 can be etched by dry etching using CF, C2F6, SF6, or the like. Alternatively, the insulating layer 111 can be etched by wet etching using HF.

[0043] The insulating layer 111 can be etched by atomic layer etching (ALE). After the gate opening 111a is formed in this manner, the resist pattern is removed using an organic solvent or the like. If effective recess etching is desired in the subsequent recess etching process, such as by utilizing the battery effect, part or all of the insulating layer 111 on the source electrode 108 and the drain electrode 109 can be removed.

[0044] Next, using the insulating layer 111 as a mask, the cap layer 106 is etched through the gate opening 111a to form a recess region 106a. For this etching, if the cap layer 106 is made of InGaAs, InAlAs, or a composite layer of these, a citric acid-based etching solution is generally used. The stopper layer 111 made of InP is hardly etched by the etching solution described above, and serves as an etching stopper layer (stopper layer), preventing the barrier layer 104 from being etched. The length of the recess region 106a in the gate length direction is called the recess length. A typical recess length is 50 to 500 nm.

[0045] Next, as shown in FIG. 2D , the leg portion 107 a and the first head portion 107 b are formed (step 3). For example, a mask pattern having an opening in the region where the first head portion 107 b is to be formed is used, and a gate electrode material is deposited by, for example, vacuum deposition without removing the mask pattern. The mask pattern is then removed (lift-off) to form the leg portion 107 a and the first head portion 107 b. The first head portion 107 b is formed thinner than the head portion in a typical T-shaped gate structure.

[0046] 2E, an insulating film 201 is formed on the source electrode 108, the drain electrode 109, and the insulating layer 111 to cover the first head portion 107b. Next, as shown in FIG. 2F, through-holes 201a and 201b are formed in the insulating film 201 so as to reach both ends of the first head portion 107b in the gate length direction.

[0047] Next, as shown in Fig. 2G, a lift-off mask 203 is formed, which is open above the first head portion 107b. Next, a gate electrode material is deposited on the lift-off mask 203 by, for example, vacuum evaporation. Thereafter, the lift-off mask 203 is removed (lifted off), thereby obtaining the gate electrode 107 having the first side portion 107d, the second side portion 107e, and the second head portion 107c, as shown in Fig. 2H.

[0048] The insulating layer (film) used in the above-mentioned gate electrode formation process is deposited by CVD, PVD, ALD, sputtering, etc., and is typically made of SiO, SiN, or a composite deposited layer (film) of these. A BCB film formed by spin coating and then heat-curing can be used as the insulating film.

[0049] In the case of an insulating film such as SiO or SiN, etching in the gate electrode formation process can be performed by dry etching using CF, C2F6, SF, or the like, or by wet etching using HF, or by ALE. The metal layer used in the gate electrode can be formed by electrolytic plating, electroless plating, vacuum deposition, sputtering, or the like, and the metal film can be made of a single metal such as Ni, Ti, Pt, Au, or Mo, or a composite of these metals deposited thereon.

[0050] 2I, as in a standard field effect transistor, a source electrode 108 and a drain electrode 109 are formed in an element region 131 (device formation region), and a gate electrode 107 is formed between the source electrode 108 and the drain electrode 109. Both ends of the gate electrode 107 extend to the outside of the element region 131, and typically, one end serves as a feed section 120 that inputs a signal to the transistor.

[0051] It is generally known that the speed of an electrical signal propagating through a conductor on a dielectric is slower than the speed of an electromagnetic wave propagating through a vacuum (the speed of light). Therefore, in order to propagate terahertz waves at a higher speed, the insulating layer 112 inside and around the hollow rectangular shape of the gate electrode 107 can be removed.

[0052] The insulating layer inside the hollow rectangular portion (rectangular tube) of the gate electrode 107, which is composed of the first head 107b, the second head 107c, the first side 107d, and the second side 107e, can be removed, for example, as follows. Consider the case where the insulating layer is made of SiO. First, openings 201c and 201d are formed by etching both ends of the rectangular tube portion of the gate electrode 107 using a mask pattern formed by known photolithography. Next, as shown in FIG. 2I, metal patterns 121 are formed to cover the openings 201c and 201d.

[0053] Next, as shown in FIG. 2J , a portion of the rectangular tube of the gate electrode 107 is removed to form an opening 122, exposing the insulating layer 201 inside the rectangular tube of the gate electrode 107. Selective removal of the metal film can be achieved, for example, by using a mask pattern formed by a lithography process and selectively etching the metal by ion milling using Ar or O to form the opening 122. An etchant such as HF is poured through the formed opening 122 to remove the insulating layer 201 inside the rectangular tube. The number of openings 122 can be one or more. As shown in FIG. 2I , if both ends of the rectangular tube portion extending in the gate width direction, consisting of the first head 107b, second head 107c, first side 107d, and second side 107e of the gate electrode 107, are not blocked, the poured etchant will leak out from both ends of the gate electrode 107 and etch the insulating layer in other regions. If this etching does not pose any problems in terms of the process, the process described with reference to FIG. 2I can be omitted.

[0054] Next, the effect of reducing the gate resistance in the gate electrode structure of the field effect transistor according to the first embodiment will be described.

[0055] The cross-sectional shape of the head of a typical T-shaped gate structure, taken along a plane parallel to the gate length direction, is described below as being 500 nm wide and 500 nm high, as shown in Figure 3A. It is also assumed that current flows uniformly from the outer surface of the head to a skin depth d, and does not flow in other regions. In contrast, the cross-sectional shape of each head of gate electrode 107 in the field-effect transistor according to embodiment 1 is formed as shown in Figure 3B.

[0056] For example, when the skin depth d is 20 nm, if L1 = L2 = L3 = L4 = 100 nm, the cross-sectional area where the current flows is 38,400 nm in the conventional structure. 2 In contrast, in the structure of the first embodiment, it is 38,400 nm 2 +25,600 nm 2 = 64,000 nm 2 The cross-sectional area is 1.67 times larger. Since resistance is generally proportional to the reciprocal of the conductor cross-sectional area, the structure of Figure 3B can reduce resistance by approximately 40%. More generally, when the skin depth is d, by designing at least one of L1, L2, L3, and L4 to be larger than d, the resistance when the skin effect is taken into account can be reduced compared to the structure of Figure 3A.

[0057] Second Embodiment Next, a field-effect transistor according to a second embodiment of the present invention will be described with reference to FIG. 4. In the field-effect transistor according to the second embodiment, a gate electrode 107′ includes a leg portion 107a, a first head portion 107b, a second head portion 107c, a first side portion 107d, and a second side portion 107e, and further includes a third head portion 107f, a fourth head portion 107g, a third side portion 107h, and a fourth side portion 107i. The other structures are the same as those of the first embodiment, and therefore description thereof will be omitted.

[0058] The third head portion 107f is disposed between the first side portion 107d and the second side portion 107e in the gate length direction. The third head portion 107f is disposed between the first head portion 107b and the second head portion 107c in the thickness direction. The length of the third head portion 107f in the gate length direction is longer than that of the leg portion 107a.

[0059] The third side portion 107h and the fourth side portion 107i are formed continuously with both ends of the third head portion 107f in the gate length direction. The fourth head portion 107g is disposed between the first side portion 107d and the second side portion 107e in the gate length direction. The fourth head portion 107g is disposed between the first head portion 107b and the second head portion 107c in the thickness direction. The fourth head portion 107g is formed continuously with at least one of the third side portion and the fourth side portion, and its length in the gate length direction is longer than that of the leg portion.

[0060] The third head portion 107f and the fourth head portion 107g have a cross section perpendicular to the gate width direction that is rectangular and elongated in the gate length direction, and the third side portion 107h and the fourth side portion 107i have a cross section perpendicular to the gate width direction that is rectangular and elongated in the thickness direction.

[0061] In the second embodiment, a hollow rectangular shape (a rectangular tube extending in the gate width direction) consisting of a third head 107f, a fourth head 107g, a third side 107h, and a fourth side 107i is provided inside a hollow rectangular shape (a rectangular tube extending in the gate width direction) consisting of a first head 107b, a second head 107c, a first side 107d, and a second side 107e. In the following description of the second embodiment, the hollow rectangular shape consisting of the first head 107b, the second head 107c, the first side 107d, and the second side 107e will be referred to as the first rectangular tube, and the hollow rectangular shape consisting of the third head 107f, the fourth head 107g, the third side 107h, and the fourth side 107i will be referred to as the second rectangular tube.

[0062] The first and second rectangular tubes are electrically connected by a metal pattern or the like at a location extending outside the element region of the gate electrode 107. An insulating layer can be formed inside the second rectangular tube and between the first and second rectangular tubes. The side surface of the first rectangular tube in the gate width direction can be embedded with the insulating layer. These insulating layers can also be removed (not formed).

[0063] According to the second embodiment, the surface area can be further increased compared to the first embodiment, and therefore the gate resistance can be further reduced for electrical signals in the terahertz wave band where the skin effect is prominent.

[0064] Next, the formation of the gate electrode structure of the field effect transistor according to the second embodiment will be described with reference to FIGS. 5A to 5H.

[0065] First, leg portion 107a and first head portion 107b are formed (FIG. 5A) in the same manner as in the first embodiment. Next, as shown in FIG. 5B, insulating layer 204 is formed on insulating layer 111 so as to cover first head portion 107b.

[0066] Next, as shown in FIG. 5C , a third head portion 107f is formed on the insulating layer 204. For example, a lift-off mask having an opening where the third head portion 107f is to be formed is formed. Next, a gate electrode material is deposited on top of the lift-off mask by, for example, vacuum deposition. Thereafter, the lift-off mask is removed (lift-off), thereby forming the third head portion 107f. Thereafter, an insulating layer 205 is formed on the insulating layer 204, covering the third head portion 107f.

[0067] 5D, openings 205a and 205b reaching both ends of the third head portion 107f in the gate length direction are formed in the insulating layer 205. The openings 205a and 205b can be formed by selectively etching the insulating layer 205 using a mask pattern formed by known photolithography technology.

[0068] Next, as described above, a lift-off mask is formed, the openings 205a and 205b are filled, and metal is deposited so that a metal layer is formed on the insulating layer 205 above the third head 107f, followed by lift-off to form the fourth head 107g, the third side 107h, and the fourth side 107i, as shown in Fig. 5E. Next, an insulating layer 206 is formed on the insulating layer 205 to cover the fourth head 107g.

[0069] 5F , openings 206 a and 206 b that reach both ends of first head portion 107 b in the gate length direction are formed in insulating layer 206, insulating layer 205, and insulating layer 204. Openings 206 a and 206 b can be formed by selectively etching insulating layer 206, insulating layer 205, and insulating layer 204 using a mask pattern formed by known photolithography technology.

[0070] Next, as described above, a lift-off mask is formed, the openings 206a and 206b are filled, and metal is deposited so that a metal layer is formed on the insulating layer 206 above the first head 107b, followed by lift-off, thereby forming the first side 107d, the second side 107e, and the second head 107c, as shown in FIG. 5G.

[0071] Next, the feed section is formed. First, as shown in Fig. 5H, an opening 201e is formed in the insulating layer by etching using a mask pattern formed by known photolithography. Next, as shown in Fig. 5I, metal is deposited in the formed opening 201e to form a metal pattern 121, which electrically connects the first and second rectangular tubes at the feed section.

[0072] Third Embodiment Next, a field-effect transistor according to a third embodiment of the present invention will be described with reference to FIG. 6. In the field-effect transistor according to the third embodiment, a gate electrode 117 includes a leg portion 107a, a first head portion 107b, a second head portion 107c, a first side portion 107d, and a second side portion 107e, and further includes a third head portion 117f, a fourth head portion 117g, a third side portion 117h, a fourth side portion 117i, a fifth side portion 117j, and a sixth side portion 117k. The other structures are the same as those of the first embodiment, and therefore description thereof will be omitted.

[0073] The third head portion 117f is disposed between the first side portion 107d and the second side portion 107e in the gate length direction, and between the first head portion 107b and the second head portion 107c in the thickness direction. The length of the third head portion 117f in the gate length direction is longer than that of the leg portion 107a.

[0074] The third side portion 117h and the fourth side portion 117i are formed continuously with both ends of the third head portion 107f in the gate length direction.

[0075] The fourth head portion 117g is disposed between the third side portion 107h and the fourth side portion 107i in the gate length direction, and between the third head portion 117f and the second head portion 107c in the thickness direction. The length of the fourth head portion 117g in the gate length direction is longer than that of the leg portion 107a.

[0076] The fifth side portion 117j and the sixth side portion 117k are formed continuously with both ends of the fourth head portion 117g in the gate length direction and connected to the second head portion 107c.

[0077] The third head 117f and the fourth head 117g have a cross section perpendicular to the gate width direction that is rectangular in the gate length direction, and the third side 117h, the fourth side 117i, the fifth side, and the sixth side have a cross section perpendicular to the gate width direction that is rectangular in the thickness direction.

[0078] In the third embodiment, a hollow rectangular shape (a rectangular tube extending in the gate width direction) consisting of the first head 107b, the second head 107c, the first side 107d, and the second side 107e is provided inside the hollow rectangular shape (a rectangular tube extending in the gate width direction) consisting of the third head 117f, a portion of the second head 107c, the third side 117h, and the fourth side 117i. Furthermore, a hollow rectangular shape (a rectangular tube extending in the gate width direction) consisting of the fourth head 117g, a portion of the second head 107c, the fifth side 117j, and the sixth side 117k is provided inside the hollow rectangular shape (a rectangular tube extending in the gate width direction) consisting of the third head 117f, a portion of the second head 107c, the third side 117h, and the fourth side 117i. Each rectangular tube shares the second head 107c.

[0079] In the following description of embodiment 3, the hollow rectangular shape formed by the first head 107b, the second head 107c, the first side 107d, and the second side 107e will be referred to as the first rectangular tube, the hollow rectangular shape formed by the third head 117f, a portion of the second head 107c, the third side 117h, and the fourth side 117i will be referred to as the second rectangular tube, and the hollow rectangular shape formed by the fourth head 117g, a portion of the second head 107c, the fifth side 117j, and the sixth side 117k will be referred to as the third rectangular tube.

[0080] The first, second, and third rectangular tubes are electrically connected by a metal pattern or the like at locations extending outside the element region of the gate electrode 107. Furthermore, insulating layers can be formed inside the third rectangular tube, between the second and third rectangular tubes, and between the first and second rectangular tubes. Furthermore, the side surface of the first rectangular tube in the gate width direction can be embedded with an insulating layer. Furthermore, these insulating layers can be removed (not formed).

[0081] According to the third embodiment, the surface area can be further increased compared to the first embodiment, and therefore the gate resistance can be further reduced for electrical signals in the terahertz wave band where the skin effect is prominent.

[0082] Next, the formation of the gate electrode structure of the field effect transistor according to the third embodiment will be described with reference to FIGS. 7A to 7C.

[0083] First, as in the first embodiment described above, leg portion 107a and first head portion 107b are formed, and then insulating layer 204 is formed on insulating layer 111 to cover first head portion 107b, and third head portion 117f is formed on insulating layer 204. Furthermore, insulating layer 205 is formed to cover third head portion 117f, and fourth head portion 117g is formed on insulating layer 205. Furthermore, insulating layer 206 is formed to cover fourth head portion 117g ( FIG. 7A ).

[0084] 7B , openings 206a and 206f reaching both ends of first head portion 107b in the gate length direction are formed in insulating layer 206, insulating layer 205, and insulating layer 204. Openings 206b and 206e reaching both ends of third head portion 117f in the gate length direction are formed in insulating layer 206 and insulating layer 205. Openings 206c and 206d reaching both ends of fourth head portion 117g in the gate length direction are formed in insulating layer 206. Each opening can be formed by selective etching of the insulating layer using a mask pattern formed by known photolithography techniques.

[0085] Next, as described above, a lift-off mask is formed, and openings 206a, 206b, 206c, 206d, 206e, and 206f are filled. Metal is then deposited so that a metal layer is formed on insulating layer 206 above first head 107b, and patterned by lift-off, thereby forming first side 107d, second side 107e, third side 117h, fourth side 117i, fifth side 117j, sixth side 117k, and second head 107c, as shown in FIG. 7C.

[0086] According to the third embodiment, the process for forming each rectangular tube can be simplified compared to the second embodiment. Furthermore, the first rectangular tube, the second rectangular tube, and the third rectangular tube share the two heads 107c and are electrically connected to each other, so there is no need to form a metal pattern for electrically connecting the first rectangular tube, the second rectangular tube, and the third rectangular tube at the end of the gate electrode 107 in the gate width direction, which also simplifies the process.

[0087] [Fourth Embodiment] Next, a field-effect transistor according to a fourth embodiment of the present invention will be described with reference to Figure 8. In the field-effect transistor according to the fourth embodiment, a gate electrode 127 includes a leg portion 107a, a first head portion 107b, a second head portion 127c, a first side portion 107d, and a second side portion 107e, and further includes a third head portion 127f, a fourth head portion 127g, a fifth head portion 127k, a third side portion 127h, a fourth side portion 127i, and a fifth side portion 127j. The other structure is the same as that of the first embodiment described above, and therefore description thereof will be omitted.

[0088] The first head 107b is formed continuously on the leg 107a and has a longer length in the gate length direction than the leg 107a. The first side 107d and the second side 107e are formed continuously on both ends of the first head 107b in the gate length direction. The second head 127c is formed continuously on at least one of the first side 107d and the second side 107e and has a longer length in the gate length direction than the leg 107a. In this example, one end of the second head 127c is formed continuously on the second side 107e, and the other end of the second head 127c is not connected to the first side 107d but is connected to the upper end of the third side 127h, as described below.

[0089] The third head portion 127f is disposed between the first side portion 107d and the second side portion 107e in the gate length direction and between the first head portion 107b and the second head portion 107c in the thickness direction. The third head portion 127f has a length in the gate length direction that is longer than that of the leg portion 107a. The third side portion 127h and the fourth side portion 127i are formed so that their lower ends on the first head portion 107b side are continuous with both ends of the third head portion 127f in the gate length direction. The upper end of the third side portion 127h is connected to the other end of the second head portion 127c.

[0090] The fourth head portion 127g is disposed between the third side portion 127h and the fourth side portion 127i in the gate length direction, and between the third head portion 127f and the second head portion 127c in the thickness direction. The length of the fourth head portion 127g in the gate length direction is longer than that of the leg portion 107a. One end of the fourth head portion 127g is connected to the upper end of the fourth side portion 127i.

[0091] The fifth head 127k is arranged between the third side portion 127h and the fourth side portion 127i in the gate length direction, and between the third head 107f and the fourth head 127g in the thickness direction, and its length in the gate length direction is longer than that of the leg portion 107a.

[0092] The fifth side portion 127j is disposed between the third side portion 127h and the fourth side portion 127i in the gate length direction and is formed continuously with the fourth head portion 127g and the fifth head portion 127k. The upper end of the fifth side portion 127j is connected to the other end of the fourth head portion 127g. One end of the fifth head portion 127k is connected to the lower end of the fifth side portion 127j. The other end of the fifth head portion 127k is an open end.

[0093] The cross-sectional shape of each head portion, taken along a plane perpendicular to the gate width direction, is horizontally elongated (rectangular) in the gate length direction, and the cross-sectional shape of each side portion, taken along a plane perpendicular to the gate width direction, is vertically elongated (rectangular) in the thickness direction.

[0094] In the fourth embodiment, the first head portion 107b, the second head portion 127c, the first side portion 107d, the second side portion 107e, the third head portion 127f, the fourth head portion 127g, the fifth head portion 127k, the third side portion 127h, the fourth side portion 127i, and the fifth side portion 127j form a square spiral shape in the cross section of the plane perpendicular to the gate width direction.

[0095] Generally, when forming an amplifier circuit using high-frequency transistors, the input impedance of the transistor is important information in designing a matching circuit, etc. According to the above-described fourth embodiment, by adjusting the dimensions of first head 107b, second head 127c, first side portion 107d, second side portion 107e, third head 127f, fourth head 127g, fifth head 127k, third side portion 127h, fourth side portion 127i, and fifth side portion 127j in a plane perpendicular to the gate width direction and the spacing between each portion, it is possible to adjust the inductance component of gate electrode 127 and adjust the input impedance to a desired value.

[0096] According to the fourth embodiment, the surface area of ​​the gate electrode 107 can be further increased, which not only reduces the gate resistance in the terahertz wave band but also allows the input impedance to be controlled by intentionally increasing the parasitic inductance.

[0097] Next, the formation of the gate electrode structure of the field effect transistor according to the fourth embodiment will be described with reference to FIGS. 9A to 9J.

[0098] First, as in the first embodiment, leg portion 107a and first head portion 107b are formed. Then, insulating layer 204 is formed on insulating layer 111 to cover first head portion 107b, and third head portion 127f is formed on insulating layer 204. Furthermore, insulating layer 205 is formed to cover third head portion 127f, and fifth head portion 127k is formed on insulating layer 205. Furthermore, insulating layer 206 is formed to cover fifth head portion 127k (FIG. 9A). As shown in FIG. 9B, at one end of gate electrode 127 extending to the outside of the element region, metal pattern 123 of the feed portion is connected to fifth head portion 127k.

[0099] 9C , openings 206a and 206e reaching both ends of first head portion 107b in the gate length direction are formed in insulating layer 206, insulating layer 205, and insulating layer 204. Openings 206b and 206d reaching both ends of third head portion 127f in the gate length direction are formed in insulating layer 206 and insulating layer 205. Opening 206c reaching one end of fifth head portion 127k in the gate length direction is formed in insulating layer 206. Each opening can be formed by selective etching of the insulating layer using a mask pattern formed by known photolithography techniques.

[0100] Next, as described above, a lift-off mask is formed, openings 206a, 206b, 206c, 206d, and 206e are filled, and metal is deposited so that a metal layer is formed on insulating layer 206 above first head 107b, followed by lift-off, thereby forming metal layer 221 for forming first side portion 127d, second side portion 107e, third side portion 127h, fourth side portion 127i, fifth side portion 127j, and fourth head 127g, as shown in FIG. 9D.

[0101] Next, by selectively removing the metal layer 221 except for the portions that will become the fourth head portion 127g, the first side portion 127d, the third side portion 127h, and the second side portion 107e, the fourth head portion 127g that connects to the fifth side portion 127j and the fourth side portion 127i is formed on the insulating layer 206, as shown in FIG. 9E.

[0102] Next, insulating layer 207 is formed on insulating layer 206 so as to cover fourth head 127g, the upper end of first side portion 127d, the upper end of third side portion 127h, and the upper end of second side portion 107e, and as shown in Fig. 9F, openings 207a, 207b, and 207c are formed in insulating layer 207. The upper end of first side portion 127d is exposed in opening 207a, the upper end of third side portion 127h is exposed in opening 207b, and the upper end of second side portion 107e is exposed in opening 207c.

[0103] Next, as described above, a lift-off mask is formed, openings 207a, 207b, and 207c are filled, and metal is deposited so that a metal layer is formed on insulating layer 207 above first head portion 107b, followed by lift-off to form metal layer 222 for forming second head portion 127c, as shown in Fig. 9G. Thereafter, a portion of metal layer 222 is selectively removed to form second head portion 127c on insulating layer 207, as shown in Fig. 9H.

[0104] 9E , insulating layer 207 can be formed on insulating layer 206 so as to cover fourth head 127g, the upper end of first side portion 127d, the upper end of third side portion 127h, and the upper end of second side portion 107e, and openings 207a and 207b can be formed in insulating layer 207 as shown in Fig. 9I . In this case, the upper end of third side portion 127h is exposed in opening 207a, and the upper end of second side portion 107e is exposed in opening 207b.

[0105] Next, a lift-off mask is formed, openings 207a and 207b are filled, and metal is deposited so that a metal layer is formed on insulating layer 207 above first head portion 107b, followed by lift-off, thereby forming second head portion 127c as shown in Fig. 9J. According to the process described using Figs. 9I and 9J, the number of steps can be reduced compared to the process described using Figs. 9F to 9H.

[0106] Fifth Embodiment Next, a field-effect transistor according to a fifth embodiment of the present invention will be described with reference to Figures 10 and 11. As shown in Figure 10, in the field-effect transistor according to the fifth embodiment, a gate electrode 137 includes a leg portion 107a, a first head portion 107b, a second head portion 127c, a first side portion 107d, and a second side portion 107e, and further includes a third head portion 137f, a fourth head portion 137g, and a connecting portion 137h. The other structures are the same as those of the first embodiment, and therefore description thereof will be omitted.

[0107] The third head 137f is arranged between the first side portion 107d and the second side portion 107e in the gate length direction, and between the first head 107b and the second head 127c in the thickness direction, and its length in the gate length direction is longer than that of the leg portion 107a.

[0108] The fourth head 137g is arranged between the first side portion 107d and the second side portion 107e in the gate length direction, and between the third head 137f and the second head 127c in the thickness direction, and its length in the gate length direction is longer than that of the leg portion 107a.

[0109] The connection portion 137h is disposed between the first side portion 107d and the second side portion 107e in the gate length direction, and connects the first head portion 107b, the second head portion 127c, the third head portion 137f, and the fourth head portion 137g. The connection portion 137h is disposed so as to intersect with the second head portion 127c and the third head portion 137f at their centers.

[0110] The third head 137f and the fourth head 137g have cross-sectional shapes that are horizontally elongated in the gate length direction (rectangle) in the gate width direction, and the connecting portion 137h has a cross-sectional shape that is vertically elongated in the thickness direction (rectangle) in the gate width direction. The cross-sectional shape of the plane perpendicular to the gate width direction, consisting of the leg portion 107a, the first head 107b, the second head 127c, the first side portion 107d, the second side portion 107e, the third head 137f, the fourth head 137g, and the connecting portion 137h, has six hollow rectangular shapes (rectangular tubes extending in the gate width direction).

[0111] Alternatively, the gate electrode 147 may have the configuration shown in Fig. 11. The gate electrode 147 shown in Fig. 11 includes a leg portion 107a, a first head portion 107b, a second head portion 107c, a first side portion 107d, and a second side portion 107e, and further includes a third head portion 147b, a fourth head portion 147c, a third side portion 147d, a fourth side portion 147e, a first connecting portion 147g, and a second connecting portion 147h.

[0112] The third head 147b is disposed above the second head 107c and has a length in the gate length direction that is longer than the leg 107a. The third side 147d and the fourth side 147e are formed contiguous with both ends of the third head 147b in the gate length direction. The fourth head 147c is formed contiguous with the third side 147d and the fourth side 147e and has a length in the gate length direction that is longer than the leg 107a. The first connection 147g and the second connection 147h are formed between the second head 107c and the third head 147b and connect the second head 107c and the third head 147b.

[0113] The first head portion 107b, the second head portion 107c, the third head portion 147b, and the fourth head portion 147c have a cross-sectional shape perpendicular to the gate width direction that is elongated horizontally (rectangle) in the gate length direction, while the first side portion 107d, the second side portion 107e, the third side portion 147d, the fourth side portion 147e, the first connecting portion 147g, and the second connecting portion 147h have a cross-sectional shape perpendicular to the gate width direction that is elongated vertically (rectangle) in the thickness direction. The cross-sectional shape of a plane perpendicular to the gate width direction is formed by the portion consisting of first head 107b, second head 107c, first side 107d, second side 107e, third head 147b, fourth head 147c, third side 147d, fourth side 147e, first connecting portion 147g, and second connecting portion 147h, and has five hollow rectangular shapes (square tubes extending in the gate width direction).

[0114] The fabrication of the gate electrode structure of the field-effect transistor according to the fifth embodiment will be briefly described. First, as in the first embodiment, the leg portion 107a and the first head portion 107b are formed ( FIG. 12A ). Next, an insulating layer 204 is formed on the insulating layer 111 so as to cover the first head portion 107b. Next, openings 204a and 204b are formed in the insulating layer 205, reaching both ends of the first head portion 107b in the gate length direction, and an opening 204c is further formed that reaches the center of the first head portion 107b.

[0115] Next, as described above, a lift-off mask is formed, openings 204a, 204b, and 204c are filled, and metal is deposited to form a metal layer on insulating layer 204 above first head portion 107b, followed by lift-off, thereby forming second head portion 107c as shown in FIG. 12B. By repeating these steps, the gate electrode structure described with reference to FIG. 10 can be formed. Furthermore, by changing the position of the opening between odd-numbered and even-numbered repetitions of the above-described steps, the gate electrode structure described with reference to FIG. 11 can be formed.

[0116] Incidentally, in the manufacturing process of the gate electrode structure described above, when the metal layer is formed by vacuum deposition, depressions 211 and 212 are actually formed in the formed metal layer where the openings are filled, as shown in Fig. 12C . Therefore, if the process is repeated without changing the locations where the openings are formed, the depressions accumulate, resulting in a break 213, as shown in Fig. 12C (c). To avoid this, the metal layer is formed relatively thick, and then the surface is planarized by chemical mechanical polishing (CMP) to eliminate the depressions, allowing the process to be repeated.

[0117] In contrast, in the formation of the structure shown in Fig. 11, the position of the opening is changed with each repetition of the process, making it less likely that problems such as the above-mentioned disconnection will occur. The position of the opening does not necessarily have to be changed between odd-numbered and even-numbered processes. For example, by repeating a process twice with the same opening position and then changing the opening position, a gate electrode structure having the cross-sectional shape shown in Fig. 13 can be formed. Furthermore, by changing the opening position in the first opening formation process, the opening position in the second opening formation process, and the opening position in the third opening formation process, and repeating these processes, a gate electrode structure having the cross-sectional shape shown in Fig. 14 can be formed.

[0118] As described above, according to the embodiment of the present invention, the gate electrode is composed of a leg portion, a first head portion formed continuously on the leg portion, a first side portion and a second side portion formed continuously on each of both ends of the first head portion, and a second head portion formed continuously on at least one of the first side portion and the second side portion, thereby making it possible to prevent an increase in gate resistance due to the skin effect.

[0119] It should be noted that the present invention is not limited to the embodiments described above, and it is clear that many modifications and combinations can be made by a person having ordinary knowledge in the art within the technical concept of the present invention.

[0120] 101...semiconductor substrate, 102...buffer layer, 103...channel layer, 104...barrier layer, 105...carrier supply layer, 106...cap layer, 106a...recess region, 107...gate electrode, 107a...leg portion, 107b...first head portion, 107c...second head portion, 107d...first side portion, 107e...second side portion, 108...source electrode, 109...drain electrode, 110...stopper layer, 111...insulating layer, 112...insulating layer, 113...insulating layer.

Claims

1. A field effect transistor comprising: a buffer layer, a channel layer, a barrier layer, and a carrier supply layer formed on a semiconductor substrate; a gate electrode formed on the barrier layer; source and drain electrodes formed on the barrier layer with the gate electrode sandwiched therebetween; and a cap layer formed between the source and drain electrodes and the barrier layer, wherein the gate electrode comprises: a leg portion; a first head portion formed continuously on the leg portion and having a length in the gate length direction longer than the leg portion; first and second side portions formed continuously on each of both ends of the first head portion in the gate length direction; and a second head portion formed continuously on at least one of the first and second side portions and having a length in the gate length direction longer than the leg portion, wherein the first and second head portions have cross sections perpendicular to the gate width direction that are elongated horizontally in the gate length direction, and the first and second side portions have cross sections perpendicular to the gate width direction that are elongated vertically in the thickness direction.

2. A field effect transistor according to claim 1, wherein the gate electrode further comprises: a third head portion disposed between the first side portion and the second side portion in the gate length direction, disposed between the first head portion and the second head portion in the thickness direction, and having a length in the gate length direction longer than that of the leg portion; a third side portion and a fourth side portion formed contiguous with each of both ends of the third head portion in the gate length direction; and a fourth head portion disposed between the first side portion and the second side portion in the gate length direction, disposed between the first head portion and the second head portion in the thickness direction, formed contiguous with at least one of the third side portion and the fourth side portion, and having a length in the gate length direction longer than that of the leg portion; wherein the third head portion and the fourth head portion have cross sections that are horizontally elongated in the gate length direction in a plane perpendicular to the gate width direction, and the third side portion and the fourth side portion have cross sections that are vertically elongated in the thickness direction in a plane perpendicular to the gate width direction.

3. A field effect transistor according to claim 2, wherein the gate electrode further comprises: a fifth head portion disposed between the third side portion and the fourth side portion in the gate length direction, and disposed between the third head portion and the fourth head portion in the thickness direction, the fifth head portion having a length in the gate length direction longer than that of the leg portion; and a fifth side portion disposed between the third side portion and the fourth side portion in the gate length direction, and formed contiguous with the fourth head portion and the fifth head portion, wherein the fifth head portion has a cross section perpendicular to the gate width direction that is elongated horizontally in the gate length direction, and the fifth side portion has a cross section perpendicular to the gate width direction that is elongated vertically in the thickness direction.

4. A field effect transistor according to claim 1, wherein the gate electrode further comprises: a third head portion disposed between the first side portion and the second side portion in the gate length direction, disposed between the first head portion and the second head portion in the thickness direction, and having a length in the gate length direction longer than that of the leg portion; a third side portion and a fourth side portion formed contiguous with each of both ends of the third head portion in the gate length direction and connected to the second side portion; a fourth head portion disposed between the third side portion and the fourth side portion in the gate length direction, disposed between the third head portion and the second head portion in the thickness direction, and having a length in the gate length direction longer than that of the leg portion; and a fifth side portion and a sixth side portion formed contiguous with each of both ends of the fourth head portion in the gate length direction and connected to the second side portion; wherein the third head portion and the fourth head portion have a cross-sectional shape in a plane perpendicular to the gate width direction that is elongated horizontally in the gate length direction; A field effect transistor in which the third side portion, the fourth side portion, the fifth side portion, and the sixth side portion have a cross-sectional shape in a plane perpendicular to the gate width direction that is elongated in the thickness direction.

5. A field effect transistor according to claim 1, wherein the gate electrode further comprises: a third head portion disposed between the first side portion and the second side portion in the gate length direction, disposed between the first head portion and the second head portion in the thickness direction, and having a length in the gate length direction longer than that of the leg portion; a fourth head portion disposed between the first side portion and the second side portion in the gate length direction, disposed between the third head portion and the second head portion in the thickness direction, and having a length in the gate length direction longer than that of the leg portion; and a connection portion disposed between the first side portion and the second side portion in the gate length direction, connecting the first head portion, the second head portion, the third head portion, and the fourth head portion, wherein the third head portion and the fourth head portion have cross sections perpendicular to the gate width direction that are elongated horizontally in the gate length direction, and the connection portion has a cross section perpendicular to the gate width direction that is elongated vertically in the thickness direction.

6. A field effect transistor according to claim 1, wherein the gate electrode further comprises: a third head portion disposed above the second head portion and having a length in the gate length direction longer than the leg portion; a third side portion and a fourth side portion formed contiguous with each of both ends of the third head portion in the gate length direction; a fourth head portion formed contiguous with at least one of the third side portion and the fourth side portion and having a length in the gate length direction longer than the leg portion; and a connecting portion formed between the second head portion and the third head portion and connecting the second head portion to the third head portion, wherein the third head portion and the fourth head portion have cross sections perpendicular to the gate width direction that are elongated horizontally in the gate length direction, and the third side portion, the fourth side portion and the connecting portion have cross sections perpendicular to the gate width direction that are elongated vertically in the thickness direction.

Images