Clock and reset system for digital integrated circuit

Abstract

The present application relates to the field of integrated circuit applications, and discloses a clock and reset system for a digital integrated circuit, comprising: a reset synchronization circuit, configured to perform a cross-clock operation on inputted reset requests (including but not limited to a button reset request and a power-on reset request) to be transferred to a reference clock domain, and generate a reset source signal in the reference clock domain to reset a counter circuit and a phase-locked loop circuit; the counter circuit, configured to generate a second-stage reset signal to reset a clock switching circuit and a reset management circuit; the phase-locked loop circuit, configured to output a high-frequency clock to the clock switching circuit; the clock switching circuit, configured to realize seamless switching between a reference clock and the high-frequency clock under the control of the second-stage reset signal, a clock lock status of the phase-locked loop circuit, and related configuration information, and output a system clock; and the reset management circuit, configured to generate reset signals for other modules in a chip on the basis of the second-stage reset signal and configuration reset signals of the other modules.

Description

A digital integrated circuit clock reset system

[0001] Cross-references to related applications

[0002] This application claims priority to Chinese Patent Application No. 202410798758.8, filed on June 20, 2024, entitled “A Digital Integrated Circuit Clock Reset System”, which is incorporated herein by reference in its entirety. Technical Field

[0003] This application belongs to the field of integrated circuit applications, and in particular relates to a digital integrated circuit clock reset system. Background Technology

[0004] With the rapid development of integrated circuit design technology, the design of clock and reset circuits in digital circuit systems has become increasingly important, directly affecting the overall stability of the chip. Digital circuit design typically uses an external crystal oscillator to provide the reference clock input, while an integrated phase-locked loop (PLL) circuit provides the high-speed clock signal required by each circuit module within the system. The implementation method of the clock and reset circuit directly impacts subsequent design stages such as logic synthesis, static timing analysis, design for testability, and placement and routing. Furthermore, each module in the system has relatively independent requirements for both clock and reset. Therefore, to facilitate backend design, the clock and reset circuits are usually integrated together, employing synchronous timing design methods to achieve a stable and reliable clock and reset system.

[0005] Phase-locked loop (PLL) circuits possess clock frequency multiplication, clock duty cycle adjustment, and clock distribution delay elimination capabilities. These characteristics allow designers to use a low-frequency external crystal oscillator as a clock source and generate an internal high-frequency clock signal of the desired value through PLL circuit frequency multiplication. However, after power-on or reset, the PLL circuit typically requires a certain waiting time to output a stable clock signal. During this period, all modules in the system need to maintain a stable clock input to avoid the risk of abnormal chip operation.

[0006] Furthermore, externally input reset signals are generally asynchronous signals, and their relationship with the chip's internal clock is not fixed. Improper handling can lead to the propagation of metastable signals, causing abnormal chip operation. The clock reset circuit needs a reasonable design method to handle the relationships between various input reset signals, generate corresponding reset trigger conditions, and produce the reset signals required by each circuit module in the system. This ensures that the reset timing meets the requirements of asynchronous reset and synchronous deactivation, and avoids metastability issues.

[0007] Summary of the Invention

[0008] The purpose of this application is to overcome the problems of the prior art by disclosing a digital integrated circuit clock reset system. The device of this application eliminates the risk of abnormal working state caused by factors such as clock frequency conversion, clock switching and chip reset. At the same time, it adopts an asynchronous reset synchronous withdrawal strategy to solve the metastability problem that may occur due to the input reset being an asynchronous signal, thereby avoiding chip logic errors and ensuring chip reliability.

[0009] The objective of this application is achieved through the following technical solution:

[0010] A digital integrated circuit clock reset system, the digital integrated circuit clock reset system comprising:

[0011] The reset synchronization circuit is configured to cross the clock input reset request to the reference clock domain and output a first-stage reset signal;

[0012] The counter circuit is configured to delay the first-stage reset signal using a counter, and to output the second-stage reset signal before the phase-locked loop circuit outputs a stable clock signal;

[0013] The phase-locked loop circuit is configured to output a clock as a source clock for other circuit modules, based on a reference clock input from an external crystal oscillator and the parameters of the phase-locked loop circuit.

[0014] The clock switching circuit is configured to switch between the reference clock input from the external crystal oscillator and the high-frequency clock output from the phase-locked loop circuit, output the system clock used by other circuit modules, and avoid generating glitches when the clock changes.

[0015] The reset management circuit is configured to output reset signals for each circuit module according to the different startup timing requirements of each circuit module.

[0016] According to a preferred embodiment, the reset synchronization circuit includes a three-stage flip-flop, the input reset request is connected to the reset terminal of the three-stage flip-flop through an AND gate logic circuit, and the clock terminal of the three-stage flip-flop is connected to a reference clock input from an external crystal oscillator.

[0017] The input of the first stage of the three-stage flip-flop is connected to a high level, the input of the second stage flip-flop is connected to the output of the first stage flip-flop, the input of the third stage flip-flop is connected to the output of the second stage flip-flop, and the output of the third stage flip-flop outputs the first stage reset signal.

[0018] According to a preferred embodiment, when the counter circuit receives the first stage reset signal request, the counter circuit clears the counter; when the counter circuit detects that the first stage reset signal request is withdrawn, the counter circuit compares the value of the counter with a preset threshold.

[0019] When the value of the counter is different from the preset threshold, the counter counts and initiates a second-stage reset signal request; when the value of the counter is the same as the preset threshold, the counter stops counting and cancels the second-stage reset signal request.

[0020] According to a preferred embodiment, the preset threshold is greater than the clock period required for the phase-locked loop circuit to output a stable clock signal after reset.

[0021] According to a preferred embodiment, the trigger clock terminal of the counter circuit is connected to a reference clock input from an external crystal oscillator.

[0022] According to a preferred embodiment, the clock input of the phase-locked loop circuit is connected to a reference clock input from an external crystal oscillator;

[0023] When either the first-stage reset signal or the internal phase-locked loop configuration reset signal requests a reset, the phase-locked loop circuit enters a reset state.

[0024] According to a preferred embodiment, the clock switching circuit is configured to output a reference clock before the phase-locked loop circuit outputs a stable high-frequency clock signal, or when the internal phase-locked loop bypass configuration signal is valid;

[0025] Once the phase-locked loop circuit outputs a stable high-frequency clock signal, the clock switching circuit automatically switches the output from the reference clock to the high-frequency clock, ensuring that other circuit modules have a stable clock input.

[0026] According to a preferred embodiment, the second-stage reset signal generates a global reset signal through a two-stage flip-flop. The clock terminal of the two-stage flip-flop is connected to the system clock signal output by the clock switching circuit. The digital integrated circuit peripheral interface and bus circuit module are reset through the global reset signal.

[0027] According to a preferred embodiment, the second-stage reset signal and the internal logic configuration reset signal of the digital integrated circuit are input to the secondary flip-flop through an AND gate logic circuit to generate a logic reset signal. The clock terminal of the secondary flip-flop is connected to the system clock signal output by the clock switching circuit. The logic reset signal resets all circuits except the configuration register circuit, peripherals and bus.

[0028] According to a preferred embodiment, the second-stage reset signal and the non-logic configuration reset signal within the digital integrated circuit are input to a secondary flip-flop via an AND gate to generate a configuration reset signal. The clock terminal of the secondary flip-flop is connected to the system clock signal output by the clock switching circuit. The configuration reset signal resets other configuration register circuits within the digital integrated circuit, excluding the clock and reset functions.

[0029] The aforementioned main solution and its various further alternative solutions can be freely combined to form multiple solutions, all of which are solutions that can be adopted and are claimed in this application. Those skilled in the art, after understanding the solution of this application, will realize that there are many combinations based on the prior art and common general knowledge, all of which are technical solutions to be protected in this application, and will not be exhaustively listed here.

[0030] The beneficial effects of this application are:

[0031] To avoid the metastability issues that may occur during asynchronous reset, leading to reset failure, this application adopts an asynchronous reset with synchronous release strategy. This filters out pulse interference and metastability signals that may appear in traditional asynchronous resets. Simultaneously, it resets each circuit according to the different startup timing requirements of each module within the chip. Addressing the issues of reliable initialization and stable operation caused by clock frequency conversion, clock switching, and chip reset, the chip's internal clock switching circuit automatically switches between the reference clock and the high-frequency clock output from the phase-locked loop circuit under the control of the counter circuit, while avoiding glitches during clock changes. This application combines the advantages of external button reset and internal power-on reset, achieving precise control of the same clock source and simplified reset logic design, thus enhancing circuit reliability. Attached Figure Description

[0032] Figure 1 is a block diagram of a digital integrated circuit clock reset system according to a preferred embodiment of this application;

[0033] Figure 2 is the timing diagram of the reset synchronization circuit and the counter circuit in Figure 1;

[0034] Figure 3 is a block diagram of the clock switching circuit in Figure 1;

[0035] Figure 4 is the timing diagram of the clock switching circuit in Figure 1; and

[0036] Figure 5 is a block diagram of the reset management circuit in Figure 1;

[0037] Figure label:

[0038] 301: First AND gate; 302: Second AND gate; 303: First NOT gate; 304: Second NOT gate; 305: Third AND gate; 306: First synchronous circuit; 307: Third NOT gate; 308: Fourth AND gate; 309: Second synchronous circuit; 310: Fifth AND gate; 311: Sixth AND gate; 501: First flip-flop; 502: Second flip-flop; 503: Seventh AND gate; 504: Third flip-flop; 505: Fourth flip-flop; 506: Eighth AND gate; 507: Fifth flip-flop; 508: Sixth flip-flop. Detailed Implementation

[0039] The following specific examples illustrate the implementation of this application. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification. This application can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this application. It should be noted that, unless otherwise specified, the following embodiments and features in the embodiments can be combined with each other.

[0040] It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. In the description of this application, it should also be noted that, unless otherwise expressly specified and limited, the terms "set," "install," "connect," and "link" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal communication between two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0041] Example 1

[0042] Referring to Figures 1 to 5, this embodiment discloses a digital integrated circuit clock reset system, which includes:

[0043] The reset synchronization circuit is configured to cross the clock input reset request to the reference clock domain and output a first-stage reset signal;

[0044] The counter circuit is configured to delay the first-stage reset signal using a counter, and to output the second-stage reset signal before the phase-locked loop circuit outputs a stable clock signal;

[0045] The phase-locked loop circuit is configured to output a clock as a source clock for other circuit modules, based on a reference clock input from an external crystal oscillator and the parameters of the phase-locked loop circuit.

[0046] The clock switching circuit is configured to switch between the reference clock input from the external crystal oscillator and the high-frequency clock output from the phase-locked loop circuit, output the system clock used by other circuit modules, and avoid generating glitches when the clock changes.

[0047] The reset management circuit is configured to output reset signals for each circuit module according to the different startup timing requirements of each circuit module.

[0048] Specifically, referring to Figure 1, the button reset request in_rst_n and the power-on reset request por_rst_n are connected to the reset terminal of the three-stage flip-flop of the reset synchronization circuit through an AND gate logic circuit. The clock terminal of the three-stage flip-flop is connected to the reference clock ref_clk input from the external crystal oscillator. The input terminal of the first-stage flip-flop in the three-stage flip-flop is connected to a high level, the input terminal of the second-stage flip-flop is connected to the output terminal of the first-stage flip-flop, the input terminal of the third-stage flip-flop is connected to the output terminal of the second-stage flip-flop, and the output terminal of the third-stage flip-flop outputs the first-stage reset signal first_stage_rst_n.

[0049] As shown in Figure 2, when the button reset request in_rst_n is initiated, the first-stage reset signal first_stage_rst_n is set to 0, and the counter circuit time_cnt is simultaneously cleared. When the button reset request in_rst_n is cancelled, the first-stage reset signal first_stage_rst_n is set to 1 after 3 reference clock cycles, and the counter circuit time_cnt starts counting from 0 until it reaches a preset threshold. When the counter circuit time_cnt equals the preset threshold, the second-stage reset signal second_stage_rst_n is set to 1; otherwise, the second-stage reset signal second_stage_rst_n is set to 0.

[0050] As shown in Figure 1, the clock input terminal of the phase-locked loop circuit is connected to the reference clock ref_clk, and the reset terminal receives the first stage reset signal first_stage_rst_n. The corresponding internal phase-locked loop configuration signals, including the bypass configuration signal pll_bp, the frequency division configuration signal pll_n, the frequency multiplication configuration signal pll_m, and the output frequency division configuration signal pll_od, are connected to the corresponding ports of the phase-locked loop. The phase-locked loop circuit outputs a high-frequency clock pll_clk.

[0051] The clock switching circuit is shown in Figure 3. The phase-locked loop (PLL) bypass configuration signal `pll_bp` and the PLL circuit lock signal `pll_lock` are connected to the input of the first AND gate 301. The output of the first AND gate 301 and the first-stage reset signal `first_stage_rst_n` are connected to the input of the second AND gate 302. The second AND gate 302 outputs the clock selection signal `clk_sel`. The clock selection signal `clk_sel` is also connected to the input of the third AND gate 305 and the input of the fourth AND gate 308. The PLL clock synchronization selection signal `pll_clk_sel_sync` is connected to the input of the second NOT gate 304. The output of the second NOT gate 304 is connected to the input of the third AND gate 305. The third AND gate 305 outputs the reference clock selection signal `ref_clk_sel`. The reference clock selection signal `ref_clk_sel` is connected to the input of the first-stage flip-flop of the first synchronization circuit 306. The input of the second-stage flip-flop is connected to the output of the first-stage flip-flop, and the input of the third-stage flip-flop is connected to the output of the second-stage flip-flop. The input of the fourth-stage flip-flop is connected to the output of the third-stage flip-flop. All clock inputs of the flip-flops in the first synchronization circuit 306 are connected to the reference clock ref_clk. The fourth-stage flip-flop of the first synchronization circuit 306 outputs a reference clock synchronization selection signal ref_clk_sel_sync. This signal is connected to the input of the third NOT gate 307, and its output is connected to the input of the fourth AND gate 308. The fourth AND gate 308 outputs a phase-locked loop (PLL) clock selection signal pll_clk_sel. The pll_clk_sel signal is connected to the input of the first-stage flip-flop in the second synchronization circuit 309. The inputs of the second-stage flip-flops are connected to the outputs of the first-stage flip-flops, the third-stage flip-flops are connected to the outputs of the second-stage flip-flops, and the fourth-stage flip-flops are connected to the outputs of the third-stage flip-flops. All clock inputs of the flip-flops in the second synchronization circuit 309 are connected to the high-frequency clock pll_clk. The fourth-stage flip-flop of the second synchronization circuit 309 outputs the phase-locked loop (PLL) clock synchronization selection signal pll_clk_sel_sync. The reference clock synchronization selection signal ref_clk_sel_sync and the reference clock ref_clk are connected to the two inputs of the fifth AND gate 310. The PLL clock synchronization selection signal pll_clk_sel_sync and the high-frequency clock pll_clk are connected to the two inputs of the sixth AND gate 311. The outputs of the fifth AND gate 310 and the sixth AND gate 311 are connected to the two inputs of the OR gate 312. The OR gate 312 outputs the chip system clock signal sys_clk. The timing of switching the reference clock to the high-frequency clock is shown in Figure 4.

[0052] The reset management circuit described in this example is shown in Figure 5. The second-stage reset signal `second_stage_rst_n` is connected to the input of the first flip-flop 501, and the output of the first flip-flop 501 is connected to the input of the second flip-flop 502. The second flip-flop 502 outputs the global reset signal `global_rst_n`. The second-stage reset signal `second_stage_rst_n` and the logic configuration reset signal `cfg_logic_rst_n` are connected to the input of the seventh AND gate 503. The output of the seventh AND gate 503 is connected to the input of the third flip-flop 504, and the output of the third flip-flop 504 is connected to the input of the fourth flip-flop 505. The fourth flip-flop 505 outputs the logic reset signal `logic_rst_n`. The second-stage reset signal `se`... The `cond_stage_rst_n` and the non-logic configuration reset signal `cfg_soft_rst_n` are connected to the input of the eighth AND gate 506. The output of the eighth AND gate 506 is connected to the input of the fifth flip-flop 507. The output of the fifth flip-flop 507 is connected to the input of the sixth flip-flop 508. The sixth flip-flop 508 outputs the configuration reset signal `soft_rst_n`. The global reset signal `global_rst_n` can reset the chip's peripheral interface and bus circuits. The logic reset signal `logic_rst_n` can reset the remaining circuits except for the configuration register circuits, peripherals, and buses. The configuration reset signal `soft_rst_n` can reset the internal configuration register circuits of the chip except for the clock and reset signals.

[0053] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, and improvements made within the principles of this application should be included within the protection scope of this application.

Claims

1. A digital integrated circuit clock reset system, comprising: The reset synchronization circuit is configured to cross the clock input reset request to the reference clock domain and output a first-stage reset signal; The counter circuit is configured to delay the first-stage reset signal using a counter, and to output the second-stage reset signal before the phase-locked loop circuit outputs a stable clock signal; The phase-locked loop circuit is configured to output a clock as a source clock for other circuit modules, based on a reference clock input from an external crystal oscillator and the parameters of the phase-locked loop circuit. The clock switching circuit is configured to switch between the reference clock input from the external crystal oscillator and the high-frequency clock output from the phase-locked loop circuit, output the system clock used by other circuit modules, and avoid generating glitches when the clock changes. The reset management circuit is configured to output reset signals for each circuit module according to the different startup timing requirements of each circuit module.

2. The digital integrated circuit clock reset system as described in claim 1, wherein, The reset synchronization circuit includes a three-stage flip-flop. The input reset request is connected to the reset terminal of the three-stage flip-flop through an AND gate logic circuit. The clock terminal of the three-stage flip-flop is connected to the reference clock input of an external crystal oscillator. The input of the first stage of the three-stage flip-flop is connected to a high level, the input of the second stage flip-flop is connected to the output of the first stage flip-flop, the input of the third stage flip-flop is connected to the output of the second stage flip-flop, and the output of the third stage flip-flop outputs the first stage reset signal.

3. The digital integrated circuit clock reset system as described in claim 1, wherein, When the counter circuit receives the first stage reset signal request, the counter circuit clears the counter; when the counter circuit detects that the first stage reset signal request is cancelled, it compares the value of the counter with a preset threshold. When the value of the counter is different from the preset threshold, the counter counts and initiates a second-stage reset signal request; when the value of the counter is the same as the preset threshold, the counter stops counting and cancels the second-stage reset signal request.

4. The digital integrated circuit clock reset system as described in claim 3, wherein, The preset threshold is greater than the clock period required for the phase-locked loop circuit to output a stable clock signal after reset.

5. The digital integrated circuit clock reset system as described in claim 1, wherein, The clock input of the counter circuit is connected to the reference clock input of an external crystal oscillator.

6. The digital integrated circuit clock reset system as described in claim 1, wherein, The clock input terminal of the phase-locked loop circuit is connected to the reference clock input from an external crystal oscillator; When either the first-stage reset signal or the internal phase-locked loop configuration reset signal requests a reset, the phase-locked loop circuit enters a reset state.

7. The digital integrated circuit clock reset system as described in claim 1, wherein, The clock switching circuit is configured to output a reference clock before the phase-locked loop circuit outputs a stable high-frequency clock signal, or when the internal phase-locked loop bypass configuration signal is valid. Once the phase-locked loop circuit outputs a stable high-frequency clock signal, the clock switching circuit automatically switches the output from the reference clock to the high-frequency clock, ensuring that other circuit modules have a stable clock input.

8. The digital integrated circuit clock reset system as described in claim 1, wherein, The second-stage reset signal generates a global reset signal through a two-stage flip-flop. The clock terminal of the two-stage flip-flop is connected to the system clock signal output by the clock switching circuit. The global reset signal resets the digital integrated circuit peripheral interface and bus circuit module.

9. The digital integrated circuit clock reset system as described in claim 8, wherein, The second-stage reset signal and the internal logic configuration reset signal of the digital integrated circuit are input to the secondary flip-flop through the AND gate logic circuit to generate a logic reset signal. The clock terminal of the secondary flip-flop is connected to the system clock signal output by the clock switching circuit. The logic reset signal resets all circuits except the configuration register circuit, peripherals and bus.

10. The digital integrated circuit clock reset system as described in claim 8, wherein, The second-stage reset signal and the non-logic configuration reset signal in the digital integrated circuit are input to the secondary flip-flop through an AND gate to generate a configuration reset signal. The clock terminal of the secondary flip-flop is connected to the system clock signal output by the clock switching circuit. The configuration reset signal resets the other configuration register circuits inside the digital integrated circuit except for the clock and reset.

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