Semiconductor structure, semiconductor device and preparation method for semiconductor structure

Abstract

The present disclosure relates to the technical field of semiconductors. Provided are a semiconductor structure, a semiconductor device and a preparation method for the semiconductor structure. The semiconductor structure comprises: a substrate, wherein a plurality of active pillars arranged at intervals in a first direction and a second direction are provided inside the substrate, and the active pillars extend in a third direction; first grooves, which expose the top surfaces of the active pillars and are provided inside the substrate, wherein the first grooves are arranged at intervals in the first direction and the second direction; a first insulating layer, which is provided inside the substrate, wherein the first insulating layer isolates the first grooves; and capacitor contact structures, wherein the capacitor contact structures are located in the first grooves, cover the top surfaces of the active pillars and are configured to connect to a capacitor structure; and each capacitor contact structure comprises a metal silicide layer, a diffusion barrier layer and a metal layer, which are arranged in sequence in the extension direction of the active pillars, with the metal silicide layer being in contact with the active pillars, and the top surface of the diffusion barrier layer being lower than the top surfaces of the first grooves.

Description

Semiconductor structure, semiconductor device and method for manufacturing semiconductor structure

[0001] Cross-reference to Related Applications

[0002] This application is based on and claims priority to Chinese Patent Application No. 202410816506.3, filed on June 21, 2024, the entire contents of which are incorporated herein by reference. TECHNICAL FIELD

[0003] The present disclosure relates to the technical field of semiconductor technology, and in particular, to a semiconductor structure, a semiconductor device and a method for manufacturing semiconductor structure. BACKGROUND

[0004] Dynamic Random Access Memory (DRAM) belongs to volatile memory, which is composed of a plurality of memory cells, each memory cell mainly includes a transistor and a capacitor structure, and each memory cell is electrically connected to each other through a word line (WL) and a bit line (BL).

[0005] With the development of semiconductor technology, it has been proposed to change the horizontal transistor to a vertical transistor (Vertical Channel Transistor) architecture scheme. Such a DRAM forms a vertically extending active pillar on a substrate, forms a wraparound gate on the outside of the active pillar, and forms a buried bit line and a buried word line.

[0006] However, the DRAM with vertical transistors also faces many problems, such as the electrical connection problem between the capacitor structure and the active pillar and the etching chamber pollution problem in the etching of the capacitor hole process, which are urgent technical problems to be solved.

[0007] It should be noted that the information disclosed in the above background section is only used to strengthen the understanding of the background of the present disclosure, and therefore can include information that does not constitute prior art known to those of ordinary skill in the art.

[0008] SUMMARY

[0009] The present disclosure provides a semiconductor structure, a semiconductor device and a method for manufacturing semiconductor structure, which can reduce the contact resistance between the capacitor structure and the active pillar, and avoid the etching chamber pollution problem in the etching of the capacitor hole process.

[0010] Other characteristics and advantages of the present disclosure will become apparent from the following detailed description, or will be learned by practice of the present disclosure.

[0011] According to one aspect of the present disclosure, a semiconductor structure is provided, comprising:

[0012] a substrate, a plurality of active pillars arranged in a first direction and a second direction in the substrate, the active pillars extending in a third direction; a first recess exposing a top surface of the active pillars in the substrate, the first recess arranged in the first direction and the second direction in the substrate; and a first insulating layer in the substrate, the first insulating layer isolating the first recess; the first direction and the second direction intersecting and both being perpendicular to the third direction;

[0013] a capacitor contact structure in the first recess, the capacitor contact structure covering the top surface of the active pillars to connect a capacitor structure;

[0014] wherein the capacitor contact structure comprises, in sequence in the extending direction of the active pillars, a metal silicide layer, a diffusion barrier layer, and a metal layer, the metal silicide layer being in contact with the active pillars, and a top surface of the diffusion barrier layer being lower than a top surface of the first recess.

[0015] In one embodiment, the diffusion barrier layer is also provided on a sidewall of the first recess, and a height of the diffusion barrier layer on the sidewall of the first recess in the third direction is less than a height of the metal layer in the third direction.

[0016] In one embodiment, the height of the diffusion barrier layer on the sidewall of the first recess in the third direction is 1 / 8-1 / 2 of the height of the metal layer in the third direction.

[0017] In one embodiment, a top surface of the metal layer has a smaller projected area on the substrate than a bottom surface of the metal layer.

[0018] In one embodiment, the metal layer has a rounded corner structure.

[0019] In one embodiment, a center line of the active pillar and a center line of the capacitor contact structure substantially overlap, and a contact surface of the metal silicide layer and the active pillar is a non-planar or non-flat surface.

[0020] In one embodiment, a projected area of the first recess on the substrate is larger than a projected area of the top surface of the active pillar on the substrate.

[0021] In one embodiment, a source electrode structure, a vertical channel, and a drain electrode structure are sequentially arranged on the active pillar in the third direction, the source electrode structure being located at a top of the active pillar; a gate electrode structure is also provided in the substrate, the gate electrode structure surrounding the vertical channel of the active pillar, adjacent gate electrode structures in the second direction being in contact, and adjacent gate electrode structures in the first direction being insulated from each other; a bit line structure is also provided in the substrate, the bit line structure being located on a side of the substrate extending away from the active pillar, the bit line structure extending in the first direction, and adjacent bit line structures in the second direction being insulated from each other.

[0022] According to another aspect of the present disclosure, there is provided a semiconductor device obtained by bonding the above semiconductor structure with a first wafer having CMOS transistors of the semiconductor device.

[0023] According to yet another aspect of the present disclosure, there is provided a method for manufacturing the above semiconductor structure, comprising:

[0024] providing a substrate, forming a plurality of initial active pillars spaced apart along a first direction and a second direction in the substrate, the plurality of initial active pillars each extending along a third direction; forming a first initial insulating layer in the substrate with the plurality of initial active pillars being isolated by the first initial insulating layer; the first direction and the second direction are perpendicular to the third direction;

[0025] etching the plurality of initial active pillars to form a plurality of initial recesses spaced apart along the first direction and the second direction, the plurality of initial recesses being isolated by the first initial insulating layer; the plurality of initial active pillars after the etching are the plurality of active pillars;

[0026] forming a metal silicide layer, a diffusion barrier material layer, and a metal material layer in the plurality of initial recesses in sequence; the diffusion barrier material layer is also formed on sidewalls of the plurality of initial recesses;

[0027] etching the first initial insulating layer to expose the diffusion barrier material layer on the sidewalls of the plurality of initial recesses;

[0028] etching the diffusion barrier material layer such that a top surface of the diffusion barrier material layer is lower than a top surface of the plurality of initial recesses; the diffusion barrier material layer after the etching is a diffusion barrier layer; the metal material layer after the etching is a metal layer; the metal silicide layer, the diffusion barrier layer, and the metal layer constitute a capacitor contact structure for connecting a capacitor structure;

[0029] forming a second insulating layer, the first initial insulating layer after the etching and the second insulating layer together constitute a first insulating layer, and the plurality of initial recesses after the first insulating layer is filled are a plurality of first recesses.

[0030] In one embodiment, the exposed height of the diffusion barrier material layer on the sidewalls of the plurality of initial recesses in the third direction is 1 / 2-7 / 8 of the height of the metal material layer in the third direction.

[0031] In one embodiment, a bottom surface of the plurality of initial recesses is a non-planar or non-flat surface; an area of a normal projection of the plurality of initial recesses on the substrate is greater than an area of a normal projection of a top surface of the plurality of active pillars on the substrate.

[0032] In one embodiment, the etching of the first initial insulating layer to expose the diffusion barrier material layer on the sidewalls of the plurality of initial recesses comprises: an etching selectivity ratio of the first initial insulating layer and the diffusion barrier material layer is greater than or equal to 5, and an etching selectivity ratio of the first initial insulating layer and the metal material layer is greater than or equal to 6.

[0033] Etching a diffusion barrier material layer includes: an etching selectivity ratio of the diffusion barrier material layer and the first initial insulating layer greater than or equal to 6, and an etching selectivity ratio of the diffusion barrier material layer and the metal material layer greater than or equal to 6.

[0034] In one embodiment, a metal silicide layer, a diffusion barrier material layer, and a metal material layer are sequentially formed within an initial groove, comprising: forming a metal silicide layer at the bottom of the initial groove; continuing to deposit a diffusion barrier material layer covering the sidewalls of the initial groove and the top surface of the metal silicide layer; depositing a metal material layer covering the diffusion barrier material layer and the first initial insulating layer; and performing planarization to expose the first initial insulating layer.

[0035] In one embodiment, forming a second insulating layer, wherein the first initial insulating layer and the second insulating layer after etching constitute the first insulating layer, includes: depositing the second insulating layer to cover the metal layer and the first initial insulating layer; and planarizing the second insulating layer to expose the metal layer.

[0036] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0037] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0038] Figure 1 is a top perspective view of the substrate of the semiconductor structure provided in an embodiment of the present disclosure; Figure 2 is a cross-sectional view of the semiconductor structure at points aa and cc in one embodiment of Figure 1; Figure 3 is a cross-sectional view of the semiconductor structure at points aa and cc in another embodiment of Figure 1; Figure 4 is an enlarged view of the capacitor contact structure in the semiconductor structure in different embodiments; Figure 5 shows a schematic diagram of the structure of a semiconductor device provided in an embodiment of the present disclosure; Figure 6 shows a flowchart of the steps of the method for preparing the semiconductor structure provided in an embodiment of the present disclosure; Figures 7-17 are cross-sectional views along points aa and cc in Figure 1 during the semiconductor structure formation process in some embodiments of the present disclosure. Detailed Implementation

[0039] To facilitate understanding of this disclosure, a more complete description will now be given with reference to the accompanying drawings, in which preferred embodiments of the present disclosure are shown. However, this disclosure may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

[0040] The size of the transistor unit integrated on the substrate of the semiconductor device is gradually reduced, thereby gradually proposing a vertical transistor with a 4F 2 (F represents the minimum feature size) architecture, compared with a planar 6F 2 architecture transistor, 4F 2 The area of the vertical transistor unit of the 4F

[0041] However, in the existing semiconductor structure with a vertical transistor, the contact resistance between the active column of the vertical transistor and the capacitor structure is high, which limits the transmission rate of the vertical transistor, affects the performance of the semiconductor structure, and in the preparation process of the semiconductor structure, especially in the capacitor hole etching process, the structure of the front process will affect the precision of the etching chamber in the etching process of the capacitor hole.

[0042] Therefore, the semiconductor structure, the semiconductor device and the preparation method of the semiconductor structure are provided, the semiconductor structure is provided by setting a capacitor contact structure between the active column and the capacitor structure, the capacitor contact structure includes a metal silicide layer, a diffusion barrier layer and a metal layer, by setting in this way, the resistance between the capacitor structure and the active column is reduced, the transmission rate of the vertical transistor is improved, and the diffusion barrier layer is provided, the height of the orthographic projection of the first groove sidewall in the third direction is less than the height of the orthographic projection of the metal layer on the first groove sidewall in the third direction, thereby avoiding the problem of etching chamber pollution in the etching process of the capacitor hole.

[0043] In order to make the purpose, technical scheme and advantages of the embodiments of the present application clearer, the technical scheme in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor are within the scope of protection of the present application.

[0044] Figure 1 is a top perspective view of the substrate of the semiconductor structure provided by the embodiments of the present disclosure; Figure 2 is a sectional view of a-a and c-c of the semiconductor structure in one embodiment corresponding to Figure 1;

[0045] Referring to Figure 1, in one embodiment, the semiconductor structure 100 includes:

[0046] The substrate 110 has a plurality of active pillars 120 formed therein and arranged along a first direction and a second direction, and each of the plurality of active pillars 120 extends along a third direction; the substrate 110 is provided with a first recess 167 exposing a top surface of the active pillar 120, and the first recess 167 is arranged along the first direction and the second direction; and the substrate 110 is further provided with a first insulating layer 151, and the first insulating layer 151 separates the first recess 167; the first direction and the second direction are perpendicular to each other and perpendicular to the third direction;

[0047] Continuing to refer to FIG. 1, for example, the first direction and the second direction can be perpendicular to each other, the first direction is, for example, the Y direction in FIG. 1, the second direction is, for example, the X direction in FIG. 1, and the third direction is, for example, the Z direction in FIG. 1, that is, the thickness direction of the substrate 110. In other embodiments, the first direction and the second direction can not be perpendicular, for example, the included angle between the first direction and the second direction can be an acute angle. The material of the substrate 110 can be, for example, monocrystalline silicon, polycrystalline silicon, amorphous silicon, or silicon-on-insulator (SOI). In addition, the material of the substrate 110 can include silicon germanium, silicon germanium on insulator (SGOI), indium antimonide, lead telluride compound, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide, but is not limited thereto. The active pillars 120 in the substrate 110 are arranged in an array and extend in the thickness direction of the substrate 110, that is, the Z direction. The cross section of the active pillar 120 can be circular, square, or oval, etc., to improve the integration of the semiconductor structure 100, but is not limited thereto. The active pillar 120 is used to form a channel region (not shown), a source region (not shown), and a drain region (not shown) of a vertical transistor.

[0048] Continuing to refer to FIGS. 1 and 2, the first recess 167 exposes the top surface of the active pillar 120, that is, each active pillar corresponds to a first recess, that is, the first recess and the active pillar are arranged along the first direction and the second direction. The top view shape of the first recess can be circular, oval, polygonal, etc., and is not specifically limited, and can be reasonably set according to actual conditions. The first insulating layer 151 not only separates the first recess 167, but also separates the active pillars 120. The material of the first insulating layer 151 can be silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, or silicon carbon nitride. In this embodiment, the material of the first insulating layer 151 is silicon nitride, and the silicon nitride is low-density silicon nitride to reduce the stress of the first insulating layer 151 on the active pillar 120.

[0049] The capacitor contact structure 160 is located in the first recess 167, and covers the top surface of the active pillar 120 to connect the capacitor structure 170, that is, the spatial size of the capacitor contact structure 160 defines the spatial size of the first recess 167.

[0050] Continuing to refer to FIG. 2, the capacitor contact structure 160 includes a metal silicide layer 161, a diffusion barrier layer 162, and a metal layer 163 stacked in sequence in the direction in which the active pillar 120 extends, the metal silicide layer 161 being in contact with the active pillar 120, and the top surface of the diffusion barrier layer 162 being lower than the top surface of the first recess 167.

[0051] The metal silicide layer 161 is a compound formed by the reaction of a metal element (such as titanium, tungsten, nickel, cobalt, molybdenum, etc.) and silicon, and the formation of the metal silicide produces a direct metal-semiconductor contact. This contact reduces the interface state, reduces the contact resistance, and improves the current transmission efficiency. At the same time, the metal silicide has good adhesion between the active pillar and the metal diffusion layer, which helps to form a stable contact, reduces the interface resistance, and improves the reliability of the overall circuit. Common metal silicides include titanium silicide (TiSi2), tungsten silicide (WSi2), nickel silicide (NiSi), and cobalt silicide (CoSi2), etc. The diffusion barrier layer 162 can prevent the metal layer 163 from diffusing into the metal silicide layer 161, thereby affecting the electrical properties of the metal silicide layer 161. The diffusion barrier layer 162 is made of a metal titanium compound such as titanium nitride (TiN), which has a high melting point and chemical stability, and can maintain its structural integrity at high temperatures, effectively preventing metal diffusion into areas where they are not desired. The metal layer 163 is mainly made of metal materials such as aluminum (Al), copper (Cu), and tungsten (W), which have low resistivity and can efficiently transmit current. Moreover, the top surface of the diffusion barrier layer 162 is lower than the top surface of the first recess 167, wherein the top surface of the diffusion barrier layer 162 is the plane with the maximum height of the diffusion barrier layer 162 in the third direction, that is, the diffusion barrier layer 162 is not exposed to the top surface of the first recess 167. In this way, during the etching of the capacitor hole, the diffusion barrier layer 162 will not be etched, thereby avoiding the problem of titanium contamination of the etching chamber, and improving the etching performance when etching the capacitor hole.

[0052] By sequentially arranging the metal silicide layer 161, the diffusion barrier layer 162, and the metal layer 163, the contact resistance between the active pillar of the vertical transistor and the capacitor structure can be effectively reduced, and the transmission rate of the vertical transistor can be improved. At the same time, by arranging the top surface of the diffusion barrier layer 162 to be lower than the top surface of the first recess 167, the problem of titanium contamination of the etching chamber during the etching of the capacitor hole can be avoided, thereby improving the etching precision.

[0053] FIG. 3 is a cross-sectional view of a semiconductor structure at a-a and c-c in another embodiment corresponding to FIG. 1;

[0054] Referring to FIG. 3, in one embodiment, the diffusion barrier layer 162 is also disposed on the sidewall of the first recess 167, and the height of the diffusion barrier layer 162 on the sidewall of the first recess 167 in the third direction is less than the height of the metal layer 163 in the third direction; that is, the diffusion barrier layer 162 wraps part of the metal layer 163. In this way, the area of the projection of the diffusion barrier layer 162 on the substrate is greater than the area of the projection of the metal layer 163 on the substrate, and the diffusion barrier layer 162 is not exposed to the top surface of the first recess. In this way, not only can the problem of contamination of the etching chamber by titanium during the etching of the capacitor hole be prevented, but the size of the contact structure 160 can also be reduced, the risk of short circuit of the contact structure 160 can be reduced, and the contact area between the diffusion barrier layer 162 and the metal silicide layer 161 and the metal layer 163 can be ensured, thereby reducing the contact resistance.

[0055] Continuing to refer to FIG. 3, in one embodiment, the height of the diffusion barrier layer 162 on the sidewall of the first recess 167 in the third direction is 1 / 8-1 / 2 of the height of the metal layer 163 in the third direction. The ratio cannot be too large, and a too large ratio will still cause etching of the diffusion barrier layer 162 during etching of the capacitor hole, thereby increasing the risk of contamination of the etching chamber. The ratio cannot be too small, and a too small ratio will increase the load on the process and increase the process cost.

[0056] FIG. 4 is an enlarged view of a capacitor contact structure in a semiconductor structure in different embodiments;

[0057] Referring to FIG. 4, in one embodiment, the area of the projection of the top surface of the metal layer 163 on the substrate 110 is less than the area of the projection of the bottom surface of the metal layer 163 on the substrate 110. The bottom surface of the metal layer 163 is the contact surface between the metal layer 163 and the diffusion barrier layer 162, and the top surface of the metal layer 163 is a flat surface, that is, the top surface of the metal layer 163 is substantially parallel to the bottom surface of the metal layer 163. By setting the area of the projection of the top surface of the metal layer 163 on the substrate 110 to be less than the area of the projection of the bottom surface of the metal layer 163 on the substrate 110, as the size of the semiconductor structure is reduced, the risk of short circuit between the metal layers 163 can be reduced, and the electrical stability of the semiconductor structure can be improved.

[0058] Continuing to refer to FIG. 4, in one embodiment, the metal layer 163 has a rounded corner structure a. That is, a rounded corner structure is provided at the top or corner of the metal layer, which can improve the electric field distribution and reduce the strength of the local electric field, thereby reducing the possibility of dielectric breakdown. By using the rounded corner structure, the electric field is more uniform, which helps to prolong the service life of the semiconductor structure and improve its reliability.

[0059] Referring again to Figure 2 or Figure 3, in one embodiment, the centerline of the active pillar 120 substantially overlaps with the centerline of the capacitor contact structure 160. The centerline of the active pillar 120 and the centerline of the capacitor contact structure 160 can completely overlap, or they can only substantially overlap, indicating a manufacturing error. In other words, the centerline of the active pillar 120 must substantially overlap with the centerline of the capacitor contact structure 160 to ensure that the capacitor structure 170 is positioned directly above the active pillar 120, thus achieving a 4F capacitance. 2 (F represents the minimum feature size) vertical transistor architecture, compared to the planar 6F... 2 transistor architecture, 4F 2 The area of ​​the vertical transistor cell in the architecture can be reduced by about 30%. Meanwhile, the contact surface between the metal silicide layer 161 and the active pillar 120 is non-planar or non-flat; that is, the contact surface between the metal silicide layer 161 and the active pillar 120 can be curved. This design increases the contact area between the metal silicide layer 161 and the active pillar 120, thereby reducing the contact resistance and improving the transmission efficiency of the vertical transistor.

[0060] Referring again to Figure 2 or Figure 3, in one embodiment, the projected area of ​​the first groove 167 on the substrate 110 is larger than the projected area of ​​the top surface of the active pillar 120 on the substrate 110. The top surface of the active pillar 120 is the contact surface between the active pillar 120 and the metal silicide layer 161. The projected area of ​​the first groove 167 on the substrate 110 depends on the maximum area of ​​the projected areas of the metal silicide layer 161, the diffusion barrier layer 162, and the metal layer 163 on the substrate 110. This arrangement allows the top surface of the active pillar 120 to be completely exposed by the first groove 167, thereby increasing the contact area between the active pillar 120 and the first groove 167, reducing contact resistance, and improving the transmission efficiency of the vertical transistor. Meanwhile, the projected area of ​​capacitor structure 170 on substrate 110 is larger than the projected area of ​​capacitor contact structure 160 on substrate 110. This increases the contact area between capacitor structure 170 and capacitor contact structure 160 and reduces the contact resistance between capacitor structure 170 and capacitor contact structure 160.

[0061] Referring back to FIG. 2 or FIG. 3, in one embodiment, the active pillar 120 is sequentially provided with a source structure (not shown), a vertical channel (not shown) and a drain structure (not shown) in the third direction, wherein the source structure is located at the top of the active pillar 120; the substrate 110 is further provided with a gate structure 130, which surrounds part of the active pillar 120, i.e., the gate structure 130 surrounds the channel region of the active pillar 120. Referring to FIG. 1, adjacent gate structures 130 in the second direction, i.e., the X direction, are connected to form a word line, and adjacent gate structures 130 in the first direction, i.e., the Y direction, are insulated from each other; referring back to FIG. 2 or FIG. 3, the gate structure 130 and the active pillar 120 further comprise a gate oxide layer 131, which can be an annular structure, i.e., the gate oxide layer 131 surrounds the entire outer sidewall of the channel region of the active pillar 120. Alternatively, the gate oxide layer 131 can also be a semi-annular structure, i.e., the gate oxide layer 131 surrounds part of the outer sidewall of the channel region of the active pillar 120, and the other part of the outer sidewall of the channel region can be exposed outside the gate oxide layer 131. The material of the gate oxide layer 131 can be one or more of silicon oxide, FSG (fluorine-doped silicon dioxide), BSG (boron-doped silicon dioxide), PSG (phosphorus-doped silicon dioxide) or BPSG (boron-phosphorus-doped silicon dioxide); the substrate 110 is further provided with a bit line structure 140, which is located on the side of the substrate 110 extending away from the active pillar 120. Referring to FIG. 1, the bit line structure 140 extends in the first direction, i.e., the Y direction, and adjacent bit line structures 140 in the second direction, i.e., the X direction, are insulated from each other. Referring to FIG. 2 or FIG. 3, the bit line structure 140 is electrically connected to the active pillar 120, and the bit line structure 140 is further isolated by an isolation structure 152 below the word line structure 130. The material of the isolation structure 152 can be one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide and silicon carbonitride. In addition, the bit line structure 140 is connected to a first pad on the side of the substrate 110 extending away from the active pillar 120 through a via (not shown), which is beneficial to the subsequent bonding step.

[0062] Based on the above-mentioned embodiments, the disclosure further provides a semiconductor device. The semiconductor device is described in detail as follows.

[0063] FIG. 5 shows a structural schematic diagram of a semiconductor device provided by an embodiment of the disclosure;

[0064] Referring to FIG. 5, in one embodiment, a semiconductor device 300 is formed by bonding the semiconductor structure 100 described above with a first wafer 200 having CMOS transistors of the semiconductor device. The semiconductor device 300 can be a memory device or a non-memory device. The memory device can include, for example, a Dynamic Random Access Memory (DRAM), a Static Random Access Memory (SRAM), a flash memory, an Electrically Erasable Programmable Read-Only Memory (EEPROM), a Phase Change Random Access Memory (PRAM), or a Magnetoresistive Random Access Memory (MRAM). The non-memory device can be a logic device (e.g., a microprocessor, a digital signal processor, or a microcontroller) or a device similar thereto. The first wafer 200 has, for example, CMOS transistors therein, such as peripheral region transistors in the semiconductor device 300, e.g., a DRAM. The semiconductor structure 100 and the first wafer 200 can be bonded by bump bonding, fusion bonding, hybrid bonding, or the like. The semiconductor structure 100 and the first wafer 200 can be bonded by chip to chip bonding or wafer on wafer bonding.

[0065] In one embodiment, the semiconductor structure 100 and the first wafer 200 can be hybrid bonded. Referring to FIG. 5, the semiconductor structure 100 has internal electrical signals routed to first pads 101 through via structures (not shown), and the first wafer 200 has internal electrical signals routed to second pads 201 through via structures (not shown). The first pads 101 are isolated by a first dielectric layer 102, and the second pads 201 are isolated by a second dielectric layer 202. The semiconductor structure 100 and the first wafer 200 are hybrid bonded by annealing. The first pads 101 and the second pads 201 can be made of the same material, such as a metal, e.g., copper, gold, or aluminum. The first dielectric layer 102 and the second dielectric layer 202 can be made of the same material, such as an insulating material, e.g., silicon nitride Si3N4, silicon dioxide SiO2, silicon carbon nitride SiCN, silicon oxynitride SiON, hafnium oxide HfO, or zirconium oxide ZrO.

[0066] On the basis of the above-mentioned embodiments, the disclosure further provides a semiconductor structure preparation method (hereinafter referred to as the preparation method) for preparing the semiconductor structure 100. The preparation method is described in detail as follows.

[0067] FIG. 6 shows a flowchart of the semiconductor structure preparation method according to an embodiment of the disclosure;

[0068] FIGS. 7-17 are sectional views of the semiconductor structure along the a-a and c-c directions in FIG. 1 during the formation of the semiconductor structure according to some embodiments of the disclosure;

[0069] Referring to FIG. 6, the semiconductor structure preparation method includes the following steps.

[0070] S100, referring to FIG. 7, a substrate 110 is provided, and a plurality of initial active pillars 121 are formed in the substrate 110 and spaced apart along a first direction and a second direction, and the plurality of initial active pillars 121 all extend along a third direction; a first initial insulating layer 153 is formed in the substrate 110 and separates the initial active pillars 121; the first direction and the second direction are perpendicular to the third direction;

[0071] For example, the first direction and the second direction can be perpendicular to each other, for example, the first direction is the Y direction in FIG. 1, the second direction is the X direction in FIG. 1, and the third direction is the Z direction in FIG. 1, i.e., the thickness direction of the substrate 110. In other embodiments, the first direction and the second direction can not be perpendicular, for example, the angle between the first direction and the second direction can be an acute angle. The material of the substrate 110 can be, for example, monocrystalline silicon, polycrystalline silicon, amorphous silicon, or silicon-on-insulator (SOI). In addition, the material of the substrate 110 can include silicon germanium, silicon germanium on insulator (SGOI), indium antimonide, lead telluride compound, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide, but is not limited thereto. The initial active pillars 121 in the substrate 110 are arranged in an array and extend in the Z direction, i.e., the thickness direction of the substrate 110. The cross section of the initial active pillars 121 can be circular, square, or oval to improve the integration of the semiconductor structure 100, but is not limited thereto. The first initial insulating layer 153 separates the active pillars 120, and the material of the first initial insulating layer 153 can be one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, or silicon carbonitride. In this embodiment, the material of the first initial insulating layer 153 is silicon nitride, and the silicon nitride is low-density silicon nitride to reduce the stress of the first initial insulating layer 153 on the initial active pillars 121.

[0072] S200, referring to FIG. 8, etching the initial active pillar 121 to form an initial groove 166, the initial grooves 166 are arranged at intervals along the first direction and the second direction, and the initial grooves 166 are separated by the first initial insulating layer 153; the initial active pillar 121 after etching is the active pillar 120;

[0073] S300, referring to FIGS. 9-11, sequentially forming a metal silicide layer 161, a diffusion barrier material layer 164, and a metal material layer 165 in the initial groove 166; the diffusion barrier material layer 164 is also formed on the sidewall of the initial groove 166;

[0074] For example, the metal silicide layer 161 is a compound formed by the reaction of a metal element (such as titanium, tungsten, nickel, cobalt, molybdenum, etc.) and silicon, and the formation of the metal silicide produces a direct metal-semiconductor contact. This contact reduces the interface state, reduces the contact resistance, and improves the current transmission efficiency. At the same time, the metal silicide has good adhesion between the silicon and the metal layer, which helps to form a stable contact, reduces the interface resistance, and improves the reliability of the overall circuit. Common metal silicides include titanium silicide (TiSi2), tungsten silicide (WSi2), nickel silicide (NiSi), and cobalt silicide (CoSi2), etc.; the diffusion barrier material layer 164 can prevent the metal material layer 165 from diffusing into the metal silicide layer 161, thereby affecting the electrical properties of the metal silicide layer 161. The material of the diffusion barrier material layer 164 is a titanium compound such as titanium nitride (TiN), which has a high melting point and chemical stability, and can maintain its structural integrity at high temperatures, effectively preventing metal diffusion into areas where they are not desired. The metal material layer 165 is mainly made of metal materials such as aluminum (Al), copper (Cu), and tungsten (W), which have low resistivity and can efficiently transmit current.

[0075] S400, referring to FIG. 12 or FIG. 16, etching the first initial insulating layer 153 to expose the diffusion barrier material layer 164 on the sidewall of the initial groove 166;

[0076] S500, referring to FIG. 13 or FIG. 17, etching the diffusion barrier material layer 164 so that the top surface of the diffusion barrier material layer 164 is lower than the top surface of the initial groove 166; here, the top surface of the diffusion barrier material layer 164 is the plane with the maximum height in the third direction; the diffusion barrier material layer 164 after etching is the diffusion barrier layer 162; the metal material layer 165 after etching is the metal layer 163; the metal silicide layer 161, the diffusion barrier layer 162, and the metal layer 163 constitute a capacitor contact structure 160 for connecting a capacitor structure;

[0077] S600, referring to FIGS. 14-15, a second insulating layer 154 is formed, and the etched first initial insulating layer 153 and the second insulating layer 154 form the first insulating layer 151, and the initial recess 166 filled by the first insulating layer 151 is defined as the first recess 167.

[0078] Referring to FIG. 12 or FIG. 16, in one embodiment, the exposed height of the diffusion barrier material layer 164 on the sidewall of the initial recess 166 in the third direction is 1 / 2-7 / 8 of the height of the metal material layer 165 in the third direction. The ratio cannot be too small, and too small will still cause etching of the diffusion barrier layer 162 when etching the capacitor hole, thereby causing the risk of contamination of the etching chamber. The ratio cannot be too large, and too large will increase the load of the etching process and increase the cost of the etching process.

[0079] Referring to FIG. 8, in one embodiment, the bottom surface of the initial recess 166 is a non-planar or non-flat surface; and the area of the orthogonal projection of the initial recess 166 on the substrate 110 is greater than the area of the orthogonal projection of the top surface of the active pillar 120 on the substrate 110. The bottom surface of the initial recess 166 is a non-planar or non-flat surface, so that the contact surface between the metal silicide layer 161 and the active pillar 120 is a non-planar or non-flat surface, that is, the contact surface between the metal silicide layer 161 and the active pillar 120 can be a curved surface. By such arrangement, the contact area between the metal silicide layer 161 and the active pillar 120 can be increased, thereby reducing the contact resistance between the metal silicide layer 161 and the active pillar 120 and improving the transmission efficiency of the vertical transistor. The area of the orthogonal projection of the initial recess 166 on the substrate 110 is greater than the area of the orthogonal projection of the top surface of the active pillar 120 on the substrate 110. The top surface of the active pillar 120 is the surface exposed by the initial recess 166. By such arrangement, the top surface of the active pillar 120 can be completely exposed by the initial recess 166, thereby increasing the contact area between the active pillar 120 and the initial recess 166 and reducing the contact resistance and improving the transmission efficiency of the vertical transistor.

[0080] In one embodiment, etching the first initial insulating layer 153 to expose the diffusion barrier material layer 164 on the sidewall of the initial recess 166 includes: the etching selectivity of the first initial insulating layer 153 and the diffusion barrier material layer 164 is greater than or equal to 5, and the etching selectivity of the first initial insulating layer 153 and the metal material layer 165 is greater than or equal to 6; etching the diffusion barrier material layer 164 includes: the etching selectivity of the diffusion barrier material layer 164 and the first initial insulating layer 153 is greater than or equal to 6, and the etching selectivity of the diffusion barrier material layer 164 and the metal material layer 165 is greater than or equal to 6. Wet etching is used when etching the first initial insulating layer 153 and etching the diffusion barrier material layer 164, and wet etching generally has a better etching selectivity than dry etching (such as reactive ion etching or plasma etching), so that the etching depth can be more accurately controlled by selecting the etching selectivity and controlling the etching time.

[0081] Referring to FIGS. 9-11, in one embodiment, the metal silicide layer 161, the diffusion barrier material layer 164, and the metal material layer 165 are sequentially formed in the initial recess 166, including: forming the metal silicide layer 161 on the bottom of the initial recess 166; continuing to deposit the diffusion barrier material layer 164, which covers the sidewall of the initial recess 166 and the top surface of the metal silicide layer 161; depositing the metal material layer 165, which covers the diffusion barrier material layer 164 and the first initial insulating layer 153; and performing a planarization process to expose the first initial insulating layer 153.

[0082] Referring to FIGS. 14-15, in one embodiment, the second insulating layer 154 is formed, and the first initial insulating layer 153 and the second insulating layer 154 after etching form the first insulating layer 151, including: depositing the second insulating layer 154 to cover the metal layer 163 and the first initial insulating layer 153; and planarizing the second insulating layer 154 to expose the metal layer 163. The material of the second insulating layer 154 can be one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, or silicon carbonitride. In this embodiment, the material of the second insulating layer 154 is the same as that of the first initial insulating layer 153, i.e., both are silicon nitride. At the same time, the second insulating layer above the metal layer needs to be removed, i.e., a chemical mechanical polishing process is used to remove the second insulating layer, to make room for the subsequent deposition of the support layer of the capacitor structure.

[0083] By the preparation method, the metal silicide layer 161, the diffusion barrier layer 162 and the metal layer 163 can be sequentially stacked, the contact resistance between the active pillar of the vertical transistor and the capacitor structure can be effectively reduced, and the transmission rate of the vertical transistor is improved. Meanwhile, by etching to remove part or all of the diffusion barrier material layer on the sidewall of the initial groove, the top surface of the diffusion barrier material layer 164 is lower than the top surface of the initial groove 166, the problem of titanium pollution of the etching chamber in the process of etching the capacitor hole can be avoided, and the precision of etching the capacitor hole is improved.

[0084] In the description of the disclosure, it should be understood that the orientations or positional relationships indicated by the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer" and the like are based on the orientations or positional relationships shown in the drawings, and are only for the convenience of describing the disclosure, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the disclosure.

[0085] In the description of the disclosure, it should be understood that the terms "include" and "have" and any variations thereof used herein are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device including a series of steps or units need not be limited to those clearly listed, but can include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0086] Unless otherwise explicitly specified and limited, the terms "mount", "connect", "connect", "fix" and the like should be understood in a broad sense, for example, it can be fixed connection, or detachable connection, or become an integral part; it can be directly connected, or indirectly connected through an intermediate medium, it can be connected inside two elements or the interaction relationship between two elements. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific situation. In addition, the terms "first", "second" and the like are only for the purpose of description, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the technical features indicated.

[0087] Finally, it should be pointed out that: the above embodiments are only used to illustrate the technical solutions of the present disclosure, and not to limit them; although the present disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement for part or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A semiconductor structure (100), include: A substrate (110) is provided with a plurality of active pillars (120) arranged at intervals along a first direction and a second direction, the active pillars (120) extending along a third direction; a first groove (167) is provided in the substrate (110) to expose the top surface of the active pillars (120), the first groove (167) being arranged at intervals along the first direction and the second direction; and a first insulating layer (151) is provided in the substrate (110) to isolate the first groove (167); the first direction and the second direction intersect and are both perpendicular to the third direction; A capacitor contact structure (160) is located in the first groove (167) and covers the top surface of the active post (120) for connecting the capacitor structure (170). The capacitor contact structure (160) includes a metal silicide layer (161), a diffusion barrier layer (162), and a metal layer (163) sequentially disposed in the extension direction of the active post (120). The metal silicide layer (161) is in contact with the active post (161), and the top surface of the diffusion barrier layer (162) is lower than the top surface of the first groove (167).

2. The semiconductor structure according to claim 1, wherein, The diffusion barrier layer (162) is also disposed on the sidewall of the first groove (167), and the height of the diffusion barrier layer (162) on the sidewall of the first groove (167) in the third direction is less than the height of the metal layer (163) in the third direction.

3. The semiconductor structure according to claim 2, wherein, The height of the diffusion barrier layer (162) on the sidewall of the first groove (167) in the third direction is 1 / 8 to 1 / 2 of the height of the metal layer (163) in the third direction.

4. The semiconductor structure according to claim 1, wherein, The top surface of the metal layer (163) has a smaller projected area on the substrate (110) than the bottom surface of the metal layer (163) has a smaller projected area on the substrate (110).

5. The semiconductor structure according to claim 4, wherein, The metal layer (163) has a rounded corner structure.

6. The semiconductor structure according to claim 1, wherein, The centerline of the active pillar (120) basically overlaps with the centerline of the capacitor contact structure (160), and the contact surface between the metal silicide layer (161) and the active pillar (120) is a non-planar or non-flat surface.

7. The semiconductor structure according to claim 1, wherein, The projected area of ​​the first groove (167) on the substrate (110) is greater than the projected area of ​​the top surface of the active pillar (120) on the substrate (110).

8. The semiconductor structure according to claim 1, wherein, An active pillar (120) is provided with an active electrode structure, a vertical channel and a drain structure in sequence along the third direction, and the source structure is located at the top of the active pillar (120); a gate structure (130) is also provided in the substrate (110), the gate structure (130) surrounds the vertical channel of the active pillar (120), adjacent gate structures (130) along the second direction are in contact with each other, and adjacent gate structures (130) along the first direction are insulated from each other; a bit line structure (140) is also provided in the substrate, the bit line structure (140) is located on the side of the substrate (110) away from the extension direction of the active pillar (120), the bit line structure (140) extends along the first direction, and adjacent bit line structures (140) along the second direction are insulated from each other.

9. A semiconductor device (300), wherein, The semiconductor device is obtained by bonding a semiconductor structure (100) as described in any one of claims 1-8 to a first wafer (200), the first wafer (200) having a CMOS transistor of the semiconductor device.

10. A method for fabricating a semiconductor structure, wherein, The preparation method includes: A substrate (110) is provided, and a plurality of initial active pillars (121) are formed in the substrate (110) at intervals along a first direction and a second direction, the plurality of initial active pillars (121) extending along a third direction; a first initial insulating layer (153) is formed in the substrate (110) to isolate the initial active pillars (121); the first direction intersects the second direction and is perpendicular to the third direction; The initial active post (121) is etched to form an initial groove (166), the initial groove (166) being spaced apart along a first direction and a second direction, the initial groove (166) being etched by the first active post (121). An initial insulating layer (153) provides isolation; the etched initial active pillar is then the active pillar (120); A metal silicide layer (161), a diffusion barrier material layer (164), and a metal material layer (165) are sequentially formed in the initial groove (166); the diffusion barrier material layer (164) is also formed on the sidewall of the initial groove (166); The first initial insulating layer (153) is etched to expose the diffusion barrier material layer (164) on the sidewall of the initial groove (166); The diffusion barrier material layer (164) is etched so that the top surface of the diffusion barrier material layer (164) is lower than the top surface of the initial groove (166); the etched diffusion barrier material layer is the diffusion barrier layer (0162); the etched metal material layer is the metal layer (163); the metal silicide layer (161), the diffusion barrier layer (162), and the metal layer (163) constitute a capacitor contact structure (160) for connecting a capacitor structure; A second insulating layer (154) is formed. The first initial insulating layer and the second insulating layer after etching constitute the first insulating layer (151). The initial groove after the first insulating layer is filled is defined as the first groove (167).

11. The preparation method according to claim 10, wherein, The exposure height of the diffusion barrier material layer (164) on the sidewall of the initial groove (166) in the third direction is 1 / 2 to 7 / 8 of the height of the metal material layer (165) in the third direction.

12. The preparation method according to claim 10, wherein, The bottom surface of the initial groove (166) is a non-planar or non-flat surface; the orthographic projection area of ​​the initial groove (166) on the substrate (110) is greater than the orthographic projection area of ​​the top surface of the active pillar (120) on the substrate (110).

13. The preparation method according to claim 10, wherein, The etching of the first initial insulating layer (153) to expose the diffusion barrier material layer (164) on the sidewall of the initial groove (166) includes: the etching selectivity ratio of the first initial insulating layer (153) and the diffusion barrier material layer (164) is greater than or equal to 5, and the etching selectivity ratio of the first initial insulating layer (153) and the metal material layer (165) is greater than or equal to 6. The etching of the diffusion barrier material layer (164) includes: the diffusion barrier material layer The etching selectivity ratio of (164) and the first initial insulating layer (153) is greater than or equal to 6, and the etching selectivity ratio of the diffusion barrier material layer (164) and the metal material layer (165) is greater than or equal to 6.

14. The preparation method according to claim 10, wherein, The step of sequentially forming a metal silicide layer (161), a diffusion barrier material layer (164), and a metal material layer (165) within the initial groove (166) includes: forming a metal silicide layer (161) at the bottom of the initial groove (166); continuing to deposit the diffusion barrier material layer (164), which covers the sidewalls of the initial groove (166) and the top surface of the metal silicide layer (161); depositing the metal material layer (165), which covers the diffusion barrier material layer (164) and the first initial insulating layer (153); and performing planarization to expose the first initial insulating layer (153).

15. The preparation method according to claim 10, wherein, The formation of the second insulating layer (154), wherein the etched first initial insulating layer and the second insulating layer constitute the first insulating layer (151), includes: depositing the second insulating layer (154) to cover the metal layer (163) and the first initial insulating layer (153); and planarizing the second insulating layer (154) to expose the metal layer (163).

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