Exception handling method and apparatus, and computing device

Abstract

The present application relates to the technical field of computers. Disclosed are an exception handling method and apparatus, and a computing device. The method is applied to a processor, wherein the processor communicates with a first device, and the first device is a peripheral device of the processor. The method comprises: a processor acquiring first information, wherein the first information includes a status code, and the status code is used for representing whether an exception occurs in the process of a first device executing a first instruction issued by the processor, and / or representing the type of exception that occurred; if the status code indicates that an exception has occurred, the processor executing, on the basis of an exception handling program, exception handling corresponding to an exception type represented by the status code, wherein the exception handling program runs on the processor. A processor can directly execute, on the basis of an exception handling program, exception handling corresponding to an exception type represented by a status code, without needing to acquire, from a first device, specific information concerning an exception, thereby reducing the overhead of exception handling, and significantly improving the efficiency of exception handling.

Description

An exception processing method, device and computing device

[0001] The present application claims priority from the Chinese patent application No. 202410792658.4 filed on June 18, 2024, and entitled "An exception processing method, device and computing device", the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0002] The present application relates to the technical field of computer, and in particular to an exception processing method, device and computing device. BACKGROUND

[0003] Currently, when an application in a computer sends a read data or write data instruction to a memory or an external device through a central processing unit (CPU), if an exception occurs in the corresponding device and the device cannot correctly return data or even cannot return data, the application may lose response or even the entire operating system crashes. When the application processes the exception of the device, the specific fault information of the device needs to be obtained first, and then the type of the exception of the device is determined according to the fault information, and finally the corresponding exception processing is made. This exception processing method has a large overhead and is inefficient. SUMMARY

[0004] The present application provides an exception processing method, device and computing device, which simplifies the process of determining the type of the exception of the device and improves the efficiency of exception processing.

[0005] In a first aspect, an exception processing method is provided. The exception processing method is applied to a processor, the processor communicates with a first device, and the first device is a peripheral device of the processor. The method comprises: obtaining first information, the first information comprising a status code, the status code being used to represent whether an exception occurs in a process of executing a first instruction issued by the processor by the first device and / or a type of the exception; and if the status code indicates that the exception occurs, executing an exception processing corresponding to the type of the exception represented by the status code according to an exception processing program. The exception processing program runs on the processor.

[0006] It can be understood that, through the status code in the first information, the processor can accurately determine whether an exception occurs in a process of executing the first instruction issued by the processor by the first device, and in the case where it is determined that the exception occurs, execute an exception processing corresponding to the type of the exception represented by the status code according to the exception processing program, without the need to obtain specific information about the exception from the first device, thereby simplifying the process of exception processing and improving the efficiency of exception processing.

[0007] In a possible implementation, if the state code indicates that an exception occurs, the exception handling corresponding to the type of exception represented by the state code is performed according to the exception handling program, including: if the state code indicates that an exception occurs, writing the state code into a first register, the first register being a register in the processor; determining, according to the exception handling program, the exception handling corresponding to the type of exception represented by the state code in the first register; and performing the exception handling.

[0008] It can be understood that, because the reading and writing speed of the register in the processor is very fast, the state code is written into the first register in the processor, and the exception handling program running on the processor can directly obtain the state code from the first register, avoiding the process of obtaining specific information about the exception from the first device when the processor runs the exception handling program after the failure occurs, and the data in the register is stable and cannot be easily overwritten by other data, thereby improving the efficiency and reliability of the exception handling.

[0009] In a possible implementation, the processor obtains the first information, including: if the interrupt signal is received, determining address information corresponding to the interrupt signal; and obtaining the first information from the storage device corresponding to the address information.

[0010] It can be understood that the processor obtains the first information through the interrupt signal, which can ensure that the exception handling transaction has a high priority, and the processor obtains the first information from the storage device corresponding to the interrupt signal, which can ensure that the first information containing the state code is successfully obtained by the processor, thereby improving the reliability of the exception handling.

[0011] In a possible implementation, if the state code indicates that an exception occurs, the exception handling corresponding to the type of exception represented by the state code is performed according to the exception handling program, including: if the state code indicates that an exception occurs, determining, according to the first corresponding information, a first exception handling program corresponding to the state code; the first corresponding information including at least one state code and an exception handling program corresponding to the state code; and performing the exception handling corresponding to the type of exception represented by the state code according to the first exception handling program.

[0012] It can be understood that the first corresponding information can include a plurality of state codes and a plurality of exception handling programs corresponding to the state codes, respectively. The processor can accurately determine the exception handling program corresponding to the obtained state code according to such corresponding information, thereby improving the reliability of the exception handling.

[0013] In a possible implementation, the exception handling is determined by the exception handling program according to the state code and second corresponding information, and the second corresponding information includes a plurality of state codes and a plurality of exception handling programs corresponding to the state codes, respectively.

[0014] It can be understood that a plurality of preset state codes and respective abnormal processing corresponding to each state code can be included in the second corresponding information, and the abnormal processing program running on the processor can accurately determine the abnormal processing corresponding to the state code according to the corresponding information, so that the abnormal processing is more targeted, and the effect of the abnormal processing is improved.

[0015] In a possible implementation, if the state code indicates that an abnormality occurs, performing abnormal processing corresponding to the type of the abnormality represented by the state code according to the abnormal processing program includes: if the state code indicates that an abnormality occurs, and the abnormality is a synchronous abnormality, performing abnormal processing corresponding to the type of the abnormality represented by the state code according to the abnormal processing program.

[0016] It can be understood that, since the synchronous abnormality can cause the application to lose response or even system crash, performing abnormal processing on such an abnormality can improve the stability of the system, and meanwhile, other abnormalities (such as asynchronous abnormalities) can be processed by other ways, thereby improving the flexibility of the processor abnormal processing.

[0017] In a second aspect, an embodiment of the present application provides an abnormal processing method, which is applied to a first device, the first device communicates with a processor, the first device is a peripheral device of the processor, and the method includes: generating second information, the second information containing a state code, the state code being used to represent whether an abnormality occurs in a process in which the processor executes a first instruction issued by the processor and / or a type of the abnormality; sending the second information to the processor; the processor being used to determine whether the state code indicates that an abnormality occurs according to acquired first information, and being used to perform abnormal processing corresponding to the type of the abnormality represented by the state code according to an abnormal processing program if the state code indicates that an abnormality occurs; and the first information containing the state code in the second information.

[0018] It can be understood that, by generating the second information containing the state code and sending the second information to the processor, the first device can actively report without waiting for a response to an abnormal information acquisition request issued by the processor in the case of an abnormality, thereby simplifying the abnormal processing procedure and improving the efficiency of the abnormal processing.

[0019] In a possible implementation, the first device includes a switch device and a node device, the node device communicates with the processor through the switch device; and the generating of the second information includes: if the switch device does not receive the second information generated by the node device within a time threshold interval, the switch device generates the second information.

[0020] It can be understood that, due to the abnormality such as the node device being dead, the second information cannot be generated, and if the time threshold interval is exceeded, the second information is generated by the switch device upstream of the node device, further improving the reliability of the abnormality processing.

[0021] In a possible implementation, the second information is generated by: if an abnormality occurs in the process in which the first device executes the first instruction issued by the processor, determining a state code according to the device state information and third corresponding information; the third corresponding information contains a plurality of device state information and a state code corresponding to each of the plurality of device state information; and generating the second information containing the state code corresponding to the device state information.

[0022] It can be understood that, due to the third corresponding information containing a plurality of device state information and a state code corresponding to each of the plurality of device state information, the first device can accurately determine the state code that should be contained in the generated second information according to the corresponding information, so that the processor executes the abnormality processing corresponding to the state code according to the abnormality processing program, improving the efficiency of the abnormality processing and improving the effect of the abnormality processing.

[0023] In a third aspect, an embodiment of the present application provides an abnormality processing apparatus, which includes a module for executing the method in the first aspect or any of the implementation manners of the first aspect.

[0024] For example, the abnormality processing apparatus includes an acquisition module and an execution module, the acquisition module is configured to acquire first information, the first information contains a state code, the state code is used to represent whether an abnormality occurs in the process in which the first device executes the first instruction issued by the processor and / or the type of the abnormality; and the execution module is configured to execute the abnormality processing corresponding to the type of the abnormality represented by the state code according to an abnormality processing program if the state code indicates that the abnormality occurs; the abnormality processing program runs on the processor.

[0025] In a fourth aspect, an embodiment of the present application provides an abnormality processing apparatus, which includes a module for executing the method in the second aspect or any of the implementation manners of the second aspect.

[0026] For example, the abnormality processing apparatus includes a generation module and a sending module, the generation module is configured to generate second information, the second information contains a state code, the state code is used to represent whether an abnormality occurs in the process in which the processor executes the first instruction issued by the processor and / or the type of the abnormality; and the sending module is configured to send the second information to the processor; the processor is configured to determine whether the state code indicates that the abnormality occurs according to the acquired first information, and execute the abnormality processing corresponding to the type of the abnormality represented by the state code according to an abnormality processing program if the state code indicates that the abnormality occurs; the first information contains the state code in the second information.

[0027] In a fifth aspect, the present application provides a computing device, comprising a processor and a memory, the processor being coupled to the memory; the memory is configured to store computer instructions, the computer instructions being loaded and executed by the processor to enable the computing device to implement the exception processing method according to the above aspect.

[0028] In a sixth aspect, the present application provides a computer readable storage medium, the computer readable storage medium storing at least one computer program instruction, the computer program instruction being loaded and executed by a processor to implement the exception processing method according to the above aspect.

[0029] In a seventh aspect, the present application provides a computer program product, the computer program product comprising computer instructions stored in a computer readable storage medium. A processor of a computing device reads the computer instructions from the computer readable storage medium, and the processor executes the computer instructions to enable the computing device to perform the model appearance updating method provided in the various optional implementation manners of the first aspect.

[0030] The beneficial effects of the above third aspect to seventh aspect can refer to the description of any one of the implementation manners of the first aspect or the second aspect, which will not be repeated here. On the basis of the implementation manners of the above aspects, the present application can be further combined to provide more implementation manners. BRIEF DESCRIPTION OF DRAWINGS

[0031] FIG. 1 is a schematic diagram of data transmission of a PCIe system in the related art according to an embodiment of the present application;

[0032] FIG. 2 is a schematic diagram of a computing device according to an embodiment of the present application;

[0033] FIG. 3 is a schematic diagram of another computing device according to an embodiment of the present application;

[0034] FIG. 4 is a flowchart of an exception processing method according to an embodiment of the present application;

[0035] FIG. 5 is a schematic diagram of an architecture of a PCIe system according to an embodiment of the present application;

[0036] FIG. 6 is a flowchart of an exception processing method according to an embodiment of the present application;

[0037] FIG. 7 is a schematic diagram of an architecture of a CXL system according to an embodiment of the present application;

[0038] FIG. 8 is a flowchart of an exception processing method according to an embodiment of the present application;

[0039] FIG. 9 is a schematic diagram of an exception processing apparatus according to an embodiment of the present application;

[0040] FIG. 10 is a structural schematic diagram of another abnormality processing device according to an example embodiment of the present application. DETAILED DESCRIPTION

[0041] In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the embodiments of the present application will be further described in detail below with reference to the drawings.

[0042] In the present disclosure, “a plurality of” means two or more. “And / or” describes the association relationship of the associated objects, which means that there can be three relationships, for example, A and / or B can mean that there are three cases of A alone, A and B together, and B alone. The character “ / ” generally represents that the associated objects before and after it are in an “or” relationship.

[0043] In addition, in the description of the embodiments of the present application, unless otherwise specified, “a plurality of” means two or more. “At least one of the following” or the like means any combination of the items, including any combination of single item or multiple items. For example, at least one of a, b, or c can mean a, b, c, a-b, a-c, b-c, or a-b-c, where a, b, and c can be single or multiple.

[0044] In addition, in order to facilitate the clear description of the technical solutions of the embodiments of the present application, in the embodiments of the present application, the same items or similar items with basically the same functions and effects are distinguished by using “first”, “second”, etc. The skilled in the art can understand that “first”, “second”, etc. do not limit the quantity and execution order, and “first”, “second”, etc. also do not necessarily mean different. At the same time, in the embodiments of the present application, “exemplary” or “for example” is used to indicate as an example, illustration or description. Any embodiment or design scheme described as “exemplary” or “for example” in the embodiments of the present application should not be interpreted as more preferred or more advantageous than other embodiments or design schemes. Rather, the use of “exemplary” or “for example” is intended to present the relevant concept in a specific manner, and to facilitate understanding.

[0045] First, the application scenarios of the embodiments of the present application are exemplarily introduced.

[0046] A program running in a computing device initiates data access to a memory or an external device (collectively referred to as a peripheral device in embodiments of the present application) by issuing instructions to a processor, such as a central processing unit (CPU). There are two different types of data access forms, where the first access form is that when the processor accesses a peripheral device (such as issuing a data write request to a memory), the processor does not need to wait for the response data returned by the peripheral device, and then the processor can directly continue to execute the next instruction, such as the posted access form in the PCIe protocol. The second access form is that when the processor accesses a peripheral device (such as issuing a data read request to a memory), the processor needs to wait for the response data returned by the peripheral device, and the processor will continue to execute the next instruction only after receiving the response data, such as the non-posted access form in the PCIe protocol. In the second access form, if the processor does not receive the response data for a long time, it will cause the program in the system to lose response or even cause the operating system to crash, which can be referred to as a synchronization exception problem.

[0047] In related technologies, there are some solving mechanisms that can avoid the problems caused by the processor waiting for the response data for a long time.

[0048] For example, in the peripheral component interconnect express (PCIe) protocol, there is a completion timeout mechanism, and in the compute express link (CXL) protocol, there is a transaction timeout mechanism. These two mechanisms can replace the corresponding peripheral device with other components, such as a root complex (RC), to reply the response data to the processor when the processor accesses the peripheral device through the non-posted type of access form and does not receive the corresponding response data within a period of time, thereby ensuring that the processor can continue to run down. In some protocols, there is a set field in the response data to indicate that the response data is illegal data and cannot be consumed.

[0049] It can be understood that the root cause of the above-mentioned synchronization exception problem is that the peripheral device has an exception, or the communication link between the processor and the peripheral device has an exception, eventually causing the processor to be unable to receive the reply data of the peripheral device, or only receiving the data replied by other components to indicate the exception. The above-mentioned solution mechanism does not completely solve the synchronization exception problem, and the corresponding peripheral device may be in an abnormal state and has not recovered to a normal state, in which case the processor needs to further solve the synchronization exception caused by the failure of the peripheral device, for example, by calling an exception handling program, issuing a reset signal to the peripheral device to attempt to restore the peripheral device to a normal state, but if the processor does not immediately handle the exception, but continues to run down, it may cause the data related to the exception to be overwritten, making it more difficult to recover the failure of the peripheral device.

[0050] In the related art, the flow of the processor solving the above-mentioned exception is that the processor calls an exception handling program, then obtains specific information about the exception from the failed peripheral device, then judges the type of the exception of the device according to the logic in the exception handling program, and then makes corresponding exception handling. This exception handling method has large overhead and low efficiency.

[0051] For example, as shown in FIG. 1, FIG. 1 is a data transmission schematic diagram of a PCIe system, in which the processor communicates with each switch and endpoint through an interface module (such as a root complex). If the endpoint 3 has an exception when executing the instruction issued by the processor, in the related art, the processor needs to first call a set exception handling program, send a data acquisition request for obtaining specific information about the exception to the interface module, and then the interface module sends it to the switch 1, the switch 1 forwards it to the switch 2, and finally the switch 2 forwards it to the endpoint 3. After that, the endpoint 3 sends corresponding reply data, which will pass through the switches 1-2 and the interface module again, and finally reach the processor. This process takes a long time, and if the exception handling program needs the processor to run in a user program in a user state, the above-mentioned process may also need the processor to switch from the user state to the kernel state first, because usually only the processor in the kernel state can acquire data from the peripheral device by running the driver program. Such switching operation will further increase the overhead of exception handling and reduce the efficiency.

[0052] Therefore, an exception handling method is provided in the embodiments of the present application, which sets a status code capable of indicating the type of the exception of the peripheral device in the reply data, so that the processor can directly execute corresponding exception handling according to the status code, thereby improving the efficiency of exception handling.

[0053] In some possible embodiments, the method is applied to a processor, the processor is in communication with a first device, the first device is a peripheral device of the processor, and the method comprises the following steps: first, the processor acquires first information, the first information comprises a status code, the status code is used to represent whether an exception occurs in a process in which the first device executes a first instruction issued by the processor and / or a type of the exception; and if the status code indicates that the exception occurs, the processor executes an exception handling corresponding to the type of the exception represented by the status code according to an exception handling program. The exception handling program runs on the processor. In this way, since the processor can directly make corresponding exception handling according to the indication of the status code in the first information, without obtaining specific information about the exception from the first device, the cost of exception handling is reduced, and the efficiency of exception handling is significantly improved.

[0054] Secondly, the system architecture of the embodiment of the present application is exemplarily introduced.

[0055] As shown in FIG. 2, FIG. 2 is a schematic diagram of a computing device provided by an exemplary embodiment of the present application. In FIG. 2, the computing device 100 comprises a processor 101, a memory 102 and a first device 103, the computing device 100 is used to run the exception handling method in the embodiment of the present application, and the first device 103 is a peripheral device of the processor 101.

[0056] Specifically, when the computing device 100 in FIG. 2 runs the exception handling method in the embodiment of the present application, the processor can be the processor 101, and at least one exception handling program can run on the processor 101, and the memory 102 in FIG. 2 is used to store the logic code of the exception handling program. It should be noted that, in the embodiment of the present application, the exception handling program at least comprises a driver program and a user program.

[0057] Optionally, the processor 101 in FIG. 2 can be a central processing unit (CPU), other general-purpose processor, a digital signal processing (DSP) chip, a field programmable gate array (FPGA) chip, etc.

[0058] Optionally, the memory 102 in FIG. 2 can be a read-only memory (ROM), a random access memory (RAM).

[0059] Optionally, the processor 101 in FIG. 2 can further comprise a storage module, for example, a register, and in some possible embodiments, the register is used to store the status code in the first information acquired by the processor 101 and support reading by the exception handling program.

[0060] For example, the processor can be a central processing unit (CPU). The memory 102 in FIG. 2 can be a solid state disk (SSD) for storing the logic code of the exception handling program.

[0061] Optionally, the processor 101 in FIG. 2 can further include an interface module, for example, a root complex, and the processor 101 in FIG. 2 communicates with the first device through the interface module.

[0062] In software, the processor 101 can run an operating system (OS) and / or other programs. At least one of the foregoing programs can be used to obtain and / or process the first information, and can also be used to run the exception handling program and / or execute the exception handling corresponding to the exception type represented by the status code.

[0063] As shown in FIG. 3, FIG. 3 is a schematic diagram of another computing device provided by an exemplary embodiment of the present application. In FIG. 3, the computing device 200 includes a processor 201 and a memory 202. The computing device 200 is configured to run the exception handling method in the embodiments of the present application.

[0064] Specifically, when the computing device 200 in FIG. 3 runs the exception handling method in the embodiments of the present application, the processor can be the processor 201, and the processor 201 can run at least one exception handling program. The memory 202 in FIG. 3 is configured to store the logic code of the exception handling program. It should be noted that, in the embodiments of the present application, the exception handling program at least includes a driver program and a user program.

[0065] Optionally, the processor 201 in FIG. 3 can be a central processing unit (CPU), other general-purpose processor, DSP chip, FPGA chip, etc.

[0066] Optionally, the memory 202 in FIG. 3 can be a read-only memory (ROM) or a random access memory (RAM).

[0067] Optionally, the processor 201 in FIG. 3 can further include a storage module, for example, a register. In some possible embodiments, the register is configured to store the status code in the first information obtained by the processor 201, and support the exception handling program to read.

[0068] Optionally, the computing device 200 in FIG. 3 can further include an interface module, for example, a root complex, and the processor 201 in FIG. 3 can communicate with the first device through the interface module.

[0069] On the software, an operating system (OS) and / or other programs can be run on the processor 201, at least one of the foregoing programs can be used to obtain and process the first information, can also be used to run an exception handling program, and / or to execute an exception handling corresponding to the exception type represented by the status code.

[0070] It should be noted that in the following embodiments, the processor is taken as an example of CPU, in other words, the processor described in the following embodiments performs a certain step (such as S140 to S150 below) can be understood as: the CPU performs the step.

[0071] Moreover, the system architecture and application scenarios described in the embodiments of the present application are used to more clearly illustrate the technical solutions of the embodiments of the present application, and do not constitute a limitation on the technical solutions provided by the embodiments of the present application. Those skilled in the art can know that, with the evolution of system architecture and the appearance of new business scenarios, the technical solutions provided by the embodiments of the present application are also applicable to similar technical problems.

[0072] For ease of understanding, the following exemplary introduces the exception handling method provided by the present application, which is applicable to the computing device shown in FIG. 2 and the computing device shown in FIG. 3.

[0073] FIG. 4 shows a flowchart of an exception handling method provided by an exemplary embodiment of the present application. The exception handling method includes the following steps:

[0074] S110, the processor issues a first instruction to the first device.

[0075] In this step, the first instruction can be generated by a driver or a user program running on the processor according to its own business logic, and is issued to the corresponding first device through the processor, thereby completing the corresponding business. The first instruction can be an instruction that requires the first device to return corresponding data, such as a data read instruction in the non-posted type instruction of the PCIe protocol.

[0076] In the embodiments of the present application, the first device is a peripheral device of the processor, specifically, the first device includes but is not limited to a PCIe device connected to the processor, such as a PCIe graphics card, a PCIe network card, a PCIe sound card, a PCIe switch, a CXL storage device connected to the processor, a CXL memory expansion device, etc.

[0077] S120, the first device executes the first instruction and generates second information.

[0078] In this step, the first device executes the first instruction issued by the processor, and determines whether an exception occurs and / or the type of the exception during the execution, and generates second information containing a corresponding status code.

[0079] For example, the first instruction instructs the first device to write target data to a specified storage location, but the first device fails to write the target data because the specified storage location does not exist in the storage unit of the first device or the specified storage location is out of the range of the storage unit of the first device. In this case, the first device determines that the status code is "0x21" according to the device state information and the third corresponding information that the writing of the target data fails and / or the specified storage location is out of range, and generates second information containing "0x21".

[0080] In the embodiments of the present application, the meanings of the status codes can be set by the user, for example, "0x00" is defined as no exception, "0x10" is defined as the first device needs to be reset, and the like.

[0081] In some possible embodiments, if the status code is applied to the message format of a certain existing protocol, for example, the status code is used as a new field in the completion message in PCIe, since there can be information in the message of the protocol indicating that no exception occurs in the process of the first device executing the first instruction, in order to avoid the occurrence of repeated information in the first information and improve the proportion of effective information carried by the first information, the user can define the status code only to represent the type of the exception occurring in the process of the first device executing the first instruction, for example, the status code "0x10" is set to the first device needing to be reset, the status code "0x20" is defined as the memory region not existing, and the like.

[0082] In a possible implementation, the first device can obtain third corresponding information containing a plurality of device state information and a plurality of status codes corresponding to the device state information respectively, for example, the device state information can be that the memory is damaged, resulting in the inability to read the target data specified by the first instruction. The third corresponding information can be stored in the storage module (such as the memory) of the first device or other positions readable by the first device, and the present application does not limit this.

[0083] Further, when the first device executes the above step S120, the first device can first determine that an exception occurs in the process of executing the first instruction issued by the processor, and then determine the status code according to the device state information and the third corresponding information; and then generate second information containing the status code corresponding to the device state information.

[0084] In some possible embodiments, the first device comprises a switch device and a node device, wherein the node device communicates with the processor through the switch device, for example, in some PCIe systems, multiple PCIe network cards communicate with the processor through a PCIe switch, in such a connection topology, if the node device has a more serious abnormality such as loss of response or power failure, the node device cannot generate the second information, and cannot send the second information.

[0085] In view of the above and to further improve the reliability of abnormality processing, in the embodiments of the present application, a time threshold interval can be set, and if the switch device does not receive the second information generated by the node device within the time threshold interval, the switch device generates the second information. The switch device can monitor the device state of the node device connected thereto during normal operation, and accurately determine the state code corresponding to the device state of the node device when the node device cannot send the second information in time, to generate the second information containing the state code instead of the node device.

[0086] Through step S120, if the first device has an abnormality during execution of the first instruction issued by the processor, the specific information about the abnormality is concentrated in the state code, and the state code is contained in the second information generated by the first device, which changes the passive waiting of the first device in the related art to obtain the specific information about the abnormality by the processor, and simplifies the subsequent abnormality processing procedure and improves the efficiency of abnormality processing by actively generating the second information containing the state code.

[0087] S130, the first device sends the second information to the processor.

[0088] In this step, the second information is sent by the first device and finally acquired by the processor, and in the transmission process of the second information, other devices can also be used for forwarding. For example, in some CXL systems, the second information is sent by the CXL storage device, and the information can be forwarded through the CXL switch and finally sent to the processor. The specific transmission process of the second information can be different due to different actual connection topologies, which is not limited in the present application.

[0089] Through execution of the above step S130, since the second information sent by the first device to the processor contains the state code, the processor does not need to acquire other specific information about the abnormality from the first device when performing subsequent abnormality processing, which can simplify the abnormality processing procedure and improve the efficiency of abnormality processing.

[0090] S140, the processor acquires the first information.

[0091] In this step, the processor can actively acquire the first information or passively receive the first information, and the application does not limit this.

[0092] In some possible embodiments, the first information and the second information can be the same in data format. In other possible embodiments, the first information and the second information can be different in data format, or the first information can be generated according to the second information, for example, the second information sent by the first device is a completion message under the PCIe protocol, but the CPU cannot directly parse the message, and the second information is format-converted by other components, for example, the completion message is converted from the PCIe protocol to the CHI (coherent hub interface) protocol.

[0093] It should be noted that, in this step, the first information acquired by the processor needs to contain the status code in the second information sent by the first device in step S130. Since the status code represents whether an exception occurs and / or the type of the exception in the process of executing the first instruction issued by the processor in step S110, the subsequent processor can process the exception reported by the first device, and the reliability of the exception processing is improved.

[0094] In step S150, if the status code indicates that an exception occurs, the processor executes the exception processing corresponding to the type of the exception represented by the status code according to the exception processing program.

[0095] In this step, the processor can determine whether the status code indicates that an exception occurs according to the first corresponding information, and specific descriptions are given below, which are not repeated here. The processor executes the exception processing corresponding to the type of the exception represented by the status code according to the exception processing program, which can be understood as that the CPU calls the exception processing program or the CPU jumps to the first address of the exception processing program, and then the logic code in the exception processing program is executed by the processor, so that the processor can execute the exception processing corresponding to the type of the exception represented by the status code according to the logic in the exception processing program.

[0096] In the process that the processor executes the exception processing corresponding to the type of the exception represented by the status code according to the exception processing program, in order to ensure that the status code can be acquired by the exception processing program in the subsequent process, the processor can first write the status code into a specified memory. In the embodiment of the application, the processor writes the status code into a register (a first register) in the processor. Compared with other memories such as a memory or a hard disk that can exist in a computing device, the register in the processor has a faster read-write speed, so that writing the status code into the register in the processor can improve the efficiency of the exception processing.

[0097] In the embodiments of the present application, the number of abnormality processing programs can be in the following two cases:

[0098] In the first case, there is only one abnormality processing program, in which case the logic in the abnormality processing program can parse one or more status codes, and if the status code indicates an abnormality, the processor executes abnormality processing corresponding to the type of abnormality represented by the status code according to the abnormality processing program.

[0099] In the second case, there are two or more abnormality processing programs, in which case the processor determines the abnormality processing program corresponding to the status code according to the status code and the first corresponding information, and then the processor executes abnormality processing corresponding to the type of abnormality represented by the status code according to the abnormality processing program.

[0100] The first corresponding information includes at least one status code and the abnormality processing program corresponding to the status code. The status code and the abnormality processing program can be in a one-to-one correspondence, i.e., each status code corresponds to a different abnormality processing program, or multiple status codes can correspond to one abnormality processing program in a many-to-one relationship. The processor can match the status code in the first information with each status code in the first corresponding information, and when the match is consistent, the processor can determine the abnormality processing program corresponding to the status code.

[0101] For example, the first corresponding information can include the following corresponding relationships: (0x01, address 1), (0x10, address 2), (0x20, address 3), (0x30, address 1), etc.

[0102] Since the processor determines the abnormality processing program corresponding to the status code, and the abnormality processing program is a device for solving the type of abnormality represented by the status code, the above matching process can also be understood as the processor determining that the status code indicates an abnormality.

[0103] In some possible embodiments, if one status code corresponds to multiple abnormality processing programs, the processor needs to be further configured to call the abnormality processing programs in a certain manner, such as sequentially or simultaneously.

[0104] It can be understood that regardless of the above corresponding relationship, the abnormality processing program corresponding to the status code should have the ability to solve the type of abnormality represented by the status code through the running of the processor.

[0105] In step S150, after the processor writes the status code into the first register, when running the corresponding exception handling program, there is a corresponding logical design in the exception handling program to obtain the status code from the first register, so that the exception handling program can obtain and use the status code in the first register, thereby realizing the processor to execute the exception handling corresponding to the exception type represented by the status code according to the exception handling program.

[0106] After obtaining the status code, in one possible implementation, the exception handling program first determines the exception handling corresponding to the status code according to the second corresponding information, and then executes the exception handling, wherein the second corresponding information includes a plurality of status codes and a plurality of exception handling corresponding to the status codes respectively.

[0107] Through steps S110-S150, since the second information generated by the first device contains the status code, when the status code indicates that an exception occurs, the processor does not need to obtain specific information about the exception from the first device again, but directly makes corresponding exception handling according to the status code in the first information received by the processor, which greatly simplifies the flow of exception handling and significantly improves the efficiency of exception handling.

[0108] The following describes the exception handling method in the embodiment of the application by using a specific application scenario and combining FIGS. 5-8. Taking the status code "0x10" defined as a device reset, the status code "0x20" defined as a non-existent memory region, and the status code "0x30" defined as a memory write failure as examples, the exception handling scenarios applied in a PCIe system and a CXL system are exemplarily introduced respectively.

[0109] It should be noted that the exception handling method provided in the application can be applied to various protocols, including but not limited to PCIe protocol, CXL protocol, and the like.

[0110] As shown in FIG. 5, FIG. 5 is an architecture schematic diagram of a PCIe system provided by one exemplary embodiment of the application, which includes a central processor, a root complex (RC), PCIe switches 1-4, and PCIe end devices 1-6.

[0111] It should be noted that in the PCIe system, the root complex RC can be used to connect the central processor and other PCIe devices together, and can serve as an interface module for communication between the central processor and each PCIe device. In the embodiment of the application, the function of the root complex can be realized by an independent device, or can be integrated in the central processor.

[0112] Based on FIG. 5, the exception handling method provided in the embodiment of the present application runs on the central processor CPU in FIG. 5, which can be an advanced RISC machine (ARM) architecture, and the processor is the central processor CPU in FIG. 5, on which the exception handling program can run, the first device is a PCIe device (including a PCIe switch and a PCIe end device) for example, and in the first embodiment, the state code "0x10" is defined as a device reset.

[0113] FIG. 6 is a flowchart of an exception handling method related to the embodiment shown in FIG. 5, which specifically includes:

[0114] S210, the CPU sends a first instruction to the PCIe device.

[0115] In this step, the CPU can obtain an instruction to be executed by the CPU from the system memory of the computing device in which the CPU is located, which can be a load, store or other instruction that requires the PCIe device to reply with data.

[0116] For example, the CPU obtains a load instruction to be executed, which instructs the central processor CPU to read data in the configuration register of the PCIe end device 1. After the CPU obtains the instruction, the CPU issues a corresponding data read instruction (first instruction) to the PCIe device. Specifically, the CPU can issue a read operation in the coherent hub interface (CHI) protocol to the root complex (RC) in FIG. 5, and then the RC initiates a configuration read request (CfgRd request) to the PCIe device.

[0117] S220, the PCIe device receives and executes the first instruction.

[0118] The PCIe device involved in this step includes the PCIe switch 1 and the PCIe end device 1 in FIG. 5.

[0119] For example, the PCIe switch 1 receives the CfgRd request sent by the RC and forwards it to the PCIe end device 1, and then the PCIe end device 1 can obtain data from the configuration register specified by the first instruction through its controller after receiving the CfgRd request.

[0120] S230, the PCIe device generates second information and sends it to the CPU.

[0121] For example, if the controller of the PCIe endpoint device 1 is in a fault state, it cannot correctly return a PCIe completion message (second information), and the PCIe endpoint device 1 generates a completion message including a status code "0x10" and sends it to the processor. The status code "0x10" can be added to a newly added field in the completion message, and different values of the field can represent whether an exception occurs in the process of executing the first instruction issued by the processor by the PCIe device, and / or the type of the exception. Then, the PCIe endpoint device 1 sends the completion message to the PCIe switch 1, the PCIe switch 1 forwards the completion message to the RC, and then the RC sends it to the CPU.

[0122] If the endpoint device 1 has a more serious fault, such as power failure of the endpoint device 1, complete loss of response capability, or communication link interruption between the endpoint device 1 and the switch 1, etc., it cannot receive the configuration read request, and cannot generate the completion message. At this time, the switch 1 can replace the endpoint device 1 to return the completion message including the corresponding status code to the CPU.

[0123] When the PCIe endpoint device 1 generates the completion message including the status code "0x10" as described above, the PCIe endpoint device 1 can determine the status code corresponding to the current device state information by querying the third corresponding information. The third corresponding information includes a plurality of device state information and a plurality of device state information corresponding to the status code, which can be stored in the storage device of the device in the form of a table or other data format. The data format and storage location of the third corresponding information are not limited by the embodiments of the present application.

[0124] S240, the CPU obtains the first information and writes the status code into the first register.

[0125] For example, the CPU obtains the completion message returned by the PCIe endpoint device 1 from the RC. Specifically, the RC converts the completion message (second information) including the status code "0x10" into a compdata message (first information) under the CHI protocol, sets the resperr field in the compdata message to "0b11" to represent that there is a non-data error (NDERR) in the compdata message, and sends the compdata message to the CPU. The CPU obtains the compdata message, writes the status code "0x10" into a first register (also referred to as an I / O exception code (IOEC) register) in the CPU, and supports access by an exception handler.

[0126] In S250, if the status code indicates that an exception occurs, the CPU executes an exception handling corresponding to the type of exception represented by the status code according to an exception handler.

[0127] In the embodiments of the present application, the exception handler includes a driver that needs the CPU to run in a kernel state, and also includes a user program that needs the CPU to run in a user state. Both the above-mentioned programs can directly obtain the status code stored in the IOEC register.

[0128] In this step, the CPU can call the exception handler corresponding to the status code "0x10", specifically, the instruction pointer IP is jumped to the first address of the exception handler corresponding to the status code "0x10", so that the exception handler runs on the CPU.

[0129] In this step, due to the presence of the status code, the exception handler running on the processor does not need to obtain specific information about the exception through the RC, the PCIe switch 1 and the PCIe endpoint device 1, but can directly obtain the status code "0x10" from the IOEC register. The status code represents that the device needs to be reset, and then directly executes the reset operation of the PCIe endpoint device 1, for example, issues a PERST# signal, to complete the processing of the exception, greatly simplifying the exception handling process and significantly improving the exception handling efficiency.

[0130] In this way, through the steps S210-S250, the processor completes the reset operation of the PCIe device with the abnormality according to the state code "0x10" in the first information, and when determining that the abnormality occurs, the CPU does not need to obtain the specific information of the abnormality from the PCIe device, but directly executes the abnormality processing corresponding to the abnormality type represented by the state code in the IOEC according to the abnormality processing program, thereby significantly improving the efficiency of the abnormality processing.

[0131] As shown in FIG. 7, FIG. 7 is a schematic diagram of an architecture of a CXL system provided by an example embodiment of the present application, which includes computing devices 1-2, CXL switches 1-2 and CXL storage devices 1-4. Among them, the computing devices 1 and 2 each include a central processor and a CXL root complex, and the central processor communicates with the CXL device through the CXL root complex.

[0132] It should be noted that since the device supporting the CXL protocol can communicate through the physical and electrical interfaces under the PCIe protocol, the root complex RC in the CXL system shown in FIG. 7 is similar to the root complex RC in the PCIe system described above, and will not be described here.

[0133] Based on FIG. 7, the abnormality processing method provided by the embodiment of the present application runs in the central processor CPU in FIG. 7, which can be an advanced RISC machine (ARM) architecture, and the processor is the central processor CPU in the computing device 1 in FIG. 7, which can run the abnormality processing program, the first device is the CXL device (including the CXL switch and the CXL storage device), and in this embodiment, the state code "0x20" is defined as the memory area does not exist, and the state code "0x30" is defined as the memory write fails.

[0134] FIG. 8 is a flowchart of an abnormality processing method related to the embodiment shown in FIG. 7, which specifically includes:

[0135] S310, the CPU sends a first instruction to the CXL device.

[0136] In this step, the CPU can obtain the instruction waiting for the CPU to execute from the system memory of the computing device where the CPU is located, and the instruction can be a load, a store or other instruction that needs the CXL device to reply the response data.

[0137] Taking a load instruction to be executed by the CPU as an example, the instruction indicates the CPU to read data in the memory space corresponding to the specified logical address. After the CPU obtains the instruction, the specified logical address can be converted into a physical address by a memory management unit (MMU) in the CPU, and the physical address is mapped to the CXL device, and then the CPU sends a corresponding memory read instruction (first instruction) to the CXL device. Specifically, the CPU can send a read operation in the CHI protocol to the root complex (RC) in FIG. 7, and then the RC initiates a memory read request (MemRd request) to the CXL device.

[0138] Alternatively, taking a store instruction to be executed by the CPU as an example, the instruction indicates the CPU to write data to the memory corresponding to the specified logical address. After the CPU obtains the instruction, the specified logical address can be converted into a physical address by a memory management unit (MMU) in the CPU, and the physical address is mapped to the CXL device, and then the CPU sends a corresponding memory write instruction (first instruction) to the CXL device. Specifically, the CPU can send a write operation in the CHI protocol to the RC, and then the RC initiates a memory write request (MemWr request) to the CXL device.

[0139] S320, the CXL device receives and executes the first instruction.

[0140] The CXL device involved in this step includes the CXL switch 1 and the CXL storage device 1 in FIG. 7.

[0141] For example, if the CXL switch 1 receives the MemRd request sent by the RC, then the CXL switch 1 decodes the address information in the MemRd request, determines the CXL storage device specified by the MemRd request, and forwards the MemRd request to the CXL storage device. If the CXL switch 1 receives the MemWr request sent by the RC, then the CXL switch 1 decodes the address information in the MemWr request, determines that the CXL storage device specified by the MemWr request is the CXL storage device 1, and forwards the MemWr request to the CXL storage device 1. The CXL storage device 1 receives the MemWr request and writes data to the specified memory.

[0142] S330, the CXL device generates second information and sends it to the CPU.

[0143] For example, if the CXL switch 1 determines that the decoded address does not conform to the specified range, cannot determine the corresponding CXL storage device, and cannot obtain the corresponding data, the CXL switch 1 generates a CXL response message including a status code "0x20" and sends it to the processor.

[0144] Alternatively, for another example, if the CXL storage device 1 finds that the data cannot be written into the specified memory or the data is damaged after being written, the CXL storage device 1 generates a CXL response message including a status code "0x30" and sends it to the processor.

[0145] The status code "0x20" or "0x30" can be added to a newly added field in the CXL response message. Different values of the field can represent whether an exception occurs in the process of executing the first instruction issued by the processor by the CXL device, and / or the type of exception that occurs. Further, the CXL switch 1 sends the generated CXL response message to the RC, and the RC sends it to the CPU.

[0146] S340, the CPU obtains the first information and writes the status code into the first register.

[0147] For example, the CPU obtains the response message returned by the CXL switch 1 from the RC. Specifically, the RC can first convert the response message including the status code "0x20" or "0x30" (second information) into a compdata message (first information) under the CHI protocol, and at the same time, set the resperr field in the compdata message to "0b10" to represent that there is a data error (DERR) in the compdata message. The converted compdata message includes the status code "0x20" or "0x30" representing that the memory region does not exist. The RC sends the compdata message to the CPU, and the CPU obtains the compdata message and writes the status code "0x20" or "0x30" into the first register in the CPU. The register can also be referred to as an input / output exception (I / O exception code, IOEC) register, which supports access by an exception handling program.

[0148] S350, if the status code indicates that an exception occurs, the CPU executes an exception handling corresponding to the type of exception represented by the status code according to an exception handling program.

[0149] In the embodiments of the present application, the abnormality processing program includes a driver which needs the CPU to run in the kernel state, and also includes a user program which needs the CPU to run in the user state, and both of the above-mentioned programs can directly obtain the state code saved in the IOEC register.

[0150] In this step, the CPU can call the abnormality processing program corresponding to the state code "0x20" or "0x30", specifically, the instruction pointer IP can be jumped to the first address of the abnormality processing program corresponding to the state code "0x20" or "0x30", so that the abnormality processing program corresponding to the state code is run on the CPU.

[0151] In this step, due to the existence of the state code, the abnormality processing program running on the processor does not need to obtain specific information about the exception through the RC, CXL switch and other devices, but can directly obtain the state code from the IOEC register, such as the above-mentioned "0x20" or "0x30",

[0152] For example, if the abnormality processing program obtains the state code "0x20", since the state code represents that the memory region does not exist, the abnormality processing program can re-initiate access to the logical address through the CPU, and record the number of access failures, if the access failure exceeds the failure threshold, the retry is abandoned, and then the state code "0x20" can be displayed to the user through a visual interface to remind the user to further process.

[0153] For example, if the abnormality processing program obtains the state code "0x30", since the state code represents that the memory write fails, the abnormality processing program can write data into the logical address in another CXL storage device through the CPU, for example, write into the CXL storage device 2 in FIG. 7, and report the failure of the CXL storage device 1 to the user.

[0154] It should be noted that in the present application, since the processor needs to be solved immediately after the exception occurs, especially the synchronous exception, the IOEC register can only save the latest obtained state code, so that when the abnormality processing program obtains the state code from the IOEC register, it will usually only obtain the state code corresponding to the currently latest occurred exception, thereby avoiding confusion in abnormality processing and improving the reliability of abnormality processing.

[0155] In this way, through the above steps S310-S350, in the case where the state code indicates that an exception occurs, the CPU will obtain the state code in the first information and write it into the register inside the CPU, and call the abnormality processing program to directly execute the abnormality processing corresponding to the exception type represented by the state code, without the need to obtain specific information of the exception from the CXL device, which significantly improves the efficiency of abnormality processing.

[0156] The above describes the scheme of the embodiments of the present application mainly from the method aspect. It can be understood that the abnormality processing apparatus includes at least one of the hardware structure and the software module for executing the respective functions in order to implement the above functions. Those skilled in the art should easily realize that the units and algorithm steps of the examples described in combination with the embodiments disclosed herein can be implemented in the form of hardware or the combination of hardware and computer software. Whether a certain function is implemented in the form of hardware or computer software driving hardware depends on the specific application and design constraints of the technical solution. The skilled person can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the present application.

[0157] The embodiments of the present application can divide the functional units of the abnormality processing apparatus according to the above method examples. For example, each functional unit can be divided according to each function, or two or more functions can be integrated in one processing unit. The integrated unit can be implemented in the form of hardware or software functional unit. It should be noted that the division of units in the embodiments of the present application is illustrative, and is only a logical function division. Actual implementation can have another division manner.

[0158] For example, FIG. 9 shows a structural schematic diagram of an abnormality processing apparatus 400 provided by an example embodiment of the present application. The abnormality processing apparatus 400 is applied to a processor. The abnormality processing apparatus 400 includes:

[0159] The obtaining module 410 is configured to obtain first information. The first information includes a state code. The state code is used to represent whether an abnormality occurs in a process in which the first device executes a first instruction issued by the processor and / or a type of the abnormality.

[0160] The execution module 420 is configured to execute, if the state code indicates that the abnormality occurs, an abnormality processing corresponding to the type of the abnormality represented by the state code according to an abnormality processing program. The abnormality processing program runs on the processor.

[0161] In a possible implementation, the execution module 420 is further configured to: if the state code indicates that the abnormality occurs, write the state code into a first register. The first register is a register in the processor. Determine the abnormality processing corresponding to the type of the abnormality represented by the state code in the first register according to the abnormality processing program. Execute the abnormality processing.

[0162] In a possible implementation, the obtaining module 410 is further configured to: if an interrupt signal is received, determine address information corresponding to the interrupt signal. Obtain the first information from a storage apparatus corresponding to the address information.

[0163] In a possible implementation, the execution module 420 is further configured to: if the status code indicates that an exception occurs, determine, according to first corresponding information, a first exception handling program corresponding to the status code, wherein the first corresponding information at least includes a status code and an exception handling program corresponding to the status code; and perform an exception handling corresponding to an exception type represented by the status code according to the first exception handling program.

[0164] In a possible implementation, the exception handling is determined by the exception handling program according to the status code and second corresponding information, and the second corresponding information includes a plurality of status codes and an exception handling corresponding to each of the plurality of status codes.

[0165] In a possible implementation, the execution module 420 is further configured to: if the status code indicates that an exception occurs, and the exception is a synchronous exception, perform an exception handling corresponding to an exception type represented by the status code according to the exception handling program.

[0166] For example, FIG. 10 shows a structural schematic diagram of an exception handling apparatus 500 provided by an example embodiment of the present application. The exception handling apparatus 500 is applied to a first device. The exception handling apparatus 500 includes:

[0167] A generation module 510 is configured to generate second information, wherein the second information includes a status code, and the status code is used to represent whether an exception occurs in a process in which a processor executes a first instruction issued by the processor and / or a type of the exception.

[0168] A sending module 520 is configured to send the second information to the processor, and the processor is configured to determine, according to first information, whether the status code indicates that an exception occurs, and perform an exception handling corresponding to an exception type represented by the status code according to an exception handling program if the status code indicates that an exception occurs, wherein the first information includes the status code in the second information.

[0169] In a possible implementation, the first device includes a switch device and a node device, the node device communicates with the processor through the switch device, and the generation module 510 is further configured to: if the switch device does not receive the second information generated by the node device within a time threshold interval, the switch device generates the second information.

[0170] In a possible implementation, the generating module 510 is further configured to: if an exception occurs in the process of executing the first instruction issued by the processor by the first device, determine a state code according to device state information and third corresponding information; the third corresponding information includes a plurality of device state information and a state code corresponding to each of the plurality of device state information; and generate second information including the state code corresponding to the device state information.

[0171] In an example embodiment, a computer readable storage medium is also provided for storing at least one instruction, at least one program, a code set or an instruction set, which is loaded and executed by a processor to implement all or part of the steps of the above-mentioned exception handling method. For example, the computer readable storage medium can be a read-only memory (ROM), a random access memory (RAM), a compact disc read-only memory (CD-ROM), a magnetic tape, a floppy disk, an optical data storage device, etc.

[0172] In an example embodiment, a computer program product or computer program is also provided, which includes computer instructions stored in a computer readable storage medium. A processor of a computing device reads the computer instructions from the computer readable storage medium, and the processor executes the computer instructions to cause the computing device to perform all or part of the steps of the method shown in any of the embodiments of FIG. 4.

[0173] In some embodiments, the method shown in the embodiments of the present application can be implemented as computer program instructions encoded in a machine-readable storage medium or other non-transitory medium or article in a machine-readable format.

[0174] Through the above description of the embodiments, those skilled in the art can clearly understand that, for the convenience and brevity of description, only the division of the above functional modules is taken as an example for illustration, and in actual application, the above functions can be completed by different functional modules according to needs, i.e., the internal structure of the device is divided into different functional modules to complete all or part of the functions described above.

[0175] In several embodiments provided in the present application, it should be understood that the disclosed apparatus and method can be implemented by other manners. For example, the apparatus embodiments described above are merely illustrative, for example, the division of the modules or units is merely a logical function division, and actual implementation can have another division manner, for example, a plurality of units or components can be combined or integrated into another apparatus, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the units or components shown or discussed can be indirect coupling or communication connection through some interfaces, apparatuses or units, and can be electrical, mechanical or other forms.

[0176] The units described as separate components can or can not be physically separate, and the components shown as units can be one physical unit or a plurality of physical units, that is, can be located in one place, or can be distributed to a plurality of different places. Part or all of the units can be selected according to actual needs to achieve the purpose of the embodiment scheme.

[0177] In addition, each functional unit in each embodiment of the present application can be integrated in one processing unit, or each unit can be physically present separately, or two or more units can be integrated in one unit. The integrated unit can be realized in the form of hardware or in the form of a software functional unit.

[0178] The integrated unit, if realized in the form of a software functional unit and sold or used as an independent product, can be stored in a readable storage medium. Based on this understanding, the technical solutions of the embodiments of the present application essentially or the parts that make contributions to the prior art or the whole or part of the technical solutions can be embodied in the form of a software product, which is stored in a storage medium and includes a plurality of instructions for causing an apparatus (which can be a single-chip microcomputer, a chip, etc.) or a processor to execute all or part of the steps of the method described in the embodiments of the present application. The foregoing storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, and various storage program codes.

[0179] The above description is only optional embodiments of the present application, and does not limit the present application, and any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. An exception handling method, characterized in that, Applied to a processor that communicates with a first device, the first device being a peripheral device of the processor, the method includes: Obtain first information, the first information including a status code, the status code being used to characterize whether an exception occurs during the execution of the first instruction issued by the processor by the first device, and / or the type of exception that occurs; If the status code indicates an exception, the exception handling corresponding to the exception type represented by the status code is executed according to the exception handling program; the exception handling program runs on the processor.

2. The method according to claim 1, characterized in that, If the status code indicates an abnormality, the exception handling corresponding to the exception type represented by the status code is executed according to the exception handling procedure, including: If the status code indicates an abnormality, the status code is written to the first register, which is a register in the processor. According to the exception handling procedure, determine the exception handling corresponding to the exception type represented by the status code in the first register; Perform the exception handling.

3. The method according to claim 1 or 2, characterized in that, The acquisition of the first information includes: If an interrupt signal is received, determine the address information corresponding to the interrupt signal; The first information is obtained from the storage device corresponding to the address information.

4. The method according to any one of claims 1-3, characterized in that, If the status code indicates an abnormality, the exception handling corresponding to the exception type represented by the status code is executed according to the exception handling procedure, including: If the status code indicates an abnormality, a first exception handling procedure corresponding to the status code is determined based on the first corresponding information; the first corresponding information includes at least one status code and the exception handling procedure corresponding to the status code. The exception handling corresponding to the exception type represented by the status code is executed according to the first exception handling procedure.

5. The method according to any one of claims 1-4, characterized in that, The exception handling is determined by the exception handling program based on the status code and the second corresponding information, wherein the second corresponding information includes multiple status codes and the exception handling corresponding to each of the multiple status codes.

6. The method according to any one of claims 1-5, characterized in that, If the status code indicates an abnormality, the exception handling corresponding to the exception type represented by the status code is executed according to the exception handling procedure, including: If the status code indicates an exception, and the exception is a synchronization exception, the exception handling corresponding to the exception type represented by the status code is executed according to the exception handling procedure.

7. An exception handling method, characterized in that, Applied to a first device that communicates with a processor, the first device being a peripheral device of the processor, the method includes: Generate second information, the second information including a status code, the status code being used to characterize whether an exception occurred during the execution of the first instruction issued by the processor, and / or the type of exception that occurred; The processor sends the second information to the processor; the processor is configured to determine whether the status code indicates an exception has occurred based on the acquired first information, and if the status code indicates an exception has occurred, it is configured to perform exception handling corresponding to the exception type represented by the status code according to the exception handling program; the first information includes the status code in the second information.

8. The method according to claim 7, characterized in that, The first device includes a switch device and a node device, wherein the node device communicates with the processor through the switch device; The generation of the second information includes: If the switching device does not receive the second information generated by the node device within the time threshold interval, the switching device generates the second information.

9. The method according to claim 7 or 8, characterized in that, The generation of the second information includes: If an exception occurs during the execution of the first instruction issued by the processor by the first device, a status code is determined based on the device status information and the third corresponding information; the third corresponding information includes multiple device status information and the status code corresponding to each of the multiple device status information. Generate second information containing the status code corresponding to the device status information.

10. An anomaly handling device, characterized in that, The exception handling device is applied to a processor, the processor communicating with a first device, the first device being a peripheral device of the processor, and the device comprising: The acquisition module is used to acquire first information, the first information including a status code, the status code being used to characterize whether an exception occurs during the execution of the first instruction issued by the processor by the first device, and / or the type of exception that occurs; An execution module is configured to, if the status code indicates an exception, execute exception handling corresponding to the exception type represented by the status code according to the exception handling program; the exception handling program runs on the processor.

11. The anomaly handling device according to claim 10, characterized in that, If the status code indicates an exception, the execution module performs exception handling corresponding to the exception type represented by the status code according to the exception handling procedure, and the execution module is used to: If the status code indicates an abnormality, the status code is written to the first register, which is a register in the processor. According to the exception handling procedure, determine the exception handling corresponding to the exception type represented by the status code in the first register; Perform the exception handling.

12. The anomaly handling apparatus according to claim 10 or 11, characterized in that, The module for obtaining the first information is used to: If an interrupt signal is received, determine the address information corresponding to the interrupt signal; The first information is obtained from the storage device corresponding to the address information.

13. The anomaly handling apparatus according to any one of claims 10-12, characterized in that, If the status code indicates an exception, the execution module performs exception handling corresponding to the exception type represented by the status code according to the exception handling procedure, and the execution module is used to: If the status code indicates an abnormality, a first exception handling procedure corresponding to the status code is determined based on the first corresponding information; the first corresponding information includes at least one status code and the exception handling procedure corresponding to the status code. The exception handling corresponding to the exception type represented by the status code is executed according to the first exception handling procedure.

14. The anomaly handling apparatus according to any one of claims 10-13, characterized in that, The exception handling is determined by the exception handling program based on the status code and the second corresponding information, wherein the second corresponding information includes multiple status codes and the exception handling corresponding to each of the multiple status codes.

15. The anomaly handling apparatus according to any one of claims 10-14, characterized in that, If the status code indicates an exception, the execution module performs exception handling corresponding to the exception type represented by the status code according to the exception handling procedure, and the execution module is used to: If the status code indicates an exception, and the exception is a synchronization exception, the exception handling corresponding to the exception type represented by the status code is executed according to the exception handling procedure.

16. An anomaly handling device, characterized in that, The exception handling device is applied to a first device, which is a peripheral device of the processor, and the device includes: A generation module is used to generate second information, the second information including a status code, the status code being used to characterize whether an exception occurred during the execution of the first instruction issued by the processor, and / or the type of exception that occurred; A sending module is configured to send the second information to the processor; the processor is configured to determine whether the status code indicates an exception based on the acquired first information, and if the status code indicates an exception, to execute exception handling corresponding to the exception type represented by the status code according to the exception handling program; the first information includes the status code in the second information.

17. The anomaly handling device according to claim 16, characterized in that, The first device includes a switch device and a node device, wherein the node device communicates with the processor through the switch device; The generation module is used to generate the second information, wherein the generation module is configured to: If the switching device does not receive the second information generated by the node device within the time threshold interval, the switching device generates the second information.

18. The anomaly handling apparatus according to claim 16 or 17, characterized in that, The generation module is used to generate the second information, wherein the generation module is configured to: If an exception occurs during the execution of the first instruction issued by the processor by the first device, a status code is determined based on the device status information and the third corresponding information; the third corresponding information includes multiple device status information and the status code corresponding to each of the multiple device status information. Generate second information containing the status code corresponding to the device status information.

19. A computing device, characterized in that, include: Processor and memory; The memory is used to store a set of computer instructions, and when the processor executes the set of computer instructions, it performs the exception handling method according to any one of claims 1-6 or 7-9.

20. A computer program product, characterized in that, The computer program product includes instructions that, when executed by a computing device, cause the computing device to perform the exception handling method as described in any one of claims 1 to 6 or 7-9.

21. A computer-readable storage medium, characterized in that, It includes computer program instructions, which, when executed by a computing device, enable the computing device to perform the exception handling method as described in any one of claims 1 to 6 or 7-9.

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