Storage device and manufacturing method therefor, and memory system

Abstract

Embodiments of the present application provide a storage device and a manufacturing method therefor, and a memory system. The storage device comprises: a plurality of first stack structures which are stacked, each first stack structure comprising a plurality of first conductive layers and first dielectric layers arranged alternately in a first direction; a first conductive structure, the first conductive structure extending in the first direction and being connected one first conductive layer of each of at least two first stack structures among the plurality of first stack structures; a plurality of channel structures, the channel structures passing through the plurality of first stack structures; and at least one semiconductor layer, one semiconductor layer being connected to the channel structure in at least one first stack structure.

Description

Memory device and manufacturing method thereof, memory system

[0001] Cross Reference to Related Applications

[0002] This application claims the benefit of priority to U.S. Provisional Application No. 63 / 661,018, filed June 17, 2024, Chinese Patent Application 202411319696.4, filed September 20, 2024, Chinese Patent Application 202411321182.2, filed September 20, 2024, and Chinese Patent Application 202411320221.7, filed September 20, 2024, the entire contents of which are incorporated herein by reference. TECHNICAL FIELD

[0003] The present application relates to the technical field of semiconductor technology, in particular to a memory device, a manufacturing method thereof, and a memory system. BACKGROUND

[0004] Memory devices, such as Not-And (NAND) flash memory, have become mainstream products in the storage market due to their high storage density, controllable production cost, suitable programming and erasing speed, and retention characteristics. SUMMARY

[0005] Embodiments of the present application provide a memory device, which includes: a plurality of first stack structures arranged in a stack; each first stack structure includes a plurality of first conductive layers and a plurality of first dielectric layers arranged alternately along a first direction; a first conductive structure extending along the first direction and connected to one first conductive layer of at least two first stack structures; a plurality of channel structures; each channel structure extends through the plurality of first stack structures; and at least one semiconductor layer connected to the channel structure of at least one first stack structure.

[0006] In some embodiments, a cross-sectional shape of the plurality of first stack structures along the first direction includes a stepped shape; each step of the stepped shape corresponds to one first conductive layer and one first dielectric layer; and the first conductive structure extends along the first direction in the first stack structure and is connected to at least two steps where one first conductive layer of the at least two first stack structures is located.

[0007] In some embodiments, the memory device further includes a second stack structure including a plurality of isolation layers and a plurality of second dielectric layers arranged alternately along the first direction; the first conductive structure includes a first lead-out portion and a plurality of first connection portions; the first lead-out portion extends along the first direction in the second stack structure and is connected to each of the plurality of first connection portions; and each first connection portion is located in one isolation layer and connected to one first conductive layer of a corresponding first stack structure of the at least two first stack structures.

[0008] In some embodiments, the first conductive structure is connected to a first conductive layer of each of the plurality of first stacked structures.

[0009] In some embodiments, the first conductive layer connected to the same first conductive structure in different first stacked structures is at the same distance from the semiconductor layer connected to the channel structure in the corresponding first stacked structure.

[0010] In some embodiments, the distance between the first conductive layer connected to the same first conductive structure in two different first stacked structures and the semiconductor layer connected to the channel structure in the corresponding first stacked structure is different.

[0011] In some embodiments, the storage device further includes peripheral circuitry; the peripheral circuitry includes word line driving circuitry; and at least two first conductive layers of the first stacked structures are interconnected through the first conductive structures and connected to the same word line driving circuitry.

[0012] In some embodiments, the area where the word line driving circuit is disposed is aligned with the area where the first conductive structure is disposed along a first direction.

[0013] In some embodiments, the storage device has a first number of first stacked structures, the first stacked structures having a second number of first conductive layers; the storage device has a third number of word line driving circuits, the third number being less than or equal to the product of the first number and the second number.

[0014] In some embodiments, a plurality of first stacked structures are disposed in a first region, and a plurality of first conductive structures are disposed in a second region, the second region being located in the middle of the first region.

[0015] In some embodiments, a plurality of first stacked structures are disposed in a first region, and a plurality of first conductive structures are disposed in a second region, wherein the second region is located on at least one side of the first region along a direction perpendicular to the first direction.

[0016] In some embodiments, at least one semiconductor layer is located between two adjacent first stacked structures and is connected to the channel structures in both adjacent first stacked structures.

[0017] In some embodiments, there is at least one second conductive layer and a plurality of second conductive structures; one second conductive layer is connected to a channel structure of at least one first stacked structure; one second conductive layer includes a plurality of bit lines spaced apart along a second direction and extending along a third direction; both the second direction and the third direction are perpendicular to the first direction; the second conductive structure extends along the first direction in the first stacked structure and is connected to a bit line of at least one second conductive layer.

[0018] In some embodiments, a plurality of first stacked structures are disposed in a first region, and a plurality of second conductive structures are disposed in a third region, the third region being located on at least one side of the first region along a third direction.

[0019] In some embodiments, the memory device further includes a plurality of third conductive structures; a plurality of first conductive layers in the first stacked structure include a top selected gate layer and a gate layer; the top selected gate layer is located at one end of the respective first stacked structure along a first direction away from the semiconductor layer connected to the channel structure in the respective first stacked structure; the third conductive structure extends along the first direction in the first stacked structure and is connected to the top selected gate layer included in at least one of the plurality of first stacked structures; the first conductive structure is connected to a gate layer of at least two of the plurality of first stacked structures.

[0020] In some embodiments, a plurality of first stacked structures are disposed in a first region, all first conductive structures are disposed in a second region, and all third conductive structures are disposed in a fourth region; the fourth region is located between the first region and the second region.

[0021] In some embodiments, the third conductive structure includes a second lead-out portion, a second connection portion, and a contact portion; the second lead-out portion extends along a first direction and is connected to the second connection portion; the second connection portion extends along a second direction and is connected to the contact portion; the contact portion extends along the first direction and is connected to the top selected gate layer; the second direction is perpendicular to the first direction.

[0022] In some embodiments, a plurality of first stacked structures stacked together constitute a storage surface; the storage device includes at least two storage surfaces; two of the at least two storage surfaces are arranged side by side along a second direction; the second direction is perpendicular to the first direction; a first conductive structure is located between the two storage surfaces and is connected to a first conductive layer of a different first stacked structure in at least one storage surface.

[0023] In some embodiments, the memory device further includes peripheral circuitry; the peripheral circuitry includes a plurality of word line driving circuits; different memory surfaces are interconnected with each other and connected to the same word line driving circuit at the same location along a first direction.

[0024] This application embodiment provides another memory system, which includes the memory device provided in this application embodiment.

[0025] This application also provides a method for manufacturing a memory device, the method comprising: forming a plurality of first stacked structures stacked together; the first stacked structure comprising a plurality of first conductive layers and first dielectric layers alternately disposed along a first direction; forming a first conductive structure, the first conductive structure extending along the first direction and connected to a first conductive layer of at least two of the plurality of first stacked structures; forming a plurality of channel structures; the channel structures penetrating the plurality of first stacked structures; and forming at least one semiconductor layer, the semiconductor layer being connected to a channel structure in at least one of the first stacked structures.

[0026] In some embodiments, forming a plurality of first stacked structures includes: providing a semiconductor structure; the semiconductor structure includes a plurality of semiconductor units, each semiconductor unit including at least a stacked layer, the stacked layer including a plurality of isolation material layers and dielectric layers alternately disposed along a first direction; dividing the semiconductor structure along a second direction and / or a third direction to form a plurality of independent semiconductor units; the second direction and the third direction intersect and are both perpendicular to the first direction; stacking the plurality of semiconductor units along the first direction to form a plurality of stacked semiconductor units; and replacing the isolation material layers in the plurality of stacked semiconductor units with a first conductive layer to form a plurality of stacked first stacked structures.

[0027] In some embodiments, the semiconductor cell further includes a semiconductor layer located on a first side and a second conductive layer located on a second side; the first side and the second side are respectively located on opposite sides of the stacked layer along a first direction; the second conductive layer includes a plurality of bit lines spaced apart along a second direction and extending along a third direction; stacking the plurality of semiconductor cells along the first direction includes: stacking every two semiconductor cells in the plurality of semiconductor cells to form a plurality of semiconductor cell groups; the two semiconductor cells in each semiconductor cell group are stacked in a direction toward their respective first sides; and stacking the plurality of semiconductor cell groups along the first direction.

[0028] In some embodiments, the method further includes: removing a semiconductor layer corresponding to one of the semiconductor cells before stacking every two semiconductor cells in the plurality of semiconductor cells; the remaining semiconductor layer forms a semiconductor layer that is connected to both semiconductor cells.

[0029] In some embodiments, the method further includes: forming a semiconductor layer and a second conductive layer on opposite sides of each semiconductor cell along a first direction; the second conductive layer includes a plurality of bit lines spaced apart along a second direction and extending along a third direction; stacking the plurality of semiconductor cells along the first direction, including: stacking the plurality of semiconductor cells having the semiconductor layer and the second conductive layer formed thereon along the first direction.

[0030] In some embodiments, the semiconductor cell further includes a semiconductor layer located on a first side and a second conductive layer located on a second side; the first side and the second side are respectively located on opposite sides of the stacked layer along a first direction; the second conductive layer includes a plurality of bit lines spaced apart along a second direction and extending along a third direction; stacking the plurality of semiconductor cells along the first direction includes: stacking two semiconductor cells that are adjacent along the first direction in the plurality of semiconductor cells in a direction toward different sides of the respective semiconductor cells.

[0031] In some embodiments, stacking a plurality of semiconductor cells along a first direction includes: using a bonding process to stack a plurality of semiconductor cells along a first direction.

[0032] In some embodiments, the method further includes: when replacing the isolation material layer in a plurality of stacked semiconductor units with a first conductive layer, replacing a portion of the isolation material layer in each of the plurality of semiconductor units with the first conductive layer, wherein the stacked structure of the portion of the isolation material layer that has been replaced forms a first stacked structure, and the stacked structure of the portion of the isolation material layer that has not been replaced forms a second stacked structure; the dielectric layer corresponding to the first stacked structure is a first dielectric layer, and the dielectric layer corresponding to the second stacked structure is a second dielectric layer; forming the first conductive structure includes: forming the first conductive structure in the second stacked structure.

[0033] In some embodiments, the method further includes: forming a plurality of second conductive structures, the second conductive structures extending along a first direction in a first stacked structure and connected to a bit line of at least one second conductive layer.

[0034] In some embodiments, a plurality of first conductive layers in a first stacked structure include a top selected gate layer and a gate layer; the method further includes: forming a third conductive structure, the third conductive structure extending along a first direction in the first stacked structure and connected to a top selected gate layer of at least one of the plurality of first stacked structures; the first conductive structure is connected to a gate layer of at least two of the plurality of first stacked structures.

[0035] In some embodiments, forming a plurality of first stacked structures in a stacked manner includes: sequentially forming a plurality of first stacked structures in a stacked manner; the first stacked structure includes a plurality of alternating first conductive layers and dielectric layers; the method further includes: alternatingly forming semiconductor layers and second conductive layers on both sides of the plurality of first stacked structures along a first direction and between each pair of adjacent first stacked structures.

[0036] This application provides a storage device and its fabrication method and storage system. The storage device includes: a plurality of first stacked structures stacked together; each first stacked structure includes several first conductive layers and first dielectric layers alternately arranged along a first direction; a first conductive structure extending along the first direction and connected to a first conductive layer of at least two of the plurality of first stacked structures; a plurality of channel structures penetrating the plurality of first stacked structures; and at least one semiconductor layer connected to a channel structure in at least one of the plurality of first stacked structures. In this application embodiment, the first conductive structure, serving as a first conductive layer lead-out structure, is connected to a first conductive layer of at least two of the plurality of first stacked structures. That is, the first conductive structure connects to the plurality of first conductive layers corresponding to the plurality of first stacked structures, enabling the plurality of first conductive layers to share the first conductive structure. This reduces the total number of first conductive structures and their driving circuits, thus reducing the size of the storage device. Furthermore, the sharing of the first conductive structure extending along the first direction provides good technical support for the stacking of multiple first stacked structures (decks) along the first direction, providing a technical basis for the increased storage density brought about by multi-deck stacking.

[0037] This application provides another storage device, which includes: a plurality of first stacked structures stacked together; each first stacked structure includes a plurality of first conductive layers and first dielectric layers alternately disposed along a first direction; a plurality of channel structures; the channel structures penetrate the plurality of first stacked structures; at least one semiconductor layer; the semiconductor layer is connected to the channel structure in at least one first stacked structure; at least one second conductive layer; a second conductive layer is located between two adjacent first stacked structures and is connected to the channel structure in at least one first stacked structure; a semiconductor layer and a second conductive layer connected to the channel structure in the same first stacked structure are respectively disposed on both sides of the first stacked structure along the first direction.

[0038] In some embodiments, the second conductive layer includes a plurality of bit lines spaced apart along a second direction and extending along a third direction; the second direction intersects the third direction and is perpendicular to the first direction; a plurality of second conductive structures; the second conductive structures extend along the first direction in the first stack structure and are connected to a bit line of at least one second conductive layer.

[0039] In some embodiments, different bit lines connected to different first stacked structures through the same channel structure are all connected to the same second conductive structure.

[0040] In some embodiments, at least one of the plurality of second conductive layers is located between two adjacent first stacked structures and is connected to the channel structures in both adjacent first stacked structures.

[0041] In some embodiments, the storage device further includes peripheral circuitry; the peripheral circuitry includes a page cache; and a plurality of second conductive structures are connected to the same page cache.

[0042] In some embodiments, different bit lines connected by different first stacked structures through the same channel structure are connected to different second conductive structures.

[0043] In some embodiments, the dimensions of the second conductive layers corresponding to different first stacking structures are different along the third direction; the different second conductive structures connected to the second conductive layers corresponding to different first stacking structures are arranged sequentially along the third direction.

[0044] In some embodiments, the storage device further includes peripheral circuitry; the peripheral circuitry includes a plurality of page caches; a second conductive structure connected to a bit line of the same second conductive layer is connected to the same page cache among the plurality of page caches; and a second conductive structure connected to a bit line of a different second conductive layer is connected to a different page cache among the plurality of page caches.

[0045] In some embodiments, a plurality of first stacked structures stacked together constitute a storage module; the storage device includes at least two storage modules; two of the at least two storage modules are stacked together along a first direction; the storage device further includes a fourth conductive structure; different bit lines corresponding to different first stacked structures through which the same channel structure passes are all connected to different second conductive structures; a plurality of second conductive structures corresponding to the first stacked structures specified in different storage modules through which the same channel structure passes are interconnected through the fourth conductive structure.

[0046] In some embodiments, a plurality of first stacked structures are disposed in a first region, and a plurality of second conductive structures are disposed in a third region, wherein the third region is located on at least one side of the first region along a third direction.

[0047] In some embodiments, at least one of the plurality of semiconductor layers is located between two adjacent first stacked structures and is connected to the channel structures in both adjacent first stacked structures.

[0048] In some embodiments, two adjacent first stacked structures in a plurality of first stacked structures form a stacked structure group; the storage device includes a plurality of semiconductor layers; the plurality of semiconductor layers are respectively located between two adjacent first stacked structures in the plurality of stacked structure groups; the plurality of semiconductor layers are interconnected.

[0049] In some embodiments, the storage device further includes a plurality of first conductive structures, which extend along a first direction and are connected to a first conductive layer of at least two of the plurality of first stacked structures.

[0050] In some embodiments, the memory device further includes a plurality of third conductive structures; a plurality of first conductive layers in the first stacked structure include a top selected gate layer and a gate layer; the top selected gate layer is located at one end of the respective first stacked structure along a first direction away from the semiconductor layer connected to the channel structure in the respective first stacked structure; the third conductive structure extends along the first direction in the first stacked structure and is connected to the top selected gate layer included in at least one of the plurality of first stacked structures; the first conductive structure is connected to a gate layer of at least two of the plurality of first stacked structures.

[0051] This application embodiment provides another memory device, the memory device comprising: a plurality of first stacked structures stacked together; each first stacked structure including a plurality of first conductive layers and a first dielectric layer alternately disposed along a first direction; each of the plurality of first conductive layers in the first stacked structure including a top selected gate layer and a gate layer; the top selected gate layer being located at one end of a respective first stacked structure along the first direction away from a semiconductor layer connected to a channel structure in the respective first stacked structure; a plurality of channel structures; each channel structure penetrating the plurality of first stacked structures; at least one semiconductor layer; a semiconductor layer connected to a channel structure in at least one first stacked structure; and a plurality of third conductive structures extending along the first direction in the first stacked structure and connected to a top selected gate layer included in at least one of the plurality of first stacked structures.

[0052] In some embodiments, the memory device further includes a top-select gate isolation structure; the top-select gate isolation structure divides the top-select gate layer into multiple sub-top-select gate layers; different sub-top-select gate layers included in the same top-select gate layer are connected to different third conductive structures.

[0053] In some embodiments, different top selected gate layers of different first stacked structures are connected to different third conductive structures.

[0054] In some embodiments, the memory device further includes a plurality of second conductive layers and a plurality of second conductive structures; one second conductive layer is connected to a channel structure of at least one first stacked structure; one second conductive layer includes a plurality of bit lines, each bit line being connected to a column of channel structures; the second conductive structure extends along a first direction in the first stacked structure and is connected to a bit line of at least one second conductive layer.

[0055] In some embodiments, different bit lines corresponding to different first stacked structures through the same channel structure are connected to different second conductive structures; different top selected gate layers included in different first stacked structures are connected to the same third conductive structure.

[0056] In some embodiments, a plurality of first stacked structures stacked together constitute a storage surface; the storage device includes at least two storage surfaces; two storage surfaces in at least two storage modules are arranged side by side along a second direction; the second direction is perpendicular to the first direction; the storage device also includes a plurality of first conductive structures; the plurality of first conductive structures are located between the two storage surfaces, and the first conductive structures are connected to a gate layer of each of the different first stacked structures in at least one storage surface.

[0057] In some embodiments, the memory device further includes peripheral circuitry; the peripheral circuitry includes a plurality of word line driving circuits; the first conductive layers of different memory surfaces at the same position in the stacking direction of the first stacking structure are interconnected and connected to the same word line driving circuit.

[0058] In some embodiments, different bit lines corresponding to different first stacked structures that are connected through the same channel structure are all connected to different second conductive structures; different top selected gate layers included in different first stacked structures in the same memory plane are connected to the same third conductive structure; different top selected gate layers included in first stacked structures at the same position in the first direction of different memory planes are connected to different third conductive structures.

[0059] In some embodiments, a plurality of first stacked structures are stacked to form a memory module; the memory device includes at least two memory modules; the at least two first memory modules are stacked along a first direction; the memory device also includes a plurality of first conductive structures; the plurality of first conductive structures are connected to a gate layer of each of the first stacked structures in the two memory modules.

[0060] In some embodiments, the memory device further includes a fourth conductive structure; different bit lines corresponding to different first stacked structures through which the same channel structure passes in the same memory module are all connected to different second conductive structures; two bit lines corresponding to two specified first stacked structures in different memory modules are interconnected through the fourth conductive structure; different top selected gate layers included in different first stacked structures in the same memory module are connected to the same third conductive structure; two top selected gate layers included in two first stacked structures in different memory modules are connected to different third conductive structures.

[0061] In some embodiments, different bit lines corresponding to different first stacked structures with the same channel structure in the same memory module are all connected to the same second conductive structure; different bit lines corresponding to two first stacked structures in different memory modules are all connected to different second conductive structures; different top selected gate layers included in different first stacked structures in the same memory module are connected to different third conductive structures; and two top selected gate layers included in two first stacked structures in different memory modules are connected to the same third conductive structure.

[0062] In some embodiments, a plurality of first stacked structures are disposed in a first region, a plurality of first conductive structures are disposed in a second region, and a plurality of third conductive structures are disposed in a fourth region; the fourth region is located between the first region and the second region.

[0063] In some embodiments, the third conductive structure includes a second lead-out portion, a second connection portion, and a contact portion; the second lead-out portion extends along a first direction and is connected to the second connection portion; the second connection portion extends along a direction perpendicular to the first direction and is connected to the contact portion; the contact portion extends along the first direction and is connected to the top selected gate layer.

[0064] In some embodiments, each first stack structure includes a plurality of top select gate layers, the cross-sectional shape of the plurality of top select gate layers along a first direction including a stepped shape; each step in the stepped shape corresponds to a top select gate layer; a contact portion is connected to a step where a top select gate layer is located.

[0065] In some embodiments, at least one semiconductor layer is located between two adjacent first stacked structures and is connected to the channel structures in both adjacent first stacked structures.

[0066] In some embodiments, the memory device further includes a plurality of first conductive structures; the first conductive structures extend along a first direction and are connected to a gate layer of at least two of the plurality of first stacked structures.

[0067] This application embodiment provides another storage device, which includes: a plurality of first stacked structures stacked together; each first stacked structure includes a plurality of first conductive layers and first dielectric layers alternately disposed along a first direction; a plurality of channel structures; the channel structures penetrate the plurality of first stacked structures; at least one semiconductor layer; the semiconductor layer is connected to the channel structure in at least one first stacked structure; at least one second conductive layer; a second conductive layer is located between two adjacent first stacked structures and is connected to the channel structure in at least one first stacked structure; a semiconductor layer and a second conductive layer connected to the channel structure in the same first stacked structure are respectively disposed on both sides of the first stacked structure along the first direction. In this embodiment, the memory device includes multiple first stacked structures stacked together. A semiconductor layer (such as a source layer) and a second conductive layer (such as a bit line layer) connected by a channel structure in the same first stacked structure are respectively disposed on both sides of the first stacked structure along a first direction. A second conductive layer is located between two adjacent first stacked structures. That is, the second conductive layer is disposed between two adjacent first stacked structures (decks). The position of the second conductive layer is convenient for connection with the channel structure in its two adjacent first stacked structures, which can realize the sharing of bit line layers. This provides good technical support for the stacking of multiple decks and provides a technical basis for the improvement of storage density brought about by the stacking of multiple decks.

[0068] This application provides a storage device comprising: a plurality of first stacked structures stacked together; each first stacked structure including a plurality of first conductive layers and first dielectric layers alternately disposed along a first direction; a plurality of first conductive structures, each first conductive structure being connected to a first conductive layer of at least two of the plurality of first stacked structures; a plurality of channel structures; each channel structure penetrating the plurality of first stacked structures; at least one semiconductor layer and at least one second conductive layer; the semiconductor layer and the second conductive layer are respectively located on both sides of a first stacked structure along the first direction and are both connected to a channel structure in the first stacked structure; each second conductive layer includes a plurality of bit lines spaced apart along a second direction and extending along a third direction; the second direction and the third direction intersect and are both perpendicular to the first direction; and a plurality of second conductive structures, each second conductive structure being connected to a bit line of at least one second conductive layer.

[0069] In some embodiments, different bit lines corresponding to different first stacked structures that are traversed by the same channel structure are all connected to the same second conductive structure.

[0070] In some embodiments, at least one second conductive layer is located between two adjacent first stacked structures and is connected to the channel structures in both adjacent first stacked structures.

[0071] In some embodiments, the storage device further includes peripheral circuitry; the peripheral circuitry includes a page cache; and a plurality of second conductive structures are connected to the same page cache.

[0072] In some embodiments, different bit lines corresponding to different first stacked structures that are connected through the same channel structure are all connected to different second conductive structures.

[0073] In some embodiments, the dimensions of the second conductive layers corresponding to different first stacking structures are different along the third direction; the different second bit lines connected to the second conductive layers corresponding to different first stacking structures are arranged sequentially along the third direction.

[0074] In some embodiments, the storage device further includes peripheral circuitry; the peripheral circuitry includes a plurality of page caches; a second conductive structure connected to a bit line of the same second conductive layer is connected to the same page cache among the plurality of page caches; and a second conductive structure connected to a bit line of a different second conductive layer is connected to a different page cache among the plurality of page caches.

[0075] In some embodiments, at least one semiconductor layer is located between two adjacent first stacked structures and is connected to the channel structures in both adjacent first stacked structures.

[0076] In some embodiments, two adjacent first stacked structures in a plurality of first stacked structures form a stacked structure group; the storage device includes a plurality of semiconductor layers; the plurality of semiconductor layers are respectively located between two adjacent first stacked structures in the plurality of stacked structure groups; the plurality of semiconductor layers are interconnected.

[0077] In some embodiments, the cross-sectional shape of the plurality of first stacked structures along the first direction includes a stepped shape; each step in the stepped shape corresponds to an adjacent first conductive layer and a first dielectric layer; the first conductive structure extends along the first direction in the first stacked structure and is connected to at least two steps where a first conductive layer of at least two first stacked structures is located.

[0078] In some embodiments, the storage device further includes a second stacked structure, the second stacked structure including a plurality of alternately arranged isolation layers and a second dielectric layer; the first conductive structure includes a first lead-out portion and a plurality of first connection portions; the first lead-out portion is connected along a first line in the second stacked structure and is connected to the plurality of first connection portions; each first connection portion is located in an isolation layer and is connected to a first conductive layer of a corresponding first stacked structure in at least two first stacked structures.

[0079] In some embodiments, the first conductive structure is connected to a first conductive layer in each first stacked structure that is equidistant from the semiconductor layer connected to the channel structure of the corresponding first stacked structure.

[0080] In some embodiments, the first conductive structure is connected to a first conductive layer in each first stacked structure that is at a different distance from the semiconductor layer connected to the channel structure of the corresponding first stacked structure.

[0081] In some embodiments, the memory device further includes peripheral circuitry; the peripheral circuitry includes a plurality of word line driving circuits; a first conductive layer of at least two first stacked structures is interconnected through the first conductive structure and connected to the same word line driving circuit.

[0082] In some embodiments, the memory device further includes a plurality of third conductive structures; the first conductive layer in the first stacked structure includes a top selected gate layer and a gate layer; the top selected gate layer is located at one end of the respective first stacked structure along a first direction away from the semiconductor layer connected to the channel structure in the respective first stacked structure; the third conductive structure extends along the first direction in the first stacked structure and is connected to the top selected gate layer included in at least one of the plurality of first stacked structures; the first conductive structure is connected to a gate layer of at least two of the plurality of first stacked structures.

[0083] In some embodiments, the memory device further includes a top-select gate isolation structure; the top-select gate isolation structure divides the top-select gate layer into multiple sub-top-select gate layers; different sub-top-select gate layers included in the same top-select gate layer are connected to different third conductive structures.

[0084] In some embodiments, different top selected gate layers of different first stacked structures are connected to different third conductive structures; different bit lines corresponding to different first stacked structures through which the same channel structure passes are all connected to the same second conductive structure.

[0085] In some embodiments, different bit lines corresponding to different first stacked structures through the same channel structure are connected to different second conductive structures; different top selected gate layers included in different first stacked structures are connected to the same third conductive structure.

[0086] In some embodiments, a plurality of first stacked structures stacked together constitute a memory surface; the memory device includes a first memory surface and a second memory surface; the first memory surface and the second memory surface are arranged side by side along a second direction; the memory device further includes a plurality of word line driving circuits; a plurality of first conductive structures are located between the first memory surface and the second memory surface, and the first conductive structures are connected to a gate layer of at least one different first stacked structure in at least one memory surface; the first conductive layers of the first memory surface and the second memory surface at the same position in the first direction are interconnected and connected to the same word line driving circuit.

[0087] In some embodiments, different bit lines corresponding to different first stacked structures that are connected through the same channel structure are all connected to different second conductive structures; different top selected gate layers included in different first stacked structures in the same memory plane are connected to the same third conductive structure; different top selected gate layers included in first stacked structures at the same position in the first direction of different memory planes are connected to different third conductive structures.

[0088] In some embodiments, a plurality of first stacked structures arranged in a stacked manner constitute a memory module; the memory device includes a first memory module and a second memory block; the first memory module and the second memory block are stacked in a first direction; a plurality of first conductive structures are connected to a gate layer of each of the first stacked structures in the first memory module and the second memory block.

[0089] In some embodiments, different bit lines corresponding to different first stacked structures with the same channel structure in the same memory module are connected to different second conductive structures; two bit lines corresponding to two specified first stacked structures in different memory modules are connected to each other; different top selected gate layers included in different first stacked structures in the same memory module are connected to the same third conductive structure; two top selected gate layers included in two first stacked structures in different memory modules are connected to different third conductive structures.

[0090] In some embodiments, different bit lines corresponding to different first stacked structures with the same channel structure in the same memory module are all connected to the same second conductive structure; different bit lines corresponding to two first stacked structures in different memory modules are all connected to different second conductive structures; different top selected gate layers included in different first stacked structures in the same memory module are connected to different third conductive structures; and two top selected gate layers included in two first stacked structures in different memory modules are connected to the same third conductive structure.

[0091] In some embodiments, a plurality of first stacked structures are disposed in a first region, a plurality of first conductive structures are disposed in a second region, a plurality of second conductive structures are disposed in a third region, and a plurality of third conductive structures are disposed in a fourth region; the second region is located in the middle of the first region; or, the second region is located on at least one side of the first region along a direction perpendicular to the stacking direction; the third region is located on at least one side of the first region along a third direction; and the fourth region is located between the first region and the second region.

[0092] This application embodiment also provides a control method for a memory device, the memory device including the memory device provided in this application embodiment, wherein the channel structure is divided into multiple sub-channel structures by a semiconductor layer and a second conductive layer; a plurality of first conductive layers in a first stacked structure include a top selected gate layer and a gate layer; the top selected gate layer is located at one end of the corresponding first stacked structure along a first direction away from the end connected to the semiconductor layer of the channel structure in the corresponding first stacked structure; the control method for the memory device includes:

[0093] During the read operation, a first voltage is applied to the top select gate and / or the bit line coupled to the unselected sub-channel structure in the multiple sub-channel structures, and a second voltage is applied to the top select gate and the bit line coupled to the selected sub-channel structure in the multiple sub-channel structures; a pass voltage is applied to all unselected gate layers, and a read voltage is applied to the selected gate layer.

[0094] In some embodiments, the first voltage includes a cutoff voltage, and the second voltage includes a first on voltage; applying the first voltage to the top select gate of an unselected subchannel structure and / or its coupled bit lines, and applying the second voltage to the top select gate of a selected subchannel structure and its coupled bit lines, includes: applying a cutoff voltage to the top select gate of the unselected subchannel structure and applying the first on voltage to the top select gate of the selected subchannel structure.

[0095] In some embodiments, the first voltage includes a programmable disable voltage, and the second voltage includes a programmable enable voltage; applying the first voltage to the top select gate of an unselected sub-channel structure and / or its coupled bit lines, and applying the second voltage to the top select gate of a selected sub-channel structure and its coupled bit lines, includes: applying a programmable disable voltage to the bit lines coupled to the unselected sub-channel structure, and applying a programmable enable voltage to the bit lines coupled to the selected sub-channel structure; applying a first enable voltage to all top select gate layers.

[0096] In some embodiments, a plurality of first conductive layers in the first stacked structure further include bottom select gate layers; the bottom select gate layers are located at one end of the respective first stacked structure along a first direction, near the end of the semiconductor layer connected to the channel structure in the respective first stacked structure; the method further includes: applying a second on-state voltage to all bottom select gate layers during a read operation.

[0097] This application embodiment further provides a control method for a memory device, the memory device including the memory device provided in this application embodiment, wherein the channel structure is divided into multiple sub-channel structures by a semiconductor layer and a second conductive layer; a plurality of first conductive layers in the first stack structure include a top selected gate layer and a gate layer; the top selected gate layer is located at one end of the corresponding first stack structure along a first direction away from the end connected to the semiconductor layer of the channel structure in the corresponding first stack structure; the control method for the memory device includes:

[0098] During the programming operation, a first voltage is applied to the top selection gate and / or the bit lines coupled to the unselected sub-channel structures in the multiple sub-channel structures; a second voltage is applied to the top selection gate and the bit lines coupled to the selected sub-channel structures in the multiple sub-channel structures; a pass voltage is applied to all unselected gate layers; and a programming voltage is applied to the selected gate layers.

[0099] In some embodiments, the first voltage includes a cutoff voltage and the second voltage includes an on voltage; applying the first voltage to the top select gate of an unselected subchannel structure and / or its coupled bit lines, and applying the second voltage to the top select gate of a selected subchannel structure and its coupled bit lines, includes: applying a cutoff voltage to the top select gate of the unselected subchannel structure and applying an on voltage to the top select gate of the selected subchannel structure.

[0100] In some embodiments, the first voltage includes a programmable disable voltage, and the second voltage includes a programmable enable voltage; applying the first voltage to the top select gate of an unselected sub-channel structure and / or its coupled bit lines, and applying the second voltage to the top select gate of a selected sub-channel structure and its coupled bit lines, includes: applying a programmable disable voltage to the bit lines coupled to the unselected sub-channel structure, applying a programmable enable voltage to the bit lines coupled to the selected sub-channel structure; and applying an enable voltage to all top select gate layers.

[0101] In some embodiments, a plurality of first conductive layers in a first stacked structure further include bottom select gate layers; the bottom select gate layers are located at one end of the respective first stacked structure along a first direction near the end of the semiconductor layer connected to the channel structure in the respective first stacked structure; the method further includes: applying a cutoff voltage to all bottom select gate layers during a programming operation.

[0102] This application provides a storage device and its control method; wherein the storage device includes: a plurality of first stacked structures stacked together; each first stacked structure includes a plurality of first conductive layers and first dielectric layers alternately arranged along a first direction; a plurality of first conductive structures, each first conductive structure being connected to a first conductive layer of at least two of the plurality of first stacked structures; a plurality of channel structures; each channel structure penetrating the plurality of first stacked structures; at least one semiconductor layer and at least one second conductive layer; the semiconductor layer and the second conductive layer are respectively located on both sides of a first stacked structure along the first direction and are both connected to the channel structures in the first stacked structure; each second conductive layer includes a plurality of bit lines spaced apart along a second direction and extending along a third direction; a plurality of second conductive structures, each second conductive structure being connected to a bit line of at least one second conductive layer.

[0103] In this embodiment, the memory device includes multiple first stacked structures (decks), and each deck has a second conductive layer and a semiconductor layer disposed on both sides along a first direction. This improves the problem of reduced channel saturation current caused by an excessive number of gate layers. Simultaneously, the first conductive structure, serving as the lead-out structure of the first conductive layer, is connected to a first conductive layer of at least two of the multiple first stacked structures. In other words, the first conductive structure connects to multiple first conductive layers corresponding to multiple first stacked structures, enabling multiple first conductive layers to share the first conductive structure. This reduces the total number of first conductive structures and their driving circuits, thus reducing the size of the memory device. Furthermore, the sharing of the first conductive structure extending along the first direction provides strong technical support for the stacking of multiple decks along the first direction, providing a technical foundation for the increased storage density brought about by the stacking of multiple decks. Attached Figure Description

[0104] Figure 1 is a schematic diagram of the layout of the peripheral circuit including the word line driving circuit SD provided in an embodiment of this application;

[0105] Figure 2A is a perspective view of the storage device architecture provided in an embodiment of this application;

[0106] Figure 2B is a two-dimensional schematic diagram of the storage device architecture provided in the embodiment of this application;

[0107] Figure 2C is a three-dimensional schematic diagram of the storage device architecture provided in an embodiment of this application;

[0108] Figure 2D is a three-dimensional schematic diagram of the storage device architecture provided in the embodiment of this application;

[0109] Figure 2E is a three-dimensional schematic diagram of the storage device architecture provided in an embodiment of this application;

[0110] Figure 3A is a schematic diagram of the formation process of the storage device architecture provided in an embodiment of this application;

[0111] Figure 3B is a schematic diagram of the formation process of the storage device architecture provided in an embodiment of this application;

[0112] Figure 3C is a schematic diagram of the formation process of the storage device architecture provided in the embodiment of this application;

[0113] Figure 4A is a perspective view of a first stacked structure and a first conductive structure including storage devices provided in an embodiment of this application;

[0114] Figure 4B is a two-dimensional schematic diagram of a first stacked structure and a first conductive structure including storage devices provided in an embodiment of this application.

[0115] Figure 4C is a three-dimensional schematic diagram of a first stacked structure and a first conductive structure including storage devices provided in an embodiment of this application.

[0116] Figure 5A is a perspective view of the first stacked structure and the first conductive structure including the storage device provided in the embodiment of this application;

[0117] Figure 5B is a three-dimensional schematic diagram of a first stacked structure and a first conductive structure including storage devices provided in an embodiment of this application.

[0118] Figure 5C is a perspective view of the first stacked structure and the first conductive structure including the storage device provided in the embodiment of this application.

[0119] Figure 5D is a perspective view of the first stacked structure and the first conductive structure including the storage device provided in the embodiment of this application;

[0120] Figure 6A is a cross-sectional schematic diagram of a specific form of the first conductive structure including the storage device provided in an embodiment of this application;

[0121] Figure 6B is a cross-sectional schematic diagram of the specific form of the first conductive structure including the storage device provided in the embodiment of this application;

[0122] Figure 6C is a cross-sectional schematic diagram of the specific form of the first conductive structure including the storage device provided in the embodiment of this application;

[0123] Figure 7A is a top view of the layout including the array area and the connection area provided in an embodiment of this application;

[0124] Figure 7B is a cross-sectional view of X1-X1' in Figure 7A;

[0125] Figure 8A is a top view of the layout including the array area and the connection area provided in an embodiment of this application;

[0126] Figure 8B is a cross-sectional view of X2-X2' in Figure 8A;

[0127] Figure 9A is a top view of the layout including the array area and the connection area provided in an embodiment of this application;

[0128] Figure 9B is a cross-sectional view of Y1-Y1' in Figure 9A;

[0129] Figure 10A is a three-dimensional schematic diagram of the layout of the array of storage devices and peripheral circuits provided in an embodiment of this application;

[0130] Figure 10B is a top view of the lead-out structure of the BL and TSG of the deck 1 including the storage device provided in an embodiment of this application;

[0131] Figure 10C is a top view of the lead-out structure of the BL and TSG of the deck 2 including the storage device provided in the embodiment of this application;

[0132] Figure 10D is a cross-sectional schematic diagram of the lead-out structure of the BL including the storage device provided in an embodiment of this application;

[0133] Figure 10E is a cross-sectional schematic diagram of the lead-out structure of a TSG including a storage device provided in an embodiment of this application;

[0134] Figure 11A is a two-dimensional schematic diagram of the layout of the array of storage devices and peripheral circuits provided in an embodiment of this application;

[0135] Figure 11B is a top view of the BL lead-out structure of each deck including the storage device provided in the embodiment of this application;

[0136] Figure 11C is a top view of the lead-out structure of the BL of each deck including the storage device provided in the embodiment of this application;

[0137] Figure 11D is a cross-sectional schematic diagram of the lead-out structure of the TSG of each deck including the storage device provided in the embodiment of this application;

[0138] Figure 11E is a cross-sectional schematic diagram of the lead-out structure of the TSG of each deck including the storage device provided in the embodiment of this application;

[0139] Figure 12A is a three-dimensional schematic diagram of the layout of the array of storage devices and peripheral circuits provided in an embodiment of this application;

[0140] Figure 12B is a top view of the BL lead-out structure of each deck including the storage device provided in the embodiment of this application;

[0141] Figure 12C is a top view of the lead-out structure of the BL of each deck including the storage device provided in the embodiment of this application;

[0142] Figure 12D is a cross-sectional schematic diagram of the lead-out structure of the TSG of each deck including the storage device provided in the embodiment of this application;

[0143] Figure 12E is a cross-sectional schematic diagram of the lead-out structure of the TSG of each deck including the storage device provided in the embodiment of this application;

[0144] Figure 13A is a three-dimensional schematic diagram of the layout of the array of storage devices and peripheral circuits provided in an embodiment of this application;

[0145] Figure 13B is a top view of the BL lead-out structure of each deck including the storage device provided in the embodiment of this application;

[0146] Figure 13C is a top view of the lead-out structure of the BL of each deck including the storage device provided in the embodiment of this application;

[0147] Figure 13D is a top view of the lead-out structure of the BL and TSG of Model 1, which includes a storage device, provided in an embodiment of this application.

[0148] Figure 13E is a top view of the lead-out structure of the BL and TSG of Model 2, which includes a storage device, provided in an embodiment of this application.

[0149] Figure 13F is a cross-sectional schematic diagram of the lead-out structure of the TSG of each deck including the storage device provided in the embodiment of this application;

[0150] Figure 14A is a schematic diagram of the layout of functional layers coupled to a single channel structure including storage devices, provided in an embodiment of this application.

[0151] Figure 14B is a schematic diagram of the voltage applied to each functional layer in the selected sub-channel structure during the read operation provided in the embodiment of this application;

[0152] Figure 14C is a schematic diagram of the voltage applied to each functional layer in the unselected subchannel structure during the read operation provided in the embodiment of this application;

[0153] Figure 14D is a schematic diagram of the voltage applied to each functional layer in the selected subchannel structure during the programming operation provided in the embodiment of this application;

[0154] Figure 14E is a schematic diagram of the voltage applied to each functional layer in the unselected sub-channel structure during the read operation provided in the embodiment of this application;

[0155] Figure 15A is a schematic diagram of the layout of functional layers coupled to a single channel structure, including storage devices, provided in an embodiment of this application.

[0156] Figure 15B is a schematic diagram of the voltage applied to each functional layer in the selected sub-channel structure during the read operation provided in the embodiment of this application;

[0157] Figure 15C is a schematic diagram of the voltage applied to each functional layer in the unselected subchannel structure during the read operation provided in the embodiment of this application;

[0158] Figure 15D is a schematic diagram of the voltage applied to each functional layer in the selected subchannel structure during the programming operation provided in the embodiment of this application;

[0159] Figure 15E is a schematic diagram of the voltage applied to each functional layer in the unselected sub-channel structure during the read operation provided in the embodiment of this application;

[0160] Figure 16 is a schematic diagram of the implementation flow of the operation method including the storage device provided in the embodiment of this application;

[0161] Figure 17 is a schematic diagram of an exemplary system including a memory system provided in an embodiment of this application;

[0162] Figure 18 is a schematic diagram of an exemplary memory card including a memory system provided in an embodiment of this application;

[0163] Figure 19 is a schematic diagram of an exemplary solid-state driver including a memory system provided in an embodiment of this application.

[0164] In the above figures (which are not necessarily drawn to scale), similar reference numerals may describe similar parts in different views. Similar reference numerals with different letter suffixes may indicate different examples of similar parts. The figures illustrate, by way of example and not limitation, the various embodiments discussed herein. Detailed Implementation

[0165] Exemplary embodiments of the present application will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present application are shown in the drawings, it should be understood that the present application can be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided to enable a more thorough understanding of the present application and to fully convey the scope of the present application to those skilled in the art.

[0166] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this application. However, it will be apparent to those skilled in the art that this application can be practiced without one or more of these details. In other instances, to avoid confusion with this application, some technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0167] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0168] It should be understood that spatial relation terms such as “below,” “under,” “below,” “below,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “below” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0169] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0170] In order to gain a more detailed understanding of the features and technical content of the embodiments of this application, the implementation of the embodiments of this application will be described in detail below with reference to the accompanying drawings. The accompanying drawings are for reference and illustration only and are not intended to limit the embodiments of this application.

[0171] The technological trend in three-dimensional (3D) NAND flash memory is to achieve higher storage density, better performance, and lower cost. Increasing the number of stacked layers in 3D NAND flash memory is an effective way to increase storage density and reduce the cost per unit capacity. However, increasing the number of layers leads to a gradual increase in the area occupied by the string driver (SD) circuit. This increased area, in turn, leads to a decrease in array efficiency, ultimately resulting in low utilization of the 3D NAND flash memory chip. Simultaneously, as the number of stacked layers increases, the minimum operating unit block size gradually increases, consequently weakening the performance of the 3D NAND flash memory.

[0172] Therefore, with the increase in the number of stacked layers of 3D NAND memory, how to improve the effective utilization of the array area and / or reduce the size of the memory block is an urgent problem to be solved.

[0173] In some embodiments, the effective utilization rate of the array region is improved by reducing the size of the word line drive circuit and thus reducing its occupied area; simultaneously, the performance of the 3D NAND memory chip is improved by reducing the number of finger memory regions contained in a single memory block and thus reducing the memory block size. However, reducing the number of finger regions in a single memory block leads to an increase in the length of the word line drive circuit within the memory block along the X-axis direction perpendicular to the bit line extension direction, resulting in an increase in the occupied area of ​​the word line drive circuit, which in turn reduces the effective utilization rate of the array region. Here, each memory block includes multiple finger memory regions arranged side by side along the Y-axis direction of the bit line extension direction, divided by the gate gap structure (GLS).

[0174] Figure 1 shows a schematic diagram of the layout of the peripheral circuit including the word line driving circuit in an embodiment of this application. A specific calculation method for the aforementioned array area utilization rate and memory block size is as follows: Array area utilization rate = number of BLs / (number of BLs located in the core area + number of SDs located in the area); Memory block size = number of WL layers * number of strings * number of BLs * TLC (3) or QLC (4). Here and thereafter, the array area utilization rate can be simply referred to as array efficiency. Here, each memory block includes multiple memory slabs arranged side-by-side in the Y-axis direction along the bit line extension direction, divided by the GLS and the top select gate isolation structure TSGCUT. The number of strings included in a memory block is the number of strings.

[0175] It should be noted that, for ease of description, the various directions involved in this application are uniformly defined here. In the embodiments of this application, the first direction can be the direction in which the gate layer and the dielectric layer are stacked in the stacked structure; the second direction can be the direction in which the bit lines are spaced apart; and the third direction can be the direction in which the bit lines extend. Both the second direction and the third direction are perpendicular to the first direction. In some specific embodiments, the second direction is perpendicular to the third direction. For example, the first direction can be the extension direction of the Z-axis shown in the figures; the second direction can be the extension direction of the X-axis shown in the figures; and the third direction can be the extension direction of the Y-axis shown in the figures.

[0176] Figure 2A shows a schematic diagram of a memory device architecture according to an embodiment of this application. In some embodiments, as shown in Figure 2A, the memory device includes a memory array and peripheral circuitry. The memory array includes an array region GB and a connection region SS. Exemplarily, the connection region is located in the middle of the array region. A stacked structure and a channel structure (not shown in Figure 2A) are disposed in the array region. The stacked structure includes alternately stacked gate layers and dielectric layers. A plurality of first conductive structures (also called word line connection structures or word line lead-out structures) are disposed in the connection region. Each first conductive structure is connected to a gate layer to lead out the gate layer (or word line WL) and connect it to the peripheral circuitry, specifically to the word line driving circuit SD in the peripheral circuitry. In this embodiment, the number of gate layers is the same as the number of SD layers, as shown in Figure 2A, both being N*1. In this embodiment, bit line layers and source layers (not shown in Figure 2A) are respectively disposed on opposite sides of the stacked structure along a first direction.

[0177] Figures 2B to 2E show schematic diagrams of the storage device architecture of embodiments of this application, from two to five. Figures 3A to 3C show schematic diagrams of the formation process of the storage device architecture of embodiments of this application, from one to three.

[0178] In some embodiments, as shown in FIG2B, the memory device includes a memory array and peripheral circuitry. The memory array includes N stacked structures arranged along a first direction. Each stack (shown as a deck in FIG2B) includes one gate layer (shown as WL in FIG2B). Each stacked structure has a bit line layer (shown as BL in FIG2B) and a source layer (shown as ACS in FIG2B) respectively disposed on both sides along the first direction. Two adjacent stacked structures along the first direction can share the same BL or ACS. The memory array may further include multiple first conductive structures, each of which is connected to a gate layer of at least two stacked structures (such as N decks) to lead out these connected gate layers for connection to the SD in the peripheral circuitry.

[0179] As shown in Figure 3A and Figure 2B, the architecture of the memory device can be obtained by dividing a stacked structure into N parts along the Y-axis (third direction), and then stacking these N parts along the Z-axis. It should be noted that the architecture of the memory device shown in Figure 2B only illustrates the array region, omitting the connection region. Furthermore, the total number of gate layers in Figure 2B is also N*1. The architecture of the memory device shown in Figures 2B and 3A will be referred to below as the array Y-axis folded architecture.

[0180] In some embodiments, as shown in FIG2C, the memory device includes a memory array and peripheral circuitry. The memory array includes N stacked structures arranged along a first direction. Each stack (shown as a deck in FIG2C) includes one gate layer (shown as WL in FIG2C). Each stacked structure has a bit line layer (shown as BL in FIG2C) and a source layer (shown as ACS in FIG2C) on both sides along the first direction. Two adjacent stacked structures along the first direction can share the same BL or ACS. The memory array may also have multiple first conductive structures, each of which is connected to a gate layer of at least two stacked structures (such as N decks) to lead out these connected gate layers for connection to the SD in the peripheral circuitry.

[0181] As shown in Figure 3B and Figure 2C, the architecture of the memory device can be obtained by dividing a stacked structure into N parts along the X-axis (the second direction), and then stacking these N parts along the Z-axis. It should be noted that the architecture of the memory device shown in Figure 2C only illustrates the array region, omitting the connection region. Furthermore, the total number of gate layers in Figure 2C is also N*1. The architecture of the memory device shown in Figures 2C and 3B will be referred to as the array X-axis folded architecture in the following text.

[0182] It is understandable that if the total number of array position lines in an undivided stack structure is Q KB (where Q is a positive integer, such as 16KB), then the total number of array position lines in the example of Figure 2B is still Q KB (such as 16KB), while the total number of array position lines in the example of Figure 2C is Q / N KB (such as 16 / N KB).

[0183] In some embodiments, as shown in FIG2D, the memory device includes a memory array and peripheral circuitry. The memory array includes a plurality of M memory modules stacked along a first direction. Each memory module (schematically represented as "Model" in FIG2D) includes N stacked structures. Each N stacked structure can be N stacked structures of the array Y-axis folded architecture shown in FIG2B, and each N stacked structure can also be N stacked structures of the array X-axis folded architecture shown in FIG2C. The memory array may also include a plurality of first conductive structures, each first conductive structure being connected to a gate layer of at least two stacked structures (e.g., N decks) to lead out these connected gate layers to SD connections in the peripheral circuitry. It should be noted that the architecture of the memory device shown in FIG2D only illustrates the array region and ignores the connection region. The architecture of the memory device shown in FIG2D is referred to below as the array X-axis + Y-axis folded architecture.

[0184] The array folding structure in the X-axis + Y-axis direction can be formed in at least two ways.

[0185] In some specific embodiments, as shown in Figure 3C, N stacked structures are first folded in the X-axis direction to obtain a storage module, and M storage modules are obtained accordingly. The M storage modules are then folded along the Y-axis to obtain M storage modules. This scheme is referred to as X-axis + Y-axis folding scheme 1.

[0186] In some specific embodiments, N stacked structures are first folded along the Y-axis to obtain a storage module, and M storage modules are obtained accordingly. The M storage modules are then folded along the X-axis to obtain M storage modules. This scheme is referred to as X-axis + Y-axis folding scheme 2.

[0187] It is understandable that the folding order differs between the two array X-axis + Y-axis folding architectures described above. Taking the generation of two storage modules as an example, Scheme 1 divides an undivided stacked structure into 4*2=8 parts along the X-axis and Y-axis, while Scheme 2 divides an undivided stacked structure into 2*4=8 parts along the X-axis and Y-axis. Although both involve dividing into 8 parts and stacking the 8 parts along the Z-axis, if the dimensions of the undivided stacked structure itself are different along the X-axis and Y-axis, the final dimensions of each part in Scheme 1 and Scheme 2 may differ.

[0188] In some embodiments, as shown in FIG2E, the storage device includes a memory array and peripheral circuitry. The memory array includes two storage planes (Plane 0 and Plane 1 shown in FIG2E) arranged side-by-side along the X-axis direction, i.e., the second direction. Each storage plane can be a stacked structure of an array Y-axis folded architecture shown in FIG2B (in which case the total number of bit lines per storage plane is Q KB, such as 16 KB); each storage plane can also be a stacked structure of an array X-axis folded architecture shown in FIG2C (in which case the total number of bit lines per storage plane is Q / N KB, such as 16 / N KB); each storage plane can also be a stacked structure of an array X-axis + Y-axis folded architecture shown in FIG2D (for folding first in the X-axis direction and then in the Y-axis direction, the total number of bit lines per storage plane is Q / N KB, such as 16 / N KB).

[0189] The memory array also includes a connection region located between the two memory planes. This connection region contains multiple conductive structures shared by the two memory planes. One of these conductive structures can be connected to a gate layer of each of the multiple stacked structures (e.g., N decks) in the two memory planes, for leading the gate layer out to connect to the storage devices (SDs) in the peripheral circuitry. Thus, the number of SDs in Figure 2D can be 1. The architecture of the memory device shown in Figure 2E is referred to below as a memory plane merging architecture.

[0190] It is understandable that in the array Y-axis folding architecture shown in Figure 2B, the word line lead-out structures (i.e., the first conductive structures) in the N decks are shared, achieving a reduction of the SD area by N times, thereby improving the effective utilization of the array area while increasing the number of stacking layers. In the array X-axis folding architecture shown in Figure 2C, the total number of BLs is reduced to 1 / N of the original number before folding. The folding and word line lead-out structures (i.e., the first conductive structures) are shared, achieving a reduction of the SD area by N times, and the memory block area is also reduced by 1 / N. In the array X-axis + Y-axis folding architecture shown in Figure 2D, the advantages of the two architectures are combined, which can both improve the effective utilization of the array area and reduce the memory block area. The memory surface merging architecture shown in Figure 2E further shares the word line lead-out structures, further improving the effective utilization of the array area. In other words, the above four memory device architectures successfully resolve the contradiction in the architecture shown in Figure 2A where reducing the number of fingers to reduce the memory block area leads to an increase in the SD area.

[0191] The implementation details of the four memory device architectures described above will be elaborated below. It should be noted that the implementation details discussed below can be applied to the aforementioned four memory device architectures.

[0192] This application provides a storage device comprising: a plurality of first stacked structures stacked together; each first stacked structure including a plurality of first conductive layers and first dielectric layers alternately disposed along a first direction; a first conductive structure extending along the first direction and connected to a first conductive layer of at least two of the plurality of first stacked structures; a plurality of channel structures penetrating the plurality of first stacked structures; and at least one semiconductor layer connected to a channel structure in at least one of the first stacked structures.

[0193] In this application embodiment, the first stacked structure can be understood as the stacked structure (deck) in the embodiments of the aforementioned four memory device architectures. In some embodiments, the material of the first conductive layer may include conductive materials, including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polycrystalline silicon, doped silicon, silicides, or any combination thereof. In some embodiments, each first conductive layer includes a metal layer, such as a tungsten layer. In some embodiments, each first conductive layer includes a doped polycrystalline silicon layer. In some embodiments, the material of the first dielectric layer may include an oxide. In some embodiments, the material of the first dielectric layer includes silicon oxide.

[0194] In some embodiments, a channel structure spanning each of a plurality of first stacked structures may include a gate dielectric layer, a charge storage layer, a tunneling layer, and a channel layer. In some specific embodiments, the channel structure may have a cylindrical shape (e.g., a pillar shape). In some embodiments, the channel layer, tunneling layer, charge storage layer, and gate dielectric layer are arranged radially from the center of the pillar toward the outer surface of the pillar in this order. The tunneling layer may include silicon oxide, silicon oxynitride, or any combination thereof. The charge storage layer may include silicon nitride, silicon oxynitride, or any combination thereof. The gate dielectric layer may include silicon oxide, silicon oxynitride, a high dielectric constant (high k) dielectric, or any combination thereof. In some embodiments, the tunneling layer, charge storage layer, and gate dielectric layer may be collectively referred to as a memory film, which may include a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0195] In this embodiment, the semiconductor layer can be used as a source layer, which is connected to the channel layer in the channel structure. In some embodiments, the material of the semiconductor layer may include various semiconductor materials. In some embodiments, the material of the semiconductor layer includes polycrystalline silicon.

[0196] In some embodiments, the memory device may further include at least one second conductive layer, which is connected to a channel structure of at least one first stacked structure; the second conductive layer includes a plurality of bit lines spaced apart along a second direction and extending along a third direction; both the second direction and the third direction are perpendicular to the first direction. In embodiments of this application, a semiconductor layer and a second conductive layer connected to a channel structure in the same first stacked structure are respectively disposed on both sides of the first stacked structure along the first direction.

[0197] In some embodiments, at least one semiconductor layer is located between two adjacent first stacked structures and is connected to the channel structures in both adjacent first stacked structures.

[0198] In some embodiments, as shown in FIG4A, a second conductive layer (indicated by BL in FIG4A) and a semiconductor layer (indicated by ACS in FIG4A) are respectively disposed on both sides of the first stacked structure along the first direction, and a second conductive layer and a semiconductor layer are disposed between two adjacent first stacked structures along the first direction.

[0199] In some embodiments, as shown in Figures 4B and 4C, a second conductive layer (indicated by BL in Figures 4B and 4C) and a semiconductor layer (indicated by ACS in Figures 4B and 4C) are respectively disposed on both sides of the first stacked structure along the first direction, and a common second conductive layer or a common semiconductor layer is disposed between two adjacent first stacked structures along the first direction. It should be noted that this common second conductive layer or common semiconductor layer is connected to the channel layers of the channel structures in the first stacked structures located on both sides of it, and is shared by the channel structures in the first stacked structures located on both sides of it.

[0200] In some other embodiments, if the second semiconductor layer and the semiconductor layer are not shared, then two second conductive layers or two common semiconductor layers may be provided between two adjacent first stacked structures along the first direction, with each of the two second conductive layers or each of the two common semiconductor layers belonging to the first stacked structures on both sides respectively.

[0201] In some embodiments, each of the first conductive layers in a first stacked structure includes a plurality of gate layers, or word lines. In some embodiments, each of the first conductive layers in a first stacked structure further includes a top select gate layer and a bottom select gate layer. The gate layer in each first stacked structure located away from the semiconductor layer can serve as the top select gate layer of the corresponding stacked structure, and the gate layer in each stacked structure located near the semiconductor layer can serve as the bottom select gate layer of the corresponding stacked structure. The gate layer between the top select gate layer and the bottom select gate layer can serve as a word line.

[0202] In this embodiment, the first conductive structure may include a word line lead-out structure. One first conductive structure is connected to a gate layer of at least two first stacked structures, respectively, for leading out the gate layer (or word line WL) and connecting it to peripheral circuits, specifically to a word line driving circuit SD in the peripheral circuits. In some embodiments, the first stacked structures include N structures, and one first conductive structure is connected to a first conductive layer in one of the M first stacked structures out of the N stacked structures; that is, one first conductive structure is connected to the M first conductive layers corresponding to the M stacked structures. Here, M and N are both positive integers, and N ≥ M ≥ 2.

[0203] In some embodiments, the first conductive structure may connect to a gate layer of two adjacent first stacked structures (decks), a gate layer of spaced-apart first stacked structures (decks), or a gate layer of all first stacked structures (decks). The first conductive structure may connect to a gate layer of one deck and pass through that deck, and connect to a gate layer of an adjacent deck. Alternatively, the first conductive structure may pass through all decks and connect to the gate layers of all decks.

[0204] In some embodiments, the first conductive structure is connected to a first conductive layer of each of the plurality of first stacked structures.

[0205] In some specific embodiments, the first conductive layer connected to the same first conductive structure in different first stacked structures is at the same distance from the semiconductor layer connected to the channel structure in the corresponding first stacked structure.

[0206] In this embodiment of the application, a first conductive structure CT1 is connected to a first conductive layer of each of the multiple first stacked structures, and the distance between the first conductive layer connected in each first stacked structure and the semiconductor layer or second semiconductor layer connected to the channel structure in the corresponding first stacked structure is the same.

[0207] For example, as shown in Figures 4A and 4C, each first stacked structure includes l gate layers. Taking l=5 as an example, the gate layers from the second conductive layer (BL) to the semiconductor layer (ACS) of each first stacked structure are WL1, WL2, WL3, WL4, and WL5, respectively. When the first conductive structure CT1 connects to the gate layers of multiple decks, the first conductive structure CT1 can connect to the same gate layer of different decks. For example, one of the multiple first conductive structures CT1 connects to the WL2 of all the first stacked structures, and another first conductive structure CT2 connects to the WL4 of all the stacked structures.

[0208] In some specific embodiments, the distance between the first conductive layer connected to the same first conductive structure in two different first stacked structures and the semiconductor layer connected to the channel structure in the corresponding first stacked structure is different.

[0209] In this embodiment, a first conductive structure is connected to a first conductive layer of each of the plurality of first stacked structures, and the distance between the first conductive layer connected in at least two first stacked structures and the semiconductor layer or second semiconductor layer connected to the channel structure in the corresponding first stacked structure is different.

[0210] For example, as shown in FIG4B, each first stack structure includes l gate layers. Taking l=5 as an example, the gate layers from the second conductive layer (BL) to the semiconductor layer (ACS) of each first stack structure are WL1, WL2, WL3, WL4, and WL5, respectively. When the first conductive structure CT1 connects to the gate layers of multiple decks, the first conductive structure CT1 can be connected to different gate layers of different decks. For example, one of the multiple first conductive structures CT1, CT1-3, is connected to WL2 of deck 1, and CT1-3 is connected to WL4 of deck 2. Another first conductive structure CT1-4 among the multiple first conductive structures CT1 is connected to WL4 of deck 1, and CT2 is connected to WL2 of deck 2.

[0211] In some embodiments, the first conductive structure is connected to a first conductive layer in each of the plurality of first stacked structures, so that the number of first conductive layers connected to a first conductive structure is equal to the number N of decks.

[0212] In some embodiments, different first conductive layers of the first stacked structure are connected to different first conductive structures. That is, different gate layers of the deck are led out through different first conductive structures.

[0213] In some embodiments, the number of first conductive structures is the same as the number of first conductive layers contained in the first stacked structure; the total number of first conductive layers contained in the plurality of first stacked structures is greater than twice the number of first conductive structures.

[0214] In this embodiment, the positional relationship between the first region of the plurality of first stacked structures and the second region of the first conductive structure can include a variety of factors.

[0215] In some embodiments, a plurality of first stacked structures are disposed in a first region S1, and a plurality of first conductive structures are disposed in a second region S2, wherein the second region S2 is located in the middle of the first region S1.

[0216] In some embodiments, a plurality of first stacked structures are disposed in a first region S1, and a plurality of first conductive structures are disposed in a second region S2, wherein the second region S2 is located on at least one side of the first region S2 along the two sides perpendicular to the first direction.

[0217] Here, the first region can be understood as the aforementioned array region GB, and the second region can be understood as the aforementioned connection region SS.

[0218] In some implementations, along the X-axis direction, i.e. the second direction, a second region S2 is located on one side of a first region S1 (as shown on the right side in Figure 5A), and all the first conductive structures are located on the same side of the first region. The area of ​​the second region S2 is smaller, and the area utilization rate is higher.

[0219] In some implementations, along the X direction, i.e. the second direction, two second regions S2 are located on opposite sides of a first region S1. Part of the first conductive structure is located on the left side of the first region S1, and part of the first conductive structure is located on the right side of the first region S1. The first conductive structures connected to all gate layers of the same deck are located on the same side of the array region, and the first conductive structures corresponding to any adjacent deck are located on different sides of the first region S1. For example, as shown in FIG5B, when N=4, the first conductive structures connected to the gate layers of deck1 and deck3 are all located on the right side of the first region S1, and the first conductive structures connected to the gate layers of deck2 and deck4 are all located on the left side of the first region S1.

[0220] In some embodiments, along the X direction (the second direction), two second regions S2 are located on opposite sides of a first region S1. A portion of the first conductive structure is located on the left side of the first region S1, and a portion of the first conductive structure is located on the right side of the first region S1. Furthermore, the first conductive structures connected to all gate layers of the same deck are located on the same side of the first region S1. At least two adjacent decks may have their corresponding first conductive structures located on the same side of the first region S1. For example, as shown in FIG5C, when N=4, all the first conductive structures connected to the gate layers of deck 1 are located on the right side of the first region S1, and all the first conductive structures connected to the gate layers of deck 3 are located on the left side of the first region S1.

[0221] In some embodiments, along the X direction (the second direction), two second regions S2 are located on opposite sides of a first region S1. A portion of the first conductive structure is located on the left side of the first region S1, and another portion is located on the right side. Furthermore, the first conductive structures connected to all gate layers of the same deck are located on different sides of the first region S1. For example, as shown in FIG5D, when N=4, a portion of the first conductive structures connected to a portion of the gate layers of deck 1 are located on the left side of the first region S1, and another portion of the first conductive structures connected to another portion of the gate layers of deck 1 are located on the right side of the first region S1. Thus, the area of ​​the second region S2 is smaller, resulting in higher area utilization.

[0222] It should be noted that in other embodiments of this application, the arrangement of the first conductive structure in the second region may also be a combination of the above-mentioned arrangement methods.

[0223] In some embodiments, the first conductive structure at least partially penetrates all of the first stacked structures and is connected to a gate layer of each of the partial first stacked structures. In some embodiments, the first conductive structure may completely penetrate all of the first stacked structures and be connected to a gate layer of each of the partial first stacked structures. In the embodiments of this application, the first conductive structure may include various structural forms, some of which are described below.

[0224] In some embodiments, the cross-sectional shape of the plurality of first stacked structures along the first direction includes a stepped shape; each step in the stepped shape corresponds to an adjacent first conductive layer and a first dielectric layer; the first conductive structure extends along the first direction in the first stacked structure and is connected to at least two steps where a first conductive layer of at least two first stacked structures is located.

[0225] In this embodiment, the connection of gate layers of different decks can be achieved by a step-like manner, as shown in FIG6A. A step structure is formed in the second region of each first stack structure. The step structure has a step shape and includes multiple steps. Each step corresponds to an adjacent first conductive layer and a first dielectric layer. Each first conductive structure CT1 connects to the gate layer corresponding to a step of each of the multiple decks.

[0226] It should be noted that in this embodiment, each step corresponds to a gate layer, and the arrangement of the step structure is not limited; it can present a regular or irregular increasing or decreasing arrangement. In this embodiment, the first conductive structure can be located in the first stacked structure, that is, the second region is in the first stacked structure.

[0227] In some embodiments, the storage device further includes a second stacked structure, the second stacked structure including an isolation layer and a second dielectric layer alternately disposed along a first direction; the first conductive structure includes a first lead-out portion and a plurality of first connection portions; the first lead-out portion extends along the first direction in the second stacked structure and is connected to the plurality of first connection portions; each first connection portion is located in an isolation layer and is connected to a first conductive layer of a corresponding first stacked structure in at least two first stacked structures.

[0228] In some embodiments, the material of the isolation layer includes, but is not limited to, silicon nitride, and the material of the second dielectric layer includes, but is not limited to, silicon oxide. In this embodiment, the first conductive layer and the isolation layer are disposed on the same layer, and the first dielectric layer and the second dielectric layer are disposed on the same layer. The first conductive structure may be located in the second stacked structure, that is, the second region is in the second stacked structure. The second stacked structure may be located in the middle or on both sides of the first stacked structure.

[0229] In this embodiment, the first lead-out portion may penetrate all the first stacked structures along the first direction or only penetrate to the first conductive layer that needs to be connected to the corresponding first stacked structure; the first lead-out portion may be solid or hollow; the first lead-out portion may have the same aperture or a varying aperture along the first direction.

[0230] In some embodiments, the first lead-out portion includes a dielectric structure extending along a first direction and a peripheral conductive layer surrounding the dielectric structure; the peripheral conductive layer is connected to a plurality of the first connection portions.

[0231] In this embodiment, the WL connection of different decks is achieved through vias. For example, as shown in FIG6B, the first lead-out portion CT1-A can be a segmented structure. Taking three first stacked structures as an example, each first stacked structure has a gate layer connected to the same first lead-out portion CT1-A. The first lead-out portion CT1-A includes a first sub-segment, a second sub-segment, and a third sub-segment. The first sub-segment is located above the gate layer corresponding to the uppermost first stacked structure; the second sub-segment is located between the gate layer corresponding to the uppermost first stacked structure and the gate layer corresponding to the middle first stacked structure; and the third sub-segment is located between the gate layer corresponding to the middle first stacked structure and the gate layer corresponding to the lowermost first stacked structure. The dimension of the first sub-segment along the second direction is larger than the dimension of the second sub-segment along the second direction, and the dimension of the second sub-segment along the second direction is larger than the dimension of the third sub-segment along the second direction. The gate layer corresponding to each first stacked structure is connected to a first connection portion CT1-B extending along the second direction, and connected to the first lead-out portion CT1-A through the corresponding first connection portion CT1-B.

[0232] In some embodiments, the first lead-out portion includes a conductive post.

[0233] In this embodiment, the WL connection of different decks is achieved through SCT. For example, as shown in FIG6C, the first lead-out portion CT1-A includes conductive pillars extending through multiple second stacked structures. A gate layer of each first stacked structure is connected to the conductive pillars through a first connection portion CT1-B extending in a second direction. The conductive pillars are filled with conductive material, such as tungsten.

[0234] In some embodiments, the memory device further includes peripheral circuitry; the peripheral circuitry includes word line driving circuitry; at least two first conductive layers of the first stacked structures are interconnected through the first conductive structures and connected to the same word line driving circuitry SD.

[0235] In this embodiment, the peripheral circuit may include multiple word line driving circuits. At least two decks' first conductive layers are interconnected along a first direction and then connected to the same SD. That is, the same first conductive structure connects multiple interconnected gate layers in different decks to the same SD, and these interconnected gate layers can share a single SD. It is understood that allowing multiple gate layers to share a single SD can reduce the total number of SDs.

[0236] In some embodiments, the area where the word line driving circuit is disposed is aligned with the area where the first conductive structure is disposed along a first direction. This reduces the trace distance between them, resulting in lower resistivity, lower power consumption, and lower delay between the word line driving circuit and the corresponding gate layer.

[0237] In some embodiments, the storage device has a first number of first stacked structures, the first stacked structures having a second number of first conductive layers; the storage device has a third number of word line driving circuits, the third number being less than the product of the first number and the second number.

[0238] Here, the first quantity refers to the number of first stacked structures, the second quantity refers to the number of first conductive layers contained in each first stacked structure, and the third quantity refers to the number of SDs. In embodiments of this application without deck stacking (shown in FIG2A), the number of SDs and the number of WLs (gate layers) are the same. In embodiments of this application with deck stacking (shown in FIG2B, 2C, and 2D), the number of SDs can be the same as the number of first conductive structures, and the number of SDs is smaller than the total number of WLs; the number of WLs is N times the number of SDs (deck number, i.e., the first quantity). In some embodiments, the first conductive layer is WL, then the total number of WLs = N * the number of SDs.

[0239] In some embodiments, there is at least one second conductive layer and a plurality of second conductive structures; one second conductive layer is connected to a channel structure of at least one first stacked structure; one second conductive layer includes a plurality of bit lines spaced apart along a second direction and extending along a third direction; both the second direction and the third direction are perpendicular to the first direction; the second conductive structure extends along the first direction in the first stacked structure and is connected to a bit line of at least one second conductive layer.

[0240] In some embodiments, a plurality of first stacked structures are disposed in a first region, and a plurality of second conductive structures are disposed in a third region, the third region being located on at least one side of the first region along a third direction.

[0241] Here, the second conductive structure is the lead-out structure corresponding to the bit line. The structural form and setting position of the second conductive structure will be further described later.

[0242] In some embodiments, the memory device further includes a third conductive structure; a plurality of first conductive layers in the first stacked structure include a top selected gate layer and a gate layer; the top selected gate layer is located at one end of the respective first stacked structure along a first direction away from the semiconductor layer connected to the channel structure in the respective first stacked structure; the third conductive structure extends along the first direction in the first stacked structure and is connected to the top selected gate layer included in at least one of the plurality of first stacked structures; the first conductive structure is connected to a gate layer of at least two of the plurality of first stacked structures.

[0243] In some embodiments, a plurality of first stacked structures are disposed in a first region, all first conductive structures are disposed in a second region, and all third conductive structures are disposed in a fourth region; the fourth region is located between the first region and the second region.

[0244] In some embodiments, the third conductive structure includes a second lead-out portion, a second connection portion, and a contact portion; the second lead-out portion extends along a first direction and is connected to the second connection portion; the second connection portion extends along a second direction and is connected to the contact portion; the contact portion extends along the first direction and is connected to the top selected gate layer; the second direction is perpendicular to the first direction.

[0245] Here, the third conductive structure is the lead-out structure corresponding to the top selected gate layer. The structural form and setting position of the third conductive structure will be further described later.

[0246] In some embodiments, a plurality of first stacked structures stacked together constitute a storage surface; the storage device includes at least two storage surfaces; two of the at least two storage surfaces are arranged side by side along a second direction; the second direction is perpendicular to the first direction; a first conductive structure is located between the two storage surfaces and is connected to a first conductive layer of a different first stacked structure in at least one storage surface.

[0247] In this embodiment, the first conductive structure is located between two storage surfaces, but it is not limited whether the two storage surfaces share the first conductive structure. That is, a first conductive structure can connect the first conductive layers of different decks of a storage surface, and a first conductive structure can also connect the first conductive layers of different decks of each of two parallel storage surfaces.

[0248] In some embodiments, the memory device further includes peripheral circuitry; the peripheral circuitry includes a plurality of word line driving circuits; different memory surfaces are interconnected with each other and connected to the same word line driving circuit at the same location along a first direction.

[0249] Here, the description of the storage surface can be referred to in Figure 2E above. The first conductive layer at the same position along the first direction on different storage surfaces can be understood as the first conductive layer in the same layer on different storage surfaces. The first conductive layer in the same layer is connected to the same first conductive structure and is connected to the same SD through the same first conductive structure.

[0250] As previously mentioned, each first stacked structure is provided with its corresponding semiconductor layer (source layer) and second conductive layer (a layer formed by multiple bit lines, which may also be referred to as a bit line layer in the following text). In the embodiments of this application, the semiconductor layer or the second conductive layer can be shared between two adjacent first stacked structures along the first direction.

[0251] In some embodiments, at least one semiconductor layer is located between two adjacent first stacked structures and is connected to the channel structures in both adjacent first stacked structures.

[0252] In some embodiments, at least one of the second conductive layers is located between two adjacent first stacked structures and is connected to the channel structures in both adjacent first stacked structures.

[0253] In some embodiments, as shown in Figures 7A and 7B, the memory device includes a first stacked structure located in the array region GB (first region) and a second stacked structure located in the connection region SS (second region). The first stacked structure includes alternating stacked first conductive layers and first dielectric layers, and the second stacked structure includes alternating stacked isolation layers and second dielectric layers. The first conductive layer and isolation layer are disposed in the same layer, and the first dielectric layer and second dielectric layer are disposed in the same layer. The memory device includes a plurality of first stacked structure decks stacked along a first direction (four decks are shown in Figure 7B). Adjacent decks may share a bit line layer (such as the bit line layer between deck 2 and deck 3). The bit lines of all decks along the first direction (all bit lines connected in the same channel structure) may be interconnected. The bit line connection can be through conductive pillars (not shown in Figures 7A and 7B, refer to the dashed lines in Figure 6C), through a structure similar to that in a channel (such as a dummy channel), or through a structure in a gate gap structure.

[0254] In some implementations, two adjacent decks along the first direction may share a source layer ACS. The source layers of all decks may or may not be interconnected. The source layers of all decks may be interconnected through channel layers in a channel structure.

[0255] In some embodiments, as shown in Figures 8A and 8B, the memory device includes a plurality of channel structures CH located in the array region GB (first region). The channel structures CH can extend through two adjacent stacked structures deck. The channel structure may include a channel layer and functional layers surrounding the channel layer. The functional layers include a tunneling layer, a charge trapping layer, and a charge blocking layer arranged from the inside out. In some embodiments, each end of the channel structure is connected to a bit line BL. A common source layer ACS (such as the ACS between deck 1 and deck 2, and the ACS between deck 3 and deck 4) is provided between two adjacent first stacked structures. The common source ACS is connected to the channel layer of the channel structure. The material of the common source ACS includes, but is not limited to, polysilicon.

[0256] In some implementations, the functional layers of the channel structure can be discontinuous, and the functional layers include a first functional layer located above the common source ACS and a second functional layer located below the common source ACS, with the first functional layer and the second functional layer isolated from each other by the common source layer.

[0257] In some embodiments, as shown in Figures 8A and 8B, the bit lines BL connected to both ends of the channel structure can be led out and connected to the peripheral circuit CMOS, or they can be connected and then led out from one of the bit lines before being connected to the peripheral circuit, or other methods can be used to implement the bit lines and the peripheral circuit. In some embodiments, a connection structure J is also provided between the bit line connected to the channel structure and the corresponding channel structure on the side away from the peripheral circuit. The material of this connection structure can include doped polysilicon, or other materials used to achieve ohmic contact between the channel structure and the bit line.

[0258] In some embodiments, as shown in Figures 9A and 9B, the memory device further includes multiple second stacked structures and multiple third stacked structures in addition to the first stacked structure. The second and third stacked structures are arranged along the Y-axis and are both located within the connection region SS. The third stacked structure includes alternately stacked third conductive layers and third dielectric layers, and the second stacked structure includes alternately stacked isolation layers and second dielectric layers. The first conductive layer, second conductive layer, and isolation layer are on the same layer, as are the first dielectric layer, second dielectric layer, and third dielectric layer. The memory device may also include a gate gap structure (GLS) extending along the X-axis and passing through the third stacked structure along the Z-axis. The memory device may also include virtual channel structures (DCHs) located on both sides of the GLS. The DCHs may be made of the same material as the CHs or different materials, such as being entirely filled with dielectric layers.

[0259] In some embodiments, as shown in Figures 9A and 9B, a first conductive structure CT1 penetrating through multiple second stacked structures can be connected to a first conductive layer of each of the multiple first stacked structures and to a third conductive layer of each of the multiple third stacked structures. In some embodiments, an insulating medium is also provided on the outside of the first conductive structure CT1, so that the first conductive structure CT1 is connected to a first conductive layer / third conductive layer of the first stacked structure / third stacked structure, and is isolated from the other conductive layers of the first stacked structure / third stacked structure.

[0260] This application provides a storage device comprising: a plurality of first stacked structures stacked together; each first stacked structure including a plurality of first conductive layers and first dielectric layers alternately disposed along a first direction; a plurality of channel structures; the channel structures penetrating the plurality of first stacked structures; at least one semiconductor layer; the semiconductor layer being connected to the channel structure in at least one first stacked structure; at least one second conductive layer; a second conductive layer being located between two adjacent first stacked structures and connected to the channel structure in at least one first stacked structure; a semiconductor layer and a second conductive layer connected to the channel structure in the same first stacked structure being disposed on opposite sides of the first stacked structure along the first direction.

[0261] Here, the first stacked structure, the first conductive layer, the first dielectric layer, the channel structure, the semiconductor layer, and the second conductive layer can all be understood with reference to the corresponding structures in the foregoing embodiments, and will not be repeated here.

[0262] In some embodiments, the second conductive layer includes a plurality of bit lines spaced apart along a second direction and extending along a third direction; the second direction intersects the third direction and is perpendicular to the first direction; a plurality of second conductive structures; the second conductive structures extend along the first direction in the first stack structure and are connected to a bit line of at least one second conductive layer.

[0263] In some embodiments, the second conductive structure includes a conductive post extending along a first direction.

[0264] Here, the second conductive layer can be understood as a bit line layer. The bit line layer may include multiple bit lines spaced apart along the X-axis and extending along a third direction. The second conductive structure is the lead-out structure corresponding to the bit line. In some embodiments, the bit line lead-out structure may penetrate one or more first stacked structures in the bit line lead-out direction. That is, the bit line may be led out in the form of a through silicon contact (TSC). The TSC penetrates multiple first stacked layers and connects to the bit line BL in the common bit line region (the region between deck2 and deck3 shown in Figures 7B and 8B) (the TSC penetrates one or more first stacked structures on the bit line lead-out side).

[0265] In some embodiments, different bit lines connected to different first stacked structures through the same channel structure are all connected to the same second conductive structure.

[0266] Here, the same channel structure can be understood as a channel structure that extends along the first direction and penetrates all the first stacked structures. Different bit lines connected by the same channel structure are all connected to the same second conductive structure. This situation can be applied to the Y-axis folding and XY-axis folding architecture of the memory device involved in Figures 2B and 2D above, which will be further explained in the following examples.

[0267] In some specific embodiments, at least one of the plurality of second conductive layers is located between two adjacent first stacked structures and is connected to the channel structures in both adjacent first stacked structures.

[0268] In this embodiment of the application, when bit lines BL interconnects are led out in different first stacked structures, the bit line layers between two adjacent first stacked structures can be shared.

[0269] In some specific embodiments, the storage device further includes peripheral circuitry; the peripheral circuitry includes a page cache; and multiple second conductive structures are connected to the same page cache PB.

[0270] In this embodiment of the application, when different bit lines connected to different first stacked structures that pass through the same channel structure are all connected to the same second conductive structure, the bit lines of different decks are respectively led out to the same page cache. In the memory device architecture folded along the Y-axis direction in FIG2B, multiple second conductive structures can be connected to the same PB.

[0271] In some embodiments, different bit lines connected by different first stacked structures through the same channel structure are connected to different second conductive structures.

[0272] Here, the same channel structure can be understood as a channel structure that extends along the first direction and runs through all the first stack structures. Different bit lines connected by the same channel structure are connected to different second conductive structures. This situation can be applied to the array Y-axis folding architecture and memory plane merging architecture shown in Figures 2C and 2E above, and will be further explained in the following examples.

[0273] In some specific embodiments, the dimensions of the second conductive layer corresponding to different first stacking structures are different along the third direction; the different second conductive structures connected to the second conductive layers corresponding to different first stacking structures are arranged sequentially along the third direction.

[0274] In this embodiment of the application, when bit lines BL in different first stacked structures are led out, the different second conductive structures connected to the second conductive layers corresponding to the different first stacked structures are arranged sequentially along a third direction (i.e., the bit line extension direction). That is, the regions of the multiple second conductive structures corresponding to each first stacked structure along the first direction are arranged sequentially along a third direction.

[0275] In some specific embodiments, the storage device further includes peripheral circuitry; the peripheral circuitry includes a plurality of page caches; a second conductive structure connected to a bit line of the same second conductive layer is connected to the same page cache among the plurality of page caches; and a second conductive structure connected to bit lines of different second conductive layers is connected to different page caches among the plurality of page caches.

[0276] In some specific embodiments, the area where the page cache is set is aligned with the area where the plurality of first stack structures are set along a first direction.

[0277] In this embodiment, when different bit lines connected to different first stacked structures passing through the same channel structure are all connected to the same second conductive structure, the bit lines of different decks are led out to different page buffers. As shown in Figure 2C above, multiple second conductive structures in the array X-axis folding architecture can be connected to different page buffers (PBs). In this case, the number of PBs can be the same as the number of decks, and the bit lines of the same deck are led out to the same PB.

[0278] In some embodiments, a plurality of first stacked structures are disposed in a first region, and a plurality of second conductive structures are disposed in a third region, wherein the third region is located on at least one side of the first region along a third direction.

[0279] In this embodiment of the application, the area where the first stacked structure is located is the first region, the area where the second conductive structure, i.e. the bit line lead-out structure, is located is the third region, and the second region where the first conductive structure, i.e. the word line lead-out structure, is located is the second region. The second region and the third region are located on different sides of the first region. Specifically, the second region is located on at least one side of the two sides of the first region along the second direction, and the third region is located on at least one side of the two sides of the first region along the third direction.

[0280] It is understandable that for the array Y-axis folded architecture shown in Figure 2B, compared to the foldless memory device architecture shown in Figure 2A, the number of black bars (BLs) remains unchanged (e.g., the number of BLs is between 130K and 160K), but the number of white gates (SDs) decreases. For the array X-axis folded architecture shown in Figure 2C, compared to the foldless memory device architecture shown in Figure 2A, the number of BLs becomes 1 / N (e.g., the number of BLs is between (130K and 160K) / N, where N is the number of decks). For the array X-axis + Y-axis folded architecture shown in Figure 2D, its number of BLs is the same as that in the array X-axis folded architecture shown in Figure 2C, but the lead-out structures corresponding to the bit lines and the lead-out structures corresponding to the top selected gate layer are different.

[0281] In some embodiments, a plurality of first stacked structures stacked together constitute a storage module; the storage device includes at least two storage modules; two of the at least two storage modules are stacked together along a first direction; the storage device further includes a fourth conductive structure; different bit lines corresponding to different first stacked structures through which the same channel structure passes are all connected to different second conductive structures; a plurality of second conductive structures corresponding to the first stacked structures specified in different storage modules through which the same channel structure passes are interconnected through the fourth conductive structure.

[0282] Here, the description of the storage module can be found in Figure 2D above. In this embodiment, within the same storage module, different bit lines corresponding to a channel structure in different decks are brought out separately; in different storage modules, different bit lines corresponding to a channel structure in a specified deck are brought out together.

[0283] Here, the deck is specified in relation to the folding rules. Taking folding in the X-axis direction followed by folding in the Y-axis direction as an example, referring to the left half of Figure 3C, the channel structure in Model 1 and Model 2 is led out from different bit lines in different decks. The first left-hand deck in Model 1 and the first left-hand deck in Model 2 are two decks led out together by the specified bit lines. The second left-hand deck in Model 1 and the second left-hand deck in Model 2 are two decks led out together by the specified bit lines. The third left-hand deck in Model 1 and the third left-hand deck in Model 2 are two decks led out together by the specified bit lines. The fourth left-hand deck in Model 1 and the fourth left-hand deck in Model 2 are two decks led out together by the specified bit lines.

[0284] In this embodiment of the application, the second conductive structures of two decks led out together by the specified bit lines are connected by a fourth conductive structure, which is located on either side of the plurality of first stacked structures along the first direction.

[0285] In some embodiments, at least one of the plurality of semiconductor layers is located between two adjacent first stacked structures and is connected to the channel structures in both adjacent first stacked structures.

[0286] In some embodiments, two adjacent first stacked structures in a plurality of first stacked structures form a stacked structure group; the storage device includes a plurality of semiconductor layers; the plurality of semiconductor layers are respectively located between two adjacent first stacked structures in the plurality of stacked structure groups; the plurality of semiconductor layers are interconnected.

[0287] Here, the semiconductor layers can be understood with reference to the structural features of the semiconductor layers in the foregoing embodiments, and will not be repeated here.

[0288] In some embodiments, the storage device further includes a first conductive structure that extends along a first direction and is connected to a first conductive layer of at least two of the plurality of first stacked structures.

[0289] Here, the first conductive structure can be understood with reference to the structural features of the first conductive structure in the aforementioned embodiments, and will not be repeated here.

[0290] In some embodiments, the memory device further includes a third conductive structure; a plurality of first conductive layers in the first stacked structure include a top selected gate layer and a gate layer; the top selected gate layer is located at one end of the respective first stacked structure along a first direction away from the semiconductor layer connected to the channel structure in the respective first stacked structure; the third conductive structure extends along the first direction in the first stacked structure and is connected to the top selected gate layer included in at least one of the plurality of first stacked structures; the first conductive structure is connected to a gate layer of at least two of the plurality of first stacked structures.

[0291] Here, the third conductive structure is the lead-out structure corresponding to the top selected gate layer. The structural form and setting position of the third conductive structure will be further described later.

[0292] This application provides a memory device comprising: a plurality of first stacked structures stacked together; each first stacked structure including a plurality of first conductive layers and a first dielectric layer alternately disposed along a first direction; each of the plurality of first conductive layers in the first stacked structure including a top selected gate layer and a gate layer; the top selected gate layer being located at one end of a respective first stacked structure along the first direction away from a semiconductor layer connected to a channel structure in the respective first stacked structure; a plurality of channel structures; each channel structure penetrating the plurality of first stacked structures; at least one semiconductor layer; a semiconductor layer connected to a channel structure in at least one first stacked structure; and a third conductive structure extending along the first direction in the first stacked structure and connected to a top selected gate layer included in at least one of the plurality of first stacked structures.

[0293] Here, the first stacked structure, the first conductive layer, the first dielectric layer, the channel structure, and the semiconductor layer can all be understood with reference to the corresponding structures in the foregoing embodiments, and will not be described again here.

[0294] In this embodiment, the third conductive structure is a lead-out structure corresponding to the top selected gate layer. The top selected gate layer in the first stacked structure may include one or more layers. When multiple layers are included, the multiple layers may be led out together or separately. In this embodiment, the third conductive structure penetrates multiple first stacked structure decks, and the third conductive structure is electrically connected to the TSG layer of at least one deck.

[0295] In some embodiments, the memory device further includes a top-select gate isolation structure; the top-select gate isolation structure divides the top-select gate layer into multiple sub-top-select gate layers; different sub-top-select gate layers included in the same top-select gate layer are connected to different third conductive structures.

[0296] Here, the top selected gate isolation structure TSGCUT extends in a similar direction to the gate gap structure GLS shown in Figures 9A and 9B. The difference is that GLS penetrates all the first conductive layers of all first stacked structures, while the top isolation structure penetrates a portion of the first conductive layer of each first stacked structure. More specifically, the top isolation structure penetrates the top selected gate layer in the first conductive layer of each first stacked structure. For example, the top selected gate layer may include one or three layers.

[0297] In this embodiment, the top-select gate isolation structure divides the top-select gate layer into multiple sub-top-select gate layers, and the channel structure corresponding to each sub-top-select gate layer forms a memory chip (String). Different sub-top-select gate layers connected to different memory chips are connected to different third conductive structures.

[0298] It should be noted that both the bit line and the top select gate layer are connected by channel structures, enabling the selection and deselection of the connected channel structures. The difference lies in that the bit line extends along a third direction, connecting a channel structure column, which includes multiple channel structures arranged along the third direction; the top select gate connects multiple channel structure rows, each including multiple channel structures arranged along a second direction. Since both the bit line and the top select gate layer provide selection functionality for the channel structures, to save on the layout area of ​​their corresponding lead-out structures, their corresponding lead-out structures can be integrated and laid out in a unified manner under different memory architectures.

[0299] It should be noted that the top select gate layer is used to select strings, and the bottom select gate layer can actually play the same role. Based on this, without causing conflict, the top select gate layer can be replaced by the bottom select gate layer in this embodiment. In some embodiments, different top select gate layers included in different first stack structures are connected to different third conductive structures. In this embodiment, the top select gate layers of different decks are led out separately. It should be noted that for the architectures of the four memory devices mentioned above, the top select gate layers of different decks can be led out separately. The lead-out structures corresponding to the bit lines of different decks are connected together. As shown in Figure 2B above, the array Y-axis folding architecture must lead out the top select gate layers of different decks separately to achieve separate selection and deselection of the sub-channel structures in different decks. Here, the number of first stack structures is N, and the channel structure includes N sub-channel structures corresponding to N first stack structures.

[0300] In some embodiments, the memory device further includes a plurality of second conductive layers and a plurality of second conductive structures; one second conductive layer is connected to a channel structure of at least one first stacked structure; one second conductive layer includes a plurality of bit lines, each bit line being connected to a column of channel structures; the second conductive structure extends along a first direction in the first stacked structure and is connected to a bit line of at least one second conductive layer.

[0301] Here, the second conductive layer can be understood as a bit line layer. The bit line layer may include multiple bit lines spaced apart along the X-axis and extending along a third direction. The second conductive structure is the lead-out structure corresponding to the bit lines. The specific features of the second conductive layer and the second conductive structure can be understood with reference to the description in the foregoing embodiments, and will not be repeated here.

[0302] In some specific embodiments, different bit lines corresponding to different first stacked structures through the same channel structure are all connected to different second conductive structures; different top selected gate layers included in different first stacked structures are connected to the same third conductive structure.

[0303] In this embodiment, when the bit lines of different decks are brought out separately (as shown in the array X-axis folding architecture in Figure 2C above), the top select gate layers of different decks can be brought out together. In this way, the sub-channel structures in different decks can be selected and deselected separately, which saves the layout area of ​​the top select gate layer corresponding to the brought-out structure compared to bringing out the top select gate layers of different decks separately.

[0304] In some embodiments, a plurality of first stacked structures stacked together constitute a storage surface; the storage device includes at least two storage surfaces; two storage surfaces in at least two storage modules are arranged side by side along a second direction; the second direction is perpendicular to the first direction; the storage device further includes a first conductive structure; the first conductive structure is located between the two storage surfaces, and the first conductive structure is connected to a gate layer of each of the different first stacked structures in at least one storage surface.

[0305] In this embodiment, the first conductive structure is located between two storage surfaces, but it is not limited whether the two storage surfaces share the first conductive structure. That is, a first conductive structure can connect the first conductive layers of different decks of a storage surface, and a first conductive structure can also connect the first conductive layers of different decks of each of two parallel storage surfaces.

[0306] In some embodiments, the memory device further includes peripheral circuitry; the peripheral circuitry includes a plurality of word line driving circuits; the first conductive layers of different memory surfaces at the same position in the stacking direction of the first stacking structure are interconnected and connected to the same word line driving circuit.

[0307] Here, the description of the storage surface can be referred to in Figure 2E above. The first conductive layer at the same position along the first direction on different storage surfaces can be understood as the first conductive layer in the same layer on different storage surfaces. The first conductive layer in the same layer is connected to the same first conductive structure and is connected to the same SD through the same first conductive structure.

[0308] In some embodiments, different bit lines corresponding to different first stacked structures that are connected through the same channel structure are all connected to different second conductive structures; different top selected gate layers included in different first stacked structures in the same memory plane are connected to the same third conductive structure; different top selected gate layers included in first stacked structures at the same position in the first direction of different memory planes are connected to different third conductive structures.

[0309] In this embodiment, the top select gate layers of different decks in the same memory plane are led out together; the top select gate layers of different memory planes are led out separately, and the top select gate layers of different memory planes located in the same layer are also led out separately.

[0310] It should be noted that the above-described bit line and top select gate layer lead-out scheme is applicable to array X-axis folded architectures in each memory plane. When array Y-axis folded architectures are used in each memory plane, the top select gate layers of different decks in the same memory plane are led out separately; the top select gate layers of different memory planes are led out separately.

[0311] In some embodiments, a plurality of first stacked structures stacked together form a memory module; the memory device includes at least two memory modules; the at least two first memory modules are stacked together along a first direction; the memory device further includes a first conductive structure; the first conductive structure is connected to a gate layer of each of the first stacked structures in the two memory modules.

[0312] Here, the description of the storage module can be found in Figure 2D above. The first conductive structure can be understood by referring to the structural features of the first conductive structure in the previous embodiment, and will not be repeated here.

[0313] In some embodiments, the memory device further includes a fourth conductive structure; different bit lines corresponding to different first stacked structures through which the same channel structure passes in the same memory module are all connected to different second conductive structures; two bit lines corresponding to two specified first stacked structures in different memory modules are interconnected through the fourth conductive structure; different top selected gate layers included in different first stacked structures in the same memory module are connected to the same third conductive structure; two top selected gate layers included in two first stacked structures in different memory modules are connected to different third conductive structures.

[0314] In this embodiment, the aforementioned array architecture, which folds first along the X-axis and then along the Y-axis, is applicable. Within the same memory module, different bit lines corresponding to a channel structure in different decks are led out separately, and different top selected gate layers corresponding to different decks are led out together; within different memory modules, different bit lines corresponding to a channel structure in a specified deck are led out together, and different top selected gate layers corresponding to different decks are led out separately.

[0315] Here, the deck is specified in relation to the folding rules. Taking folding in the X-axis direction followed by folding in the Y-axis direction as an example, referring to the left half of Figure 3C, the channel structure in Model 1 and Model 2 is led out from different bit lines in different decks. The first left-hand deck in Model 1 and the first left-hand deck in Model 2 are two decks led out together by the specified bit lines. The second left-hand deck in Model 1 and the second left-hand deck in Model 2 are two decks led out together by the specified bit lines. The third left-hand deck in Model 1 and the third left-hand deck in Model 2 are two decks led out together by the specified bit lines. The fourth left-hand deck in Model 1 and the fourth left-hand deck in Model 2 are two decks led out together by the specified bit lines.

[0316] In some embodiments, the fourth conductive structure is located on one side of the region where the second conductive structure is located along the first direction; the two second conductive structures corresponding to the two first stacked structures specified in different storage modules are interconnected through the fourth conductive structure.

[0317] In this embodiment of the application, the second conductive structures of two decks led out together by the specified bit lines are connected by a fourth conductive structure, which is located on either side of the plurality of first stacked structures along the first direction.

[0318] In some embodiments, different bit lines corresponding to different first stacked structures with the same channel structure in the same memory module are all connected to the same second conductive structure; different bit lines corresponding to two first stacked structures in different memory modules are all connected to different second conductive structures; different top selected gate layers included in different first stacked structures in the same memory module are connected to different third conductive structures; and two top selected gate layers included in two first stacked structures in different memory modules are connected to the same third conductive structure.

[0319] In this embodiment, the aforementioned array architecture, which folds first along the Y-axis and then along the X-axis, is applicable. Within the same memory module, different bit lines corresponding to a channel structure in different decks are brought out together, and different top select gate layers corresponding to different decks are brought out separately; within different memory modules, different bit lines corresponding to a channel structure in different decks are brought out separately, and different top select gate layers corresponding to different decks are brought out together.

[0320] It should be noted that, for the same X-axis + Y-axis folding architecture, the bit lines and top select gate layers are led out differently depending on whether the X-axis folding is performed first and then the Y-axis folding, or vice versa. The lead-out methods are related to the folding pattern. Specifically, when folding in the X-axis direction, the number of bit lines in each deck remains unchanged after folding. In this case, the bit lines of a single-channel structure in different decks need to be led out separately, while the top select gate layers of different decks can be led out separately. When folding in the Y-axis direction, the number of bit lines in each deck changes by 1 / N (where N is the number of decks) after folding. In this case, the bit lines of a single-channel structure in different decks can be led out together, while the top select gate layers of different decks need to be led out separately.

[0321] In some embodiments, a plurality of first stacked structures are disposed in a first region, all first conductive structures are disposed in a second region, and all third conductive structures are disposed in a fourth region; the fourth region is located between the first region and the second region.

[0322] Here, the first region and the second region can be understood with reference to the first region and the second region in the foregoing embodiments. The fourth region, which is the third conductive structure, i.e., the top selected gate layer, is located between the first region and the second region. In some embodiments, the second region is located in the middle of the first region, and the fourth region can be divided into two parts, both of which are located on both sides of the second region along the second direction and close to the second region.

[0323] In some embodiments, the third conductive structure includes a second lead-out portion, a second connection portion, and a contact portion; the second lead-out portion extends along a first direction and is connected to the second connection portion; the second connection portion extends along a direction perpendicular to the first direction and is connected to the contact portion; the contact portion extends along the first direction and is connected to the top selected gate layer.

[0324] Here, the third conductive structure is the lead-out structure corresponding to the top selected gate layer. The structural form of the third conductive structure will be further described later.

[0325] In some embodiments, each first stack structure includes a plurality of top select gate layers, the cross-sectional shape of the plurality of top select gate layers along a first direction including a stepped shape; each step in the stepped shape corresponds to a top select gate layer; a contact portion is connected to a step where a top select gate layer is located.

[0326] In this embodiment, each first stacked structure comprises multiple top-select gate layers. If the voltage strategies applied to these multiple layers are the same, the multiple layers can be brought out together; if the voltage strategies applied to these multiple layers are different, the multiple layers can be brought out separately. In one embodiment, the multiple layers can form a stepped structure, the stepped structure being step-like, each step including a top-select gate layer, and a third conductive structure can be connected to each step.

[0327] In some embodiments, at least one semiconductor layer is located between two adjacent first stacked structures and is connected to the channel structures in both adjacent first stacked structures.

[0328] Here, the semiconductor layer can be understood with reference to the structural features of the semiconductor layer in the foregoing embodiments, and will not be repeated here.

[0329] In some embodiments, the memory device further includes a first conductive structure; the first conductive structure extends along a first direction and is connected to a gate layer of at least two of the plurality of first stacked structures.

[0330] Here, the first conductive structure can be understood with reference to the structural features of the first conductive structure in the aforementioned embodiments, and will not be repeated here.

[0331] Figure 10A is a schematic diagram of the layout of an array including storage devices and peripheral circuits provided in an embodiment of this application; Figure 10B is a top view of the lead-out structure of the BL and TSG of deck 1 including storage devices provided in an embodiment of this application; Figure 10C is a top view of the lead-out structure of the BL and TSG of deck 2 including storage devices provided in an embodiment of this application; Figure 10D is a cross-sectional view of the lead-out structure of the BL including storage devices provided in an embodiment of this application; Figure 10E is a cross-sectional view of the lead-out structure of the TSG including storage devices provided in an embodiment of this application.

[0332] Figure 11A is a second schematic diagram of the layout of the array including the memory device and the peripheral circuit provided in an embodiment of this application; Figure 11B is a second schematic diagram of the top view of the BL lead-out structure of each deck including the memory device provided in an embodiment of this application; Figure 11C is a second schematic diagram of the top view of the BL lead-out structure of each deck including the memory device provided in an embodiment of this application; Figure 11D is a second schematic diagram of the cross-sectional view of the TSG lead-out structure of each deck including the memory device provided in an embodiment of this application; Figure 11E is a second schematic diagram of the cross-sectional view of the TSG lead-out structure of each deck including the memory device provided in an embodiment of this application.

[0333] Figure 12A is a schematic diagram of the layout of the array including the memory device and the peripheral circuit provided in the embodiment of this application; Figure 12B is a top view of the BL lead-out structure of each deck including the memory device provided in the embodiment of this application; Figure 12C is a top view of the BL lead-out structure of each deck including the memory device provided in the embodiment of this application; Figure 12D is a cross-sectional view of the TSG lead-out structure of each deck including the memory device provided in the embodiment of this application; Figure 12E is a cross-sectional view of the TSG lead-out structure of each deck including the memory device provided in the embodiment of this application.

[0334] Figure 13A is a schematic diagram of the layout of the array and peripheral circuits including the memory devices provided in an embodiment of this application; Figure 13B is a top view of the BL lead-out structure of each deck including the memory devices provided in an embodiment of this application; Figure 13C is a top view of the BL lead-out structure of each deck including the memory devices provided in an embodiment of this application; Figure 13D is a top view of the BL and TSG lead-out structure of Model 1 including the memory devices provided in an embodiment of this application; Figure 13E is a top view of the BL and TSG lead-out structure of Model 2 including the memory devices provided in an embodiment of this application; Figure 13F is a cross-sectional view of the TSG lead-out structure of each deck including the memory devices provided in an embodiment of this application.

[0335] The following will describe in detail the implementation of the lead-out structure (second conductive structure) of the lower bit line BL and the lead-out structure (third conductive structure) of the top selected gate layer TSG in different folding architectures, with reference to Figures 10A to 10E, 11A to 11E, 12A to 12E, and 13A to 13F.

[0336] This application provides a memory device for the aforementioned array Y-axis folded architecture, as shown in Figures 10A to 10E. In this embodiment, the original array is divided along the Y-axis and stacked, and a memory array Array is formed by sharing a gate layer WL. The Array includes an array region GB and a connection region SS. In some embodiments, along the X-axis, the connection region is located in the middle of the memory array Array, between two array regions (this is shown in Figure 10A). In some embodiments, along the X-axis, the connection region may be located at the edge of the Array, on one side of the array region, such as the left or right edge of the array structure.

[0337] In this embodiment, the Array may include multiple first conductive structures CT1, which may be located in the connection region, i.e., the second region S2. Each deck has a gate layer WL that can be connected to a first conductive structure CT1. The second region S2 may include a stepped structure, or it may not have a stepped structure, or other connection structures that can lead out the gate layer WL.

[0338] In this embodiment, the memory device further includes peripheral circuitry CMOS. The array and CMOS can be combined through bonding or other means. The peripheral circuitry may include word line driver circuitry SD and page buffer PB; wherein, there may be multiple SDs, each of which is a small cuboid as shown in Figure 10A (two SDs are shown in Figure 10A). Each first conductive structure CT1 can be connected to one SD, and the setting area of ​​the SD can be located directly above the connection area SS, and the setting area of ​​the PB can be located above the array area GB. In this way, the wiring can be reduced, and the manufacturing process can be simplified.

[0339] In this embodiment, the Array includes a memory block, which comprises multiple first stacked structures decks stacked along the Z-axis (N decks are shown in Figure 10A, i.e., deck1-deckN). Each first stacked structure includes a top select gate layer (TSG). The structure includes at least one top select gate isolation structure (TSG CUT) extending along the X-axis through the top select gate layer (TSG) and dividing the TSG into multiple sub-top select gate layers. Each top select gate layer corresponds to a memory string (P strings are shown in Figures 10B and 10C, i.e., string1-stringP). The material of the TSG CUT includes, but is not limited to, silicon oxide.

[0340] In this embodiment, as shown in Figures 10B and 10C, the memory device includes multiple bit lines BL extending along the Y-axis and spaced apart along the X-axis. Each bit line BL is connected to each channel structure in a channel structure CH column. The lead-out structure corresponding to the bit line, i.e., the second conductive structure CT2, is disposed in the third region S3. Each bit line extends further along its extension direction, and the further extended portion is connected to the second conductive structure CT2. In this embodiment, different bit lines connected in different decks of a channel structure are led out together, i.e., connected to the page cache PB in the peripheral circuit through the same second conductive structure. In this embodiment, a memory block may include one page cache PB.

[0341] In this embodiment of the application, as shown in FIG10D, the second conductive structure CT2 connects different bit lines of a channel structure in different decks through a conductive structure with a similar morphology to the channel structure, and connects to PB (the part connected to PB is not shown in FIG10D). It should be noted that FIG10D only shows the case where the storage device includes two decks; the case with multiple decks can be deduced by analogy from this figure.

[0342] In the facility example of this application, as shown in Figures 10B and 10C, the TSGs of different decks are led out through different third conductive structures CT3. The third conductive structure CT3 includes a second lead-out portion TSGTSC, a second connection portion B, and a contact portion TSGCT; the second lead-out portion TSGTSC extends along the Z-axis direction and is connected to the second connection portion B; the second connection portion B extends along a direction perpendicular to the Z-axis direction and is connected to the contact portion TSGCT; the contact portion TSGCT extends along the Z-axis direction and is connected to the top select gate layer. The second lead-out portion TSGTSC extends along the Z-axis direction through all decks, and the TSGCTs of each deck can be aligned along a first direction. The projections of the TSGCTs of all decks in the same string onto a plane perpendicular to the Z-axis direction overlap. The TSGCTs are connected to the second lead-out portion TSC through conductive structures extending along the X-axis direction. The TSGCTs of different decks in the same string are connected to the same TSGTSC. The materials of TSGCT, B, and TSGTSC include, but are not limited to, tungsten. The number of TSGTSCs is greater than or equal to the number of decks.

[0343] In the facility example of this application, as shown in FIG10B, taking deck 1 as an example, deck 1 may include a sub-TSG, and multiple sub-TSGs may be respectively connected to different TSGCTs. Different TSGCTs are connected to the same TSGTSC, or different TSGCTs may be connected to different TSGTSCs (this situation is shown in FIG10E, which is a cross-sectional view corresponding to X3-X3′ in FIG10B). In other embodiments, deck 1 further includes a TSG, which is connected to a TSGCT, and the TSGCT is connected to the TSGTSC through a second connecting part B.

[0344] In the facility example of this application, as shown in FIG10C, taking deck 2 as an example, deck 2 may include a sub-TSG, and the multiple sub-TSGs may be respectively connected to different TSGCTs. Different TSGCTs are connected to the same TSGTSC, or different TSGCTs may be connected to different TSGTSCs (this case is shown in FIG10E). In other embodiments, deck 1 also includes a TSG, which is connected to a TSGCT, and the TSGCT is connected to the TSGTSC through a second connection part B.

[0345] It should be noted that in Figures 10B and 10C, the TSGCT is connected to different TSGTSCs via a second connecting portion B extending in the opposite direction (B along the X-axis + in deck 1, B along the X-axis - in deck 2). It can be understood that, for deck 3, the TSGCT is connected to different TSGTSCs via a second connecting portion B extending along the Y-axis + direction. The specific extension direction of the second connecting portion B mentioned above is not intended to limit the extension direction of the second connecting portion B in the embodiments of this application, but only to illustrate that in different decks, the TSGCT can be connected to different TSGTSCs via second connecting portions B extending in different directions.

[0346] This application provides a memory device for the aforementioned array X-axis folded architecture, as shown in Figures 11A to 11E. In this embodiment, the original array is divided along the X-axis and stacked, and a memory array Array is formed by sharing a gate layer WL. The Array includes an array region GB and a connection region SS. In some embodiments, along the X-axis, the connection region is located in the middle of the memory array Array, or between two array regions (this is shown in Figure 11A). In some embodiments, along the X-axis, the connection region may be located at the edge of the Array, on one side of the array region, such as the left or right edge of the array structure.

[0347] In this embodiment, the Array may include multiple first conductive structures CT1, which may be located in the connection region, i.e., the second region S2. Each deck has a gate layer WL that can be connected to a first conductive structure CT1. The second region S2 may include a stepped structure, or it may not have a stepped structure, or other connection structures that can lead out the gate layer WL.

[0348] In this embodiment, the memory device further includes peripheral circuitry CMOS. The array and CMOS can be combined through bonding or other means. The peripheral circuitry may include word line driver circuitry SD and page cache PB; wherein, PB and SD may include multiple PBs, such as PB1 to PBN, with the bit lines of each of the N decks connected to one PB; each SD is a small cuboid as shown in Figure 11A (Figure 11A shows two SDs). Each first conductive structure CT1 can be connected to one SD, and the setting area of ​​the SD can be located directly above the connection area SS, while the setting area of ​​the PB can be located above the array area GB. This reduces wiring and lowers the difficulty of fabrication.

[0349] In this embodiment, as shown in Figure 11A, the Array includes multiple first stacked structures (decks are shown in Figure 11A, i.e., deck1-deckN) stacked along the Z-axis. Each deck is connected to a second conductive layer, i.e., bit line layers BL1-BLN. PB can include multiple layers, such as PB1-PBN. The bit lines BL of different stacked structures are led out to their corresponding PBs. For example, the bit line layer BL1 of deck1 is connected to PB1, and the bit line BLN of deckN is connected to PBN. It should be noted that Figure 11A only illustrates the connection relationship between the bit line layers of the deck and the corresponding PBs; this connection relationship does not reflect the actual position of the bit line lead-out structure, i.e., the second conductive structure. It is clear that in this embodiment, different bit lines connected by a channel structure in different decks are led out through different second conductive structures.

[0350] In this embodiment of the application, as shown in FIG11B, the lengths of the bit line layers BL1-BLN corresponding to each deck can be different along their extension direction. Based on this, in the top view of FIG11B, adjacent bit line layers are disconnected along the Y-axis direction. BL1 to BL4 in FIG11C show the variation in bit line lengths in the bit line layers corresponding to different decks from another perspective. This facilitates the easier extraction of the second conductive structure. It should be noted that the bit lines of deck 1 can be located on the top layer of all first stacked structures, and they do not require a special second conductive structure to extract them. Based on this, in FIG11B, the bit lines in BL1 are connected to the channel structure CH, while the bit lines in BL2-BLN are connected to the second conductive structure CT2.

[0351] In this embodiment of the application, as shown in FIG11C, the bit lines of all decks are led out from the same side, for example, from the top of the first stacked structure. The second conductive structure CT2 connected to the bit lines of the deck extends through all decks between the bit line BL and the top of the structure. For example, the second conductive structure CT2 connected to the bit line layer BL2 of deck 2 extends through deck 2 and deck 1; the second conductive structure CT2 connected to the bit line layer BL4 of deck 4 extends through all decks. In other embodiments, the bit lines of all decks may also be led out from the bottom of the first stacked structure, and the bit line BL and the second conductive structure CT2 may also have other lead-out methods.

[0352] In this embodiment of the application, as shown in FIG11D, the third region S3 where the second conductive structure CT2 connected to the bit line is located is located on at least one side of the first region where the first stacked structure is located along the Y direction. The first stacked structure is provided with a plurality of channel structures CH, and the second conductive structure CT2 connected to the bit line can pass through the stacked structure in which conductive layers and dielectric layers are alternately stacked, or it can pass through the dielectric structure.

[0353] In this embodiment, the Array includes a memory block, which comprises multiple first stacked structures decks stacked along the Z-axis. Each first stacked structure includes a top selected gate layer (TSG). The structure includes at least one top selected gate isolation structure (TSG CUT) extending along the X-axis through the TSG, dividing the TSG into multiple sub-top selected gate layers. Each top selected gate layer corresponds to a memory string (P strings are shown in Figure 11D, i.e., string1-stringP). The material of the TSG CUT includes, but is not limited to, silicon oxide.

[0354] In the facility example of this application, as shown in Figures 11D and 11E (Figure 11E is a cross-sectional view corresponding to X4-X4′ in Figure 11D), the TSGs of different decks are led out through the same third conductive structure CT3. The third conductive structure CT3 includes a second lead-out portion TSGTSC, a second connection portion B, and a contact portion TSGCT; the second lead-out portion TSGTSC extends along the Z-axis direction and is connected to the second connection portion B; the second connection portion B extends along a direction perpendicular to the Z-axis direction and is connected to the contact portion TSGCT; the contact portion TSGCT extends along the Z-axis direction and is connected to the top select gate layer. The second lead-out portion TSGTSC extends along the Z-axis direction through all decks, and the TSGCTs of each deck can be aligned along a first direction. The projections of the TSGCTs of all decks in the same string onto the plane perpendicular to the Z-axis direction overlap. The TSGCTs are connected to the second lead-out portion TSGTSC through conductive structures extending along the X-axis direction. The TSGCTs of different decks in the same string are connected to the same TSGTSC. The materials of TSGCT, B, and TSGTSC include, but are not limited to, tungsten. The number of TSGTSCs is greater than or equal to the number of decks.

[0355] In the facility example of this application, as shown in FIG11D, for deck1-deckN, each deck may include a sub-TSG, and the multiple sub-TSGs may be respectively connected to different TSGCTs and different TSGGTSCs. In other embodiments, each deck may also include a TSG, which is connected to a TSGCT, and the TSGCT is connected to the TSGGTSC through a second connecting part B.

[0356] In the facility example of this application, as shown in FIG11E, for the same string, deck1-deckN can share the same second lead-out portion TSGTSC. The TSGs of different decks can be connected to the same second lead-out portion through different second connection layers B and contact portions TSGCT, thereby realizing that the TSGs of different decks are led out through the same third conductive structure CT3.

[0357] This application provides a storage device. Regarding the aforementioned storage plane merging architecture, each of the two merged storage planes can be a Y-axis folding architecture, an X-axis folding architecture, or a + Y-axis folding architecture. The following description will only use the example of each of the two merged storage planes being an X-axis folding architecture.

[0358] As shown in Figures 12A to 12E, in the embodiments of this application, the memory device includes a memory array Array. The Array includes two memory surfaces and a connection region SS located between the two memory surfaces. The two memory surfaces share a gate WL. Each memory surface includes multiple first stacked structures deck. Each deck has a bit line layer BL (i.e., a second semiconductor layer) and a source layer ACS respectively disposed on both sides along a first direction. In some embodiments, two adjacent decks along the Z-axis alternately share the bit line layer BL and the source layer ACS.

[0359] In this embodiment of the application, as shown in FIG12A, the Array may include multiple first conductive structures CT1. The first conductive structures CT1 may be located in the connection region, i.e., the second region S2. Each deck has a gate layer WL that can be connected to a first conductive structure CT1. The second region S2 may include a stepped structure, or it may not have a stepped structure, or other connection structures that can realize the gate layer WL being led out.

[0360] In this embodiment, the memory device further includes peripheral circuitry CMOS. The array and CMOS can be combined through bonding or other means. The peripheral circuitry may include word line driver circuitry SD and page cache PB; wherein, PB and SD may include multiple PBs, such as PB1 to PBN, with the bit lines of each of the N decks connected to one PB; each SD is a small cuboid as shown in Figure 12A (Figure 12A shows two SDs). Each first conductive structure CT1 can be connected to one SD, and the setting area of ​​the SD can be located directly above the connection area SS, while the setting area of ​​the PB can be located above the memory surface. This reduces wiring and lowers the difficulty of fabrication.

[0361] Figures 12B and 12C can be understood by referring to Figures 11B and 11C, and will not be elaborated here.

[0362] In this embodiment, the Array includes a memory block, which comprises multiple first stacked structures decks stacked along the Z-axis. Each first stacked structure includes a top selected gate layer (TSG). The structure includes at least one top selected gate isolation structure (TSG CUT) extending along the X-axis through the TSG, dividing the TSG into multiple sub-top selected gate layers. Each top selected gate layer corresponds to a memory string (P strings are shown in Figure 12D, i.e., string1-stringP). The material of the TSG CUT includes, but is not limited to, silicon oxide.

[0363] In the facility example of this application, as shown in Figures 12D and 12E (Figure 12E is a cross-sectional view corresponding to X5-X5′ in Figure 12D), the TSGs of different decks are led out through the same third conductive structure CT3. The third conductive structure CT3 includes a second lead-out portion TSGTSC, a second connection portion B, and a contact portion TSGCT; the second lead-out portion TSGTSC extends along the Z-axis direction and is connected to the second connection portion B; the second connection portion B extends along a direction perpendicular to the Z-axis direction and is connected to the contact portion TSGCT; the contact portion TSGCT extends along the Z-axis direction and is connected to the top select gate layer. The second lead-out portion TSGTSC extends along the Z-axis direction through all decks, and the TSGCTs of each deck can be aligned along a first direction. The projections of the TSGCTs of all decks in the same string onto the plane perpendicular to the Z-axis direction overlap. The TSGCTs are connected to the second lead-out portion TSGTSC through conductive structures extending along the X-axis direction. The TSGCTs of different decks in the same string are connected to the same TSGTSC. The materials of TSGCT, B, and TSGTSC include, but are not limited to, tungsten. The number of TSGTSCs is greater than or equal to the number of decks.

[0364] In the facility example of this application, as shown in FIG12E, for deck1-deckN, each deck may include a sub-TSG, and multiple sub-TSGs form a stepped structure. The cross-sectional shape of the stepped structure along the first direction is stepped. Each step in the stepped structure corresponds to a top select gate layer. A contact portion TSGCT is connected to a step where the top select gate layer is located. Multiple sub-TSGs can be connected to different TSGCTs respectively. Multiple TSGCTs in the same string can be connected to the same second lead TSGTSC, or they can be connected to different second leads TSGTSCs (in FIG12D, the three contact portions TSGCTs in the same string are respectively connected to different second leads TSGTSCs).

[0365] It should be noted that Figure 12D shows the second connecting part B used to connect the contact part TSGCT and the second lead-out structure TSGTSC, while Figure 12E does not show the second connecting part B due to the perspective of the cross-section.

[0366] This application provides a storage device for the aforementioned array X-axis + Y-axis folding architecture. As described above, the array X-axis + Y-axis folding architecture can be folded first in the X-axis direction and then in the Y-axis direction, or it can be folded first in the Y-axis direction and then in the X-axis direction. The following description will only take folding first in the X-axis direction and then in the Y-axis direction as an example.

[0367] As shown in Figures 13A to 13F, in this embodiment of the application, the original array is divided along the X-axis and Y-axis directions and then stacked to form a memory array Array by sharing a gate layer WL. This Array includes an array region GB and a connection region SS. In some embodiments, along the X-axis direction, the connection region is located in the middle of the memory array Array, or between two array regions (this is shown in Figure 13A). In some embodiments, along the X-axis direction, the connection region may be located at the edge of the Array, on one side of the array region, such as the left or right edge of the array structure.

[0368] In this embodiment of the application, as shown in Figure 13A, the Array includes multiple storage modules (Model1-ModelM are shown in Figure 13A, where M is a positive integer greater than or equal to 2). Each Model includes multiple first stacked structure decks (N decks are shown in Figure 13A, where N is a positive integer greater than or equal to 2). Each deck has a bit line layer BL (BL1-BLN are shown in Figure 13A, where the bit line layers of the N decks included in each Model are BL1-BLN) i.e., a second semiconductor layer and a source layer ACS on both sides along a first direction. In some embodiments, two adjacent decks along the Z-axis alternately share the bit line layer BL and the source layer ACS. Each deck is correspondingly connected to a second conductive layer i.e., the bit line layer.

[0369] In this embodiment of the application, as shown in Figure 13A, the Array may further include multiple first conductive structures CT1. The first conductive structures CT1 may be located in the connection region, i.e., the second region S2. Each deck has a gate layer WL that can be connected to a first conductive structure CT1. The second region S2 may include a stepped structure, or it may not have a stepped structure, or other connection structures that can realize the gate layer WL being led out.

[0370] In this embodiment, the memory device further includes peripheral circuitry CMOS. The array and CMOS can be combined through bonding or other means. The peripheral circuitry may include word line driver circuitry SD and page cache PB; wherein, PB and SD may include multiple PBs, such as PB1 to PBN. The bit lines of each of the N decks in each memory module are connected to a corresponding PB. For example, the bit line layer BL1 of deck1 is connected to PB1, and the bit line BLN of deckN is connected to PBN. The bit lines of the same deck of different memory modules Model are connected in parallel to the corresponding PB. For example, the bit line layer BL1 of deck1 of Model1 and the bit line layer BL1 of deck1 of Model1 are both connected to PB1. The bit lines of deckN of each memory module are all connected to PBN. Each SD is a small cuboid as shown in Figure 13A (two SDs are shown in Figure 13A). Each first conductive structure CT1 can be connected to one SD, and the setting area of ​​the SD can be located directly above the connection area SS. The setting area of ​​the PB can be located above the memory surface. In this way, the wiring can be reduced, and the manufacturing process can be simplified.

[0371] In this embodiment of the application, in the same memory module, different bit lines corresponding to a channel structure in different decks are brought out separately; in different memory modules, different bit lines corresponding to a channel structure in a specified deck are brought out together.

[0372] In this embodiment of the application, as shown in FIG13B, the lengths of the bit line layers BL1-BLN corresponding to each deck in each Model can be different along their extension direction. Based on this, in the top view of FIG13B, adjacent bit line layers are disconnected along the Y-axis direction. In FIG13C, the length changes of the bit lines in the bit line layers corresponding to different decks can be seen from another perspective in Model 1 and Model 2 from BL1 to BL4. This makes it easier to bring out the second conductive structure. It should be noted that the bit lines of deck 1 of Model 1 can be located on the top layer of all the first stacked structures, and they do not need to be specially set up with a second conductive structure to bring them out. Based on this, in FIG13B, the bit lines in BL1 of Model 1 are connected to the channel structure CH, while the bit lines in the other bit line layers (BL2-BLN) of Model 1 and all bit line layers (BL1-BLN) of Model 2 are connected to the second conductive structure CT2.

[0373] In this embodiment of the application, as shown in FIG13C, the bit lines of all decks are led out from the same side, for example, from the top of the first stack structure. The second conductive structure CT2 connected to the bit lines of the deck extends through all decks between the bit line BL and the top of the structure. For example, in Model 1, the second conductive structure CT2 connected to the bit line layer BL2 of deck 2 extends through deck 2 and deck 1, and the second conductive structure CT2 connected to the bit line layer BL4 of deck 4 extends through all decks; in Model 2, the second conductive structure CT2 connected to the bit line layer BL1 of deck 1 extends through all decks of Model 1, and the second conductive structure CT2 connected to the bit line layer BL4 of deck 4 extends through all decks of Model 1 and all decks of Model 2. In other embodiments, the bit lines of all decks may also be led out from the bottom of the first stack structure, and the bit line BL and the second conductive structure CT2 may also have other lead-out methods.

[0374] In this embodiment of the application, as shown in FIG13C, the Array may further include multiple fourth conductive structures CT4, all disposed on top of all first stacked structures. Each fourth conductive structure is used to connect the second conductive structures CT2 of two specified decks in two different Models. For example, one CT4 connects the second conductive structure CT2 corresponding to deck 1 of Model 1 with the second conductive structure CT2 corresponding to deck 1 of Model 2. In some embodiments, the fourth conductive structure CT4 may include a combination of multiple conductive structures extending in different directions. In other embodiments, the multiple fourth conductive structures CT4 may also be disposed at the bottom of all first stacked structures.

[0375] In this embodiment, the Array includes a memory block, which comprises multiple first stacked structures decks stacked along the Z-axis. Each first stacked structure includes a top selected gate layer (TSG). The structure includes at least one top selected gate isolation structure (TSG CUT) extending along the X-axis through the TSG, dividing the TSG into multiple sub-top selected gate layers. Each top selected gate layer corresponds to a memory string (P strings are shown in Figures 13D and 13E, i.e., string1-stringP). The material of the TSG CUT includes, but is not limited to, silicon oxide.

[0376] In the embodiments of this application, in the same memory module, the different top selected gate layers corresponding to a channel structure in different decks are led out together; in different memory modules, the different top selected gate layers corresponding to a channel structure in different decks are led out separately.

[0377] In the facility example of this application, as shown in Figures 13D and 13E, the TSGs of different decks are led out through the same third conductive structure CT3. The third conductive structure CT3 includes a second lead-out portion TSGTSC, a second connection portion B, and a contact portion TSGCT; the second lead-out portion TSGTSC extends along the Z-axis direction and is connected to the second connection portion B; the second connection portion B extends along a direction perpendicular to the Z-axis direction and is connected to the contact portion TSGCT; the contact portion TSGCT extends along the Z-axis direction and is connected to the top select gate layer. The second lead-out portion TSGTSC extends along the Z-axis direction through all decks, and the TSGCTs of each deck can be aligned along a first direction. The projections of the TSGCTs of all decks in the same string onto a plane perpendicular to the Z-axis direction overlap. The TSGCTs are connected to the second lead-out portion TSGTSC through conductive structures extending along the X-axis direction. The TSGCTs of different decks in the same string are connected to the same TSGTSC. The materials of TSGCT, B, and TSGTSC include, but are not limited to, tungsten. The number of TSGTSCs is greater than or equal to the number of decks.

[0378] In the facility example of this application, as shown in FIG13D, taking Model 1 as an example, each deck in deck 1-deck N of Model 1 may include a sub-TSG. Multiple sub-TSGs may be respectively connected to different TSGCTs. Different TSGCTs are connected to the same TSGTSC, or different TSGCTs may be connected to different TSGTSCs (this case is shown in FIG13D). In other embodiments, deck 1 further includes a TSG connected to a TSGCT, and the TSGCT is connected to the TSGTSC through a second connection part B.

[0379] In the facility example of this application, as shown in FIG13E, taking Model 2 as an example, each deck in deck 1-deck N of Model 2 may include a sub-TSG, and multiple sub-TSGs may be respectively connected to different TSGCTs. Different TSGCTs are connected to the same TSGTSC, or different TSGCTs may be connected to different TSGTSCs (this case is shown in FIG13E). In other embodiments, deck 1 also includes a TSG, which is connected to a TSGCT. The TSGCT is connected to the TSGTSC through a second connection part B.

[0380] It should be noted that in Figures 13D and 13E, the TSGCT is connected to different TSGTSCs via a second connecting portion B extending in the opposite direction (B along the X-axis + in Model 1, B along the X-axis - in Model 2). It is understood that for different Models, the TSGCT is connected to different TSGTSCs via second connecting portions B extending in different directions. The specific extension direction of the second connecting portion B mentioned above is not intended to limit the extension direction of the second connecting portion B in the embodiments of this application, but only to illustrate that in different Models, the TSGCT can be connected to different TSGTSCs via second connecting portions B extending in different directions.

[0381] In the facility example of this application, as shown in Figure 13F (Figure 13F is the cross-sectional view corresponding to X6-X6′ in Figure 13D), for deck 1-deck N in Model 1, different decks can be connected to the same second lead-out portion TSGTSC through different contact portions TSGCT and different second connecting portions B; for deck 1-deck N in Model 2, different decks can be connected to the same second lead-out portion TSGTSC through different contact portions TSGCT and different second connecting portions B; wherein, the second lead-out portion TSGTSC in Model 1 may be different from the second lead-out portion TSGTSC in Model 2, the second lead-out portion TSGTSC in Model 1 may only penetrate each deck in Model 1, or penetrate each deck in both Model 1 and Model 2; the second lead-out portion TSGTSC in Model 2 penetrates each deck in both Model 1 and Model 2.

[0382] This application provides a storage device, which includes:

[0383] A plurality of first stacked structures are stacked; each first stacked structure includes a plurality of first conductive layers and first dielectric layers alternately arranged along a first direction; a plurality of first conductive structures, each first conductive structure being connected to a first conductive layer of at least two of the plurality of first stacked structures; a plurality of channel structures; each channel structure penetrating the plurality of first stacked structures; at least one semiconductor layer and at least one second conductive layer; the semiconductor layer and the second conductive layer are respectively located on both sides of a first stacked structure along the first direction and are both connected to a channel structure in the first stacked structure; each second conductive layer includes a plurality of bit lines spaced apart along a second direction and extending along a third direction; the second direction and the third direction intersect and are both perpendicular to the first direction; a plurality of second conductive structures, each second conductive structure being connected to a bit line of at least one second conductive layer.

[0384] In some embodiments, different bit lines corresponding to different first stacked structures that are traversed by the same channel structure are all connected to the same second conductive structure.

[0385] In some embodiments, at least one second conductive layer is located between two adjacent first stacked structures and is connected to the channel structures in both adjacent first stacked structures.

[0386] In some embodiments, the storage device further includes peripheral circuitry; the peripheral circuitry includes a page cache; and a plurality of second conductive structures are connected to the same page cache.

[0387] In some embodiments, different bit lines corresponding to different first stacked structures that are connected through the same channel structure are all connected to different second conductive structures.

[0388] In some embodiments, the dimensions of the second conductive layers corresponding to different first stacking structures are different along the third direction; the different second bit lines connected to the second conductive layers corresponding to different first stacking structures are arranged sequentially along the third direction.

[0389] In some embodiments, the storage device further includes peripheral circuitry; the peripheral circuitry includes a plurality of page caches; a second conductive structure connected to a bit line of the same second conductive layer is connected to the same page cache among the plurality of page caches; and a second conductive structure connected to a bit line of a different second conductive layer is connected to a different page cache among the plurality of page caches.

[0390] In some embodiments, at least one semiconductor layer is located between two adjacent first stacked structures and is connected to the channel structures in both adjacent first stacked structures.

[0391] In some embodiments, two adjacent first stacked structures in a plurality of first stacked structures form a stacked structure group; the storage device includes a plurality of semiconductor layers; the plurality of semiconductor layers are respectively located between two adjacent first stacked structures in the plurality of stacked structure groups; the plurality of semiconductor layers are interconnected.

[0392] In some embodiments, the cross-sectional shape of the plurality of first stacked structures along the first direction includes a stepped shape; each step in the stepped shape corresponds to an adjacent first conductive layer and a first dielectric layer; the first conductive structure extends along the first direction in the first stacked structure and is connected to at least two steps where a first conductive layer of at least two first stacked structures is located.

[0393] In some embodiments, the storage device further includes a second stacked structure, the second stacked structure including a plurality of alternately arranged isolation layers and a second dielectric layer; the first conductive structure includes a first lead-out portion and a plurality of first connection portions; the first lead-out portion is connected along a first line in the second stacked structure and is connected to the plurality of first connection portions; each first connection portion is located in an isolation layer and is connected to a first conductive layer of a corresponding first stacked structure in at least two first stacked structures.

[0394] In some embodiments, the first conductive structure is connected to a first conductive layer in each first stacked structure that is equidistant from the semiconductor layer connected to the channel structure of the corresponding first stacked structure.

[0395] In some embodiments, the first conductive structure is connected to a first conductive layer in each first stacked structure that is at a different distance from the semiconductor layer connected to the channel structure of the corresponding first stacked structure.

[0396] In some embodiments, the memory device further includes peripheral circuitry; the peripheral circuitry includes a plurality of word line driving circuits; a first conductive layer of at least two first stacked structures is interconnected through the first conductive structure and connected to the same word line driving circuit.

[0397] In some embodiments, the memory device further includes a plurality of third conductive structures; the first conductive layer in the first stacked structure includes a top selected gate layer and a gate layer; the top selected gate layer is located at one end of the respective first stacked structure along a first direction away from the semiconductor layer connected to the channel structure in the respective first stacked structure; the third conductive structure extends along the first direction in the first stacked structure and is connected to the top selected gate layer included in at least one of the plurality of first stacked structures; the first conductive structure is connected to a gate layer of at least two of the plurality of first stacked structures.

[0398] In some embodiments, the memory device further includes a top-select gate isolation structure; the top-select gate isolation structure divides the top-select gate layer into multiple sub-top-select gate layers; different sub-top-select gate layers included in the same top-select gate layer are connected to different third conductive structures.

[0399] In some embodiments, different top selected gate layers of different first stacked structures are connected to different third conductive structures; different bit lines corresponding to different first stacked structures through which the same channel structure passes are all connected to the same second conductive structure.

[0400] In some embodiments, different bit lines corresponding to different first stacked structures that are connected through the same channel structure are all connected to different second conductive structures.

[0401] Different first stacked structures include different top selected gate layers connected to the same third conductive structure.

[0402] In some embodiments, a plurality of first stacked structures stacked together constitute a memory surface; the memory device includes a first memory surface and a second memory surface; the first memory surface and the second memory surface are arranged side by side along a second direction; the memory device further includes a plurality of word line driving circuits; a plurality of first conductive structures are located between the first memory surface and the second memory surface, and the first conductive structures are connected to a gate layer of at least one different first stacked structure in at least one memory surface; the first conductive layers of the first memory surface and the second memory surface at the same position in the first direction are interconnected and connected to the same word line driving circuit.

[0403] In some embodiments, different bit lines corresponding to different first stacked structures that are connected through the same channel structure are all connected to different second conductive structures; different top selected gate layers included in different first stacked structures in the same memory plane are connected to the same third conductive structure; different top selected gate layers included in first stacked structures at the same position in the first direction of different memory planes are connected to different third conductive structures.

[0404] In some embodiments, a plurality of first stacked structures arranged in a stacked manner constitute a memory module; the memory device includes a first memory module and a second memory block; the first memory module and the second memory block are stacked in a first direction; a plurality of first conductive structures are connected to a gate layer of each of the first stacked structures in the first memory module and the second memory block.

[0405] In some embodiments, different bit lines corresponding to different first stacked structures with the same channel structure in the same memory module are connected to different second conductive structures; two bit lines corresponding to two specified first stacked structures in different memory modules are connected to each other; different top selected gate layers included in different first stacked structures in the same memory module are connected to the same third conductive structure; two top selected gate layers included in two first stacked structures in different memory modules are connected to different third conductive structures.

[0406] In some embodiments, different bit lines corresponding to different first stacked structures with the same channel structure in the same memory module are all connected to the same second conductive structure; different bit lines corresponding to two first stacked structures in different memory modules are all connected to different second conductive structures; different top selected gate layers included in different first stacked structures in the same memory module are connected to different third conductive structures; and two top selected gate layers included in two first stacked structures in different memory modules are connected to the same third conductive structure.

[0407] In some embodiments, a plurality of first stacked structures are disposed in a first region, a plurality of first conductive structures are disposed in a second region, a plurality of second conductive structures are disposed in a third region, and a plurality of third conductive structures are disposed in a fourth region; the second region is located in the middle of the first region; or, the second region is located on at least one side of the first region along a direction perpendicular to the stacking direction; the third region is located on at least one side of the first region along a third direction; and the fourth region is located between the first region and the second region.

[0408] It should be noted that in the embodiments of this application, the "one side of another area" refers to the relative positional relationship between the two areas, not the affiliation relationship between them. That is to say, "one side of an area" in the embodiments of this application can be understood as one end or edge of the area (i.e., belonging to the area), or it can be understood as one side or side of the area (i.e., belonging to the area outside the area).

[0409] It should be noted that the descriptions of the various components in the storage device in the above embodiments of this application can be understood with reference to the descriptions of the corresponding structures in the foregoing embodiments.

[0410] In this embodiment, a first conductive structure CT1 connects to any gate layer WL in each of the multiple first stacked structure decks. The first conductive structure CT1 can be located in either the first or second stacked structure. The first conductive structure CT1 can partially or completely penetrate either the first or second stacked structure. The first conductive structure CT1 can be located in the middle or at the edge of the first stacked structure. The multiple gate layers of the first stacked structure can form a stepped structure or be flush with a plane perpendicular to the first direction (the direction in which WL extends). The first conductive structure CT1 can include conductive pillars or hollow conductive layers, and optionally include a first connection portion perpendicular to the first direction. The first conductive structure CT1 connects any gate layer WL in each of the multiple first stacked structure decks to the word line driving circuit SD.

[0411] In this embodiment of the application, the first conductive structure CT1 is connected to any gate layer WL in each of the multiple first stacked structure decks. Then, the total number of gate layers included in a memory block is equal to the product of the number of decks and the number of word line driving circuits SD corresponding to the memory block.

[0412] In this embodiment of the application, for a fixed storage capacity, if the number of bit lines corresponding to a storage block in the folded architecture (as shown in Figure 2A) is Q (where Q is a positive integer); then the total number of storage blocks corresponding to a storage block in the array Y-axis folded architecture (as shown in Figure 2B) is still Q; then the total number of storage blocks corresponding to a storage block in the array X-axis folded architecture (as shown in Figure 2C) is still Q / N, where N is the number of decks included in a storage block, and N is an integer greater than 1; then the total number of storage blocks corresponding to a storage block in the array X-axis + Y-axis folded architecture (as shown in Figure 2D) is still Q / N, where N is the number of decks included in a storage block, and N is an integer greater than 1; then in the storage surface combined architecture (which can also be seen as a combination of two folded storage blocks, as shown in Figure 2E), the situation of each storage surface in the two combined storage surfaces can refer to the situation of the specific folded architecture, but the first conductive structure CT1 is shared by the two storage surfaces, and the sharing rate of the first conductive structure CT1 is further improved.

[0413] In this embodiment, each deck is interconnected via a source layer ACS and a bit line layer BL, and two decks form a two-stack structure architecture. Two-stack structures can be mixed-bonded to form multi-stack structure architectures, or adjacent decks can sequentially share a bit line layer BL or a shared ACS to form multiple multi-stack structure architectures. This not only improves the channel saturation current reduction problem caused by too many gate layers in folded architectures, but also saves on the corresponding bit line layers BL and ACS, reducing manufacturing costs.

[0414] In this embodiment, all decks' BLs are connected to the page buffer PB in the peripheral circuit through the second conductive structure CT2. The specific shape of the second conductive structure CT2 can be a circular, rectangular, or channel-like CH-shaped conductive post, or it can be directly set in the GLS.

[0415] In this embodiment, the parameters of the storage devices under various architectures are shown in Table 1. It should be noted that the explanations of the various parameters and quantities in Table 1 can be understood by referring to the descriptions of the various parameters and quantities mentioned above, where the memory block size and array efficiency can be calculated using the aforementioned calculation methods.

[0416] In Table 1, RS represents the resistance of the entire gate layer (WL). Among them, the resistance of the entire gate layer in the X-axis folding, multi-memory surface combination, and X+Y axis folding schemes is significantly reduced compared to the resistance of the entire gate layer in the non-folding scheme. This can reduce latency and thus improve the speed of read and write operations.

[0417] As shown in Table 1, compared to the non-folding scheme, each folding scheme can achieve at least one of the following: a reduction in memory block size or an improvement in array efficiency. The Y-folding scheme mainly improves array efficiency, the X-folding scheme mainly reduces memory block size, and the X+Y axis folding scheme achieves both a reduction in memory block size and an improvement in array efficiency.

[0418] Table 1

[0419] In this application embodiment, all four folding architectures can solve the problem of channel saturation current decrease as the number of stacked layers increases. In the array Y-axis folding architecture, the shared storage space (WL) of N decks allows for shared storage devices (SDs), thus reducing the total number of SDs, i.e., reducing the SD area occupied, and ultimately reducing the storage device area. In the array X-axis folding architecture, by reducing the storage space (BL) to 1 / N, the shared WL of N decks reduces the SD area by a factor of N, the chip size (CHIP*diesize) is reduced by 1 / N, the storage block size is reduced by 1 / N, and the WL RC is reduced by 1 / N². The storage plane combined architecture further reduces the SD area, improves array efficiency, and reduces the storage device area. The array X-axis + Y-axis folding architecture combines the advantages of the array Y-axis folding architecture and the array X-axis folding architecture.

[0420] In this embodiment, a channel structure runs through all the first stacked structure decks. The portion of the channel structure corresponding to each deck is called a sub-channel structure. During the execution of a read operation or a programming operation (or write operation), each sub-channel structure can be selected and deselected through the semiconductor layer (source layer ACS) and the second conductive layer (bit line layer BL) of the corresponding deck.

[0421] It should be noted that during each read operation, one sub-channel structure within a channel structure is the selected sub-channel group structure. The BL and TSG corresponding to this selected group channel structure are both selected BL (SelBL) and selected TSG (SelTSG). All other sub-channel groups within the same channel structure are unselected sub-channel groups, and their corresponding BL and TSG are both unselected BL (unSelBL) and selected TSG (unSelTSG). In each deck, the selected gate layer is SelWL, and the unselected gate layer is unSelWL.

[0422] In this application embodiment, the architecture of the aforementioned four types of folded storage devices is abstracted into two main categories: the first category: the BL of each deck is interconnected and the TSG is brought out separately; the second category: the TSG of each deck is interconnected and the BL is brought out separately.

[0423] Figure 14A is a schematic diagram of the layout of functional layers coupled to a channel structure including a storage device according to an embodiment of this application; Figure 14B is a schematic diagram of applying voltage to each functional layer in a selected sub-channel structure during a read operation according to an embodiment of this application; Figure 14C is a schematic diagram of applying voltage to each functional layer in an unselected sub-channel structure during a read operation according to an embodiment of this application; Figure 14D is a schematic diagram of applying voltage to each functional layer in a selected sub-channel structure during a programming operation according to an embodiment of this application; Figure 14E is a schematic diagram of applying voltage to each functional layer in an unselected sub-channel structure during a read operation according to an embodiment of this application.

[0424] Figure 15A is a second schematic diagram of the layout of functional layers coupled to a single channel structure including a storage device according to an embodiment of this application; Figure 15B is a second schematic diagram of applying voltage to each functional layer in a selected sub-channel structure during a read operation according to an embodiment of this application; Figure 15C is a second schematic diagram of applying voltage to each functional layer in an unselected sub-channel structure during a read operation according to an embodiment of this application; Figure 15D is a second schematic diagram of applying voltage to each functional layer in a selected sub-channel structure during a programming operation according to an embodiment of this application; Figure 15E is a second schematic diagram of applying voltage to each functional layer in an unselected sub-channel structure during a read operation according to an embodiment of this application.

[0425] The following will provide a detailed explanation of how to implement read and write operations for these two categories, using Figures 14A to 14E and 15A to 15E as examples.

[0426] This application provides a control method for a memory device. The memory device includes the memory device provided in this application. The channel structure is divided into multiple sub-channel structures by a semiconductor layer and a second conductive layer. A plurality of first conductive layers in a first stack structure include a top select gate layer and a gate layer. The top select gate layer is located at one end of the corresponding first stack structure along a first direction away from the end connected to the semiconductor layer of the channel structure in the corresponding first stack structure. The control method for the memory device includes: during a read operation, applying a first voltage to the top select gate and / or its coupled bit lines of an unselected sub-channel structure in the plurality of sub-channel structures; applying a second voltage to the top select gate and its coupled bit lines of a selected sub-channel structure in the plurality of sub-channel structures; applying a pass voltage to all unselected gate layers; and applying a read voltage to the selected gate layers.

[0427] In this embodiment, when the architecture of the memory device is of different types, the first voltage and the second voltage will differ based on the difference in the applied object. However, when the architecture of the memory device is of different types, the voltage applied to all unselected gate layers and the selected gate layers remains unchanged.

[0428] It should be noted that for unselected sub-channel structures, there is no selected gate layer. However, considering the sharing of gate layers among multiple decks, the gate layer in an unselected sub-channel structure that is connected to the selected gate layer in a selected sub-channel structure is also referred to as the selected gate layer. For unselected sub-channel structures, since their channels are in a deselected state, a read operation will not be performed even if a read voltage is applied to the gate layer.

[0429] In some embodiments, a plurality of first conductive layers in the first stacked structure further include bottom select gate layers; the bottom select gate layers are located at one end of the respective first stacked structure along a first direction, near the end of the semiconductor layer connected to the channel structure in the respective first stacked structure; the control method further includes: applying a second on-state voltage to all bottom select gate layers during a read operation.

[0430] In this embodiment, the storage device includes N (e.g., three) first stacked structures. For the first type: each deck has a separate BL interconnect and a separately brought-out TSG, as shown in Figure 14A. From top to bottom, it includes a first first stacked structure deck1, a second first stacked structure deck2, and a third first stacked structure deck3. Deck1 and deck2 share a source layer (Source), and deck2 and deck3 share a bit line layer (BL). Each first stacked structure includes a top select gate (TSG), multiple gate layers, and a bottom select gate (BSG). The multiple gate layers are illustrated as WL1 and WL2. The WL1 interconnect, WL2 interconnect, BL interconnect, BSG interconnect, Source interconnect, and TSG of all first stacked structures are separately brought out.

[0431] In some embodiments, the first voltage includes a cutoff voltage, and the second voltage includes a first on voltage; applying the first voltage to the top select gate of an unselected subchannel structure and / or its coupled bit lines, and applying the second voltage to the top select gate of a selected subchannel structure and its coupled bit lines, includes: applying a cutoff voltage to the top select gate of the unselected subchannel structure and applying the first on voltage to the top select gate of the selected subchannel structure.

[0432] In this embodiment, as shown in Figures 14B and 14C, a cutoff voltage (e.g., ground voltage) is applied to the top select gate (unSel TSG) of the unselected sub-channel structure, deactivating the unselected sub-channel structure. A first turn-on voltage (e.g., a voltage greater than the top select transistor threshold voltage) is applied to the top select gate (Sel TSG) of the selected sub-channel structure, turning the selected sub-channel structure on. Furthermore, a second turn-on voltage is applied to the bottom select gate (BSG) and the unselected gate layer (Unsel WL), a ground voltage is applied to the source layer, and a read voltage is applied to the selected gate layer (Sel WL). The BL current is then read to determine the storage state of the memory cell. Here, the first turn-on voltage may be the same as or different from the second turn-on voltage. The read voltage may be first-order or multi-order as shown in Figures 14B and 14C.

[0433] In this embodiment, the storage device includes N (e.g., three) first stacked structures. For the first type, each deck has a TSG interconnect and a separate BL (Bottom Layer), as shown in Figure 15A. From top to bottom, it includes a first first stacked structure deck1, a second first stacked structure deck2, and a third first stacked structure deck3. Deck1 and deck2 share a common source layer. Each first stacked structure includes a top select gate (TSG), multiple gate layers, and a bottom select gate (BSG). The multiple gate layers are illustrated as WL1 and WL2. The WL1 interconnect, WL2 interconnect, TSG interconnect, BSG interconnect, Source interconnect, and BL of all first stacked structures are brought out separately.

[0434] In some embodiments, the first voltage includes a programmable disable voltage, and the second voltage includes a programmable enable voltage; applying the first voltage to the top select gate of an unselected sub-channel structure and / or its coupled bit lines, and applying the second voltage to the top select gate of a selected sub-channel structure and its coupled bit lines, includes: applying a programmable disable voltage to the bit lines coupled to the unselected sub-channel structure, and applying a programmable enable voltage to the bit lines coupled to the selected sub-channel structure; applying a first enable voltage to all top select gate layers.

[0435] In this embodiment, as shown in Figures 15B and 15C, a programmable disable voltage (such as a ground voltage) is applied to the bit line unsel BL in the unselected sub-channel structure, causing the unselected sub-channel structure to be de-conducted; a programmable enable voltage is applied to the bit line Sel BL in the selected sub-channel structure, causing the selected sub-channel structure to be conducted. Furthermore, a second turn-on voltage is applied to the bottom select gate (BSG) and the unselected gate layer (Unsel WL), a ground voltage is applied to the source layer, and a read voltage is applied to the selected gate layer (Sel WL). Then, the BL current is read to determine the storage state of the memory cell. Here, the first turn-on voltage may be the same as or different from the second turn-on voltage. The read voltage may include a first order or multiple orders as shown in Figures 15B and 15C.

[0436] This application provides a control method for a memory device. The memory device includes the memory device provided in this application, wherein a channel structure is divided into multiple sub-channel structures by multiple first stacked structures; a plurality of first conductive layers in the first stacked structures include a top select gate layer and a gate layer; the top select gate layer is located at one end of the corresponding first stacked structure along a first direction away from the end connected to the semiconductor layer of the channel structure in the corresponding first stacked structure; the control method for the memory device includes: during a programming operation, applying a first voltage to the top select gate and / or its coupled bit lines of an unselected sub-channel structure in the plurality of sub-channel structures, applying a second voltage to the top select gate and its coupled bit lines of the selected sub-channel structures in the plurality of sub-channel structures; applying a pass voltage to all unselected gate layers, and applying a programming voltage to the selected gate layers.

[0437] In this embodiment, when the architecture of the memory device is of different types, the first voltage and the second voltage will differ based on the difference in the applied object. However, when the architecture of the memory device is of different types, the voltage applied to all unselected gate layers and the selected gate layers remains unchanged.

[0438] It should be noted that for unselected sub-channel structures, there is no selected gate layer. However, considering the sharing of gate layers among multiple decks, the gate layer in an unselected sub-channel structure that is connected to the selected gate layer in a selected sub-channel structure is also referred to as the selected gate layer. For unselected sub-channel structures, since their channels are in a deselected state, programming operations will not be performed even if a programming voltage is applied to the gate layer.

[0439] In some embodiments, a plurality of first conductive layers in a first stacked structure further include a bottom select gate layer; the bottom select gate layer is located at one end of the respective first stacked structure along a first direction near the end of the semiconductor layer connected to the channel structure in the respective first stacked structure; the control method further includes: applying a cutoff voltage to all bottom select gate layers during a programming operation.

[0440] In this embodiment, the storage device includes N (e.g., three) first stacked structures. For the first type: each deck has a separate BL interconnect and a separately brought-out TSG, as shown in Figure 14A. From top to bottom, it includes a first first stacked structure deck1, a second first stacked structure deck2, and a third first stacked structure deck3. Deck1 and deck2 share a source layer (Source), and deck2 and deck3 share a bit line layer (BL). Each first stacked structure includes a top select gate (TSG), multiple gate layers, and a bottom select gate (BSG). The multiple gate layers are illustrated as WL1 and WL2. The WL1 interconnect, WL2 interconnect, BL interconnect, BSG interconnect, Source interconnect, and TSG of all first stacked structures are separately brought out.

[0441] In some embodiments, the first voltage includes a cutoff voltage and the second voltage includes an on voltage; applying the first voltage to the top select gate of an unselected subchannel structure and / or its coupled bit lines, and applying the second voltage to the top select gate of a selected subchannel structure and its coupled bit lines, includes: applying a cutoff voltage to the top select gate of the unselected subchannel structure and applying an on voltage to the top select gate of the selected subchannel structure.

[0442] In this embodiment, as shown in Figures 14D and 14E, a cutoff voltage (e.g., ground voltage) is applied to the top select gate (unsel TSG) of the unselected sub-channel structure, deactivating the unselected sub-channel structure. A first turn-on voltage (e.g., a voltage greater than the top select transistor threshold voltage) is applied to the top select gate (Sel TSG) of the selected sub-channel structure, turning the selected sub-channel structure on. Furthermore, the bottom select gate (BSG) is activated, a cutoff voltage (e.g., ground voltage) is applied, a second turn-on voltage is applied to the unselected gate layer (Unsel WL), a ground voltage is applied to the source layer, and a programming voltage is applied to the selected gate layer (Sel WL). Afterward, the selected sub-channel structure completes the programming operation. Here, the first turn-on voltage can be the same as or different from the second turn-on voltage. The second turn-on voltage applied to the unselected gate layer (Unsel WL) must begin before the programming voltage is applied to the selected gate layer (Sel WL) and end after the programming voltage is applied to the selected gate layer (Sel WL). Furthermore, given the high programming voltage, the final programming voltage can be obtained by multiple boosting steps as shown in Figures 14D and 14E.

[0443] In this embodiment, the storage device includes N (e.g., three) first stacked structures. For the first type, each deck has a TSG interconnect and a separate BL (Bottom Layer), as shown in Figure 15A. From top to bottom, it includes a first first stacked structure deck1, a second first stacked structure deck2, and a third first stacked structure deck3. Deck1 and deck2 share a common source layer. Each first stacked structure includes a top select gate (TSG), multiple gate layers, and a bottom select gate (BSG). The multiple gate layers are illustrated as WL1 and WL2. The WL1 interconnect, WL2 interconnect, TSG interconnect, BSG interconnect, Source interconnect, and BL of all first stacked structures are brought out separately.

[0444] In some embodiments, the first voltage includes a programmable disable voltage, and the second voltage includes a programmable enable voltage; applying the first voltage to the top select gate of an unselected sub-channel structure and / or its coupled bit lines, and applying the second voltage to the top select gate of a selected sub-channel structure and its coupled bit lines, includes: applying a programmable disable voltage to the bit lines coupled to the unselected sub-channel structure, applying a programmable enable voltage to the bit lines coupled to the selected sub-channel structure; and applying an enable voltage to all top select gate layers.

[0445] In this embodiment, as shown in Figures 15D and 15E, a programmable disable voltage (such as a ground voltage) is applied to the bit line unSel BL in the unselected sub-channel structure, deactivating the unselected sub-channel structure; a programmable enable voltage is applied to the bit line Sel BL in the selected sub-channel structure, enabling the selected sub-channel structure. Furthermore, a bottom select gate (BSG) is established, and a cutoff voltage (such as a ground voltage) is applied. A second turn-on voltage is applied to the unselected gate layer Unsel WL, a ground voltage is applied to the source layer, and a programming voltage is applied to the selected gate layer Sel WL. Afterward, the selected sub-channel structure completes the programming operation. Here, the first turn-on voltage can be the same as or different from the second turn-on voltage. The second turn-on voltage applied to the unselected gate layer Unsel WL needs to begin before the programming voltage is applied to the selected gate layer Sel WL and end after the programming voltage is applied to the selected gate layer Sel WL. Furthermore, given the high programming voltage, multiple boosting steps as shown in Figures 15D and 15E can be used to obtain the final programming voltage.

[0446] This application provides a method for manufacturing a storage device, as shown in FIG16. The method for manufacturing the storage device includes:

[0447] Step 1601: Form a plurality of first stacked structures arranged in a stacked manner; the first stacked structure includes a plurality of first conductive layers and first dielectric layers arranged alternately along a first direction.

[0448] Step 1602: Form a first conductive structure, the first conductive structure extending along a first direction and connected to a first conductive layer of at least two of the plurality of first stacked structures.

[0449] Step 1603: Form multiple channel structures; the channel structures penetrate multiple first stacked structures.

[0450] Step 1604: Form at least one semiconductor layer, wherein the semiconductor layer is connected to at least one channel structure in a first stacked structure.

[0451] It should be noted that the steps shown in Figure 16 are not exclusive, and other steps can be performed before, after, or between any of the steps shown in the operation; the order of the steps shown in Figure 16 can be adjusted according to actual needs.

[0452] In some embodiments, forming a plurality of first stacked structures includes: providing a semiconductor structure; the semiconductor structure includes a plurality of semiconductor units, each semiconductor unit including at least a stacked layer, the stacked layer including a plurality of isolation material layers and dielectric layers alternately disposed along a first direction; dividing the semiconductor structure along a second direction and / or a third direction to form a plurality of independent semiconductor units; the second direction and the third direction intersect and are both perpendicular to the first direction; stacking the plurality of semiconductor units along the first direction to form a plurality of stacked semiconductor units; and replacing the isolation material layers in the plurality of stacked semiconductor units with a first conductive layer to form a plurality of stacked first stacked structures.

[0453] In this embodiment, the folded storage device is formed by dividing along the X-axis and / or Y-axis and stacking the divided semiconductor unit structures along the Z-axis.

[0454] In some implementations, laser cutting is used to divide the semiconductor structure into multiple semiconductor units.

[0455] In some embodiments, stacking a plurality of semiconductor cells along a first direction includes: using a bonding process to stack a plurality of semiconductor cells along a first direction.

[0456] In some implementations, the materials of the isolation material layer include, but are not limited to, silicon nitride; the materials of the first conductive layer include, but are not limited to, tungsten and polysilicon; and the materials of the dielectric layer include, but are not limited to, silicon oxide. In some embodiments, wet etching and deposition processes can be used to replace the isolation material layer in a plurality of stacked semiconductor cells with the first conductive layer.

[0457] In some embodiments, the semiconductor cell further includes a semiconductor layer located on a first side and a second conductive layer located on a second side; the first side and the second side are respectively located on opposite sides of the stacked layer along a first direction; the second conductive layer includes a plurality of bit lines spaced apart along a second direction and extending along a third direction; stacking the plurality of semiconductor cells along the first direction includes: stacking every two semiconductor cells in the plurality of semiconductor cells to form a plurality of semiconductor cell groups; the two semiconductor cells in each semiconductor cell group are stacked in a direction toward their respective first sides; and stacking the plurality of semiconductor cell groups along the first direction.

[0458] In this embodiment, the semiconductor unit includes a semiconductor layer and a second conductive layer on both sides along the Z-axis. After dicing, the subsequent stacking process can be directly executed, and two adjacent semiconductor units are stacked in the direction of the semiconductor layer.

[0459] In some embodiments, the number of independent semiconductor units formed is a first number N; the semiconductor structure is divided along the second direction, and the number of bit lines contained in the semiconductor unit is a fourth number (folded in the X-axis direction, the number of bit lines is 1 / N of the original); the semiconductor structure is divided along the third direction, and the number of bit lines contained in the semiconductor unit is a fifth number (folded in the Y-axis direction, the number of bit lines remains unchanged); the fifth number is the product of the first number and the fourth number.

[0460] In some embodiments, the manufacturing method further includes: removing the semiconductor layer corresponding to one of the semiconductor cells before stacking every two semiconductor cells in the plurality of semiconductor cells; the remaining semiconductor layer forms a semiconductor layer that is connected to both semiconductor cells.

[0461] In this embodiment of the application, before stacking two adjacent semiconductor units in the direction of the semiconductor layer, one semiconductor layer is removed to form a common semiconductor layer between the two adjacent semiconductor units.

[0462] In other embodiments, two adjacent semiconductor units are stacked directly with both facing the semiconductor layer, thereby obtaining a structure with two semiconductor layers between the two stacked semiconductor units.

[0463] In some embodiments, the semiconductor cell further includes a semiconductor layer located on a first side and a second conductive layer located on a second side; the first side and the second side are respectively located on opposite sides of the stacked layer along a first direction; the second conductive layer includes a plurality of bit lines spaced apart along a second direction and extending along a third direction; stacking the plurality of semiconductor cells along the first direction includes: stacking two semiconductor cells that are adjacent along the first direction in the plurality of semiconductor cells in a direction toward different sides of the respective semiconductor cells.

[0464] In this embodiment, the semiconductor unit includes a semiconductor layer and a second conductive layer on both sides along the Z-axis. After dicing, the subsequent stacking process can be performed directly. Two adjacent semiconductor units are stacked with one facing the semiconductor layer and the other facing the second conductive layer.

[0465] In some embodiments, the manufacturing method further includes: forming a semiconductor layer and a second conductive layer on opposite sides of each semiconductor cell along a first direction; the second conductive layer includes a plurality of bit lines spaced apart along a second direction and extending along a third direction; stacking the plurality of semiconductor cells along the first direction, including: stacking the plurality of semiconductor cells having the semiconductor layer and the second conductive layer formed thereon along the first direction.

[0466] In this embodiment, the semiconductor unit may not include a semiconductor layer and a second conductive layer on both sides along the Z-axis. Based on this, after the dicing is performed, a semiconductor layer and a second conductive layer can be formed on both sides of the diced structure along the Z-axis before the stacking process is performed.

[0467] In some embodiments, the manufacturing method further includes: when replacing the isolation material layer in a plurality of stacked semiconductor units with a first conductive layer, replacing a portion of the isolation material layer in each of the plurality of semiconductor units with the first conductive layer, wherein the stacked structure of the portion of the isolation material layer that has been replaced forms a first stacked structure, and the stacked structure of the portion of the isolation material layer that has not been replaced forms a second stacked structure; the dielectric layer corresponding to the first stacked structure is a first dielectric layer, and the dielectric layer corresponding to the second stacked structure is a second dielectric layer; forming the first conductive structure includes: forming the first conductive structure in the second stacked structure.

[0468] In this embodiment, the basic frameworks of the first and second stacked structures are formed together. Then, the insulating material layer is replaced with a portion of the first conductive structure to form the first stacked structure, and the portion of the stacked structure where the insulating material layer is not replaced forms the second stacked structure. It can be seen that the first dielectric layer and the second dielectric layer are on the same layer and are made of the same material; the remaining insulating material layer forms an insulating layer, which is on the same layer as the first conductive layer, but they are made of different materials.

[0469] In some embodiments, the storage device includes a first stacked structure, a second stacked structure, and a third stacked structure. The second stacked structure and the third stacked structure are arranged along the Y-axis and are both located in the connection region SS. The third stacked structure includes an alternately stacked third conductive layer and a third dielectric layer. The second stacked structure includes an alternately stacked isolation layer and a second dielectric layer. The first conductive layer, the second conductive layer, and the isolation layer are on the same layer, and the first dielectric layer, the second dielectric layer, and the third dielectric layer are on the same layer.

[0470] In some embodiments, the process of forming the first stacked structure, the second stacked structure, and the third stacked structure may include the following steps:

[0471] First, an initial stacked structure of isolation material layer and dielectric layer is formed in the array region GB and the connection region SS; then, all the isolation layers in the array region are replaced with the first conductive layer to form the first stacked structure; then, a portion of the isolation layers in the connection regions on both sides of the gate gap structure are replaced with the third conductive layer to form the third stacked structure; in the connection regions, the isolation layers and dielectric layers that have not been replaced are retained to form the second stacked structure.

[0472] In some embodiments, the manufacturing method further includes: forming a plurality of second conductive structures, the second conductive structures extending along a first direction in a first stacked structure and connected to a bit line of at least one second conductive layer.

[0473] In some embodiments, a dry etching process and a deposition process can be used to form the second conductive structure.

[0474] In some embodiments, a plurality of first conductive layers in the first stacked structure include a top selected gate layer and a gate layer; the manufacturing method further includes: forming a third conductive structure, the third conductive structure extending along a first direction in the first stacked structure and connected to a top selected gate layer of at least one of the plurality of first stacked structures; the first conductive structure is connected to a gate layer of at least two of the plurality of first stacked structures.

[0475] In some embodiments, forming the third conductive structure includes: for each first stacked structure, forming a contact portion of the third conductive structure extending along the stacking direction of the plurality of first stacked structures and connected to a top selected gate layer; and forming a second connection portion of the third conductive structure extending along a direction perpendicular to the stacking direction and connected to the contact structure; forming a third contact hole penetrating the plurality of first stacked structures, and forming a second insulating layer on the sidewall of the third contact hole; filling the third contact hole with the second insulating layer with conductive material to form a second lead-out portion of the third conductive structure; and connecting the second lead-out portion to a second connection portion corresponding to one or more first stacked structures.

[0476] In addition to the aforementioned cutting and stacking method, folded memory devices can also be formed directly through layer-by-layer growth in this embodiment. In some embodiments, forming a plurality of first stacked structures includes: sequentially forming a plurality of first stacked structures; the first stacked structure includes a plurality of alternating first conductive layers and dielectric layers; the manufacturing method further includes: alternately forming semiconductor layers and second conductive layers on both sides of the plurality of first stacked structures along a first direction and between each pair of adjacent first stacked structures.

[0477] In this embodiment, multiple stacked structures can be formed along the Z-axis direction; the multiple stacked structures can be divided along the Z-axis direction to split the stacked structure into multiple independent stacked structures; a bit line layer BL and a source layer ACS can be formed on the upper and lower sides of each stacked structure to form multiple independent semiconductor units; all semiconductor units can be formed into a memory device.

[0478] The following will provide an exemplary description of the manufacturing methods for the four memory device architectures described above.

[0479] This application provides a method for manufacturing a storage device, specifically for the aforementioned array Y-axis folded architecture, as shown in FIG3A. The method for manufacturing the storage device includes:

[0480] Step a1: Provide a semiconductor structure, which includes a stacked structure, the stacked structure including a plurality of semiconductor units arranged along the Y-axis direction, the Y-axis direction being parallel to the extension direction of the bit line BL, the semiconductor unit including the stacked structure and the bit line layer BL and the source layer ACS located on the upper and lower sides of the stacked structure respectively.

[0481] Step a2: Divide the stacked structure along the Y direction to separate all semiconductor units from each other.

[0482] Step a3: Stack all semiconductor cells along the Z-axis to form a memory device.

[0483] In some implementations, there are various ways to stack all the semiconductor cells, including but not limited to face-to-face stacking, back-to-back stacking, or a combination thereof. Here, after dividing the memory block, each semiconductor cell includes a top surface and a bottom surface. Face-to-face stacking may include the top surface of one semiconductor cell contacting and stacking with the top surface of another semiconductor cell, or the bottom surface of one semiconductor cell contacting and stacking with the bottom surface of another semiconductor cell. Back-to-back stacking may include the top surface of one semiconductor cell contacting and stacking with the bottom surface of another semiconductor cell.

[0484] In some implementations, the stacking method between semiconductor cells includes, but is not limited to, hybrid bonding.

[0485] In some embodiments, the formed memory device includes N first stacked structures, each first stacked structure includes l gate layers WL, the number of bit lines BL corresponding to the stacked structure is Q, the number of bit lines BL corresponding to each semiconductor unit is Q, and the number of bit lines BL of the memory device formed by stacking the semiconductor units is also Q.

[0486] This application provides a method for manufacturing a storage device, specifically for the aforementioned array Y-axis folded architecture, as shown in FIG3B. The method for manufacturing the storage device includes:

[0487] Step b1: Provide a semiconductor structure, which includes a stacked structure comprising a plurality of semiconductor cells arranged along the X-axis direction, the X-axis direction being perpendicular to the extension direction of the bit line BL;

[0488] Step b2: Divide the stacked structure along the X direction to separate multiple semiconductor units from each other;

[0489] Step b3: Stack all semiconductor cells along the Z-axis to form a memory device.

[0490] In some implementations, there are various ways to stack all the semiconductor units, including but not limited to stacking all the semiconductor units face to face, stacking all the semiconductor units face to back, or a combination thereof.

[0491] In some implementations, the stacking method between semiconductor cells includes, but is not limited to, hybrid bonding.

[0492] In some embodiments, the formed memory device includes N first stacked structures, each first stacked structure includes l gate layers WL, the number of bit lines BL corresponding to the stacked structure is Q, the number of bit lines BL corresponding to each semiconductor unit is Q / N, and the number of bit lines BL of the memory device formed by stacking the semiconductor units is also Q / N.

[0493] This application provides a method for manufacturing a storage device, specifically for the aforementioned array Y-axis folded architecture, as shown in FIG3C. The method for manufacturing the storage device includes:

[0494] Step c1: Provide a semiconductor structure, which includes a stacked structure comprising a plurality of semiconductor units arranged along the X-axis and the Y-axis, wherein the X-axis is perpendicular to the extension direction of the bit line BL and the Y-axis is parallel to the extension direction of the bit line BL.

[0495] Step c2: Divide the initial storage device along the X direction to separate multiple unit structures from each other;

[0496] Step c3: Divide the unit structure along the Y direction to separate all semiconductor units from each other;

[0497] Step c4: Stack all semiconductor cells along the Z-axis to form a memory device.

[0498] In some implementations, there are various ways to stack all the semiconductor units, including but not limited to stacking all the semiconductor units face to face, stacking all the semiconductor units face to back, or a combination thereof.

[0499] In some implementations, the stacking method between semiconductor cells includes, but is not limited to, hybrid bonding.

[0500] In other embodiments, the semiconductor structure can be implemented in various other ways, such as first dividing along the Y-axis and then dividing along the X-axis to form a memory device, or other methods that can stack different semiconductor units.

[0501] In other embodiments, the arrangement of stacking all semiconductor units can take various forms. They can be arranged according to Model, where all unit structures with the same finger are stacked together to form a semiconductor unit cell comprising multiple stacked structures, and then these multiple semiconductor unit cells are stacked together to form a storage device. Alternatively, all semiconductor units can be stacked sequentially, such that all unit structures with the same Model are stacked together, or any other feasible method can be used. For example, a stacking structure arranged from top to bottom could have semiconductor units 1 to N in the first row corresponding to Model 1, and semiconductor units 1 to N in the second row corresponding to Model 2. Similarly, a stacking structure arranged from left to right could have semiconductor units 1 to N in the first column corresponding to Model 1, and semiconductor units 1 to N in the second column corresponding to Model 2.

[0502] In one embodiment, the formed memory device includes M memory modules, each memory module includes N stacked structures, each stacked structure includes l gate layers WL, the number of bit lines BL corresponding to the stacked structure is Q, the number of bit lines BL corresponding to each semiconductor unit is Q / N, and the number of bit lines BL of the memory device formed by stacking the semiconductor units is also Q / N.

[0503] This application provides another storage system, including: the storage device as described in the above embodiments of this application.

[0504] In some embodiments, the storage device includes a three-dimensional NAND flash memory.

[0505] The memory array in this application embodiment may include multiple memory cells. Each memory cell may be configured to store at least one bit of data. For example, the memory cell in this application embodiment may be an SLC configured to store one bit of data, or an MLC configured to store two bits of data, or a TLC configured to store three bits of data, or a QLC configured to store four bits of data, or even configured to store more bits of data.

[0506] In some embodiments, the storage system further includes a memory controller connected to the storage device and used to control the storage device.

[0507] In some embodiments, the system described above may be a memory system 102 as shown in FIG. 17. The memory system 102 includes a memory controller 106 and a memory device 104 coupled to the memory controller 106. The controller in the above embodiments may be the memory controller 106 as shown in FIG. 17, 18, and 19. In other embodiments, the system described above may be a system 100 as shown in FIG. 17. The system 100 includes a host device 108 and a memory system 102 coupled to the host device 108. The controller in the above embodiments may be a control component independent of the memory controller 106, such as the CPU in the host device. The input data here includes vectors or matrices.

[0508] According to some embodiments, as shown in FIG17, a memory controller 106 is coupled to a memory device 104 and a host device 108, and is configured to control the operation of the memory device 104, such as read, erase, program, and compute operations. The memory controller 106 can manage data stored in the memory device 104 and communicate with the host device 108. In some embodiments, the memory controller 106 is designed to operate in low duty cycle environments, such as secure digital cards, compact flash memory cards, Universal Serial Bus flash drives, or other media used in electronic devices such as personal calculators, digital cameras, mobile phones, etc. In some embodiments, the memory controller 106 is designed to operate in high duty cycle environments, such as SSDs or embedded multimedia cards used as data storage in mobile devices such as smartphones, tablet computers, laptop computers, etc., and in enterprise memory arrays.

[0509] The memory controller 106 and one or more memory devices 104 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an embedded multimedia card package). That is, the memory system 102 can be implemented and packaged into different types of end electronic products. In one example shown in FIG. 18, the memory controller 106 and a single memory device 104 can be integrated into a memory card 202. The memory card 202 can include a compact flash card, a smart media card, a memory stick, a multimedia card, a secure digital card, UFS, etc. The memory card 202 may also include a memory card connector 204 that couples the memory card 202 to a host device (e.g., host device 108 in FIG. 17). In another example shown in FIG. 19, the memory controller 106 and multiple memory devices 104 can be integrated into an SSD 206. The SSD 206 may also include an SSD connector 208 that couples the SSD 206 to a host device (e.g., host device 108 in FIG. 17). In some implementations, the storage capacity and / or operating speed of SSD 206 is greater than that of memory card 202.

[0510] This application embodiment also provides a method for manufacturing a storage system, including:

[0511] A storage device is formed; in some embodiments, the storage device may include a three-dimensional NAND type memory; in some embodiments, the storage device may be the storage device as described in the above embodiments of this application;

[0512] A memory controller is formed, which is connected to the memory device and is used to control the memory device.

[0513] It should be noted that the technical solutions described in the embodiments of this application can be combined arbitrarily without conflict.

[0514] This application provides specific embodiments, but its scope of protection is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A memory device, comprising: a plurality of first stack structures arranged in a stack; the first stack structure comprises a plurality of first conductive layers and a plurality of first dielectric layers arranged alternately along a first direction; a first conductive structure extending along the first direction and connected to one first conductive layer of at least two first stack structures among the plurality of first stack structures; a plurality of channel structures penetrating the plurality of first stack structures; at least one semiconductor layer connected to a channel structure in at least one first stack structure.

2. The memory device of claim 1, wherein, a cross-sectional shape of the plurality of first stack structures along the first direction comprises a step shape; each step in the step shape corresponds to one first conductive layer and one first dielectric layer adjacent to each other; the first conductive structure extends along the first direction in the first stack structure and is connected to at least two steps where one first conductive layer of the at least two first stack structures is located.

3. The memory device of claim 1, wherein, the memory device further comprises a second stack structure comprising a plurality of isolation layers and a plurality of second dielectric layers arranged alternately along the first direction; the first conductive structure comprises a first lead-out portion and a plurality of first connection portions; the first lead-out portion extends along the first direction in the second stack structure and is connected to the plurality of first connection portions; each first connection portion is located in one isolation layer and is connected to one first conductive layer of a corresponding first stack structure among the at least two first stack structures.

4. The memory device of any one of claims 1 to 3, wherein, the first conductive structure is connected to one first conductive layer of each first stack structure among the plurality of first stack structures.

5. The memory device of claim 4, wherein, first conductive layers connected to the same first conductive structure in different first stack structures are located at the same distance from the semiconductor layer connected to the channel structure in the corresponding first stack structure.

6. The memory device of claim 4, wherein, first conductive layers connected to the same first conductive structure in two different first stack structures are located at different distances from the semiconductor layer connected to the channel structure in the corresponding first stack structure.

7. The memory device of any one of claims 1 to 3, wherein, the memory device further comprises a peripheral circuit; the peripheral circuit comprises a word line driving circuit; one first conductive layer of the at least two first stack structures is connected to the same word line driving circuit through the first conductive structure.

8. The memory device of claim 7, wherein, an area where the word line driving circuit is arranged and an area where the first conductive structure is arranged are aligned with each other along the first direction.

9. The memory device of claim 7, wherein, the memory device has a first number of first stack structures, and each first stack structure has a second number of first conductive layers; the memory device has a third number of word line driving circuits, and the third number is less than or equal to a product of the first number and the second number.

10. The memory device of any one of claims 1 to 3, wherein, the plurality of first stack structures are arranged in a first area, and the first conductive structure is arranged in a second area located in the middle of the first area.

11. The memory device of any one of claims 1 to 3, wherein, the plurality of first stack structures are arranged in a first area, and the first conductive structure is arranged in a second area located on at least one side of the first area along a direction perpendicular to the first direction.

12. The memory device of any one of claims 1 to 3, wherein, One of the at least one semiconductor layer is located between and connected to channel structures in two adjacent first stack structures.

13. The memory device of any one of claims 1 to 3, wherein, at least one second conductive layer and a plurality of second conductive structures; One of the second conductive layers is connected to the channel structure of at least one of the first stack structures; one of the second conductive layers comprises a plurality of bit lines spaced apart along a second direction and extending along a third direction; the second direction and the third direction are both perpendicular to the first direction; The second conductive structures extend along the first direction in the first stack structures and are connected to one of the bit lines of at least one of the second conductive layers.

14. The memory device of claim 13, wherein, The plurality of first stack structures are arranged in a first region, and the plurality of second conductive structures are arranged in a third region, the third region being located on at least one side of the first region along the third direction.

15. The memory device of any one of claims 1 to 3, wherein, The memory device further comprises third conductive structures; a plurality of the first conductive layers in the first stack structures comprise a top select gate layer and a gate layer; the top select gate layer is located at one end of the corresponding first stack structure along the first direction, away from the semiconductor layer connected to the channel structure in the corresponding first stack structure; The third conductive structures extend along the first direction in the first stack structures and are connected to the top select gate layer comprised by at least one of the first stack structures; The first conductive structures are connected to one of the gate layers of at least two of the first stack structures.

16. The memory device of claim 15, wherein, The plurality of first stack structures are arranged in a first region, and the first conductive structures are arranged in a second region, and the third conductive structures are arranged in a fourth region; The fourth region is located between the first region and the second region.

17. The memory device of claim 15, wherein, The third conductive structures comprise a second lead-out portion, a second connecting portion, and a contact portion; the second lead-out portion extends along the first direction and is connected to the second connecting portion; the second connecting portion extends along a second direction and is connected to the contact portion; the contact portion extends along the first direction and is connected to the top select gate layer; the second direction is perpendicular to the first direction.

18. The memory device of any one of claims 1 to 3, wherein, The plurality of first stack structures are arranged in a first region, and the first conductive structures are arranged in a second region, and the third conductive structures are arranged in a fourth region; The fourth region is located between the first region and the second region.

19. The memory device of claim 18, wherein, The third conductive structures comprise a second lead-out portion, a second connecting portion, and a contact portion; the second lead-out portion extends along the first direction and is connected to the second connecting portion; the second connecting portion extends along a second direction and is connected to the contact portion; the contact portion extends along the first direction and is connected to the top select gate layer; the second direction is perpendicular to the first direction. The plurality of first stack structures are arranged in a first region, and the first conductive structures are arranged in a second region, and the third conductive structures are arranged in a fourth region; 20. A memory system comprising: The fourth region is located between the first region and the second region. The third conductive structures comprise a second lead-out portion, a second connecting portion, and a contact portion; the second lead-out portion extends along the first direction and is connected to the second connecting portion; the second connecting portion extends along a second direction and is connected to the contact portion; the contact portion extends along the first direction and is connected to the top select gate layer; the second direction is perpendicular to the first direction. The plurality of first stack structures are arranged in a first region, and the first conductive structures are arranged in a second region, and the third conductive structures are arranged in a fourth region; The fourth region is located between the first region and the second region. The third conductive structures comprise a second lead-out portion, a second connecting portion, and a contact portion; the second lead-out portion extends along the first direction and is connected to the second connecting portion; the second connecting portion extends along a second direction and is connected to the contact portion; the contact portion extends along the first direction and is connected to the top select gate layer; the second direction is perpendicular to the first direction. The plurality of first stack structures are arranged in a first region, and the first conductive structures are arranged in a second region, and the third conductive structures are arranged in a fourth region; The fourth region is located between the first region and the second region. The third conductive structures comprise a second lead-out portion, a second connecting portion, and a contact portion; the second lead-out portion extends along the first direction and is connected to the second connecting portion; the second connecting portion extends along a second direction and is connected to the contact portion; the contact portion extends along the first direction and is connected to the top select gate layer; the second direction is perpendicular to the first direction. The plurality of first stack structures are arranged in a first region, and the first conductive structures are arranged in a second region, and the third conductive structures are arranged in a fourth region; The fourth region is located between the first region and the second region. The third conductive structures comprise a second lead-out portion, a second connecting portion, and a contact portion; the second lead-out portion extends along the first direction and is connected to the second connecting portion; the second connecting portion extends along a second direction and is connected to the contact portion; the contact portion extends along the first direction and is connected to the top select gate layer; the second direction is perpendicular to the first direction. The memory device of any one of claims 1 to 19.

21. A manufacturing method of a memory device, comprising: forming a plurality of first stack structures arranged in a stack; the first stack structures comprising a plurality of first conductive layers and first dielectric layers arranged alternately along a first direction; forming a first conductive structure, the first conductive structure extending along the first direction and connecting to one first conductive layer of at least two first stack structures among the plurality of first stack structures; forming a plurality of channel structures; the channel structures penetrating the plurality of first stack structures; forming at least one semiconductor layer, one semiconductor layer connecting to channel structures in at least one first stack structure.

22. The method of manufacturing a memory device according to claim 21, wherein, forming a plurality of first stack structures arranged in a stack, comprising: providing a semiconductor structure; the semiconductor structure comprising a plurality of semiconductor units, each semiconductor unit comprising at least a stack layer, the stack layer comprising a plurality of insulating material layers and dielectric layers arranged alternately along a first direction; dividing the semiconductor structure along a second direction and / or a third direction to form a plurality of independent semiconductor units; the second direction and the third direction intersecting and both being perpendicular to the first direction; stacking the plurality of semiconductor units along the first direction to form a plurality of semiconductor units arranged in a stack; replacing insulating material layers in the plurality of semiconductor units arranged in a stack with first conductive layers to form a plurality of first stack structures arranged in a stack.

23. The method of manufacturing a memory device according to claim 22, wherein, each semiconductor unit further comprises a semiconductor layer on a first side and a second conductive layer on a second side; the first side and the second side are respectively on opposite sides of the stack layer along the first direction; the second conductive layer comprises a plurality of bit lines spaced along the second direction and extending along the third direction; stacking the plurality of semiconductor units along the first direction comprises: stacking every two semiconductor units in the plurality of semiconductor units to form a plurality of semiconductor unit groups; the two semiconductor units in each semiconductor unit group are stacked in a direction towards respective first sides of the two semiconductor units; stacking the plurality of semiconductor unit groups along the first direction.

24. The method of manufacturing a memory device according to claim 23, wherein, the method further comprises: before stacking every two semiconductor units in the plurality of semiconductor units, removing a semiconductor layer corresponding to one semiconductor unit; a remaining semiconductor layer connects to both semiconductor units.

25. The method of manufacturing a memory device according to claim 22, wherein, the method further comprises: forming a semiconductor layer and a second conductive layer on opposite sides of each semiconductor unit along the first direction; the second conductive layer comprises a plurality of bit lines spaced along the second direction and extending along the third direction; stacking the plurality of semiconductor units along the first direction comprises: stacking the plurality of semiconductor units formed with semiconductor layers and second conductive layers along the first direction.

26. The method of manufacturing a memory device according to claim 22, wherein, each semiconductor unit further comprises a semiconductor layer on a first side and a second conductive layer on a second side; the first side and the second side are respectively on opposite sides of the stack layer along the first direction; the second conductive layer comprises a plurality of bit lines spaced along the second direction and extending along the third direction; stacking the plurality of semiconductor units along the first direction comprises: stacking two semiconductor units adjacent along the first direction in the plurality of semiconductor units in a direction towards different sides of the respective semiconductor units.

27. The method of fabricating a memory device according to any one of claims 23 to 26, wherein, stacking the plurality of semiconductor units along the first direction comprises: The plurality of semiconductor units are stacked along the first direction by a bonding process.

28. The method of manufacturing a memory device according to claim 22, wherein, The method further comprises: When replacing the isolation material layers in the plurality of semiconductor units in the stacked arrangement with the first conductive layers, a portion of each isolation material layer in the plurality of semiconductor units is replaced with the first conductive layer, a portion of the stacked structure of the isolation material layer that is replaced forms the first stacked structure, and a portion of the stacked structure of the isolation material layer that is not replaced forms a second stacked structure; the dielectric layer corresponding to the first stacked structure is a first dielectric layer, and the dielectric layer corresponding to the second stacked structure is a second dielectric layer; The first conductive structure is formed by: The first conductive structure is formed in the second stacked structure.

29. The method of manufacturing a memory device according to Claim 21, wherein, The method further comprises: A plurality of second conductive structures are formed, the second conductive structures extend along the first direction in the first stacked structure and are connected to one bit line of at least one second conductive layer.

30. The method of manufacturing a memory device according to Claim 21, wherein, The first conductive layers in the first stacked structure include a top select gate layer and a gate layer. The method further comprises: A third conductive structure is formed, the third conductive structure extends along the first direction in the first stacked structure and is connected to one top select gate layer of at least one first stacked structure of the plurality of first stacked structures. The first conductive structure is connected to one gate layer of at least two first stacked structures of the plurality of first stacked structures.

31. The method of manufacturing a memory device according to claim 21, wherein, The plurality of first stacked structures arranged in a stacked manner are formed by: The plurality of first stacked structures arranged in a stacked manner are formed sequentially; the first stacked structure includes a plurality of first conductive layers and dielectric layers arranged alternately. The method further comprises: the semiconductor layers and the second conductive layers are formed alternately on both sides of the plurality of first stacked structures along the first direction and between each adjacent two first stacked structures.

32. A memory device, comprising: a plurality of first stacked structures arranged in a stacked manner; the first stacked structure includes a plurality of first conductive layers and first dielectric layers arranged alternately along a first direction; a plurality of channel structures; the channel structures pass through the plurality of first stacked structures; at least one semiconductor layer; the semiconductor layer is connected to the channel structure in at least one first stacked structure; at least one second conductive layer; one second conductive layer is located between two adjacent first stacked structures and is connected to the channel structure in at least one first stacked structure; one semiconductor layer and one second conductive layer connected to the channel structure in the same first stacked structure are arranged on both sides of the first stacked structure along the first direction, respectively.

33. The memory device of claim 32, wherein, The second conductive layer includes a plurality of bit lines spaced along a second direction and extending along a third direction; the second direction and the third direction intersect and are both perpendicular to the first direction; a plurality of second conductive structures; The second conductive structure extends along the first direction in the first stacked structure and is connected to one bit line of at least one second conductive layer.

34. The memory device of claim 33, wherein, Different bit lines connected to different first stacked structures of the same channel structure are all connected to the same second conductive structure.

35. The memory device of claim 34, wherein, At least one of the second conductive layers is located between two adjacent first stack structures and connected to a channel structure in each of the two adjacent first stack structures.

36. The memory device of claim 34, wherein, The memory device further includes a peripheral circuit; the peripheral circuit includes a page buffer; The plurality of second conductive structures are connected to a same page buffer.

37. The memory device of claim 33, wherein, Different bit lines corresponding to different first stack structures that are penetrated by a same channel structure are connected to different second conductive structures.

38. The memory device of claim 37, wherein, The second conductive layers corresponding to different first stack structures have different sizes along the third direction. Different second conductive structures connected by the second conductive layers corresponding to different first stack structures are arranged in sequence along the third direction.

39. The memory device of claim 37, wherein, The memory device further includes a peripheral circuit; the peripheral circuit includes a plurality of page buffers; Second conductive structures connected to bit lines of a same second conductive layer are connected to a same page buffer in the plurality of page buffers; Second conductive structures connected to bit lines of different second conductive layers are connected to different page buffers in the plurality of page buffers.

40. The memory device of claim 33, wherein, The plurality of first stack structures arranged in layers constitute a memory module; the memory device includes at least two memory modules; two memory modules in the at least two memory modules are arranged in layers along the first direction; the memory device further includes fourth conductive structures; Different bit lines corresponding to different first stack structures that are penetrated by a same channel structure are connected to different second conductive structures. A plurality of second conductive structures corresponding to specified first stack structures in different memory modules that are penetrated by a same channel structure are connected to each other through the fourth conductive structures.

41. The memory device of claim 33, wherein, The plurality of first stack structures are arranged in a first region, and the plurality of second conductive structures are arranged in a third region; the third region is located on at least one side of the first region along a third direction.

42. The memory device of any one of claims 32-41, wherein, At least one of the plurality of semiconductor layers is located between two adjacent first stack structures and connected to a channel structure in each of the two adjacent first stack structures.

43. The memory device of claim 42, wherein, Two adjacent first stack structures in the plurality of first stack structures form a stack structure group. The memory device includes a plurality of semiconductor layers; the plurality of semiconductor layers are respectively located between two adjacent first stack structures in a plurality of stack structure groups; and the plurality of semiconductor layers are connected to each other.

44. The memory device of any one of claims 32-41, wherein, The memory device further includes a plurality of first conductive structures; the first conductive structures extend along the first direction and are connected to a first conductive layer in each of at least two first stack structures in the plurality of first stack structures.

45. The memory device of claim 44, wherein, The memory device further includes a plurality of third conductive structures; a plurality of the first conductive layers in the first stack structures include a top select gate layer and a gate layer; the top select gate layer is located at an end of a corresponding first stack structure along the first direction, which is away from a semiconductor layer connected to a channel structure in the corresponding first stack structure; The third conductive structures extend along the first direction in the first stack structures and are connected to the top select gate layer included in at least one of the plurality of first stack structures. The first conductive structure is connected with one gate layer of at least two first stack structures in the plurality of first stack structures.

46. A memory device, comprising: a plurality of first stack structures arranged in a stack manner; the first stack structure comprises a plurality of first conductive layers and a plurality of first dielectric layers arranged alternately in a first direction; the plurality of first conductive layers in the first stack structure comprises a top select gate layer and a gate layer; the top select gate layer is located at one end of the corresponding first stack structure in the first direction, which is far away from a semiconductor layer connected with a channel structure in the corresponding first stack structure; a plurality of channel structures; each channel structure penetrates through the plurality of first stack structures; at least one semiconductor layer; one semiconductor layer is connected with a channel structure in at least one first stack structure; a plurality of third conductive structures, the third conductive structures extend in the first direction in the first stack structure and are connected with the top select gate layer included in at least one first stack structure in the plurality of first stack structures.

47. The memory device of claim 46, wherein, The memory device further comprises a top select gate isolation structure; the top select gate isolation structure divides the top select gate layer into a plurality of sub-top select gate layers; different sub-top select gate layers included in the same top select gate layer are connected with different third conductive structures.

48. The memory device of claim 46, wherein, different top select gate layers included in different first stack structures are connected with different third conductive structures.

49. The memory device of claim 46, wherein, The memory device further comprises a plurality of second conductive layers and a plurality of second conductive structures; one second conductive layer is connected with the channel structure of at least one first stack structure; one second conductive layer comprises a plurality of bit lines, each bit line is connected with a column of channel structures; the second conductive structure extends in the first direction in the first stack structure and is connected with one bit line of at least one second conductive layer.

50. The memory device of claim 49, wherein, different bit lines corresponding to different first stack structures penetrating through the same channel structure are connected with different second conductive structures; different top select gate layers included in different first stack structures are connected with the same third conductive structure.

51. The memory device of claim 49, wherein, The plurality of first stack structures arranged in a stack manner constitutes one storage surface; the memory device comprises at least two storage surfaces; two storage surfaces in the at least two storage modules are arranged side by side in a second direction; the second direction is perpendicular to the first direction; The memory device further comprises a plurality of first conductive structures; the plurality of first conductive structures is located between the two storage surfaces, and the first conductive structure is connected with one gate layer of different first stack structures in at least one storage surface, respectively.

52. The memory device of claim 51, wherein, The memory device further comprises a peripheral circuit; the peripheral circuit comprises a plurality of word line driving circuits; the first conductive layers at the same position in the stacking direction of the first stack structure of different storage surfaces are connected with each other and connected with the same word line driving circuit.

53. The memory device of claim 51, wherein, different bit lines corresponding to different first stack structures penetrating through the same channel structure are connected with different second conductive structures; Different top select gate layers included in different first stack structures in the same storage surface are connected with the same third conductive structure; Different top select gate layers included in the first stack structures of different storage surfaces at the same position in the first direction are connected with different third conductive structures.

54. The memory device of claim 49, wherein, The plurality of first stack structures are arranged in a stack along the first direction; the memory device comprises at least two storage modules; the at least two first storage modules are arranged in a stack along the first direction; The memory device further comprises a plurality of first conductive structures; each of the two storage modules is connected with one gate layer of each first stack structure.

55. The memory device of claim 54, wherein, The memory device further comprises a fourth conductive structure; Different bit lines corresponding to different first stack structures of the same channel structure in the same storage module are connected with different second conductive structures; Two bit lines corresponding to two first stack structures in different storage modules are connected with each other through the fourth conductive structure. Different top select gate layers included in different first stack structures in the same storage surface are connected with the same third conductive structure; Different top select gate layers included in two first stack structures in different storage modules are connected with different third conductive structures.

56. The memory device of claim 54, wherein, Different bit lines corresponding to different first stack structures of the same channel structure in the same storage module are connected with the same second conductive structure; Different bit lines corresponding to two first stack structures in different storage modules are connected with different second conductive structures. Different top select gate layers included in different first stack structures in the same storage module are connected with different third conductive structures. Different top select gate layers included in two first stack structures in different storage modules are connected with the same third conductive structure.

57. The memory device of claim 46, wherein, The plurality of first stack structures are arranged in a first region, the plurality of first conductive structures are arranged in a second region, and the plurality of third conductive structures are arranged in a fourth region; The fourth region is located between the first region and the second region.

58. The memory device of claim 46, wherein, The third conductive structure comprises a second leading portion, a second connecting portion, and a contact portion; the second leading portion extends along the first direction and is connected with the second connecting portion; the second connecting portion extends along a direction perpendicular to the first direction and is connected with the contact portion; and the contact portion extends along the first direction and is connected with the top select gate layer.

59. The memory device of claim 58, wherein, Each first stack structure comprises a plurality of top select gate layers, and a cross-sectional shape of the plurality of top select gate layers along the first direction comprises a stepped shape; each step in the stepped shape corresponds to one top select gate layer. One contact portion is connected to a step in which one top select gate layer is located.

60. The memory device of claim 46, wherein, One semiconductor layer in the at least one semiconductor layer is located between two adjacent first stack structures and connected with channel structures in the two adjacent first stack structures.

61. The memory device of claim 46, wherein, The memory device further includes a plurality of first conductive structures; The first conductive structures extend along the first direction and are connected to a gate layer of at least two first stack structures.

62. A memory device, comprising: a plurality of first stack structures arranged in a stack; The first stack structures include a plurality of first conductive layers and a plurality of first dielectric layers arranged alternately along a first direction; a plurality of first conductive structures, each of which is connected to a first conductive layer of at least two first stack structures; a plurality of channel structures, each of which penetrates the plurality of first stack structures; at least one semiconductor layer and at least one second conductive layer; Each of the semiconductor layers and the second conductive layers is located on both sides of a first stack structure along the first direction and is connected to a channel structure in the first stack structure; each of the second conductive layers includes a plurality of bit lines arranged in a second direction and extending in a third direction; the second direction and the third direction intersect and are both perpendicular to the first direction; a plurality of second conductive structures, each of which is connected to a bit line of at least one second conductive layer.

63. The memory device of claim 62, wherein, Different bit lines corresponding to different first stack structures penetrated by the same channel structure are connected to the same second conductive structure.

64. The memory device of claim 63, wherein, At least one second conductive layer is located between two adjacent first stack structures and is connected to channel structures in the two adjacent first stack structures.

65. The memory device of claim 63, wherein, The memory device further includes a peripheral circuit; the peripheral circuit includes a page buffer; The plurality of second conductive structures are connected to the same page buffer.

66. The memory device of claim 62, wherein, Different bit lines corresponding to different first stack structures penetrated by the same channel structure are connected to different second conductive structures.

67. The memory device of claim 66, wherein, The sizes of the second conductive layers corresponding to different first stack structures along the third direction are different. Different second bit lines connected by the second conductive layers corresponding to different first stack structures are arranged in sequence along the third direction.

68. The memory device of claim 66, wherein, The memory device further includes a peripheral circuit; the peripheral circuit includes a plurality of page buffers; Second conductive structures connected to bit lines of the same second conductive layer are connected to the same page buffer in the plurality of page buffers; Second conductive structures connected to bit lines of different second conductive layers are connected to different page buffers in the plurality of page buffers.

69. The memory device of claim 62, wherein, At least one semiconductor layer is located between two adjacent first stack structures and is connected to channel structures in the two adjacent first stack structures.

70. The memory device of claim 69, wherein, Two adjacent first stack structures in the plurality of first stack structures form a stack structure group; The memory device includes a plurality of semiconductor layers; the plurality of semiconductor layers are respectively located between two adjacent first stack structures in a plurality of stack structure groups; and the plurality of semiconductor layers are connected to each other.

71. The memory device of claim 62, wherein, The cross-sectional shape of the plurality of first stack structures along the first direction includes a stepped shape; each step in the stepped shape corresponds to an adjacent first conductive layer and an adjacent first dielectric layer. The first conductive structure extends along the first direction in the first stack structure and is connected to at least two steps where one first conductive layer of the at least two first stack structures is located.

72. The memory device of claim 62, wherein, The memory device further comprises a second stack structure, the second stack structure comprising a plurality of layers of isolation layers and second dielectric layers arranged alternately; The first conductive structure comprises a first lead-out portion and a plurality of first connection portions; the first lead-out portion is connected to each of the plurality of first connection portions in the second stack structure; each of the first connection portions is located in one of the isolation layers and is connected to one first conductive layer of a corresponding first stack structure of the at least two first stack structures.

73. The memory device of claim 62, wherein, The first conductive structure is connected to one first conductive layer of each of the first stack structures which is away from a semiconductor layer connected to a channel structure of the corresponding first stack structure by a same distance.

74. The memory device of claim 62, wherein, The first conductive structure is connected to one first conductive layer of each of the first stack structures which is away from a semiconductor layer connected to a channel structure of the corresponding first stack structure by a different distance.

75. The memory device of claim 62, wherein, The memory device further comprises a peripheral circuit; the peripheral circuit comprises a plurality of word line driving circuits; One first conductive layer of the at least two first stack structures is connected to each other through the first conductive structure and is connected to a same word line driving circuit.

76. The memory device of claim 62, wherein, The memory device further comprises a plurality of third conductive structures; the first conductive layer in the first stack structure comprises a top select gate layer and a gate layer; the top select gate layer is located at one end of the corresponding first stack structure along the first direction which is away from a semiconductor layer connected to a channel structure of the corresponding first stack structure; The third conductive structure extends along the first direction in the first stack structure and is connected to the top select gate layer comprised by at least one of the plurality of first stack structures; The first conductive structure is connected to one gate layer of at least two first stack structures of the plurality of first stack structures.

77. The memory device of claim 76, wherein, The memory device further comprises a top select gate isolation structure; the top select gate isolation structure divides the top select gate layer into a plurality of sub-top select gate layers; Different sub-top select gate layers comprised by a same top select gate layer are connected to different third conductive structures.

78. The memory device of claim 76, wherein, Different top select gate layers comprised by different first stack structures are connected to different third conductive structures; Different bit lines corresponding to different first stack structures which are penetrated by a same channel structure are connected to a same second conductive structure.

79. The memory device of claim 76, wherein, Different bit lines corresponding to different first stack structures which are penetrated by a same channel structure are connected to different second conductive structures. Different top select gate layers comprised by different first stack structures are connected to a same third conductive structure.

80. The memory device of claim 76, wherein, The plurality of first stack structures arranged alternately constitutes a memory surface; the memory device comprises a first memory surface and a second memory surface; the first memory surface and the second memory surface are arranged side by side along a second direction; the memory device further comprises a plurality of word line driving circuits; The first conductive structures are connected to one gate layer of different first stack structures in at least one of the first and second storage surfaces; The first conductive layers at the same position in the first direction of the first and second storage surfaces are connected to each other and to the same word line driving circuit.

81. The memory device of claim 80, wherein, Different bit lines corresponding to different first stack structures of the same channel structure are connected to different second conductive structures; Different top select gate layers included in different first stack structures in the same storage surface are connected to the same third conductive structure; Different top select gate layers included in the first stack structures at the same position in the first direction of different storage surfaces are connected to different third conductive structures.

82. The memory device of claim 76, wherein, The plurality of first stack structures arranged in layers form a storage module; the memory device comprises a first storage module and a second storage module; the first storage module and the second storage module are arranged in layers along the first direction; The plurality of first conductive structures are connected to one gate layer of each first stack structure in the first storage module and the second storage module.

83. The memory device of claim 82, wherein, Different bit lines corresponding to different first stack structures of the same channel structure in the same storage module are connected to different second conductive structures; Two bit lines corresponding to two first stack structures in different storage modules are connected to each other; Different top select gate layers included in different first stack structures in the same storage module are connected to the same third conductive structure; Two top select gate layers included in two first stack structures in different storage modules are connected to different third conductive structures.

84. The memory device of claim 82, wherein, Different bit lines corresponding to different first stack structures of the same channel structure in the same storage module are connected to the same second conductive structure; Different bit lines corresponding to two first stack structures in different storage modules are connected to different second conductive structures; Different top select gate layers included in different first stack structures in the same storage module are connected to different third conductive structures; Two top select gate layers included in two first stack structures in different storage modules are connected to the same third conductive structure.

85. The memory device of claim 76, wherein, The plurality of first stack structures are arranged in a first region, the plurality of first conductive structures are arranged in a second region, the plurality of second conductive structures are arranged in a third region, and the plurality of third conductive structures are arranged in a fourth region; The second region is located in the middle of the first region; or the second region is located on at least one side of the first region in a direction perpendicular to the layering direction; The third region is located on at least one side of the first region in the third direction; and the fourth region is located between the first region and the second region. 86.A control method of a memory device, the memory device comprising the memory device of any one of claims 1 to 24, the channel structure is divided into a plurality of sub-channel structures by the semiconductor layer and the second conductive layer; a plurality of the first conductive layers in the first stack structure comprise a top select gate layer and a gate layer; the top select gate layer is located at one end of the corresponding first stack structure along a first direction, which is away from the end of the corresponding first stack structure connecting the semiconductor layer of the channel structure; the control method comprising: in the process of performing a read operation, applying a first voltage on the top select gate of the unselected sub-channel structure and / or the bit line coupled thereto, and applying a second voltage on the top select gate of the selected sub-channel structure and the bit line coupled thereto; applying a pass voltage to all unselected gate layers, and applying a read voltage to the selected gate layer.

87. The control method of claim 86, wherein, The first voltage comprises a cutoff voltage, and the second voltage comprises a first conduction voltage; applying a first voltage on the top select gate of the unselected sub-channel structure and / or the bit line coupled thereto, and applying a second voltage on the top select gate of the selected sub-channel structure and the bit line coupled thereto, comprises: applying a cutoff voltage to the top select gate of the unselected sub-channel structure, and applying a first conduction voltage to the top select gate of the selected sub-channel structure.

88. The control method of claim 86, wherein, The first voltage comprises a program inhibit voltage, and the second voltage comprises a program enable voltage; applying a first voltage on the top select gate of the unselected sub-channel structure and / or the bit line coupled thereto, and applying a second voltage on the top select gate of the selected sub-channel structure and the bit line coupled thereto, comprises: applying a program inhibit voltage to the bit line coupled to the unselected sub-channel structure, and applying a program enable voltage to the bit line coupled to the selected sub-channel structure; applying a first conduction voltage to all top select gate layers.

89. The control method of claim 86, wherein, a plurality of the first conductive layers in the first stack structure further comprise a bottom select gate layer; the bottom select gate layer is located at one end of the corresponding first stack structure along the first direction, which is close to the end of the corresponding first stack structure connecting the semiconductor layer of the channel structure; the method further comprises: in the process of performing a read operation, applying a second conduction voltage to all bottom select gate layers.

90. A control method of a memory device, comprising: The memory device comprises the memory device of any one of claims 1 to 24, the channel structure is divided into a plurality of sub-channel structures by the plurality of first stack structures; a plurality of the first conductive layers in the first stack structure comprise a top select gate layer and a gate layer; the top select gate layer is located at one end of the corresponding first stack structure along the first direction, which is away from the end of the corresponding first stack structure connecting the semiconductor layer of the channel structure; the control method comprising: In the process of performing the programming operation, a first voltage is applied to the top select gate of the unselected sub-channel structure and / or the bit line coupled thereto, and a second voltage is applied to the top select gate of the selected sub-channel structure and the bit line coupled thereto; a pass voltage is applied to all unselected gate layers, and a programming voltage is applied to the selected gate layer.

91. The control method of claim 90, wherein, The first voltage comprises a cutoff voltage, and the second voltage comprises a turn-on voltage. Applying the first voltage to the top select gate of the unselected sub-channel structure and / or the bit line coupled thereto, and applying the second voltage to the top select gate of the selected sub-channel structure and the bit line coupled thereto, comprises: Applying a cutoff voltage to the top select gate of the unselected sub-channel structure and a turn-on voltage to the top select gate of the selected sub-channel structure.

92. The control method of claim 290, wherein, The first voltage comprises a forbidden programming voltage, and the second voltage comprises an allowed programming voltage. Applying the first voltage to the top select gate of the unselected sub-channel structure and / or the bit line coupled thereto, and applying the second voltage to the top select gate of the selected sub-channel structure and the bit line coupled thereto, comprises: Applying a forbidden programming voltage to the bit line coupled to the unselected sub-channel structure and an allowed programming voltage to the bit line coupled to the selected sub-channel structure. A pass voltage is applied to all top select gate layers.

93. The control method of claim 90, wherein, The first conductive layer in the first stack structure further comprises a bottom select gate layer; the bottom select gate layer is located at one end of the corresponding first stack structure along the first direction, which is close to the channel structure connecting semiconductor layer in the corresponding first stack structure; The method further comprises: In the process of performing the programming operation, a cutoff voltage is applied to all bottom select gate layers.

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