Latch circuit, dynamic latch, dynamic d flip-flop, and related device

Abstract

The present disclosure relates to a latch circuit, a dynamic latch, a dynamic D flip-flop, and a related device. The latch circuit comprises: an input end; an output end; a first transistor having a first conductivity type, wherein a control end of the first transistor is configured to receive a first clock signal; a second transistor having a second conductivity type different from the first conductivity type, wherein a control end of the second transistor is configured to receive a second clock signal that is phase-inverted with respect to the first clock signal; and a third transistor, wherein a control end of the third transistor is configured to receive the same clock signal as that received by the control end of the transistor, among the first transistor and the second transistor, having the same conductivity type as the third transistor. A first transmission end of the first transistor and a first transmission end of the second transistor are jointly connected to the input end. A second transmission end of the first transistor is connected to the output end via the third transistor. A second transmission end of the second transistor is connected to the output end.

Description

Latch circuit, dynamic latch, dynamic D flip-flop and related devices

[0001] Cross-references to related applications

[0002] This application is based on and claims priority to CN application No. 202410782479.2, filed on June 18, 2024, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] This disclosure generally relates to the field of integrated circuit technology, and more specifically to latch circuits, dynamic latches, dynamic D flip-flops, registers, processors, and computing devices. Background Technology

[0004] With the widespread application of high-performance computing in fields such as exploration, climate change, transportation, and artificial intelligence, the requirements for the power consumption, processing speed, and area (cost) of computing chips are becoming increasingly stringent. Computing chips require latches for data latching, and the greater the computational load, the more latches a computing chip uses. Therefore, the performance of the latches directly affects the performance of the computing chip. Summary of the Invention

[0005] According to a first aspect of this disclosure, a latching circuit is provided, comprising: an input terminal; an output terminal; a first transistor having a first conductivity type, the control terminal of which is configured to receive a first clock signal; a second transistor having a second conductivity type different from the first conductivity type, the control terminal of which is configured to receive a second clock signal inversely phase to the first clock signal; and a third transistor, the control terminal of which is configured to receive the same clock signal as the clock signal received by the control terminal of the transistor having the same conductivity type as the third transistor in the first and second transistors. A first transmission terminal of the first transistor and a first transmission terminal of the second transistor are both connected to the input terminal. A second transmission terminal of the first transistor is connected to the output terminal via the third transistor. A second transmission terminal of the second transistor is connected to the output terminal.

[0006] According to a second aspect of this disclosure, a dynamic latch is provided, comprising: a data input terminal configured to receive a data signal; a data output terminal configured to output a data signal; a clock control terminal configured to receive a clock signal; and a latching unit and an inverting drive unit connected in series between the data input terminal and the data output terminal. The latching unit is configured to latch or transmit the data signal from the data input terminal under the control of the clock signal. The inverting drive unit is configured to transmit the data signal from the latching unit in reverse phase.

[0007] In some embodiments, the latching unit includes the latching circuitry described in the first aspect of this disclosure.

[0008] In some embodiments, the latch unit includes a latch circuit as described in the first aspect of this disclosure, and an inverter connected in series between the data input terminal and the latch circuit.

[0009] According to a third aspect of this disclosure, a dynamic D flip-flop is provided, comprising: a data input terminal configured to receive a data signal; a data output terminal configured to output a data signal; a clock control terminal configured to receive a clock signal; and a first latch unit, a second latch unit, and an inverting drive unit connected in series between the data input terminal and the data output terminal. The first latch unit is configured to latch or transmit the data signal from the data input terminal under the control of the clock signal. The second latch unit is configured to latch or transmit the data signal from the first latch unit under the control of the clock signal. The inverting drive unit is configured to transmit the data signal from the second latch unit in reverse phase.

[0010] In some embodiments, the first latching unit includes the latching circuit described in the first aspect of this disclosure.

[0011] In some embodiments, the first latch unit includes an inverter and a latch circuit according to the first aspect of the present disclosure, which are connected in series between the data input terminal and the second latch unit.

[0012] In some embodiments, the second latch unit includes an inverter and the latch circuit described in the first aspect of the present disclosure, which are connected in series between the first latch unit and the inverting drive unit.

[0013] According to a fourth aspect of this disclosure, a register is provided, comprising: a plurality of data input terminals configured to receive data signals; a plurality of data output terminals configured to output data signals; a clock control terminal configured to receive a clock signal; a clock buffer configured to buffer the clock signal received by the clock control terminal and provide a clock signal to a plurality of register cells; and the plurality of register cells connected in parallel between the plurality of data input terminals and the plurality of data output terminals, and configured to perform at least one of writing data and reading data under the control of the clock signal. The register cells are either dynamic latches as described in a second aspect of this disclosure or dynamic D flip-flops as described in a third aspect of this disclosure.

[0014] According to a fifth aspect of this disclosure, a processor is provided that includes a dynamic latch according to a second aspect of this disclosure, a dynamic D flip-flop according to a third aspect of this disclosure, or a register according to a fourth aspect of this disclosure.

[0015] According to a sixth aspect of this disclosure, a computing device is provided, the computing device including the processor described in the fifth aspect of this disclosure.

[0016] Other features and advantages of this disclosure will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings. Attached Figure Description

[0017] The accompanying drawings, which form part of this specification, illustrate embodiments of the present disclosure and, together with the specification, serve to explain the principles of the present disclosure. The present disclosure can be more clearly understood from the following detailed description, with reference to the accompanying drawings, wherein:

[0018] Figure 1 shows a circuit diagram of a dynamic latch according to a comparative example of the present disclosure;

[0019] Figure 2 shows a schematic diagram of the equivalent circuit of Figure 1;

[0020] Figure 3 illustrates a dynamic latch according to some embodiments of the present disclosure;

[0021] Figure 4 illustrates a clock buffer according to some embodiments of the present disclosure;

[0022] Figure 5 illustrates a dynamic latch and its associated clock circuit according to some embodiments of the present disclosure;

[0023] Figures 6 to 17 respectively show circuit diagrams of dynamic latches according to some embodiments of the present disclosure;

[0024] Figure 18 illustrates a dynamic D flip-flop according to some embodiments of the present disclosure;

[0025] Figures 19 to 27 show circuit diagrams of dynamic D flip-flops according to some embodiments of the present disclosure;

[0026] Figure 28 illustrates registers according to some embodiments of the present disclosure;

[0027] Figure 29 shows an example timing diagram of the circuit of the dynamic latch shown in Figure 10;

[0028] Figure 30 shows an example timing diagram of the circuit of the dynamic latch shown in Figure 16.

[0029] Note that in the embodiments described below, the same reference numerals are sometimes used across different figures to denote the same parts or parts having the same function, and repeated descriptions are omitted. In this specification, similar reference numerals and letters are used to denote similar items; therefore, once an item is defined in one figure, it need not be further discussed in other figures unless otherwise stated.

[0030] For ease of understanding, the positions, dimensions, and extents of the structures shown in the accompanying drawings and other materials may not represent actual positions, dimensions, and extents. Therefore, the disclosed invention is not limited to the positions, dimensions, and extents disclosed in the accompanying drawings and other materials. Furthermore, the drawings are not necessarily drawn to scale, and some features may be enlarged to show details of specific components. Detailed Implementation

[0031] Various exemplary embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. It should be noted that, unless otherwise specifically stated, the relative arrangement, numerical expressions, and values ​​of the components and steps set forth in these embodiments do not limit the scope of the present disclosure.

[0032] The following description of at least one exemplary embodiment is merely illustrative and is in no way intended to limit the scope of this disclosure or its application or use. That is, the structures and methods herein are shown in an exemplary manner to illustrate different embodiments of the structures and methods in this disclosure. However, those skilled in the art will understand that they merely illustrate exemplary ways that can be used to implement this disclosure, and not exhaustive ways. Furthermore, the drawings are not necessarily drawn to scale, and some features may be enlarged to show details of specific components.

[0033] In addition, techniques, methods and equipment known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods and equipment should be considered part of the specification.

[0034] In all examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not as limitations. Therefore, other examples of exemplary embodiments may have different values.

[0035] It should be understood that although the accompanying figures are mainly illustrated using metal-oxide-semiconductor (MOS) transistors, this disclosure is not limited to this, and any other suitable transistors may be used, including but not limited to bipolar junction (BJT) transistors.

[0036] It should also be understood that, in this text, the control terminal of a transistor can refer to the port used to control the current flow and switching state of the transistor, while the transmission terminal of a transistor can refer to the port of the current or signal input and output transistor. Specifically, for a MOS transistor, the control terminal is the gate, and the transmission terminals are the source and drain; for a BJT transistor, the control terminal is the base, and the transmission terminals are the emitter and collector. Furthermore, for example, for a MOS transistor, the first conductivity type is either P-type or N-type, and the second conductivity type is the other of P-type and N-type; for a BJT transistor, the first conductivity type is either PNP or NPN, and the second conductivity type is the other of PNP or NPN.

[0037] It should also be understood that in this article, power supply and ground are relative concepts; they exist relative to each other and are used to describe the polarity and direction of voltage in a circuit. For example, power supply can represent a high level, and ground can represent a low level.

[0038] Compared to static latches, dynamic latches significantly simplify the circuit structure by eliminating the feedback circuitry used to maintain the operating state, thus reducing both chip area and power consumption. These advantages have enabled the widespread use of dynamic latches in computing chips. However, because dynamic latches contain nodes that are floating for a portion of the time, the parasitic capacitance at these nodes needs to maintain the correct voltage state during this period.

[0039] To prevent leakage current from affecting the node's voltage, dynamic latches must operate at a relatively high frequency to reduce leakage time and prevent malfunctions. This significantly limits the chip's usability. For example, in some processor states such as sleep or idle, dynamic latches may operate at relatively low frequencies, making malfunctions more likely.

[0040] Figure 1 illustrates a dynamic latch 10 according to a comparative example of the present disclosure. The dynamic latch 10 includes a transmission gate 11 and an inverter 12 connected in series between a data input terminal D and a data output terminal Q. Specifically, the transmission gate 11 includes a P-type metal-oxide-semiconductor (PMOS) transistor and an N-type metal-oxide-semiconductor (NMOS) transistor connected in parallel, the gates of which receive clock signals that are inverted relative to each other. The inverter 12 includes a PMOS transistor and an NMOS transistor connected in series between a power supply VDD and a ground VSS, their gates connected together to form the input of the inverter 12, and their drains connected together to form the output of the inverter 12. Thus, assuming that the data input terminal D receives a data signal S, when the clock signal CLKP is high and the clock signal CLKN is low, the transmission gate 11 is turned on, and the data signal S passes through the transmission gate 11 to the inverter 12, where it is inverted, resulting in an inverted version of the data signal S being output at the data output terminal Q. In other words, dynamic latch 10 is a dynamic latch used to provide inverted output.

[0041] As shown in Figure 1, node A is formed between transmission gate 11 and inverter 12. Data is temporarily stored on node A through the parasitic capacitance of inverter 12. However, during the operation of dynamic latch 10, the potential of node A can be floating for a portion of the clock cycle. Dynamic leakage will cause the data temporarily stored on node A to be lost.

[0042] Referring to Figures 1 and 2, when CLKP is high and CLKN is low, transmission gate 11 is turned on, thereby transmitting data from the data input terminal D to node A, so as to write the data into the parasitic capacitance C of node A. When CLKP goes low and CLKN goes high, transmission gate 11 is turned off, and the data previously transmitted by transmission gate 11 is retained in the parasitic capacitance C of node A.

[0043] With CLKP low and CLKN high, assuming node A stores "0" data, if the data at data input D changes to "1", a pull-up leakage path is formed through transmission gate 11 (as shown in Figure 2(a)), charging the parasitic capacitance C. When the clock frequency is low, i.e., the period when CLKP is low and CLKN is high (or the off period) is long enough, the level of node A will change from "0" to "1", causing data loss.

[0044] With CLKP low and CLKN high, assuming node A stores "1" data, if the data at data input D changes to "0", a pull-down leakage path is formed through transmission gate 11 (as shown in Figure 2(b)), discharging the parasitic capacitance C. When the clock frequency is low, i.e., the off period is long enough, the level of node A will change from "1" to "0", causing data loss.

[0045] In other words, when CLKP is low and CLKN is high, transmission gate 11 may not remain ideally closed, and a certain leakage path exists. In particular, the risk of data loss increases as the shutdown period lengthens. However, as process nodes continue to shrink (e.g., 7nm, 5nm, etc.), leakage intensifies, requiring the shutdown period to become increasingly shorter.

[0046] Specifically, assuming the charge stored in the parasitic capacitor C is Q, the capacitance of the parasitic capacitor C is C, and the voltage across the parasitic capacitor C is V, then Q = C * V. If the leakage current is I... leakage Then the leakage time T (corresponding to the shutdown period) is T = Q / I leakage =C*V / I leakage The leakage time is directly proportional to the clock period, i.e., the clock frequency F. clk ∝1 / T=I leakage / (C*V). Therefore, dynamic leakage current limits the minimum operating frequency of the dynamic latch. If the operating frequency of the dynamic latch is too low, malfunctions may occur.

[0047] To this end, this disclosure provides a dynamic latch that effectively suppresses dynamic leakage current, thereby enabling normal operation at lower operating frequencies. This is beneficial for reducing power consumption, especially when such dynamic latches are widely used in computing chips, significantly reducing the overall power consumption of the computing chip. The dynamic latches according to various embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. It should be understood that actual dynamic latches may also include other components, but to avoid obscuring the key points of this disclosure, these other components will not be discussed herein and are not shown in the accompanying drawings.

[0048] Figure 3 illustrates a dynamic latch 100 according to some embodiments of the present disclosure. The dynamic latch 100 includes a data input terminal 101, a data output terminal 102, a clock control terminal 103, and a latching unit 104 and an inverting drive unit 105 connected in series between the data input terminal 101 and the data output terminal 102. The data input terminal 101 is configured to receive a data signal. The data output terminal 102 is configured to output a data signal. The clock control terminal 103 is configured to receive a clock signal. The latching unit 104 is configured to latch or transmit the data signal from the data input terminal 101 under the control of the clock signal. The inverting drive unit 105 is configured to transmit the data signal from the latching unit 104 in reverse phase.

[0049] Figure 4 shows a clock buffer 200 used to provide a clock signal. The clock buffer 200 consists of two stages of inverters 201 and 202 connected in series. The clock buffer 200 buffers the input clock signal CK and provides inverted clock signals CLKN and CLKP. Only two inverters are shown in Figure 4, but the number of inverters is not limited to two and can be more. The clock buffer 200 can be used to provide a clock signal to the dynamic latch 100. As shown in Figure 5, the clock signal CK, after being buffered by the clock buffer 200, provides inverted clock signals CLKN and CLKP to the dynamic latch 100. Similarly, the clock buffer 200 can be used to provide inverted clock signals CLKN and CLKP to dynamic D flip-flops, registers, etc., described later.

[0050] In some embodiments, the latch unit 104 may include a latch circuit according to various embodiments of the present disclosure. The latch circuit includes: an input terminal; an output terminal; a first transistor having a first conductivity type, the control terminal of which is configured to receive a first clock signal; a second transistor having a second conductivity type different from the first conductivity type, the control terminal of which is configured to receive a second clock signal that is inversely phase to the first clock signal; and a third transistor, the control terminal of which is configured to receive the same clock signal as the clock signal received by the control terminal of the transistor having the same conductivity type as the third transistor in the first and second transistors.

[0051] The first transmission terminal of the first transistor and the first transmission terminal of the second transistor are both connected to the input terminal. The second transmission terminal of the first transistor is connected to the output terminal via a third transistor. The second transmission terminal of the second transistor is also connected to the output terminal. Such a latch circuit can be configured to provide a non-inverting output.

[0052] In some embodiments, the third transistor has a first conductivity type. In other embodiments, the third transistor has a second conductivity type.

[0053] Specifically, in some embodiments, the latching circuit may include a first sub-circuit and a second sub-circuit connected in parallel between the input and the output, wherein a first transistor and a third transistor are included in the first sub-circuit and connected in series with each other, and a second transistor is included in the second sub-circuit.

[0054] For example, referring to FIG6, a circuit 300 of a dynamic latch 100 according to some embodiments of the present disclosure is shown. As shown in FIG6, the circuit 300 includes a latch circuit 320 (which acts as a latch unit 104 (specifically, a non-inverting latch unit) of the dynamic latch 100) and an inverter 330 (which acts as an inverting drive unit 105 of the dynamic latch 100) connected in series between a data input terminal D and a data output terminal Q.

[0055] Inverter 330 includes a PMOS transistor 331 and an NMOS transistor 332 connected in series between power supply VDD and ground VSS. The control terminals (gates) of these two transistors are connected together to form the input terminal of inverter 330, and the drain terminals (drains) of these two transistors are connected together to form the output terminal of inverter 330. The output terminal of inverter 330 can directly provide the data output terminal Q of circuit 300.

[0056] The latch circuit 320 has an input terminal 3201 and an output terminal 3202. The input terminal 3201 of the latch circuit 320 can directly provide the data input terminal D of the circuit 300. The output terminal 3202 of the latch circuit 320 is connected to the input terminal of the inverter 330, forming a node A with a floating potential for a certain period of time.

[0057] As shown in Figure 6, the latch circuit 320 includes a first sub-circuit (here, the upper sub-circuit) and a second sub-circuit (here, the lower sub-circuit) connected in parallel between the input terminal 3201 and the output terminal 3202. A first transistor 321 (here, an NMOS transistor) is included in the first sub-circuit, and a second transistor 322 (here, a PMOS transistor) is included in the second sub-circuit. The first transmission terminal (here, the drain) of the first transistor 321 and the first transmission terminal (here, the source) of the second transistor 322 are both connected to the input terminal 3201. The second transmission terminal (here, the drain) of the second transistor 322 is connected to the output terminal 3202. The latch circuit 320 also includes a third transistor 323 (here, an NMOS transistor), which is also included in the first sub-circuit and connected in series with the first transistor 321. The second transmission terminal (here, the source) of the first transistor 321 is connected to the output terminal 3202 via the third transistor 323. Typically, the substrate regions (bulk) of these transistors are not suspended. The substrate region of a PMOS transistor can be connected to a power supply, while the substrate region of an NMOS transistor can be grounded.

[0058] In the example of Figure 6, the third transistor 323 and the first transistor 321 have the same conductivity type, and they both receive the clock signal CLKP. Although not shown, the control terminals (here, the gates) of the third transistor 323 and the first transistor 321 can be connected together to receive the clock signal CLKP. Furthermore, the second transistor 322 has a different conductivity type than the first transistor 321, so that the control terminal (here, the gate) of the second transistor 322 receives a clock signal CLKN that is inverted from the clock signal CLKP.

[0059] Compared to the dynamic latch 10 in Figure 1, Figure 6 achieves an extended-channel NMOS transistor by connecting the third transistor 323 in series with the first transistor 321, thereby reducing leakage current and enabling a lower minimum operating frequency.

[0060] This is particularly advantageous in digital circuits, because unlike analog circuits where transistor sizes can be arbitrarily designed, digital circuits typically use transistors from a standard cell library. The channel length selection for transistors in a standard cell library is limited, usually including two options: one with a 1-unit channel and the other with a 1.2-unit channel. Simply replacing a 1-unit channel transistor with a 1.2-unit channel transistor results in channel length extension, which cannot adequately suppress dynamic leakage current. Increasing the transistor's threshold voltage V... TH While this can reduce leakage current, the choice of threshold voltage for transistors in the standard cell library is limited. Typically, transistors in the standard cell library are divided into several levels (usually 3-4 levels) based on their threshold voltage. Transistors with higher threshold voltages are slower but have lower leakage current, while transistors with lower threshold voltages are faster but have higher leakage current. Selecting a transistor with a higher threshold voltage can reduce leakage current. However, due to the limited number of levels, there is a certain gradient in threshold voltage between levels. Therefore, the following situation often occurs: selecting a transistor with a lower threshold voltage results in excessive leakage current, while selecting a transistor with a higher threshold voltage results in too much speed reduction, and in low-voltage applications, it may even be more difficult to conduct. Thus, adjusting the threshold voltage cannot achieve precise suppression of dynamic leakage current. To address this, this disclosure proposes that by connecting transistors of a certain threshold voltage level (e.g., a low threshold voltage) in series, the threshold voltage of the series-connected transistor group can be positioned between the current threshold voltage and the next higher threshold voltage, thereby reducing leakage current while maintaining speed.

[0061] Therefore, in some embodiments, the third transistor may include a plurality of third transistors connected in series with the first transistor. The second transmission terminal of the first transistor may be connected to the output terminal via the plurality of third transistors. By controlling the number of third transistors connected in series, the desired channel extension effect can be achieved according to specific needs, thereby effectively suppressing dynamic leakage current. Of course, the number of third transistors should not be too large, otherwise it will slow down the speed of the dynamic latch. In some examples, the number of third transistors does not exceed two, for example, one.

[0062] Figure 7 illustrates a circuit 300 of a dynamic latch 100 according to some other embodiments of the present disclosure. Compared to Figure 6, the third transistor 323 in Figure 7 has the same conductivity type as the second transistor 322 (both are P-type), and they both receive a clock signal CLKN. Although not shown, the control terminals (here, the gates) of the third transistor 323 and the second transistor 322 can be connected together to receive the clock signal CLKN. In some cases, Figure 6 may be more advantageous than Figure 7 because the circuit of Figure 7 may require a higher supply voltage. Nevertheless, connecting the third transistor 323, which has a different conductivity type than the first transistor 321, in series with the first transistor 321 still helps to suppress leakage current, thereby reducing the minimum operating frequency of the dynamic latch.

[0063] Figure 8 illustrates a circuit 300 of a dynamic latch 100 according to some other embodiments of the present disclosure. Compared to Figure 6, in Figure 8, the first transistor 321 and the third transistor 323 are both P-type transistors and both receive a clock signal CLKN. Additionally, the second transistor 322 is N-type transistor and receives a clock signal CLKP.

[0064] Figure 9 illustrates a circuit 300 of a dynamic latch 100 according to some other embodiments of the present disclosure. Compared to Figure 7, in Figure 9, the second transistor 322 and the third transistor 323 are both N-type and both receive a clock signal CLKP. Additionally, the first transistor 321 is P-type and receives a clock signal CLKN.

[0065] Furthermore, in some embodiments, the latching circuit may further include a fourth transistor, the control terminal of which is configured to receive the same clock signal as the control terminal of the first transistor and the second transistor, which has the same conductivity type as the fourth transistor. Specifically, the second transmission terminal of the second transistor is connected to the output terminal via the fourth transistor. In some embodiments, the fourth transistor has a first conductivity type. In other embodiments, the fourth transistor has a second conductivity type.

[0066] Specifically, in some embodiments, the latching circuit may include a first sub-circuit and a second sub-circuit connected in parallel between the input and the output, wherein a first transistor and a third transistor are included in the first sub-circuit and connected in series with each other, and a second transistor and a fourth transistor are included in the second sub-circuit and connected in series with each other.

[0067] For example, referring to FIG10, a circuit 300 of a dynamic latch 100 according to some embodiments of the present disclosure is shown. Compared with FIG6, in FIG10, the latch circuit 320 further includes a fourth transistor 324 (here a PMOS transistor), which is also included in the second sub-circuit and connected in series with the second transistor 322. The second transmission terminal (here a drain) of the second transistor 322 is connected to the output terminal 3202 via the fourth transistor 324.

[0068] In the example of Figure 10, the fourth transistor 324 and the second transistor 322 have the same conductivity type, and they both receive the clock signal CLKN. Although not shown, the control terminals (here, the gates) of the fourth transistor 324 and the second transistor 322 can be connected together to receive the clock signal CLKN.

[0069] Compared to the dynamic latch 10 in Figure 1, Figure 10 achieves a channel-extended PMOS transistor by connecting the fourth transistor 324 in series with the second transistor 322, thereby reducing leakage current and enabling a lower minimum operating frequency.

[0070] In some embodiments, the fourth transistor may include a plurality of fourth transistors connected in series with the second transistor. The second transmission terminal of the second transistor may be connected to the output terminal via the plurality of fourth transistors. By controlling the number of fourth transistors connected in series, the desired channel extension effect can be achieved according to specific needs, thereby effectively suppressing dynamic leakage current. Of course, the number of fourth transistors should not be too large, otherwise it will slow down the speed of the dynamic latch. In some examples, the number of fourth transistors does not exceed two, for example, one.

[0071] Figure 11 illustrates a circuit 300 of a dynamic latch 100 according to some other embodiments of the present disclosure. Compared to Figure 10, the fourth transistor 324 of Figure 11 has the same conductivity type as the first transistor 321 (both are N-type), and they both receive the clock signal CLKP. Although not shown, the fourth transistor 324 can be connected together with the control terminal (here, the gate) of the first transistor 321 and the third transistor 323 to receive the clock signal CLKP. In some cases, Figure 10 may be more advantageous than Figure 11 because the circuit of Figure 11 may require a higher supply voltage. Nevertheless, connecting the fourth transistor 324, which has a different conductivity type than the second transistor 322, in series with the second transistor 322 still helps to suppress leakage current, thereby reducing the minimum operating frequency of the dynamic latch.

[0072] Figure 12 illustrates a circuit 300 of a dynamic latch 100 according to some other embodiments of the present disclosure. Compared to Figure 10, in Figure 12, the third transistor 323 and the second transistor 322 have the same conduction type (both P-type), and they both receive a clock signal CLKN. Although not shown, the control terminals (here, the gates) of the third transistor 323 and the second transistor 322 can be connected together to receive the clock signal CLKN. Additionally, the fourth transistor 324 and the first transistor 321 have the same conduction type (both N-type), and they both receive a clock signal CLKP. Although not shown, the control terminals (here, the gates) of the fourth transistor 324 and the first transistor 321 can be connected together to receive the clock signal CLKP. In some cases, Figure 10 may be more advantageous than Figure 12 because the circuit of Figure 12 may require a higher supply voltage. Nevertheless, connecting a third transistor 323, which has a different conductivity type than the first transistor 321, in series with the first transistor 321, and connecting a fourth transistor 324, which has a different conductivity type than the second transistor 322, in series with the second transistor 322, still helps to suppress leakage current and thus reduce the minimum operating frequency of the dynamic latch.

[0073] Figure 13 illustrates a circuit 300 of a dynamic latch 100 according to some other embodiments of the present disclosure. Compared to Figure 10, in Figure 13, two third transistors 323, 323' of the same conductivity type as the first transistor 321 (here, N-type) are connected in series with the first transistor 321, and two fourth transistors 324, 324' of the same conductivity type as the second transistor 322 (here, P-type) are connected in series with the second transistor 322. It is understood that although the number of transistors in the two sub-circuits of the latch circuit 320 is depicted as the same herein, this is merely exemplary and not limiting. The number of transistors in the two sub-circuits can be adjusted separately according to actual needs. For example, when the transistor process determines that the leakage current of an NMOS transistor is more severe than that of a PMOS transistor, the number of transistors included in the sub-circuit formed by the NMOS transistor (here, the upper sub-circuit) can be greater than the number of transistors included in the sub-circuit formed by the PMOS transistor (here, the lower sub-circuit). Conversely, when the transistor manufacturing process dictates that PMOS transistors have more severe leakage current than NMOS transistors, the number of transistors in a sub-circuit formed by PMOS transistors (here, the lower sub-circuit) can be greater than the number of transistors in a sub-circuit formed by NMOS transistors (here, the upper sub-circuit). Additionally, the balance of operating speeds between different sub-circuits is also a consideration. For example, when the transistor manufacturing process dictates that NMOS transistors are faster than PMOS transistors, the number of transistors in a sub-circuit formed by NMOS transistors (here, the upper sub-circuit) can be greater than the number of transistors in a sub-circuit formed by PMOS transistors (here, the lower sub-circuit). Conversely, when the transistor manufacturing process dictates that PMOS transistors are faster than NMOS transistors, the number of transistors in a sub-circuit formed by PMOS transistors (here, the lower sub-circuit) can be greater than the number of transistors in a sub-circuit formed by NMOS transistors (here, the upper sub-circuit). However, in general, low leakage current devices are usually high threshold devices, and high threshold devices are slower than low threshold devices. Therefore, considering both speed and leakage current when determining the number of transistors, the final conclusion may be consistent.

[0074] In summary, in various embodiments, the latch circuit 320 may include a first sub-circuit and a second sub-circuit connected in parallel between the input terminal 3201 and the output terminal 3202. The first and second sub-circuits include transistors of different conduction types (e.g., the first sub-circuit includes a first transistor of a first conduction type, and the second sub-circuit includes a second transistor of a second conduction type). At least one of the first and second sub-circuits includes a plurality of transistors connected in series (e.g., the first sub-circuit also includes a third transistor connected in series with the first transistor, and / or the second sub-circuit also includes a fourth transistor connected in series with the second transistor). The number of transistors included in each of the first and second sub-circuits may be determined by considering factors such as transistor manufacturing processes; for example, a sub-circuit with higher leakage current due to transistor manufacturing processes may include more transistors, and / or the speed of different sub-circuits may be balanced by controlling the number of transistors. In some examples, the first sub-circuit and the second sub-circuit connected in parallel therewith may include the same number of transistors, which may facilitate manufacturing processes. In fact, having fewer transistors in one of the first and second sub-circuits than the other does not necessarily lead to a reduction in chip area in terms of manufacturing process. The chip area occupied by the latch circuit 320 is often determined by the sub-circuit with a larger number of transistors.

[0075] Alternatively, the latch circuit 320 may also include a third sub-circuit and a fourth sub-circuit connected in series between the input terminal 3201 and the output terminal 3202. Each of the third and fourth sub-circuits may include transistors of different conduction types connected in parallel.

[0076] Specifically, in some embodiments, the conductivity type of the fourth transistor may be different from that of the third transistor, the first transistor and the second transistor are included in the third sub-circuit and connected in parallel with each other, and the third transistor and the fourth transistor are included in the fourth sub-circuit and connected in parallel with each other.

[0077] Therefore, the second transmission terminal of the first transistor and the second transmission terminal of the second transistor are connected together to the first transmission terminal of the third transistor, the first transmission terminal of the fourth transistor is also connected to the first transmission terminal of the third transistor, and the second transmission terminals of the third transistor and the second transmission terminals of the fourth transistor are connected together to the output terminal.

[0078] For example, referring to FIG14, a circuit 300 of a dynamic latch 100 according to some embodiments of the present disclosure is shown. Compared with FIG10, the latch circuit 320 of FIG14 includes a third sub-circuit (here, the left sub-circuit) and a fourth sub-circuit (here, the right sub-circuit) connected in series between an input terminal 3201 and an output terminal 3202. A first transistor 321 and a second transistor 322 of different conductivity types are included in the third sub-circuit and connected in parallel with each other. A third transistor 323 and a fourth transistor 324 of different conductivity types are included in the fourth sub-circuit and connected in parallel with each other.

[0079] In Figure 14, the second transmission terminal (here, the source) of the first transistor 321 and the second transmission terminal (here, the drain) of the second transistor 322 are both connected to the first transmission terminal (here, the drain) of the third transistor 323. The first transmission terminal (here, the source) of the fourth transistor 324 is also connected to the first transmission terminal (here, the drain) of the third transistor 323. Furthermore, the second transmission terminal (here, the source) of the third transistor 323 and the second transmission terminal (here, the drain) of the fourth transistor 324 are both connected to the output terminal 3202. Although not shown, the control terminal (here, the gate) of the third transistor 323 and the first transistor 321 can be connected together to receive the clock signal CLKP, and the control terminal (here, the gate) of the fourth transistor 324 and the second transistor 322 can be connected together to receive the clock signal CLKN.

[0080] The third and fourth sub-circuits can each be considered as a transmission gate. Since the transmission gates themselves do not have driving capability, it is not advisable to connect more similar sub-circuits in series here, otherwise it will affect the operation of the dynamic latch.

[0081] Compared to the dynamic latch 10 in Figure 1, Figure 14, by adding a fourth sub-circuit including a third transistor 323 and a fourth transistor 324, and connecting the fourth sub-circuit in series with the third sub-circuit including a first transistor 321 and a second transistor 322, is also equivalent to realizing a transistor with extended channel, thereby reducing leakage current and enabling a lower minimum operating frequency.

[0082] It is understood that the foregoing embodiments can be freely combined. Thus, at least one of the third and fourth sub-circuits can be modified into a parallel connection of the first and second sub-circuits of any of the foregoing embodiments. Therefore, in some embodiments, the third sub-circuit includes the first and second sub-circuits connected in parallel, a first transistor is included in the first sub-circuit of the third sub-circuit and a second transistor is included in the second sub-circuit of the third sub-circuit, the fourth sub-circuit includes the first and second sub-circuits connected in parallel, a third transistor is included in the first sub-circuit of the fourth sub-circuit and a fourth transistor is included in the second sub-circuit of the fourth sub-circuit, wherein the latching circuit further includes one or more of the following: one or more fifth transistors connected in series with the first transistor in the first sub-circuit of the third sub-circuit; one or more sixth transistors connected in series with the second transistor in the second sub-circuit of the third sub-circuit; one or more seventh transistors connected in series with the third transistor in the first sub-circuit of the fourth sub-circuit; and one or more eighth transistors connected in series with the fourth transistor in the second sub-circuit of the fourth sub-circuit. The control terminal of each of the fifth, sixth, seventh, and eighth transistors can be configured to receive the same clock signal as the control terminal of the first and second transistors, which have the same conduction type. Each of the fifth, sixth, seventh, and eighth transistors can have either a first or a second conduction type. For example, the fifth and first transistors can have the same conduction type, the sixth and second transistors can have the same conduction type, the seventh and third transistors can have the same conduction type, and the eighth and fourth transistors can have the same conduction type. This can help reduce the power supply voltage required by the circuit.

[0083] For example, referring to Figure 15, the first transistor 321, the second transistor 322, the fifth transistor 325, and the sixth transistor 326 constitute the third sub-circuit. The first transistor 321 and the fifth transistor 325, connected in series, constitute the first sub-circuit of the third sub-circuit, and the second transistor 322 and the sixth transistor 326, also connected in series, constitute the second sub-circuit of the third sub-circuit. Furthermore, the first and second sub-circuits of the third sub-circuit are connected in parallel. Additionally, the third transistor 323, the fourth transistor 324, the seventh transistors 327 and 327', and the eighth transistors 328 and 328' constitute the fourth sub-circuit. The third transistor 323, the seventh transistors 327 and 327', connected in series, constitute the first sub-circuit of the fourth sub-circuit, and the fourth transistor 324, the eighth transistors 328 and 328', also connected in series, constitute the second sub-circuit of the fourth sub-circuit. The first and second sub-circuits of the fourth sub-circuit are connected in parallel. The third and fourth sub-circuits are connected in series between the input terminal 3201 and the output terminal 3202. The sub-circuit combinations of the latch circuit 320 in Figure 15 are merely exemplary and not limiting, and may take the form of a combination of the first sub-circuit, second sub-circuit, third sub-circuit and / or fourth sub-circuit described in any embodiment of this disclosure.

[0084] In the above embodiments, such as the one shown in Figure 10, the dynamic latch is active high. Referring to Figures 10 and 29, initially, the input data at data input terminal D is "0", and data output terminal Q provides inverted output data "1". Next, the input data at data input terminal D changes from "0" to "1", but because CLKP is low and CLKN is high at this time, the latch circuit 320 is off, so data output terminal Q remains "1". As CLKP becomes high and CLKN becomes low, the latch circuit 320 turns on, and the input data "1" at data input terminal D is inverted by the inverter 330 after in-phase transmission through the latch circuit 320, causing data output terminal Q to provide inverted output data "0".

[0085] Furthermore, the application of clock signals CLKP and CLKN in any embodiment of this paper can be interchanged. For example, referring to FIG16, compared with FIG10, the application of clock signals CLKP and CLKN is interchanged, so that the first transistor 321 and the third transistor 323 receive the clock signal CLKN while the second transistor 322 and the fourth transistor 324 receive the clock signal CLKP, thereby realizing a low-level active dynamic latch. Combining FIG16 and FIG30, initially, the input data at the data input terminal D is "0", and the data output terminal Q provides inverted output data "1". Then, the input data at the data input terminal D changes from "0" to "1", but because CLKP is high and CLKN is low at this time, the latch circuit 320 is turned off, so the data output terminal Q remains "1". As CLKP goes low and CLKN goes high, latch circuit 320 turns on. The input data "1" at data input terminal D is transmitted in phase by latch circuit 320 and then inverted by inverter 330, so that data output terminal Q provides inverted output data "0".

[0086] The preceding descriptions, in conjunction with Figures 6 to 16, illustrate various exemplary implementations of the dynamic latch 100 as a dynamic latch providing an inverted output. However, this disclosure is not limited thereto. The dynamic latch 100 can also be implemented as a dynamic latch providing a non-inverting output, for example, by further including an inverter connected in series between the data input terminal and the latch circuit in the latch unit. For example, referring to Figure 17, compared to Figure 10, an inverter 310 is provided connected in series between the data input terminal D and the latch circuit 320. The inverter 310 includes a PMOS transistor 311 and an NMOS transistor 312 connected in series between the power supply VDD and ground VSS. The control terminals (gates) of these two transistors are connected together to form the input terminal of the inverter 310, and the drain terminals (drains) of these two transistors are connected together to form the output terminal of the inverter 310. The output terminal of the inverter 310 can be directly connected to the input terminal 3201 of the latch circuit 320. The input terminal of inverter 310 can directly provide the data input terminal D of circuit 300. The combination of inverter 310 and latch circuit 320 can serve as the latch unit 104 (specifically, the inverting latch unit) of dynamic latch 100. It is understood that the latch circuit 320 shown herein is merely exemplary and can be replaced by the latch circuit described in any embodiment of this disclosure. The latch circuits involved in the circuits shown in the following figures are also exemplary and can be replaced by the latch circuit described in any embodiment of this disclosure, and will not be described in detail hereafter.

[0087] This disclosure also provides a dynamic D flip-flop that effectively suppresses dynamic leakage current, thereby enabling normal operation at lower operating frequencies. Various embodiments of the dynamic D flip-flop according to this disclosure will now be described in detail with reference to the accompanying drawings. It should be understood that actual dynamic D flip-flops may include other components, but to avoid obscuring the essential points of this disclosure, these other components will not be discussed herein and are not shown in the drawings.

[0088] Figure 18 illustrates a dynamic D flip-flop 400 according to some embodiments of the present disclosure. The dynamic D flip-flop 400 includes a data input terminal 401, a data output terminal 402, a clock control terminal 403, and a first latch unit 404, a second latch unit 405, and an inverting drive unit 406 connected in series between the data input terminal 401 and the data output terminal 402. The data input terminal 401 is configured to receive a data signal. The data output terminal 402 is configured to output a data signal. The clock control terminal 403 is configured to receive a clock signal. The first latch unit 404 is configured to latch or transmit the data signal from the data input terminal 401 under the control of the clock signal. The second latch unit 405 is configured to latch or transmit the data signal from the first latch unit 404 under the control of the clock signal. The inverting drive unit 406 is configured to transmit the data signal from the second latch unit 405 in reverse phase.

[0089] Compared to static D flip-flops, dynamic D flip-flops significantly simplify the circuit structure by reducing the feedback circuitry used to maintain the operating state, thus reducing both chip area and power consumption. These advantages have enabled the widespread use of dynamic D flip-flops in computing chips. However, because dynamic D flip-flops have nodes with floating potentials for a portion of the time (e.g., the node formed between the first latch unit 404 and the second latch unit 405, and the node formed between the second latch unit 405 and the inverting drive unit 406), the parasitic capacitance at these nodes needs to maintain the correct voltage state during these periods. To prevent leakage current from affecting the voltage of these nodes, dynamic D flip-flops must operate at a higher frequency to reduce leakage time and prevent malfunctions. This greatly limits the chip's usability. For example, in some processor states such as sleep or idle, dynamic D flip-flops may operate at relatively low frequencies, which can potentially lead to malfunctions.

[0090] In some embodiments, the first latch unit 404 may include a latch circuit according to any embodiment of the present disclosure. The input of such a latch circuit may, for example, directly provide the data input 401 of the dynamic D flip-flop. As described above, by employing the latch circuit of the present disclosure in the first latch unit 404, leakage current can be effectively suppressed, thereby reducing the minimum operating frequency of the dynamic D flip-flop.

[0091] In some examples, the second latch unit 405 may include a tri-state gate. For example, referring to FIG19, a circuit 500 of a dynamic D flip-flop 400 according to some embodiments of the present disclosure is shown. As shown in FIG19, the circuit 500 includes a latch circuit 520 (which acts as a first latch unit 404 of the dynamic D flip-flop 400 (specifically, a non-inverting latch unit)), a tri-state gate 530 (which acts as a second latch unit 405 of the dynamic D flip-flop 400 (specifically, an inverting latch unit)), and an inverter 570 (which acts as an inverting drive unit 406 of the dynamic D flip-flop 400) connected in series between the data input terminal D and the data output terminal Q. Node A formed between the latch circuit 520 and the tri-state gate 530, and node B formed between the tri-state gate 530 and the inverter 570, are floating for a portion of the time.

[0092] The latch circuit 520 includes NMOS transistors 521, 522, 523, and 524, which are non-limitingly arranged as shown in the example arrangement in FIG10. The inverter 570 includes PMOS transistors 571 and 572 connected in series between power supply VDD and ground VSS. The tri-state gate 530 includes PMOS transistors 531, 532, 533, and 534 connected in series between power supply VDD and ground VSS. Specifically, NMOS transistors 521, 523, and 532 receive a clock signal CLKP, and PMOS transistors 522, 524, and 533 receive a clock signal CLKN. Thus, the clock signal can cause the tri-state gate 530 to conduct when the latch circuit 520 is off, and to close when the latch circuit 520 is on. Therefore, when CLKP is high and CLKN is low, latch circuit 520 is turned on and tri-state gate 530 is turned off. Data from data input terminal D is transmitted in phase through latch circuit 520 and output to node A (e.g., rewriting the data of node A), but cannot continue to pass through tri-state gate 530. When CLKP becomes low and CLKN becomes high, latch circuit 520 is turned off and tri-state gate 530 is turned on. Data from data input terminal D cannot pass through latch circuit 520, the data of node A is retained, and the data from node A is transmitted inverted through tri-state gate 520 and output to node B (e.g., rewriting the data of node B). After further inversion through inverter 570, it is output to data output terminal Q. When CLKP goes high again and CLKN goes low again, latch circuit 520 turns on and tri-state gate 530 turns off. Data from data input terminal D is transmitted in phase through latch circuit 520 and output to node A (e.g., rewriting the data at node A), but cannot continue to pass through tri-state gate 530, and the data at node B is retained. Similarly, the application of clock signals CLKP and CLKN can also be reversed, i.e., NMOS transistors 521, 523, and 532 receive clock signal CLKN, and PMOS transistors 522, 524, and 533 receive clock signal CLKP, thereby changing the effective level accordingly. Furthermore, the arrangement of tri-state gate 530 is not limited to this; it can also be replaced by having the gates of PMOS transistors 531 and 534 receive the corresponding clock signals, while the gates of PMOS transistors 532 and 533 are connected together to receive the data signal. Tri-state gates mentioned elsewhere in this document are similar and will not be repeated hereafter.

[0093] In some examples, the second latch unit 405 may include an inverter and a transmission gate connected in series between the first latch unit 404 and the inverting drive unit 406. For example, referring to FIG. 20, compared to FIG. 19, the tri-state gate 530 is replaced by a combination of an inverter 540 and a transmission gate 550, which acts as the second latch unit 405 (specifically, the inverting latch unit) of the dynamic D flip-flop 400. The inverter 540 includes a PMOS transistor 541 and an NMOS transistor 542 connected in series between the power supply VDD and ground VSS. The transmission gate 550 includes an NMOS transistor 551 and a PMOS transistor 552 connected in parallel between the inverter 540 and the inverter 570. The inverter 540 can provide drive capability for the transmission gate 550. The timing control of FIG. 20 is similar to that of FIG. 19 and will not be described in detail here.

[0094] In some examples, the second latch unit 405 may include an inverter and a latch circuit according to any embodiment of the present disclosure, connected in series between the first latch unit 404 and the inverting drive unit 406. For example, referring to FIG. 21, compared to FIG. 20, the transmission gate 550 is replaced by a latch circuit 560, and the combination of the inverter 540 and the latch circuit 560 serves as the second latch unit 405 (specifically, the inverting latch unit) of the dynamic D flip-flop 400. The inverter 540 can provide drive capability for the latch circuit 560. The latch circuit 560 includes NMOS transistors 561, 562, 563, and 564, which are non-limitingly arranged as shown in the example arrangement of FIG. 16. Thus, the latch circuit 520 can mitigate the effects of dynamic leakage current at node A, and the latch circuit 560 can mitigate the effects of dynamic leakage current at node B, thereby further reducing the minimum operating efficiency of the dynamic D flip-flop. The timing control of FIG. 21 is similar to that of FIG. 19 and will not be described in detail here.

[0095] In other embodiments, the first latch unit 404 may include an inverter and a latching circuit according to any embodiment of the present disclosure, connected in series between the data input terminal 401 and the second latch unit 405. The input of such an inverter may, for example, directly provide the data input terminal 401 of a dynamic D flip-flop. In such embodiments, the second latch unit 405 may include, for example, one of the following: a tri-state gate; an inverter and a transmission gate connected in series between the first latch unit 404 and the inverter driving unit 406; or an inverter and a latching circuit according to any embodiment of the present disclosure connected in series between the first latch unit 404 and the inverter driving unit 406.

[0096] For example, FIG22 illustrates a circuit 600 of a dynamic D flip-flop 400 according to some embodiments of the present disclosure. As shown in FIG22, the circuit 600 includes an inverter 610, a latch circuit 620 (the combination of inverter 610 and latch circuit 620 serves as a first latch unit 404 (specifically, an inverting latch unit) of the dynamic D flip-flop 400), a tri-state gate 630 (which serves as a second latch unit 405 (specifically, an inverting latch unit) of the dynamic D flip-flop 400), and an inverter 670 (which serves as an inverting drive unit 406 of the dynamic D flip-flop 400). Inverter 610 includes a PMOS transistor 611 and an NMOS transistor 612, which are connected in series between power supply VDD and ground VSS. Latch circuit 620 includes NMOS transistor 621, PMOS transistor 622, NMOS transistor 623, and PMOS transistor 624, which are non-limitingly arranged as illustrated in FIG10. The tri-state gate 630 includes a PMOS transistor 631, a PMOS transistor 632, an NMOS transistor 633, and an NMOS transistor 634 connected in series between the power supply VDD and ground VSS. The inverter 670 includes a PMOS transistor 671 and an NMOS transistor 672 connected in series between the power supply VDD and ground VSS.

[0097] Compared to Figure 22, in Figure 23, the tri-state gate 630 is replaced by a combination of an inverter 640 and a transmission gate 650, which acts as the second latch unit 405 (specifically, an inverting latch unit) of the dynamic D flip-flop 400. The inverter 640 includes a PMOS transistor 641 and an NMOS transistor 642 connected in series between power supply VDD and ground VSS. The transmission gate 650 includes an NMOS transistor 651 and a PMOS transistor 652 connected in parallel between the inverter 640 and the inverter 670. The inverter 640 provides drive capability for the transmission gate 650.

[0098] Compared to Figure 23, in Figure 24, the transmission gate 650 is replaced by a latch circuit 660. The combination of inverter 640 and latch circuit 660 serves as the second latch unit 405 (specifically, an inverting latch unit) of the dynamic D flip-flop 400. Inverter 640 provides drive capability for latch circuit 660. Latch circuit 660 includes NMOS transistors 661, 662, 663, and 664, which are non-limitingly arranged as shown in the example arrangement in Figure 16. Thus, latch circuit 620 can mitigate the effects of dynamic leakage current at node A, and latch circuit 660 can mitigate the effects of dynamic leakage current at node B, further reducing the minimum operating efficiency of the dynamic D flip-flop.

[0099] The timing control of the dynamic D flip-flops shown in Figures 22 to 24 for providing inverted output is similar to the timing control of the dynamic D flip-flops shown in Figures 19 to 21 for providing non-inverted output, and will not be described in detail here.

[0100] In other embodiments, the second latch unit 405 may include an inverter and a latch circuit according to any embodiment of the present disclosure, connected in series between the first latch unit 404 and the inverter drive unit 406. In such embodiments, the first latch unit 404 may include, for example, one of the following: a transmission gate; a tri-state gate; an inverter and a transmission gate connected in series between the data input terminal 401 and the second latch unit 405.

[0101] For example, FIG25 illustrates a circuit 700 of a dynamic D flip-flop 400 according to some embodiments of the present disclosure. As shown in FIG25, the circuit 700 includes a tri-state gate 710 (which acts as a first latch unit 404 (specifically, an inverting latch unit) of the dynamic D flip-flop 400) connected in series between the data input terminal D and the data output terminal Q, an inverter 750, a latch circuit 760 (the combination of the inverter 750 and the latch circuit 760 acts as a second latch unit 405 (specifically, an inverting latch unit) of the dynamic D flip-flop 400), and an inverter 770 (which acts as an inverting drive unit 406 of the dynamic D flip-flop 400). The tri-state gate 710 includes a PMOS transistor 711, a PMOS transistor 712, an NMOS transistor 713, and an NMOS transistor 714 connected in series between the power supply VDD and the ground VSS. The inverter 750 includes a PMOS transistor 751 and an NMOS transistor 752 connected in series between the power supply VDD and the ground VSS. The latch circuit 760 includes NMOS transistors 761, 762, 763, and 764, arranged non-limitingly as shown in the example arrangement in Figure 16. An inverter 750 provides drive capability for the latch circuit 760. The inverter 770 includes a PMOS transistor 771 and an NMOS transistor 772 connected in series between power supply VDD and ground VSS. The timing control of the dynamic D flip-flop shown in Figure 25 for providing the inverted output is similar to that in Figure 19 and will not be described further here.

[0102] Compared to Figure 25, in Figure 26, the tri-state gate 710 is replaced by a combination of an inverter 720 and a transmission gate 730, which acts as the first latch unit 404 (specifically, the inverting latch unit) of the dynamic D flip-flop 400. The inverter 720 includes a PMOS transistor 721 and an NMOS transistor 722 connected in series between power supply VDD and ground VSS. The transmission gate 730 includes an NMOS transistor 731 and a PMOS transistor 732 connected in parallel between the inverter 720 and the inverter 750. The timing control of the dynamic D flip-flop shown in Figure 26 for providing the inverted output is similar to that in Figure 19 and will not be described in detail here.

[0103] Compared to Figure 26, in Figure 27, the combination of inverter 720 and transmission gate 730 is replaced by transmission gate 740, which acts as the first latch unit 404 (specifically, the non-inverting latch unit) of the dynamic D flip-flop 400. Transmission gate 740 includes an NMOS transistor 741 and a PMOS transistor 742 connected in parallel between the data input terminal D and the inverter 750. The timing control of the dynamic D flip-flop shown in Figure 27 for providing the non-inverting output is similar to that in Figure 19 and will not be described in detail here.

[0104] This disclosure provides a register in another aspect. As shown in FIG28, register 800 includes: a plurality of data input terminals D[n:0] configured to receive data signals; a plurality of data output terminals Q[n:0] configured to output data signals; and a clock control terminal CK configured to receive clock signals. Register 800 also includes a clock buffer 802 configured to buffer the clock signal received by the clock control terminal CK and provide clock signals (CLKP, CLKN) to a plurality of register units 801. Clock buffer 802 is similar to the aforementioned clock buffer 200 and will not be described again here. Register 800 also includes a plurality of register units 801 connected in parallel between the plurality of data input terminals D[n:0] and the plurality of data output terminals Q[n:0], and configured to write and / or read data under the control of the clock signal. In particular, the register units in the plurality of register units 801 may be dynamic latches according to any embodiment of this disclosure, or dynamic D flip-flops according to any embodiment of this disclosure.

[0105] Typically, individual latches or D flip-flops require a clock buffer to generate inverted clock signals for timing control. If a separate clock buffer is configured for each latch or D flip-flop, the clock buffers consume considerable chip area and power in applications requiring multiple latches or D flip-flops. Therefore, the register according to embodiments of this disclosure uses a single clock buffer to drive multiple dynamic latches or dynamic D flip-flops simultaneously, effectively reducing area and power consumption.

[0106] In another aspect, this disclosure provides a processor that may include a dynamic latch according to any embodiment of this disclosure, or a dynamic D flip-flop according to any embodiment of this disclosure, or a register according to any embodiment of this disclosure.

[0107] This disclosure also provides a computing device that may include a processor according to any embodiment of this disclosure. Such a computing device may include, for example, computing chips for fields such as exploration, climate change, transportation, and artificial intelligence, or electronic devices incorporating such computing chips.

[0108] The terms “left,” “right,” “front,” “back,” “top,” “bottom,” “upper,” “lower,” “high,” “lower,” etc., used in the specification and claims, if present, are for descriptive purposes and not necessarily for describing unchanging relative positions. It should be understood that such terms are interchangeable where appropriate, so that embodiments of this disclosure described herein can operate, for example, in orientations different from those shown or otherwise described herein. For example, when the device in the drawings is reversed, a feature previously described as “above” other features may now be described as “below” other features. The device may also be oriented in other ways (rotated 90 degrees or in other orientations), in which case the relative spatial relationships will be interpreted accordingly.

[0109] In the specification and claims, when an element is described as being "on top of," "attached to," "connected to," "coupled to," or "in contact with" another element, the element may be directly located on top of, directly attached to, directly connected to, directly coupled to, or directly in contact with the other element, or one or more intermediate elements may be present. Conversely, when an element is described as being "directly" located on top of, directly attached to, directly connected to, directly coupled to, or directly in contact with another element, no intermediate elements are present. In the specification and claims, when a feature is arranged "adjacent" to another feature, it may mean that a feature has a portion overlapping with the adjacent feature or a portion located above or below the adjacent feature.

[0110] As used herein, the term "exemplary" means "serving as an example, instance, or illustration," and not as a "model" to be precisely copied. Any implementation described herein by example is not necessarily to be construed as preferred or advantageous over other implementations. Furthermore, this disclosure is not limited to any theory expressed or implied as given in the art, background, summary of the invention, or detailed description.

[0111] As used herein, the term "substantially" means any minor variation resulting from design or manufacturing defects, device or component tolerances, environmental influences, and / or other factors. The term "substantially" also allows for differences from the perfect or ideal situation due to parasitic effects, noise, and other practical considerations that may exist in the actual implementation.

[0112] Additionally, terms such as “first,” “second,” etc., may be used in this document for reference purposes only and are not intended to be limiting. For example, unless the context clearly indicates otherwise, the words “first,” “second,” and other such numerical terms relating to structures or elements do not imply order or sequence.

[0113] It should also be understood that the term "including / comprises" as used herein indicates the presence of the indicated feature, whole, step, operation, unit, and / or component, but does not preclude the presence or addition of one or more other features, wholes, steps, operations, units, and / or components, and / or combinations thereof. In this disclosure, the term "provide" is used broadly to cover all ways of obtaining an object; therefore, "providing an object" includes, but is not limited to, "purchasing," "preparing / manufacturing," "arranging / setting," "installing / assembling," and / or "ordering" an object.

[0114] As used herein, the term “and / or” includes any and all combinations of one or more of the listed items in association. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of this disclosure. As used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise.

[0115] The same or similar parts between the various embodiments of this disclosure can be referred to mutually, and each embodiment focuses on describing the differences from other embodiments. In the description of this disclosure, the reference to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," "exemplary," etc., means that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this disclosure. In this disclosure, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in a suitable manner in any one or more embodiments or examples. Furthermore, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this disclosure and the features of the different embodiments or examples.

[0116] Additionally, when used in this disclosure, the terms “here,” “above,” “below,” “this,” “the following,” “the text,” “the preceding,” and similar terms should refer to the entire disclosure and not any particular part of it. Furthermore, unless expressly stated otherwise or otherwise understood in the context in which they are used, conditional language used herein, such as “may,” “possibly,” “for example,” “like,” etc., is generally intended to express that certain embodiments include, while other embodiments do not, certain features, elements, and / or states. Therefore, such conditional language is not generally intended to imply that one or more embodiments require features, elements, and / or states in any way, or whether such features, elements, and / or states are included or performed in any particular embodiment.

[0117] Those skilled in the art will recognize that the boundaries between the above operations are merely illustrative. Multiple operations may be combined into a single operation, a single operation may be distributed among additional operations, and operations may be performed with at least partial overlap in time. Moreover, alternative embodiments may include multiple instances of a particular operation, and the order of operations may be changed in various other embodiments. However, other modifications, variations, and substitutions are equally possible. Aspects and elements of all the embodiments disclosed above may be combined in any way and / or in combination with aspects or elements of other embodiments to provide multiple additional embodiments. Therefore, this specification and the accompanying drawings should be considered illustrative rather than restrictive.

[0118] While specific embodiments of this disclosure have been described in detail by way of example, those skilled in the art should understand that the examples are for illustrative purposes only and not intended to limit the scope of this disclosure. The various embodiments disclosed herein can be combined in any way without departing from the spirit and scope of this disclosure. Those skilled in the art should also understand that various modifications can be made to the embodiments without departing from the scope and spirit of this disclosure. The scope of this disclosure is defined by the appended claims.

Claims

1. A latching circuit, the latching circuit comprising: Input terminal; Output terminal; A first transistor having a first conductivity type, wherein the control terminal of the first transistor is configured to receive a first clock signal; A second transistor having a second conductivity type different from the first conductivity type, wherein the control terminal of the second transistor is configured to receive a second clock signal that is inversely phase to the first clock signal; as well as A third transistor, wherein the control terminal of the third transistor is configured to receive the same clock signal as the control terminal of the first transistor and the second transistor, which have the same conduction type as the third transistor. The first transmission terminal of the first transistor and the first transmission terminal of the second transistor are both connected to the input terminal, the second transmission terminal of the first transistor is connected to the output terminal via the third transistor, and the second transmission terminal of the second transistor is connected to the output terminal.

2. The latching circuit according to claim 1, wherein, The latching circuit includes a first sub-circuit and a second sub-circuit connected in parallel between the input terminal and the output terminal, wherein the first transistor and the third transistor are included in the first sub-circuit and connected in series with each other, and the second transistor is included in the second sub-circuit.

3. The latching circuit according to claim 1 or 2, wherein, The third transistor has the first conductivity type.

4. The latching circuit according to claim 1 or 2, wherein, The third transistor includes a plurality of third transistors connected in series with the first transistor.

5. The latching circuit according to claim 1, wherein, The latching circuit further includes a fourth transistor, the control terminal of which is configured to receive the same clock signal as the control terminal of the first transistor and the second transistor of the same conduction type as the fourth transistor. The second transmission terminal of the second transistor is connected to the output terminal via the fourth transistor.

6. The latching circuit according to claim 5, wherein, The latching circuit includes a first sub-circuit and a second sub-circuit connected in parallel between the input terminal and the output terminal, wherein the first transistor and the third transistor are included in the first sub-circuit and connected in series with each other, and the second transistor and the fourth transistor are included in the second sub-circuit and connected in series with each other.

7. The latching circuit according to claim 5 or 6, wherein, The fourth transistor has the second conductivity type.

8. The latching circuit according to claim 5 or 6, wherein, The fourth transistor includes a plurality of fourth transistors connected in series with the second transistor.

9. The latching circuit according to claim 5, wherein, The fourth transistor has a different conductivity type than the third transistor. The latching circuit includes a third sub-circuit and a fourth sub-circuit connected in series between the input terminal and the output terminal. The first transistor and the second transistor are included in the third sub-circuit and connected in parallel with each other. The third transistor and the fourth transistor are included in the fourth sub-circuit and connected in parallel with each other.

10. The latching circuit according to claim 9, wherein, The third sub-circuit includes a first sub-circuit and a second sub-circuit connected in parallel, wherein the first transistor is included in the first sub-circuit of the third sub-circuit and the second transistor is included in the second sub-circuit of the third sub-circuit. The fourth sub-circuit includes a first sub-circuit and a second sub-circuit connected in parallel. The third transistor is included in the first sub-circuit of the fourth sub-circuit, and the fourth transistor is included in the second sub-circuit of the fourth sub-circuit. The latching circuit further includes one or more of the following: One or more fifth transistors are connected in series with the first transistor in the first sub-circuit of the third sub-circuit; or One or more sixth transistors are connected in series with the second transistor in the second sub-circuit of the third sub-circuit; or One or more seventh transistors are connected in series with the third transistor in the first sub-circuit of the fourth sub-circuit; or One or more eighth transistors are connected in series with the fourth transistor in the second sub-circuit of the fourth sub-circuit. The control terminal of each of the fifth, sixth, seventh, and eighth transistors is configured to receive the same clock signal as the control terminal of the first and second transistors with the same conduction type.

11. The latching circuit according to claim 2, 6, or 10, wherein, The first sub-circuit and the second sub-circuit connected in parallel with the first sub-circuit both comprise the same number of transistors.

12. The latching circuit according to claim 1, wherein, The transistor in the latching circuit is a metal-oxide-semiconductor (MOS) transistor.

13. A dynamic latch, the dynamic latch comprising: The data input terminal is configured to receive data signals. The data output terminal is configured to output data signals. The clock control terminal is configured to receive clock signals. as well as A latch unit and an inverting drive unit are connected in series between the data input terminal and the data output terminal. The latch unit is configured to latch or transmit the data signal from the data input terminal under the control of a clock signal, and the inverting drive unit is configured to transmit the data signal from the latch unit in reverse phase. The latching unit includes a latching circuit according to any one of claims 1 to 12.

14. The dynamic latch according to claim 13, wherein, The latch unit also includes an inverter connected in series between the data input terminal and the latch circuit.

15. A dynamic D flip-flop, the dynamic D flip-flop comprising: The data input terminal is configured to receive data signals. The data output terminal is configured to output data signals. The clock control terminal is configured to receive clock signals. as well as A first latch unit, a second latch unit, and an inverting drive unit are connected in series between the data input terminal and the data output terminal. The first latch unit is configured to latch or transmit the data signal from the data input terminal under the control of a clock signal. The second latch unit is configured to latch or transmit the data signal from the first latch unit under the control of a clock signal. The inverting drive unit is configured to transmit the data signal from the second latch unit in reverse phase. The first latch unit includes a latch circuit according to any one of claims 1 to 12.

16. The dynamic D flip-flop according to claim 15, wherein, The second latch unit includes one of the following: Three-state gate; or An inverter and a transmission gate are connected in series between the first latch unit and the inverting drive unit; or An inverter and a latching circuit according to any one of claims 1 to 12 are connected in series between the first latching unit and the inverting drive unit.

17. A dynamic D flip-flop, the dynamic D flip-flop comprising: The data input terminal is configured to receive data signals. The data output terminal is configured to output data signals. The clock control terminal is configured to receive clock signals. as well as A first latch unit, a second latch unit, and an inverting drive unit are connected in series between the data input terminal and the data output terminal. The first latch unit is configured to latch or transmit the data signal from the data input terminal under the control of a clock signal. The second latch unit is configured to latch or transmit the data signal from the first latch unit under the control of a clock signal. The inverting drive unit is configured to transmit the data signal from the second latch unit in reverse phase. The first latch unit includes an inverter and a latch circuit according to any one of claims 1 to 12, which are connected in series between the data input terminal and the second latch unit.

18. The dynamic D flip-flop according to claim 17, wherein, The second latch unit includes one of the following: Three-state gate; or An inverter and a transmission gate are connected in series between the first latch unit and the inverting drive unit; or An inverter and a latching circuit according to any one of claims 1 to 12 are connected in series between the first latching unit and the inverting drive unit.

19. A dynamic D flip-flop, the dynamic D flip-flop comprising: The data input terminal is configured to receive data signals. The data output terminal is configured to output data signals. The clock control terminal is configured to receive clock signals. as well as A first latch unit, a second latch unit, and an inverting drive unit are connected in series between the data input terminal and the data output terminal. The first latch unit is configured to latch or transmit the data signal from the data input terminal under the control of a clock signal. The second latch unit is configured to latch or transmit the data signal from the first latch unit under the control of a clock signal. The inverting drive unit is configured to transmit the data signal from the second latch unit in reverse phase. The second latch unit includes an inverter connected in series between the first latch unit and the inverting drive unit, and a latch circuit according to any one of claims 1 to 12.

20. The dynamic D flip-flop according to claim 19, wherein, The first latch unit includes one of the following: Transmission gate; or Three-state gate; or An inverter and a transmission gate are connected in series between the data input terminal and the second latch unit.

21. A register, the register comprising: Multiple data input terminals are configured to receive data signals; Multiple data output terminals are configured to output data signals; The clock control terminal is configured to receive clock signals. A clock buffer is configured to buffer the clock signal received by the clock control terminal and provide clock signals to multiple register units; as well as The plurality of register units are connected in parallel between the plurality of data input terminals and the plurality of data output terminals, and are configured to perform at least one of writing data and reading data under the control of a clock signal. The register unit among the plurality of register units is a dynamic latch according to claim 13 or 14, or a dynamic D flip-flop according to any one of claims 15 to 20.

22. A processor comprising a dynamic latch according to claim 13 or 14, or a dynamic D flip-flop according to any one of claims 15 to 20, or a register according to claim 21.

23. A computing device comprising the processor according to claim 22.

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