Display panel and display device

Abstract

Embodiments of the present disclosure relate to the technical field of display, and provide a display panel and a display device, for use in improving the display uniformity of the display panel and increasing the PPI of the display panel. The display panel comprises a plurality of pixel circuits arranged in an array, each pixel circuit comprises a storage capacitor, and the storage capacitor comprises a second electrode plate. The display panel further comprises a substrate, a fourth conductive layer, and a second conductive layer. The fourth conductive layer is located on the substrate, the fourth conductive layer comprises a plurality of initialization signal lines, the initialization signal lines extend along a second direction, and the second direction is a column direction in which the plurality of pixel circuits are arranged. The second conductive layer is located on the side of the fourth conductive layer close to the substrate, and the second electrode plate of the storage capacitor is located on the second conductive layer. The orthographic projection of the initialization signal lines on the substrate overlaps the orthographic projection of second electrode plates of a plurality of storage capacitors of a column of pixel circuits on the substrate. The display panel is used for displaying an image.

Description

Display panel and display device

[0001] This application claims priority to Chinese patent application No. 202410814785.X, filed on June 21, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This disclosure relates to the field of display technology, and more particularly to a display panel and display device. Background Technology

[0003] With the continuous development of display technology, display devices have gradually become ubiquitous in people's lives. Among them, organic light-emitting diode (OLED) display panels are widely used in display devices such as mobile phones, televisions, and laptops due to their advantages such as self-illumination, low power consumption, wide viewing angle, fast response speed, and high contrast. Summary of the Invention

[0004] On one hand, a display panel is provided. The display panel includes a plurality of pixel circuits arranged in an array, each pixel circuit including a storage capacitor, and the storage capacitor including a second electrode plate.

[0005] The display panel further includes a substrate, a fourth conductive layer, and a second conductive layer. The fourth conductive layer is located on the substrate and includes multiple initialization signal lines extending along a second direction, which is the column direction in which the plurality of pixel circuits are arranged. The second conductive layer is located on the side of the fourth conductive layer closest to the substrate, and the second plates of the storage capacitors are located on the second conductive layer. The orthographic projection of the initialization signal lines onto the substrate overlaps with the orthographic projection of the second plates of the multiple storage capacitors of a column of pixel circuits onto the substrate.

[0006] In some embodiments, the display panel further includes a fifth conductive layer located on the side of the fourth conductive layer away from the substrate, and the fifth conductive layer includes a first voltage signal line.

[0007] The second electrode of the storage capacitor of the plurality of pixel circuits includes a plurality of second electrode pairs. Each second electrode pair includes two adjacent second electrodes in a first direction, which is the row direction in which the plurality of pixel circuits are arranged. The second conductive layer also includes a first connection portion, through which two second electrodes belonging to a second electrode pair are connected.

[0008] The fourth conductive layer further includes a first transition pattern, and the first connection portion is connected to the first voltage signal line through the first transition pattern. In a projection onto the substrate, the first transition pattern is located between the two second plates within the second plate pair.

[0009] In some embodiments, the display panel further includes a first semiconductor layer located on the side of the second conductive layer near the substrate. The pixel circuit further includes a first light-emitting control transistor, which includes an active layer pattern located on the first semiconductor layer. The fourth conductive layer further includes a second transition pattern, through which a first voltage signal line within the display panel is connected to the active layer pattern of the first light-emitting control transistor. Specifically, along a first direction, the second transition pattern is located between two adjacent initialization signal lines.

[0010] In some embodiments, the first adapter pattern and the second adapter pattern are spaced apart.

[0011] In some embodiments, the pixel circuit further includes a third reset transistor, the third reset transistor including an active layer pattern located on the first semiconductor layer. The fourth conductive layer further includes a third transition pattern, the active layer pattern of the third reset transistor being connected to the active layer pattern of the first light-emitting control transistor via the third transition pattern. Wherein, along the first direction, the second transition pattern is located between two adjacent third transition patterns.

[0012] In some embodiments, the active layer pattern of the first light-emitting control transistor includes a main body extending along the second direction. In projection onto the substrate, the third transition pattern overlaps with the main body near one end of the active layer pattern of the first light-emitting control transistor.

[0013] In some embodiments, the display panel further includes a third conductive layer located between the fourth conductive layer and the second conductive layer. The third conductive layer includes a plurality of auxiliary signal lines extending along a first direction. The plurality of auxiliary signal lines include a third auxiliary signal line. The fourth conductive layer further includes a fourth transition pattern, and the third auxiliary signal line is connected to the active layer pattern of the third reset transistor of the pixel circuit via the fourth transition pattern. The orthographic projection of the active layer pattern of the third reset transistor onto the substrate overlaps with the orthographic projection of the third auxiliary signal line onto the substrate.

[0014] In some embodiments, the display panel further includes a first conductive layer located on the side of the second conductive layer near the substrate.

[0015] The first conductive layer includes a second reset control signal line extending along the first direction. The orthographic projection of the second reset control signal line onto the substrate and the orthographic projection of the third auxiliary signal line onto the substrate at least partially overlap. And / or,

[0016] The first conductive layer further includes a light-emitting control signal line extending along the first direction. The plurality of auxiliary signal lines also include a first auxiliary signal line, which, in its orthographic projection onto the substrate, is located between the second plate of the storage capacitor and the third auxiliary signal line, and at least partially overlaps with the light-emitting control signal line.

[0017] In some embodiments, the pixel circuit further includes a first reset transistor, the first reset transistor including an active layer pattern located within a first semiconductor layer of the display panel. The fourth conductive layer further includes a fifth transition pattern, through which the first auxiliary signal line is connected to the active layer pattern of the first reset transistor.

[0018] In some embodiments, the initialization signal line includes a plurality of initialization signal line groups arranged along a first direction, each initialization signal line group including at least one first initialization signal line, at least one second initialization signal line, and at least one third initialization signal line. The first initialization signal line is configured to transmit a first initialization signal, the second initialization signal line is configured to transmit a second initialization signal, and the third initialization signal line is configured to transmit a third initialization signal.

[0019] In some embodiments, the fourth conductive layer further includes a sixth transition pattern. The first initialization signal line is connected to the active layer pattern of the first reset transistor within the pixel circuit via the sixth transition pattern.

[0020] In some embodiments, the display panel further includes a plurality of auxiliary signal lines, including a second auxiliary signal line and a third auxiliary signal line. The second auxiliary signal line is connected to the second initialization signal line, and the third auxiliary signal line is connected to the third initialization signal line.

[0021] In some embodiments, the fourth conductive layer further includes a seventh transition pattern and an eighth transition pattern. The second auxiliary signal line is connected to the second initialization signal line via the seventh transition pattern, and the third auxiliary signal line is connected to the third initialization signal line via the eighth transition pattern.

[0022] In some embodiments, the display panel includes a display area and a peripheral area surrounding the display area. The peripheral area includes a first border area, a second border area, a third border area, and a fourth border area, wherein the first border area and the second border area are disposed on both sides of the display area along a first direction, and the third border area and the fourth border area are disposed on both sides of the display area along a second direction.

[0023] The display panel further includes a second initialization signal bus and a third initialization signal bus, which are at least located in the first bezel area and / or the second bezel area. The second auxiliary signal line is connected to the second initialization signal bus, and the third auxiliary signal line is connected to the third initialization signal bus.

[0024] In some embodiments, the plurality of auxiliary signal lines further includes a first auxiliary signal line. The first auxiliary signal line is connected to the first initialization signal line.

[0025] In some embodiments, the display panel further includes a first initialization signal bus, which is at least disposed in a first bezel area and / or a second bezel area of ​​the display panel. The first auxiliary signal line is connected to the first initialization signal bus.

[0026] In some embodiments, the fourth bezel area of ​​the display panel is located near the bonding side of the display panel. The display panel further includes a first initialization signal bus, which is at least disposed in the fourth bezel area. The first initialization signal line and the first initialization signal bus are connected.

[0027] On the other hand, a display device is provided. The display device includes a display panel and a driver chip as described in any of the above embodiments. The driver chip is electrically connected to the display panel. Attached Figure Description

[0028] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this disclosure.

[0029] Figure 1 is a structural diagram of a display device according to some embodiments;

[0030] Figure 2 is another structural diagram of a display device according to some embodiments;

[0031] Figure 3 is a cross-sectional view of the display panel in Figure 2 along section line BB;

[0032] Figure 4 is an equivalent circuit diagram of a pixel circuit according to some embodiments;

[0033] Figure 5 is a planar structural diagram of a partial region of the pixel definition layer in a display panel according to some embodiments;

[0034] Figure 6A is a planar structural diagram of a partial region of the pixel driving layer in a display panel according to some embodiments;

[0035] Figure 6B is a plan view of a partial region of the first semiconductor layer in the pixel driving layer of a display panel according to some embodiments;

[0036] Figure 6C is a plan view of a partial region of the first conductive layer in the pixel driving layer of a display panel according to some embodiments;

[0037] Figure 6D is a plan view of a partial region of the first semiconductor layer and the first conductive layer in the pixel driving layer of a display panel according to some embodiments;

[0038] Figure 6E is a planar structural diagram of a partial region of the second conductive layer in the pixel driving layer of a display panel according to some embodiments;

[0039] Figure 6F is another planar structural diagram of a partial region of the second conductive layer in the pixel driving layer of a display panel according to some embodiments;

[0040] Figure 6G is another planar structural diagram of a partial region of the second conductive layer in the pixel driving layer of a display panel according to some embodiments;

[0041] Figure 6H is a plan view of a partial region of the second semiconductor layer in the pixel driving layer of a display panel according to some embodiments;

[0042] Figure 6I is a plan view of a partial region of the third conductive layer in the pixel driving layer of a display panel according to some embodiments;

[0043] Figure 6J is a planar structural diagram of a partial region of the fourth conductive layer in the pixel driving layer of a display panel according to some embodiments;

[0044] Figure 6K is a planar structural diagram of a partial region of the first semiconductor layer, the second conductive layer and the fourth conductive layer in the pixel driving layer of a display panel according to some embodiments;

[0045] Figure 6L is a planar structural diagram of a partial region of the first semiconductor layer, the third conductive layer and the fourth conductive layer in the pixel driving layer of a display panel according to some embodiments;

[0046] Figure 6M is a plan view of a partial region of the fifth conductive layer in the pixel driving layer of a display panel according to some embodiments;

[0047] Figure 7A is a plan view of a display device according to some embodiments;

[0048] Figure 7B is another plan view of a display device according to some embodiments;

[0049] Figure 7C is another plan view of a display device according to some embodiments;

[0050] Figure 7D is another plan view of a display device according to some embodiments;

[0051] Figure 8A is another plan view of a display device according to some embodiments;

[0052] Figure 8B is another plan view of a display device according to some embodiments;

[0053] Figure 9 is another plan view of a display device according to some embodiments;

[0054] Figure 10A is another planar structural diagram of a partial region of the pixel driving layer in a display panel according to some embodiments;

[0055] Figure 10B is another planar structural diagram of a partial region of the fourth conductive layer in the pixel driving layer of a display panel according to some embodiments;

[0056] Figure 10C is a planar structural diagram of a partial region of the second conductive layer and the fourth conductive layer in the pixel driving layer of a display panel according to some embodiments;

[0057] Figure 11A is yet another planar structural diagram of a partial area of ​​the pixel driving layer in a display panel according to some embodiments;

[0058] Figure 11B is yet another planar structural diagram of a partial region of the fourth conductive layer in the pixel driving layer of a display panel according to some embodiments;

[0059] Figure 11C is another planar structural diagram of a partial region of the first semiconductor layer, the second conductive layer and the fourth conductive layer in the pixel driving layer of a display panel according to some embodiments;

[0060] Figure 11D is another planar structural diagram of a partial region of the first semiconductor layer, the third conductive layer and the fourth conductive layer in the pixel driving layer of a display panel according to some embodiments;

[0061] Figure 11E is a planar structural diagram of a partial region of the first semiconductor layer, the first conductive layer, the third conductive layer, and the fourth conductive layer in the pixel driving layer of a display panel according to some embodiments;

[0062] Figure 12A is yet another planar structural diagram of a partial area of ​​the pixel driving layer in a display panel according to some embodiments;

[0063] Figure 12B is a plan view of a partial region of the first semiconductor layer, the first conductive layer, the second conductive layer and the third conductive layer in the pixel driving layer of a display panel according to some embodiments;

[0064] Figure 12C is a plan view of a partial region of the first semiconductor layer, the second conductive layer and the third conductive layer in the pixel driving layer of a display panel according to some embodiments;

[0065] Figure 12D is a planar structural diagram of a partial region of the first conductive layer and the third conductive layer in the pixel driving layer of a display panel according to some embodiments;

[0066] Figure 12E is yet another planar structural diagram of a partial region of the fourth conductive layer in the pixel driving layer of a display panel according to some embodiments;

[0067] Figure 12F is another planar structural diagram of a partial region of the first semiconductor layer, the third conductive layer and the fourth conductive layer in the pixel driving layer of a display panel according to some embodiments;

[0068] Figure 13A is another planar structural diagram of a partial area of ​​the pixel driving layer in a display panel according to some embodiments;

[0069] Figure 13B is another planar structural diagram of a partial region of the fourth conductive layer in the pixel driving layer of a display panel according to some embodiments;

[0070] Figure 13C is another planar structural diagram of a partial region of the first semiconductor layer, the third conductive layer, and the fourth conductive layer in the pixel driving layer of a display panel according to some embodiments. Detailed Implementation

[0071] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0072] Unless the context otherwise requires, throughout the specification and claims, the term "comprise" and its other forms, such as the third-person singular "comprises" and the present participle "comprising," are interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiments," "example," "specific example," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0073] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0074] In describing some embodiments, the terms "coupled" and "connected," and their derivative expressions, may be used. The term "connected" should be interpreted broadly; for example, a "connection" can be a fixed connection, a detachable connection, or an integral part; it can be a direct connection or an indirect connection via an intermediate medium. The term "coupled," for example, indicates that two or more components have direct physical or electrical contact. The term "coupled" or "communicatively coupled" may also refer to two or more components that do not have direct contact with each other but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content of this document.

[0075] "At least one of A, B and C" has the same meaning as "at least one of A, B or C", both including the following combinations of A, B and C: only A, only B, only C, combinations of A and B, combinations of A and C, combinations of B and C, and combinations of A, B and C.

[0076] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0077] As used herein, depending on the context, the term “if” may optionally be interpreted as meaning “when”, “in the event of”, “in response to determination”, or “in response to detection”. Similarly, depending on the context, the phrase “if it is determined that…” or “if [the stated condition or event] is detected” may optionally be interpreted as meaning “in the event of determination that…”, “in response to determination that…”, “when [the stated condition or event] is detected”, or “in response to the detection of [the stated condition or event]”.

[0078] The use of “applies to” or “configured to” in this article implies an open and inclusive language that does not preclude applicability to or configuration to devices that perform additional tasks or steps.

[0079] In addition, the use of “based on” implies openness and inclusivity, because processes, steps, calculations or other actions “based on” one or more of the stated conditions or values ​​may in practice be based on additional conditions or values ​​beyond those stated.

[0080] As used herein, “about,” “approximately,” or “approximately” includes the stated value and the average value within an acceptable range of deviation from the given value, wherein the acceptable range of deviation is determined by a person skilled in the art taking into account the measurement under discussion and the error associated with the measurement of the given quantity (i.e., the limitations of the measurement system).

[0081] As used herein, “parallel,” “perpendicular,” and “equal” include the described situation and situations that are similar to the described situation, within an acceptable range of deviation, which is determined by those skilled in the art taking into account the measurement under discussion and the error associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, “parallel” includes absolute parallelism and approximate parallelism, where an acceptable range of deviation for approximate parallelism may be, for example, within 5°; “perpendicular” includes absolute perpendicularity and approximate perpendicularity, where an acceptable range of deviation for approximate perpendicularity may also be, for example, within 5°; “equal” includes absolute equality and approximate equality, where an acceptable range of deviation for approximate equality may be, for example, a difference between the two equals being less than or equal to 5% of either one.

[0082] It should be understood that when a layer or element is referred to as being on another layer or substrate, it can mean that the layer or element is directly on the other layer or substrate, or that there is an intermediate layer between the layer or element and the other layer or substrate.

[0083] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as being limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched areas shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the areas of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0084] For ease of description below, an XYZ coordinate system is established. The third direction Z represents the thickness direction of the display device, the XY plane is perpendicular to the Z direction, and the first direction X intersects the second direction Y. For example, the first direction X and the second direction Y are perpendicular to each other.

[0085] It should be noted that, for example, T32 / C1 in the accompanying drawings of this disclosure indicates that the component is both T32 and C1, and other similar reference numerals in the drawings also follow the above description.

[0086] As shown in FIG1, some embodiments of the present disclosure provide a display device 100.

[0087] Exemplarily, the aforementioned display device 100 can be any device that displays images, whether moving (e.g., video) or fixed (e.g., still images), and whether text or images. More specifically, the embodiments described are contemplated to be implemented in or associated with a variety of electronic devices, such as (but not limited to) mobile phones, wireless devices, personal data assistants (PDAs), handheld or portable computers, GPS receivers / navigators, cameras, MP4 video players, camcorders, game consoles, watches, clocks, calculators, television monitors, flat panel displays, computer monitors, automotive displays (e.g., odometer displays, etc.), navigators, cockpit controllers and / or displays, displays of camera views (e.g., displays of rearview cameras in vehicles), electronic photographs, electronic billboards or signs, projectors, architectural structures, packaging and aesthetic structures (e.g., displays of images of a piece of jewelry), etc. Figure 1 illustrates a mobile phone as an example of the display device 100.

[0088] For example, the display device 100 may be an electroluminescent display device or a photoluminescent display device. When the display device 100 is an electroluminescent display device, it may be an organic light-emitting diode (OLED) display device or a quantum dot light-emitting diode (QLED) display device. When the display device 100 is a photoluminescent display device, it may be a quantum dot photoluminescent display device.

[0089] The display device 100 can also be a micro light-emitting diode (Micro LED) display device or a mini light-emitting diode (Mini LED) display device.

[0090] The following uses an organic light-emitting diode (OLED) display device as an example to illustrate some embodiments of the present disclosure. However, the implementation of the present disclosure includes, but is not limited to, these embodiments. Any other display device can also be considered as long as the same technical concept is applied.

[0091] In some embodiments, as shown in FIG2, FIG2 is a structural diagram of a display device 100 according to some embodiments. The display device 100 includes a display panel 10 and a driver chip 20. The driver chip 20 is electrically connected to the display panel 10 and is configured to drive the display panel 10 to display images.

[0092] For example, the driver chip 20 can be a source driver IC.

[0093] In some embodiments, the display device 100 further includes optical elements (not shown).

[0094] For example, the optical element may include a camera, enabling the display device 100 to perform various functions such as taking pictures, recording videos, or facial recognition.

[0095] Optical components may also include sensors. For example, optical components may include under-display fingerprint sensors, enabling display devices to perform functions such as fingerprint recognition. As another example, optical components may include infrared sensors.

[0096] The display panel 10 described above will be described in detail below.

[0097] In some embodiments, referring to FIG2, the display panel 10 includes a display section 11. The display section 11 of the display panel 10 has an image display function.

[0098] For example, please continue to refer to FIG2, the display section 11 of the display panel 10 can be a rectangular structure.

[0099] It should be noted that the aforementioned "rectangular structure" refers to the fact that the boundary of the display portion 11 of the display panel 10 is generally rectangular, but it is not limited to a standard rectangle. That is, the "rectangle" here includes not only the shape of a standard rectangle, but also shapes similar to rectangles, taking into account manufacturing conditions. For example, as shown in Figure 2, the long and short sides of the rectangle are curved at each intersection point (i.e., at the corner G), that is, the corner G is smooth, so that the boundary of the display portion 11 of the display panel 10 is a rounded rectangle in the plan view.

[0100] Alternatively, the display portion 11 of the display panel 10 may also be a circular structure or other shapes with corners.

[0101] The following describes some embodiments of the present disclosure using the example of a rectangular structure for the display portion 11 of the display panel 10. However, the embodiments of the present disclosure include, but are not limited to, this, and the shape of the display portion 11 of the display panel 10 can also be any other shape.

[0102] In some embodiments, referring to FIG2, the display panel 10 further includes a mounting portion 12. The mounting portion 12 of the display panel 10 can be connected to one side of the display portion 11 of the display panel 10.

[0103] For example, please continue to refer to FIG2. The driver chip 20 in the display device 100 can be encapsulated by means of chip on film (COF), chip on glass (COG), and chip on flexible material (COP), and bonded to the bonding part 12 of the display panel 10.

[0104] For example, the driver chip 20 within the display device 100 can be encapsulated using a chip-on-film (COF) package. When the driver chip 20 within the display device 100 is encapsulated using a COF package, the display device 100 includes a COF assembly, which may include a flexible printed circuit (FPC) and the driver chip 20 bonded to the FPC.

[0105] For example, please continue to refer to FIG2, the binding part 12 of the display panel 10 can be bent to the non-light-emitting side of the display panel 10.

[0106] It should be noted that the light-emitting side 10a of the display panel 10 refers to the side of the display panel 10 where the image can be displayed. The aforementioned "non-light-emitting side of the display panel 10" refers to the side opposite to the light-emitting side 10a of the display panel 10.

[0107] It is understandable that when the bonding portion 12 of the display panel 10 is bent to the non-light-emitting side of the display panel 10, the driver chip 20 bonded to the bonding portion 12 of the display panel 10 is also located on the non-light-emitting side of the display panel 10.

[0108] By bending the binding portion 12 of the display panel 10 to the non-light-emitting side of the display panel 10, the bezel of the display panel 10 can be reduced, which is beneficial for making the display panel 10 narrower.

[0109] The display section 11 of the above-mentioned display panel 10 will be described in detail below.

[0110] In some embodiments, please continue to refer to FIG2, the display portion 11 of the display panel 10 has a display area AA for displaying images and a peripheral area AN located on at least one side of the display area AA.

[0111] For example, the peripheral area AN of the display unit 11 may be located on one side of the display area AA of the display unit 11.

[0112] Alternatively, the peripheral area AN of the display unit 11 may be located on opposite sides of the display area AA of the display unit 11.

[0113] Alternatively, please continue to refer to Figure 2, the peripheral area AN of the display unit 11 can surround the display area AA of the display unit 11.

[0114] It should be noted that the specific arrangement of the peripheral area AN within the display section 11 of the display panel 10 is related to the specific design of the display panel 10 and can be designed according to actual needs. The following uses the example of the peripheral area AN of the display section 11 surrounding the display area AA of the display section 11 to illustrate some embodiments of this disclosure.

[0115] For example, referring to FIG2, when the peripheral area AN of the display unit 11 surrounds the display area AA of the display unit 11, the peripheral area AN of the display unit 11 may include a first border area B1, a second border area B2, a third border area B3, and a fourth border area B4. The first border area B1 and the second border area B2 may be disposed on both sides of the display area AA along the first direction X, and the third border area B3 and the fourth border area B4 may be disposed on both sides of the display area AA along the second direction Y.

[0116] The mounting portion 12 of the display panel 10 may be disposed close to the fourth border area B4 within the peripheral area AN of the display unit 11. That is, the fourth border area B4 within the peripheral area AN of the display unit 11 is close to the mounting side of the display panel 10.

[0117] For example, a gate driving circuit (e.g., Gate driver On Array, or GOA) and control signal lines (e.g., clock signal lines, power supply voltage signal lines, etc.) may be provided in the peripheral area AN within the display section 11 of the display panel 10. However, the function of the peripheral area AN within the display section 11 of the display panel 10 includes, but is not limited to, these.

[0118] In some embodiments, please continue to refer to FIG2. In order to realize the image display function of the display section 11 of the display panel 10, a plurality of sub-pixels 9 are provided in the display area AA of the display section 11 of the display panel 10. The sub-pixel 9 is the smallest light-emitting unit in the display area AA.

[0119] For example, multiple sub-pixels 9 within the display area AA of the display unit 11 can emit light of the same color, and the display unit 11 of the display panel 10 may further include a color filter layer disposed on the light-emitting side of the multiple sub-pixels 9. For example, the multiple sub-pixels 9 may emit light of colors such as white, red, green, or blue. In this case, the colored light emitted by the sub-pixels 9 may remain the same color after passing through the color filter layer, or be converted into other colors and emitted. Thus, when the multiple sub-pixels 9 emit light of the same color, the display unit 11 of the display panel 10 can achieve multi-color light emission.

[0120] Alternatively, multiple sub-pixels 9 within the display area AA of the display unit 11 emit light of different colors. For example, the multiple sub-pixels 9 include a red sub-pixel that emits red light, a green sub-pixel that emits green light, and a blue sub-pixel that emits blue light, so that the display unit 11 of the display panel 10 can achieve multi-color light emission.

[0121] For example, please continue to refer to FIG2, the multiple sub-pixels 9 in the display area AA of the display unit 11 can be arranged in an array.

[0122] For example, referring to Figure 2, multiple sub-pixels 9 in the display area AA of the display panel 10 can be arranged at intervals along the first direction X and the second direction Y, respectively.

[0123] The following provides a detailed explanation of sub-pixel 9.

[0124] In some embodiments, as shown in FIG3, FIG3 is a cross-sectional view of the display panel 10 in FIG2 along section line BB. The sub-pixels 9 within the display panel 10 include light-emitting devices F.

[0125] For example, referring to FIG3, when the display device 100 is an organic light-emitting diode (OLED) display device, the display panel 10 within the display device 100 is an organic light-emitting diode (OLED) display panel, and the light-emitting device F in the sub-pixel 9 within the display panel 10 may include a first electrode 311, a light-emitting part 331, and a second electrode 321. The first electrode 311, the light-emitting part 331, and the second electrode 321 are sequentially stacked along the third direction Z (i.e., the thickness direction of the display device 100).

[0126] For example, one of the first electrode 311 and the second electrode 321 can serve as the anode of the light-emitting device F, and the other can serve as the cathode of the light-emitting device F.

[0127] For example, the first electrode 311 can serve as the anode of the light-emitting device F. The first electrode 311 is configured to inject holes into the light-emitting portion 331. The second electrode 321 can serve as the cathode of the light-emitting device F. The second electrode 321 is configured to inject electrons into the light-emitting portion 331. In some examples, when the second electrode 321 serves as the cathode of the light-emitting device F, the second electrodes 321 of multiple light-emitting devices F can be interconnected to form a continuous film structure.

[0128] The following uses the first electrode 311 as the anode of the light-emitting device F and the second electrode 321 as the cathode of the light-emitting device F as an example to illustrate some embodiments of this disclosure.

[0129] For example, the material used to form the first electrode 311 may include metallic materials, such as any one or more of magnesium (Mg), silver (Ag), copper (Cu), aluminum (Al), titanium (Ti) and molybdenum (Mo).

[0130] The material used to form the first electrode 311 may also include alloys of the aforementioned metallic materials, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb).

[0131] For example, the first electrode 311 may be a single-layer structure.

[0132] Alternatively, the first electrode 311 can also be a multilayer composite structure. For example, the first electrode 311 can be a Ti / Al / Ti structure, etc. Another example is that the first electrode 311 can be a stacked structure formed of metallic materials and transparent conductive materials, such as ITO / Ag / ITO, Mo / AlNd / ITO, etc.

[0133] For example, the material used to form the second electrode 321 may include any one or more of magnesium (Mg), silver (Ag), aluminum (Al), etc.

[0134] The material used to form the second electrode 321 may also include alloys made of any one or more of magnesium (Mg), silver (Ag), aluminum (Al), etc.

[0135] The material used to form the second electrode 321 may also include a transparent conductive material, such as indium tin oxide (ITO).

[0136] In some embodiments, as shown in FIG4, FIG4 is an equivalent circuit diagram of pixel circuit 9a according to some embodiments. Sub-pixels 9 within the display panel 10 also include pixel circuit 9a. Pixel circuit 9a and light-emitting device F within sub-pixels 9 are electrically connected. Pixel circuit 9a can generate a driving signal (e.g., driving current), and light-emitting device F can emit light under the driving action of the driving signal generated by pixel circuit 9a.

[0137] For example, a pixel circuit 9a may be electrically connected to a light-emitting device F; or, a pixel circuit 9a may be electrically connected to multiple light-emitting devices F.

[0138] For example, please continue to refer to FIG2 and in conjunction with FIG4. Since the sub-pixels 9 in the display area AA of the display section 11 of the display panel 10 include pixel circuits 9a, when the multiple sub-pixels 9 in the display area AA are arranged in an array, the multiple pixel circuits 9a in the multiple sub-pixels 9 can also be arranged in an array.

[0139] For example, multiple pixel circuits 9a within multiple sub-pixels 9 can be arranged at intervals along the first direction X and the second direction Y, respectively.

[0140] When multiple pixel circuits 9a within multiple sub-pixels 9 are arranged at intervals along a first direction X and a second direction Y, the first direction X can be the row direction in which the multiple pixel circuits 9a are arranged, and the second direction Y can be the column direction in which the multiple pixel circuits 9a are arranged.

[0141] In some embodiments, please continue to refer to FIG4, the pixel circuit 9a within the sub-pixel 9 can be an 8T1C structure.

[0142] Alternatively, the pixel circuit 9a within sub-pixel 9 can also be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, or 7T1C structure. Here, T represents a transistor, and the number preceding T indicates the number of transistors; C represents a capacitor, and the number preceding C indicates the number of capacitors.

[0143] The following uses an 8T1C structure for the pixel circuit 9a within sub-pixel 9 as an example to illustrate some embodiments of this disclosure. However, the structure of the pixel circuit 9a within sub-pixel 9 in this disclosure is not limited to this.

[0144] Please continue to refer to Figure 4. When the pixel circuit 9a in the sub-pixel 9 is an 8T1C structure, the pixel circuit 9a may include 8 transistors (i.e., the first reset transistor T1, the threshold compensation transistor T2, the driving transistor T3, the data writing transistor T4, the first light-emitting control transistor T5, the second light-emitting control transistor T6, the second reset transistor T7, and the third reset transistor T8) and 1 storage capacitor C.

[0145] For example, transistors T1 to T8 (i.e., first reset transistor T1, threshold compensation transistor T2, driving transistor T3, data writing transistor T4, first light emission control transistor T5, second light emission control transistor T6, second reset transistor T7 and third reset transistor T8) in pixel circuit 9a can be P-type transistors.

[0146] Alternatively, transistors T1 to T8 in pixel circuit 9a (i.e., first reset transistor T1, threshold compensation transistor T2, driving transistor T3, data writing transistor T4, first light-emitting control transistor T5, second light-emitting control transistor T6, second reset transistor T7, and third reset transistor T8) can also be N-type transistors.

[0147] For example, the transistors in the pixel circuit 9a can be of the same type. For instance, transistors T1 through T8 in the pixel circuit 9a (i.e., the first reset transistor T1, the threshold compensation transistor T2, the driving transistor T3, the data writing transistor T4, the first light-emitting control transistor T5, the second light-emitting control transistor T6, the second reset transistor T7, and the third reset transistor T8) can all be P-type transistors or all N-type transistors. Using the same type of transistors in the pixel circuit 9a simplifies the manufacturing process, reduces the difficulty of fabricating the display panel 10, and improves the yield of the display panel 10.

[0148] Alternatively, the transistors in pixel circuit 9a can be of different types. That is, transistors T1 through T8 (i.e., first reset transistor T1, threshold compensation transistor T2, drive transistor T3, data write transistor T4, first light-emitting control transistor T5, second light-emitting control transistor T6, second reset transistor T7, and third reset transistor T8) can include P-type transistors and N-type transistors. For example, transistor T2 (i.e., threshold compensation transistor T2) is an N-type transistor, while the remaining transistors (i.e., first reset transistor T1, drive transistor T3, data write transistor T4, first light-emitting control transistor T5, second light-emitting control transistor T6, second reset transistor T7, and third reset transistor T8) are P-type transistors.

[0149] The following describes some embodiments of this disclosure using the example of transistor T2 (i.e., threshold compensation transistor T2) in pixel circuit 9a as an N-type transistor and the other transistors (i.e., first reset transistor T1, driving transistor T3, data writing transistor T4, first light-emitting control transistor T5, second light-emitting control transistor T6, second reset transistor T7, and third reset transistor T8) as P-type transistors.

[0150] For example, transistors T1 to T8 in the pixel circuit 9a (i.e., the first reset transistor T1, the threshold compensation transistor T2, the driving transistor T3, the data writing transistor T4, the first light-emitting control transistor T5, the second light-emitting control transistor T6, the second reset transistor T7, and the third reset transistor T8) can be top-gate transistors, bottom-gate transistors, or dual-gate transistors. A dual-gate transistor includes an active layer pattern and top-gate and bottom-gate patterns disposed on either side of the active layer pattern. By driving the active layer pattern through the top-gate and bottom-gate patterns, the threshold voltage can be controlled more easily; simultaneously, carrier mobility can be improved. That is, compared to top-gate and bottom-gate transistors, dual-gate transistors offer higher stability.

[0151] For example, transistors T1 to T8 (i.e., first reset transistor T1, threshold compensation transistor T2, driving transistor T3, data writing transistor T4, first light-emitting control transistor T5, second light-emitting control transistor T6, second reset transistor T7, and third reset transistor T8) in pixel circuit 9a can be low-temperature polycrystalline silicon (LTPS) thin-film transistors (LTPS), oxide thin-film transistors (OPTs), or a combination of both. The active layer of the LTPS LTPS is made of low-temperature polycrystalline silicon, while the active layer of the OPT is made of oxide. LTPS LTPS has advantages such as high mobility and fast charging, while OPTs have advantages such as low leakage current. Integrating LTPS LTPS and OPTs onto a single display panel 10 forms a low-temperature polycrystalline oxide (LTPO) display panel. Utilizing the advantages of both, the refresh rate of the display panel 10 can be switched to achieve low-frequency driving, which helps reduce power consumption and improve display quality.

[0152] In some embodiments, referring to FIG4, the pixel circuit 9a may further include a first node N1, a second node N2, a third node N3, and a fourth node N4. It should be noted that in the pixel circuit 9a provided in this embodiment, nodes do not represent actual existing components, but rather represent the junction points of related electrical connections in the equivalent circuit diagram of the pixel circuit 9a. In other words, these nodes are equivalent to the junction points of related electrical connections in the equivalent circuit diagram of the pixel circuit 9a.

[0153] The first node N1 is connected to the gate of the driving transistor T3, the first plate of the storage capacitor C, and the source of the threshold compensation transistor T2. The second node N2 is connected to the source of the driving transistor T3, the drain of the first light-emitting control transistor T5, the drain of the data writing transistor T4, and the drain of the third reset transistor T8. The third node N3 is connected to the drain of the first reset transistor T1, the source of the threshold compensation transistor T2, the source of the second light-emitting control transistor T6, and the drain of the driving transistor T3. The fourth node N4 is connected to the drain of the second light-emitting control transistor T6, the drain of the second reset transistor T7, and the light-emitting device F.

[0154] The second plate of the storage capacitor C is electrically connected to the first voltage signal line VDD, and the first plate of the storage capacitor C is connected to the first node N1, that is, the first plate of the storage capacitor C is connected to the gate of the driving transistor T3.

[0155] The source of the first reset transistor T1 is configured to receive the first initialization signal Vinit1, the drain of the first reset transistor T1 is electrically connected to the drain of the driving transistor T3, and the gate of the first reset transistor T1 is configured to be electrically connected to the first reset control signal line Reset1 to receive the reset control signal.

[0156] The source of threshold compensation transistor T2 is electrically connected to the gate of driving transistor T3, the drain of threshold compensation transistor T2 is electrically connected to the drain of driving transistor T3, and the gate of threshold compensation transistor T2 is configured to be electrically connected to the first scan signal line Ngate to receive the compensation control signal.

[0157] The gate of driving transistor T3 is connected to the first plate of storage capacitor C, the source of driving transistor T3 is connected to the second node N2, and the drain of driving transistor T3 is connected to the third node N3. Driving transistor T3 determines the magnitude of the driving current flowing between the first voltage signal line VDD and the second voltage signal line VSS based on the potential difference between its gate and source.

[0158] The drain of the data writing transistor T4 is electrically connected to the source of the driving transistor T3. The source of the data writing transistor T4 is configured to be electrically connected to the data signal line Data to receive the data signal. The gate of the data writing transistor T4 is configured to be electrically connected to the second scan signal line Pgate to receive the scan signal.

[0159] The source of the first light-emitting control transistor T5 is electrically connected to the first voltage signal line VDD, the drain of the first light-emitting control transistor T5 is electrically connected to the source of the driving transistor T3, and the gate of the first light-emitting control transistor T5 is configured to be electrically connected to the light-emitting control signal line EM to receive the light-emitting control signal.

[0160] The source of the second light-emitting control transistor T6 is electrically connected to the drain of the driving transistor T3, the drain of the second light-emitting control transistor T6 is electrically connected to the first electrode of the light-emitting device F, and the gate of the second light-emitting control transistor T6 is configured to be electrically connected to the light-emitting control signal line EM to receive the light-emitting control signal.

[0161] The source of the second reset transistor T7 is configured to receive the second initialization signal Vinit2, the drain of the second reset transistor T7 is electrically connected to the first electrode of the light-emitting device F, and the gate of the second reset transistor T7 is configured to be electrically connected to the second reset control signal line Reset2 to receive the reset control signal.

[0162] The source of the third reset transistor T8 is configured to receive the third initialization signal Vinit3, the drain of the third reset transistor T8 is electrically connected to the source of the driving transistor T3, and the gate of the third reset transistor T8 is configured to be connected to the second reset control signal line Reset2 to receive the reset control signal.

[0163] The second electrode of the light-emitting device F is electrically connected to the second voltage signal line VSS.

[0164] Among them, the first scan signal line Ngate is used to transmit the first scan signal, the second scan signal line Pgate is used to transmit the second scan signal, the first reset control signal line Reset1 is used to transmit the first reset control signal, the second reset control signal line Reset2 is used to transmit the second reset control signal, the first voltage signal line VDD is used to transmit the first voltage signal, such as a high voltage DC signal, the data signal line Data is used to transmit the data signal, the light emission control signal line EM is used to transmit the light emission control signal, and the second voltage signal line VSS is used to transmit the second voltage signal, such as a low voltage DC signal.

[0165] In some embodiments, please continue to refer to FIG4. The driving process of the pixel circuit 9a in the sub-pixel 9 driving the light-emitting device F in the sub-pixel 9 to emit light may include a first reset stage t1, a data refresh and compensation stage t2, a second reset stage t3, and an emission stage t4.

[0166] In the first reset phase t1, the threshold compensation transistor T2 is turned on under the control of the first scan signal transmitted on the first scan signal line Ngate, and the first reset transistor T1 is turned on under the control of the first reset control signal transmitted on the first reset control signal line Reset1, so that the first initialization signal Vinit1 is written to the first node N1, thereby resetting the first node N1.

[0167] At this time, the driving transistor T3 is turned on, while the writing transistor T4, the first light-emitting control transistor T5, and the second light-emitting control transistor T6 are all turned off, and the light-emitting device F does not emit light.

[0168] During the data refresh and compensation phase t2, the first reset transistor T1 is turned off under the control of the first reset control signal transmitted via the first reset control signal line Reset1. The threshold compensation transistor T2 remains on, and the write transistor T4 is turned on under the control of the second scan signal transmitted via the second scan signal line Pgate. The drive transistor T3 remains on during the first reset phase t1. Therefore, the data signal transmitted via the data signal line Data can be transmitted sequentially through the write transistor T4, the drive transistor T3, and the threshold compensation transistor T2 to the first node N1, causing the voltage of the first node N1 to change until the voltage of the first node N1 reaches the sum of the threshold voltage of the drive transistor T3 and the voltage of the data signal line Data, causing the drive transistor T3 to turn off. During the data refresh and compensation phase t2, the threshold voltage of the drive transistor T3 can be written to the first node N1 to compensate for the threshold voltage drift of the drive transistor T3, preventing changes in the drive signal generated by the drive transistor T3 and avoiding any impact on the luminous intensity of the light-emitting device F. During this phase, the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are turned off under the control of the light-emitting control signal transmitted via the light-emitting control signal line EM.

[0169] In the second reset phase t3, the compensation transistor T2 is turned off under the control of the first scan signal transmitted through the first scan signal line Ngate, the write transistor T4 is turned off under the control of the second scan signal transmitted through the second scan signal line Pgate, and the second reset transistor T7 and the third reset transistor T8 are turned on under the control of the second reset control signal transmitted through the second reset control signal line Reset2. This causes the second initialization signal Vinit2 to be written to the anode of the light-emitting device F, and the third initialization signal Vinit3 to be written to the second node N2, thereby resetting the second node N2 and the anode of the light-emitting device F (i.e., the fourth node N4).

[0170] During the light-emitting stage t4, the second reset transistor T7 and the third reset transistor T8 are disconnected under the control of the second reset control signal transmitted by the second reset control signal line Reset2. The first light-emitting control transistor T5 and the second light-emitting control transistor T6 are turned on under the control of the light-emitting control signal transmitted by the light-emitting control signal line EM. This causes the first voltage signal transmitted by the first voltage signal line VDD to be written to the source of the driving transistor T3. The anode voltage of the light-emitting device F can be written to the drain of the driving transistor T3, thereby turning on the driving transistor T3. This forms a path between the first voltage signal line VDD and the light-emitting device F, causing the light-emitting device F in the sub-pixel 9 to emit light.

[0171] The sub-pixels 9 (i.e., the light-emitting devices F and pixel circuits 9a in the sub-pixels 9) in the above-mentioned display panel 10 can be disposed in the film layer structure of the display panel 10. The film layer structure of the display panel 10 will be described in detail below.

[0172] In some embodiments, please continue to refer to FIG3, the display panel 10 includes a substrate 1.

[0173] For example, substrate 1 can be a rigid substrate. For instance, substrate 1 can be a glass substrate or a polymethyl methacrylate (PMMA) substrate, etc.

[0174] Alternatively, substrate 1 can also be a flexible substrate. For example, substrate 1 can be a polyethylene terephthalate (PET) substrate, a polyethylene naphthalate (PEN) substrate, or a polyimide (PI) substrate, etc.

[0175] In some embodiments, referring to FIG3, the display panel 10 further includes a pixel driving layer 2 and a light-emitting device layer 3. The pixel driving layer 2 and the light-emitting device layer 3 are located on one side of the substrate 1 and are stacked sequentially in a direction away from the substrate 1. The light-emitting device layer 3 is used to set the light-emitting devices F in a plurality of sub-pixels 9 within the display panel 10. The pixel driving layer 2 is used to set the pixel circuits 9a in a plurality of sub-pixels 9 within the display panel 10. The specific structure of the pixel driving layer 2 will be described in detail below.

[0176] For example, referring to FIG3, the light-emitting device layer 3 includes a first electrode layer 31, a light-emitting functional layer 33, and a second electrode layer 32, which are sequentially stacked along the third direction Z (i.e., the thickness direction of the display device 100). The first electrode layer 31 is used to provide the first electrode 311 of the light-emitting device F in the sub-pixel 9, the light-emitting functional layer 33 is used to provide the light-emitting part 331 of the light-emitting device F in the sub-pixel 9, and the second electrode layer 32 is used to provide the second electrode 321 of the light-emitting device F in the sub-pixel 9.

[0177] The first electrode layer 31 and the second electrode layer 32 can provide charge carriers such as electrons and holes to the light-emitting functional layer 33, so that the light-emitting functional layer 33 emits light. Specifically, the first electrode 311 in the first electrode layer 31 and the second electrode 321 in the second electrode layer 32 can provide charge carriers such as electrons and holes to the light-emitting part 331 in the light-emitting functional layer 33, so that the light-emitting part 331 in the light-emitting functional layer 33 emits light.

[0178] For example, please continue to refer to FIG3, the first electrode layer 31 may be closer to the substrate 1 than the second electrode layer 32.

[0179] In some embodiments, please continue to refer to FIG3 and in conjunction with FIG5, FIG5 being a plan view of a partial area of ​​a pixel definition layer (PDL) 4 in a display panel 10 according to some embodiments. The display panel 10 further includes a pixel definition layer (PDL) 4. The pixel definition layer (PDL) 4 is located on the side of the first electrode layer 31 away from the substrate 1. A plurality of pixel openings K are formed in the pixel definition layer (PDL) 4, and the pixel openings K are correspondingly disposed with respect to the first electrodes 311 in the first electrode layer 31, with each pixel opening K exposing at least a portion of a first electrode 311. The light-emitting portion 331 in the light-emitting functional layer 33 is disposed in the pixel opening K and is electrically connected to the first electrode 311 and the second electrode 321, respectively.

[0180] By exposing at least a portion of a first electrode 311 through each pixel opening K, the pixel definition layer (PDL) 4 can effectively define the actual effective area of ​​the first electrode 311 (i.e., the area where the first electrode 311 is directly electrically connected to the light-emitting part 331 in the light-emitting functional layer 33), thereby defining the light-emitting area and light-emitting region of the light-emitting device F.

[0181] In some embodiments, referring to FIG3, the display panel 10 further includes an encapsulation structure 5. The encapsulation structure 5 is located on the side of the light-emitting device layer 3 away from the substrate 1. The encapsulation structure 5 is used to encapsulate the light-emitting device layer 3, thereby protecting the light-emitting device layer 3 from corrosion caused by external water and oxygen.

[0182] For example, the encapsulation structure 5 may include an inorganic encapsulation layer and an organic encapsulation layer. The inorganic encapsulation layer is made of an inorganic material and can be used to block water and oxygen. The organic encapsulation layer is made of an organic material and can serve to flatten interfaces, cover defects, and relieve stress.

[0183] The structure of the pixel driving layer 2 described above will be explained in detail below.

[0184] In some embodiments, as shown in FIG6A, FIG6A is a planar structural view of a partial region of the pixel driving layer 2 in a display panel 10 according to some embodiments. The pixel driving layer 2 in the display panel 10 includes a first semiconductor layer 21, a first conductive layer 22, a second conductive layer 23, a second semiconductor layer 24, a third conductive layer 25, a fourth conductive layer 26, and a fifth conductive layer 27. The first semiconductor layer 21, the first conductive layer 22, the second conductive layer 23, the second semiconductor layer 24, the third conductive layer 25, the fourth conductive layer 26, and the fifth conductive layer 27 in the pixel driving layer 2 are stacked sequentially in a direction away from the substrate 1. That is, the first semiconductor layer 21 is closer to the substrate 1 than the fifth conductive layer 27.

[0185] It should be noted that, for the purpose of explaining the embodiment shown in FIG6A, the first conductive layer 22, the second conductive layer 23, the second semiconductor layer 24, the third conductive layer 25, the fourth conductive layer 26, and the fifth conductive layer 27 in FIG6A are made transparent to expose the other film layers (including at least the first semiconductor layer 21, the first conductive layer 22, the second conductive layer 23, the second semiconductor layer 24, the third conductive layer 25, and the fourth conductive layer 26) in the pixel driving layer 2 within the display panel 10, located on the side of the fifth conductive layer 27 near the substrate 1.

[0186] Figure 6A only shows the first semiconductor layer 21, the first conductive layer 22, the second conductive layer 23, the second semiconductor layer 24, the third conductive layer 25, the fourth conductive layer 26, and the fifth conductive layer 27 in the pixel driving layer 2, omitting other film layers in the pixel driving layer 2. For example, Figure 6A omits the insulating layer between two adjacent film layers in the first semiconductor layer 21, the first conductive layer 22, the second conductive layer 23, the second semiconductor layer 24, the third conductive layer 25, the fourth conductive layer 26, and the fifth conductive layer 27, as well as the bottom shielding metal (BSM) layer located on the side of the first semiconductor layer 21 near the substrate 1.

[0187] In some embodiments, as shown in FIG6B and in conjunction with FIG6A, FIG6B is a planar structural view of a partial region of the first semiconductor layer 21 in the pixel driving layer 2 within the display panel 10 according to some embodiments. The first semiconductor layer 21 in the pixel driving layer 2 is located on the side of the second conductive layer 23 in the pixel driving layer 2 closer to the substrate 1.

[0188] Please continue to refer to Figure 6B. The first semiconductor layer 21 in the pixel driving layer 2 can be used to set the active layer pattern of at least some of the transistors in the pixel circuit 9a, namely the first reset transistor T1, the threshold compensation transistor T2, the driving transistor T3, the data writing transistor T4, the first light-emitting control transistor T5, the second light-emitting control transistor T6, the second reset transistor T7, and the third reset transistor T8.

[0189] The active layer patterns of transistors T1 to T8 (i.e., first reset transistor T1, threshold compensation transistor T2, driving transistor T3, data writing transistor T4, first light-emitting control transistor T5, second light-emitting control transistor T6, second reset transistor T7, and third reset transistor T8) in pixel circuit 9a can all include source region, drain region, and channel region located between source region and drain region.

[0190] For example, referring to FIG6B, the first semiconductor layer 21 may be provided with an active layer pattern T11 of the first reset transistor T1, an active layer pattern T31 of the driving transistor T3, an active layer pattern T41 of the data writing transistor T4, an active layer pattern T51 of the first light-emitting control transistor T5, an active layer pattern T61 of the second light-emitting control transistor T6, an active layer pattern T71 of the second reset transistor T7, and an active layer pattern T81 of the third reset transistor T8.

[0191] Please refer to Figure 6B. Taking the active layer pattern T11 of the first reset transistor T1, the active layer pattern T51 of the first light-emitting control transistor T5, and the active layer pattern T81 of the third reset transistor T8 as examples, the active layer pattern T11 of the first reset transistor T1 may include a source region T11a, a drain region T11b, and a channel region T11c located between the source region T11a and the drain region T11b. The active layer pattern T51 of the first light-emitting control transistor T5 may include a source region T51a, a drain region T51b, and a channel region T51c located between the source region T51a and the drain region T51b. The active layer pattern T81 of the third reset transistor T8 may include a source region T81a, a drain region T81b, and a channel region T81c located between the source region T81a and the drain region T81b.

[0192] For example, please continue to refer to FIG6B, the active layer pattern T51 of the first light-emitting control transistor T5 includes a main body T511 extending along the second direction Y (i.e., the column direction in which the plurality of pixel circuits 9a are arranged).

[0193] For example, the material of the first semiconductor layer 21 may be low-temperature polycrystalline silicon.

[0194] Alternatively, the material of the first semiconductor layer 21 can be either indium gallium zinc oxide or a low-temperature polycrystalline oxide. For example, the material of the first semiconductor layer 21 can be indium gallium zinc oxide (IGZO). Another example is that the material of the first semiconductor layer 21 can be indium gallium zinc tin oxide (IGZTO).

[0195] It is understandable that when the material of the first semiconductor layer 21 is low-temperature polycrystalline silicon, the transistors with active layer patterns located on the first semiconductor layer 21 (e.g., the first reset transistor T1, the driving transistor T3, the data writing transistor T4, the first light-emitting control transistor T5, the second light-emitting control transistor T6, the second reset transistor T7, and the third reset transistor T8) are low-temperature polycrystalline silicon thin-film transistors.

[0196] When the material of the first semiconductor layer 21 is either indium gallium zinc oxide or low-temperature polycrystalline oxide, the transistors with active layer patterns located on the first semiconductor layer 21 (e.g., the first reset transistor T1, the driving transistor T3, the data writing transistor T4, the first light-emitting control transistor T5, the second light-emitting control transistor T6, the second reset transistor T7, and the third reset transistor T8) are oxide thin-film transistors.

[0197] The following describes some embodiments of this disclosure using the example of a low-temperature polycrystalline silicon (LTPS) material for the first semiconductor layer 21 and a low-temperature polycrystalline silicon thin-film transistor (LTPS) whose active layer pattern is located on the first semiconductor layer 21.

[0198] For example, the first semiconductor layer 21 can be obtained using an excimer laser annealing process.

[0199] Alternatively, the first semiconductor layer 21 can also be obtained using a physical vapor deposition (PVD) process.

[0200] In some embodiments, as shown in FIG6C and in conjunction with FIG6A, FIG6C is a planar structural view of a partial region of the first conductive layer 22 in the pixel driving layer 2 within the display panel 10 according to some embodiments. The first conductive layer 22 within the pixel driving layer 2 is located on the side of the second conductive layer 23 within the pixel driving layer 2 closer to the substrate 1.

[0201] For example, the first conductive layer 22 within the pixel driving layer 2 can be a first gate layer.

[0202] For example, the first conductive layer 22 can be obtained by depositing metallic materials such as MO / Ti / Al / Cu (molybdenum / titanium / aluminum / copper) using a PVD process.

[0203] Please refer to Figure 6C. The first conductive layer 22 in the pixel driving layer 2 can be used to set the gate pattern of at least some of the transistors in the pixel circuit 9a, including transistors T1 to T8 (i.e., first reset transistor T1, threshold compensation transistor T2, driving transistor T3, data writing transistor T4, first light-emitting control transistor T5, second light-emitting control transistor T6, second reset transistor T7 and third reset transistor T8), storage capacitor C, and signal lines.

[0204] For example, referring to FIG6C, the first conductive layer 22 may be provided with the gate pattern T12 of the first reset transistor T1, the gate pattern T32 of the driving transistor T3, the gate pattern T42 of the data writing transistor T4, the gate pattern T52 of the first light-emitting control transistor T5, the gate pattern T62 of the second light-emitting control transistor T6, the gate pattern T72 of the second reset transistor T7, and the gate pattern T82 of the third reset transistor T8.

[0205] Please refer to FIG6C and FIG6D, which is a planar structural diagram of a partial region of the first semiconductor layer 21 and the first conductive layer 22 in the pixel driving layer 2 of the display panel 10 according to some embodiments. It should be noted that, for the convenience of explaining the embodiment shown in FIG6D, the first conductive layer 22 in FIG6D is made transparent to expose the first semiconductor layer 21 in the pixel driving layer 2 of the display panel 10.

[0206] The gate patterns of the transistors (i.e., the first reset transistor T1, the driving transistor T3, the data writing transistor T4, the first light-emitting control transistor T5, the second light-emitting control transistor T6, the second reset transistor T7, and the third reset transistor T8) in the first conductive layer 22 are correspondingly arranged with the channel regions of the active layer patterns of the transistors (i.e., the first reset transistor T1, the driving transistor T3, the data writing transistor T4, the first light-emitting control transistor T5, the second light-emitting control transistor T6, the second reset transistor T7, and the third reset transistor T8) in the first semiconductor layer 21.

[0207] Taking the first reset transistor T1 as an example, the gate pattern T12 of the first reset transistor T1 in the first conductive layer 22 and the channel region T11c in the active layer pattern T11 of the first reset transistor T1 in the first semiconductor layer 21 are correspondingly arranged, that is, the orthographic projection of the gate pattern T12 of the first reset transistor T1 on the substrate 1 and the orthographic projection of the channel region T11c in the active layer pattern T11 of the first reset transistor T1 on the substrate 1 coincide.

[0208] For example, please continue to refer to Figure 6C, the first conductive layer 22 may also be provided with a second scan signal line Pgate, a first reset control signal line Reset1, a second reset control signal line Reset2, and a light emission control signal line EM, etc.

[0209] For example, if a second scan signal line Pgate, a first reset control signal line Reset1, a second reset control signal line Reset2, and a light emission control signal line EM are provided in the first conductive layer 22, the second scan signal line Pgate, the first reset control signal line Reset1, the second reset control signal line Reset2, and the light emission control signal line EM in the first conductive layer 22 can all extend along the first direction X (i.e., the row direction in which the multiple pixel circuits 9a are arranged).

[0210] For example, referring to FIG6C, the first electrode C1 of the storage capacitor C may also be disposed within the first conductive layer 22. In some examples, the gate pattern T32 of the driving transistor T3 also serves as the first electrode C1 of the storage capacitor C.

[0211] For example, please continue to refer to FIG6C. When the second reset control signal line Reset2, the light emission control signal line EM and the first plate C1 of the storage capacitor C are provided in the first conductive layer 22, the light emission control signal line EM can be located between the first plate C1 of the storage capacitor C and the second reset control signal line Reset2.

[0212] For example, referring to FIG6D, when a light-emitting control signal line EM is provided in the first conductive layer 22 and an active layer pattern T81 of the third reset transistor T8 is provided in the first semiconductor layer 21, the light-emitting control signal line EM and the active layer pattern T81 of the third reset transistor T8 can be spaced apart in the orthogonal projection onto the substrate 1. That is, there is no overlap between the light-emitting control signal line EM and the active layer pattern T81 of the third reset transistor T8 in the orthogonal projection onto the substrate 1.

[0213] In some embodiments, as shown in FIG6E and in conjunction with FIG6A, FIG6E is a planar structural view of a partial region of the second conductive layer 23 in the pixel driving layer 2 within the display panel 10 according to some embodiments. The second conductive layer 23 within the pixel driving layer 2 is located on the side of the fourth conductive layer 26 within the pixel driving layer 2 closer to the substrate 1.

[0214] For example, the second conductive layer 23 within the pixel driving layer 2 can be a second gate layer.

[0215] For example, the second conductive layer 23 within the pixel driving layer 2 can be obtained by depositing metallic materials such as MO / Ti / Al / Cu (molybdenum / titanium / aluminum / copper) using a PVD process.

[0216] Please refer to Figure 6E. The second conductive layer 23 within the pixel driving layer 2 can be used to set the storage capacitor C in the pixel circuit 9a, as well as signal lines, etc.

[0217] For example, please continue to refer to FIG6E, a first scan signal line Ngate may be provided in the second conductive layer 23.

[0218] For example, if a first scan signal line Ngate is provided in the second conductive layer 23, the first scan signal line Ngate in the second conductive layer 23 can extend along the first direction X (i.e., the row direction in which the multiple pixel circuits 9a are arranged).

[0219] For example, please continue to refer to Figure 6E, the second electrode C2 of the storage capacitor C may also be provided in the second conductive layer 23.

[0220] For example, as shown in Figures 6F and 6G, both Figures 6F and 6G are planar structural diagrams of a partial region of the second conductive layer 23 in the pixel driving layer 2 within a display panel 10 according to some embodiments. The second conductive layer 23 in the pixel driving layer 2 further includes a first connection portion 231.

[0221] The second plate C2 of the storage capacitor C of the multiple pixel circuits 9a includes multiple second plate pairs CD. A second plate pair CD includes two adjacent second plates C2 in the first direction X (i.e., the row direction in which the multiple pixel circuits 9a are arranged). The two second plates C2 belonging to a second plate pair CD are connected by a first connecting part 231.

[0222] For example, referring to FIG6F, two second plates C2 belonging to different second plate pairs CD and adjacent in the first direction X (i.e., the row direction in which the multiple pixel circuits 9a are arranged) can be spaced apart. That is, among the second plates C2 of the storage capacitors C in the multiple pixel circuits 9a arranged along the first direction X (i.e., the row direction in which the multiple pixel circuits 9a are arranged), there are two adjacent second plates C2 that are not connected through the first connection portion 231 in the second conductive layer 23.

[0223] Alternatively, referring to Figure 6G, two adjacent second plates C2 belonging to different second plate pairs CD and arranged in the first direction X (i.e., the row direction of the multiple pixel circuits 9a) can be connected by the first connecting portion 231. That is, among the second plates C2 of the storage capacitors C in the multiple pixel circuits 9a arranged along the first direction X (i.e., the row direction of the multiple pixel circuits 9a), any two adjacent second plates C2 are connected by the first connecting portion 231 in the second conductive layer 23. Among the second plates C2 of the storage capacitors C in the multiple pixel circuits 9a arranged along the first direction X (i.e., the row direction of the multiple pixel circuits 9a), there are no two adjacent and spaced-apart second plates C2.

[0224] The following describes some embodiments of the present disclosure using the example of two second plates C2 belonging to one second plate pair CD in the storage capacitor C of multiple pixel circuits 9a being connected by a first connecting part 231, and two second plates C2 belonging to different second plate pairs CD and adjacent in the first direction X (i.e., the row direction in which the multiple pixel circuits 9a are arranged) being spaced apart.

[0225] In some embodiments, as shown in FIG6H, FIG6H is a planar structural view of a partial region of the second semiconductor layer 24 in the pixel driving layer 2 within the display panel 10 according to some embodiments. The second semiconductor layer 24 within the pixel driving layer 2 can be used to set the active layer pattern of at least some of the transistors T1 to T8 (i.e., the first reset transistor T1, the threshold compensation transistor T2, the driving transistor T3, the data writing transistor T4, the first light-emitting control transistor T5, the second light-emitting control transistor T6, the second reset transistor T7, and the third reset transistor T8) in the pixel circuit 9a.

[0226] For example, referring to FIG6H, the second semiconductor layer 24 may have an active layer pattern T21 of a threshold compensation transistor T2. The active layer pattern T21 of the threshold compensation transistor T2 includes a source region T21a, a drain region T21b, and a channel region T21c located between the source region T21a and the drain region T21b.

[0227] For example, the material of the second semiconductor layer 24 can be low-temperature polycrystalline silicon.

[0228] Alternatively, the material of the second semiconductor layer 24 can also be either indium gallium zinc oxide or a low-temperature polycrystalline oxide. For example, the material of the second semiconductor layer 24 can be indium gallium zinc oxide (IGZO). Another example is that the material of the second semiconductor layer 24 can be indium gallium zinc tin oxide (IGZTO).

[0229] It is understandable that when the material of the second semiconductor layer 24 is low-temperature polycrystalline silicon, the transistor with the active layer pattern located on the second semiconductor layer 24 (e.g., threshold compensation transistor T2) is a low-temperature polycrystalline silicon thin-film transistor.

[0230] When the material of the second semiconductor layer 24 is either indium gallium zinc oxide or low-temperature polycrystalline oxide, the transistor with the active layer pattern located on the second semiconductor layer 24 (e.g., threshold compensation transistor T2) is an oxide thin-film transistor.

[0231] The following describes some embodiments of the present disclosure using the example of a transistor (e.g., a threshold compensation transistor T2) whose active layer pattern is located on the second semiconductor layer 24 and whose material is either indium gallium zinc oxide or low-temperature polycrystalline oxide, as well as an oxide thin-film transistor.

[0232] Understandably, referring to Figures 6B and 6H, if the material of the first semiconductor layer 21 is low-temperature polycrystalline silicon, and the transistors with active layer patterns on the first semiconductor layer 21 (e.g., the first reset transistor T1, the driving transistor T3, the data writing transistor T4, the first light-emitting control transistor T5, the second light-emitting control transistor T6, the second reset transistor T7, and the third reset transistor T8) are low-temperature polycrystalline silicon thin-film transistors, and the material of the second semiconductor layer 24 is either indium gallium zinc oxide or low-temperature polycrystalline oxide, and the transistors with active layer patterns on the second semiconductor layer 24 (e.g., the threshold compensation transistor T2) are oxide thin-film transistors, then the pixel circuit 9a in the display panel 10 includes both low-temperature polycrystalline silicon thin-film transistors and oxide thin-film transistors, thus forming a low-temperature polycrystalline oxide (LTPO) display panel.

[0233] For example, the second semiconductor layer 24 can be obtained using an excimer laser annealing process.

[0234] Alternatively, the second semiconductor layer 24 can also be obtained using a physical vapor deposition (PVD) process.

[0235] In some embodiments, as shown in FIG6I and in conjunction with FIG6A, FIG6I is a planar structural view of a partial region of the third conductive layer 25 in the pixel driving layer 2 within the display panel 10 according to some embodiments. The third conductive layer 25 in the pixel driving layer 2 is located between the fourth conductive layer 26 and the second conductive layer 23 in the pixel driving layer 2.

[0236] For example, the third conductive layer 25 within the pixel driving layer 2 can be a third gate layer.

[0237] For example, the third conductive layer 25 in the pixel driving layer 2 can be obtained by depositing metal materials such as MO / Ti / Al / Cu (molybdenum / titanium / aluminum / copper) using a physical vapor deposition (PVD) process.

[0238] Please continue to refer to Figure 6I. The third conductive layer 25 in the pixel driving layer 2 can be used to set the gate patterns of at least some of the transistors in the pixel circuit 9a, namely the first reset transistor T1, the threshold compensation transistor T2, the driving transistor T3, the data writing transistor T4, the first light-emitting control transistor T5, the second light-emitting control transistor T6, the second reset transistor T7, and the third reset transistor T8, as well as signal lines, etc.

[0239] For example, please continue to refer to FIG6I, the gate pattern T22 of the threshold compensation transistor T2 may be provided in the third conductive layer 25.

[0240] For example, referring to FIG6I, a plurality of auxiliary signal lines 25a may also be provided within the third conductive layer 25. The plurality of auxiliary signal lines 25a may include a first auxiliary signal line 251, a second auxiliary signal line 252, and a third auxiliary signal line 253. The first auxiliary signal line 251 is configured to transmit a first initialization signal Vinit1, the second auxiliary signal line 252 is configured to transmit a second initialization signal Vinit2, and the third auxiliary signal line 253 is configured to transmit a third initialization signal Vinit3.

[0241] For example, please continue to refer to FIG6I. When multiple auxiliary signal lines 25a are provided in the third conductive layer 25, the multiple auxiliary signal lines 25a in the third conductive layer 25 can extend along the first direction X (i.e., the row direction in which the multiple pixel circuits 9a are arranged).

[0242] In some embodiments, as shown in FIG6J and in conjunction with FIG6A, FIG6J is a planar structural view of a partial region of the fourth conductive layer 26 in the pixel driving layer 2 within a display panel 10 according to some embodiments. The fourth conductive layer 26 in the pixel driving layer 2 is located on the substrate 1.

[0243] For example, the fourth conductive layer 26 in the pixel driving layer 2 can be the first source-drain conductive layer.

[0244] For example, the fourth conductive layer 26 in the pixel driving layer 2 can be obtained by depositing metal materials such as MO / Ti / Al / Cu (molybdenum / titanium / aluminum / copper) using a PVD (Physical Vapor Deposition) process.

[0245] For example, please continue to refer to FIG6J, the fourth conductive layer 26 in the pixel driving layer 2 includes a first transition portion 26a.

[0246] As shown in Figure 6K, which is a planar structural view of a partial region of the first semiconductor layer 21, the second conductive layer 23, and the fourth conductive layer 26 in the pixel driving layer 2 of the display panel 10 according to some embodiments, the first connection portion 231 located in the second conductive layer 23 can be connected to the first voltage signal line VDD (not shown in the figure) in the display panel 10 via the first adapter portion 26a. Since the two second plates C2 belonging to one second plate pair CD in the storage capacitor C of the plurality of pixel circuits 9a are connected via the first connection portion 231, the first voltage signal transmitted by the first voltage signal line VDD in the display panel 10 can be transmitted to the second plate C2 of the storage capacitor C via the first adapter portion 26a and the first connection portion 231.

[0247] Please refer to Figure 6K. In the orthographic projection onto the substrate 1, the first transition portion 26a and the second plate C2 of the storage capacitor C overlap.

[0248] For example, referring to FIG6J and in conjunction with FIG6K, the fourth conductive layer 26 within the pixel driving layer 2 further includes a second transition portion 26b. The first transition portion 26a located within the fourth conductive layer 26 is connected to the active layer pattern T51 of the first light-emitting control transistor T5 via the second transition portion 26b.

[0249] Specifically, when the first light-emitting control transistor T5 is a P-type transistor, the source region T51a of the active layer pattern T51 of the first light-emitting control transistor T5 in the pixel circuit 9a is connected to the first transition portion 26a in the fourth conductive layer 26 through the second transition portion 26b in the fourth conductive layer 26. (Figure 6K shows this situation).

[0250] When the first light-emitting control transistor T5 is an N-type transistor, the drain region T51b of the active layer pattern T51 of the first light-emitting control transistor T5 in the pixel circuit 9a is connected to the first transition portion 26a in the fourth conductive layer 26 through the second transition portion 26b in the fourth conductive layer 26.

[0251] Since the first adapter 26a is connected to the first voltage signal line VDD (not shown in the figure) in the display panel 10, the first voltage signal transmitted by the first voltage signal line VDD in the display panel 10 can be transmitted through the first adapter 26a and the second adapter 26b to the source region T51a or drain region T51b in the active layer pattern T51 of the first light-emitting control transistor T5.

[0252] Please continue to refer to Figure 6K. On the orthographic projection onto the substrate 1, the second transition portion 26b can be located between the active layer patterns T51 of the first light-emitting control transistor T5 in two adjacent pixel circuits 9a.

[0253] For example, referring to FIG6J and in conjunction with FIG6K, the fourth conductive layer 26 within the pixel driving layer 2 further includes a third transition portion 26c. The active layer pattern T81 of the third reset transistor T8 within the pixel circuit 9a is connected to the active layer pattern T51 of the first light-emitting control transistor T5 within the pixel circuit 9a via the third transition portion 26c.

[0254] Specifically, please continue to refer to Figure 6K. Taking the example that the third reset transistor T8 and the first light-emitting control transistor T5 in the pixel circuit 9a are both P-type transistors, the drain region T81b in the active layer pattern T81 of the third reset transistor T8 is connected to the drain region T51b in the active layer pattern T51 of the first light-emitting control transistor T5 through the third transition portion 26c in the fourth conductive layer 26.

[0255] Please continue to refer to Figure 6K. In the orthographic projection onto the substrate 1, the third transition portion 26c and the main body T511 of the active layer pattern T51 of the first light-emitting control transistor T5 do not overlap.

[0256] For example, referring to FIG6J, the fourth conductive layer 26 within the pixel driving layer 2 further includes a fourth transition portion 26d.

[0257] As shown in Figure 6L, Figure 6L is a planar structural view of a partial region of the first semiconductor layer 21, the third conductive layer 25, and the fourth conductive layer 26 in the pixel driving layer 2 of the display panel 10 according to some embodiments. In the case where multiple auxiliary signal lines 25a are provided in the third conductive layer 25, and the multiple auxiliary signal lines 25a include a first auxiliary signal line 251, a second auxiliary signal line 252, and a third auxiliary signal line 253, the first auxiliary signal line 251 is closer to the active layer pattern T81 of the third reset transistor T8 in the pixel circuit 9a than the third auxiliary signal line 253.

[0258] Please continue to refer to Figure 6L. The third auxiliary signal line 253, which is one of the multiple auxiliary signal lines 25a located in the third conductive layer 25, is connected to the active layer pattern T81 of the third reset transistor T8 through the fourth transition part 26d.

[0259] Specifically, when the third reset transistor T8 is a P-type transistor, the source region T81a of the active layer pattern T81 of the third reset transistor T8 in the pixel circuit 9a is connected to the third auxiliary signal line 253 in the third conductive layer 25 through the fourth transition portion 26d in the fourth conductive layer 26. (Figure 6L shows this situation).

[0260] When the third reset transistor T8 is an N-type transistor, the drain region T81b of the active layer pattern T81 of the third reset transistor T8 in the pixel circuit 9a is connected to the third auxiliary signal line 253 in the third conductive layer 25 through the fourth transition portion 26d in the fourth conductive layer 26.

[0261] In some embodiments, as shown in FIG6M and in conjunction with FIG6A, FIG6M is a planar structural view of a partial region of the fifth conductive layer 27 in the pixel driving layer 2 within the display panel 10 according to some embodiments. The fifth conductive layer 27 in the pixel driving layer 2 is located on the side of the fourth conductive layer 26 away from the substrate 1.

[0262] For example, the fifth conductive layer 27 in the pixel driving layer 2 can be a second source-drain conductive layer.

[0263] For example, the fifth conductive layer 27 in the pixel driving layer 2 can be obtained by depositing metal materials such as MO / Ti / Al / Cu (molybdenum / titanium / aluminum / copper) using a PVD (Physical Vapor Deposition) process.

[0264] For example, please continue referring to FIG6M and in conjunction with FIG6K, the first voltage signal line VDD in FIG6K, which states that "the first connection portion 231 located in the second conductive layer 23 is connected to the first voltage signal line VDD in the display panel 10 through the first adapter portion 26a", can be located in the fifth conductive layer 27. That is, the fifth conductive layer 27 in the pixel driving layer 2 may include the first voltage signal line VDD.

[0265] When the fifth conductive layer 27 includes a first voltage signal line VDD, the first voltage signal line VDD in the fifth conductive layer 27 can extend along the first direction X (i.e., the row direction in which the multiple pixel circuits 9a are arranged).

[0266] In some embodiments, as shown in Figures 7A, 7B, 7C, and 7D, and in conjunction with Figure 6I, Figures 7A, 7B, 7C, and 7D are plan view structural diagrams of a display device 100 according to some embodiments. The display panel 10 within the display device 100 further includes a first initialization signal bus 61, a second initialization signal bus 62, and a third initialization signal bus 63. The first initialization signal bus 61, the second initialization signal bus 62, and the third initialization signal bus 63 are respectively connected to the driver chip 20 within the display device 100.

[0267] Multiple auxiliary signal lines 25a (i.e., first auxiliary signal line 251, second auxiliary signal line 252 and third auxiliary signal line 253) extending along the first direction X (i.e. the row direction in which multiple pixel circuits 9a are arranged) within the display panel 10 are connected to the first initialization signal bus 61, the second initialization signal bus 62 and the third initialization signal bus 63.

[0268] Specifically, the first initialization signal bus 61 is connected to the first auxiliary signal line 251 within the plurality of auxiliary signal lines 25a, and is configured to transmit the first initialization signal Vinit1. The second initialization signal bus 62 is connected to the second auxiliary signal line 252 within the plurality of auxiliary signal lines 25a, and is configured to transmit the second initialization signal Vinit2. The third initialization signal bus 63 is connected to the third auxiliary signal line 253 within the plurality of auxiliary signal lines 25a, and is configured to transmit the third initialization signal Vinit3.

[0269] Please refer to Figures 7A, 7B, 7C and 7D. The first initialization signal bus 61, the second initialization signal bus 62 and the third initialization signal bus 63 in the display panel 10 are at least located in the first border area B1 and / or the second border area B2 within the peripheral area AN of the display panel 10.

[0270] For example, referring to Figure 7A, the first initialization signal bus 61, the second initialization signal bus 62, and the third initialization signal bus 63 within the display panel 10 can be located in the first border area B1 or the second border area B2 within the peripheral area AN of the display panel 10. For instance, the first initialization signal bus 61, the second initialization signal bus 62, and the third initialization signal bus 63 within the display panel 10 can be located in the second border area B2 within the peripheral area AN of the display panel 10.

[0271] Alternatively, please refer to Figure 7B. The first initialization signal bus 61, the second initialization signal bus 62, and the third initialization signal bus 63 in the display panel 10 can also be located in the first border area B1 and the second border area B2 within the peripheral area AN of the display panel 10.

[0272] Alternatively, referring to Figure 7C, the first initialization signal bus 61, the second initialization signal bus 62, and the third initialization signal bus 63 within the display panel 10 can also be located within three of the first border area B1, the second border area B2, the third border area B3, and the fourth border area B4 within the peripheral area AN of the display panel 10. For example, the first initialization signal bus 61, the second initialization signal bus 62, and the third initialization signal bus 63 within the display panel 10 can be located within the first border area B1, the second border area B2, and the fourth border area B4 within the peripheral area AN of the display panel 10.

[0273] Alternatively, referring to Figure 7D, the first initialization signal bus 61, the second initialization signal bus 62, and the third initialization signal bus 63 within the display panel 10 can also be located within the first border area B1, the second border area B2, the third border area B3, and the fourth border area B4 within the peripheral area AN of the display panel 10. That is, the first initialization signal bus 61, the second initialization signal bus 62, and the third initialization signal bus 63 within the display panel 10 can be arranged in a closed loop.

[0274] It should be noted that although some embodiments of the arrangement of the first initialization signal bus 61, the second initialization signal bus 62, and the third initialization signal bus 63 within the display panel 10 have been described herein with reference to Figures 7A, 7B, 7C, and 7D, these descriptions are exemplary and not exhaustive, and therefore not limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope of the above embodiments.

[0275] In some embodiments, please continue to refer to FIG4. During the driving process of the pixel circuit 9a in the sub-pixel 9 driving the light-emitting device F in the sub-pixel 9 to emit light, the first initialization signal Vinit1, the second initialization signal Vinit2, and the third initialization signal Vinit3 transmitted by the multiple auxiliary signal lines 25a (i.e., the first auxiliary signal line 251, the second auxiliary signal line 252, and the third auxiliary signal line 253) in the display panel 10 can reset the first node N1, the second node N2, the third node N3, and the fourth node N4, so as to change the potential of the first node N1, the second node N2, the third node N3, and the fourth node N4, thereby raising or lowering the potential of the corresponding nodes of each pixel circuit 9a to a uniform potential, avoiding the interference of the interference source in the display panel 10 on the potential of the nodes (i.e., the first node N1, the second node N2, the third node N3, and the fourth node N4) of each pixel circuit 9a, which would cause the display panel 10 to have uneven display brightness. Therefore, the accuracy and uniformity of the first initialization signal Vinit1, the second initialization signal Vinit2, and the third initialization signal Vinit3 transmitted by the multiple auxiliary signal lines 25a (i.e., the first auxiliary signal line 251, the second auxiliary signal line 252, and the third auxiliary signal line 253) within the display panel 10 are very important.

[0276] When the first initialization signal bus 61, the second initialization signal bus 62, and the third initialization signal bus 63 within the display panel 10 are located in the first border area B1 or the second border area B2 within the peripheral area AN of the display panel 10, please continue to refer to Figure 7A. Taking the example where the first initialization signal bus 61, the second initialization signal bus 62, and the third initialization signal bus 63 within the display panel 10 are located in the second border area B2 within the peripheral area AN of the display panel 10, multiple auxiliary signal lines 25a (i.e., the first auxiliary signal line 251, the second auxiliary signal line 252, and the third auxiliary signal line 253) within the display panel 10 are connected to the first initialization signal bus 61, the second initialization signal bus 62, and the third initialization signal bus 63 located in the second border area B2 within the peripheral area AN. The first initialization signal bus 61, the second initialization signal bus 62, and the third initialization signal bus 63 are connected to the first initialization signal bus 61, the second initialization signal bus 62, and the third initialization signal bus 63 located in the second border area B2 within the peripheral area AN. The first initialization signal Vinit1, the second initialization signal Vinit2, and the third initialization signal Vinit3 transmitted by the initialization signal bus 62 and the third initialization signal bus 63 are transmitted from one side of the display area AA of the display panel 10 to multiple auxiliary signal lines 25a (i.e., the first auxiliary signal line 251, the second auxiliary signal line 252, and the third auxiliary signal line 253). Because there is resistance on the multiple auxiliary signal lines 25a (i.e., the first auxiliary signal line 251, the second auxiliary signal line 252, and the third auxiliary signal line 253), a voltage drop (IR) will occur during the transmission of the first initialization signal Vinit1, the second initialization signal Vinit2, and the third initialization signal Vinit3 within the multiple auxiliary signal lines 25a (i.e., the first auxiliary signal line 251, the second auxiliary signal line 252, and the third auxiliary signal line 253). Furthermore, the voltage drop (IR Drop) of multiple auxiliary signal lines 25a (i.e., the first auxiliary signal line 251, the second auxiliary signal line 252, and the third auxiliary signal line 253) at positions near the second border area B2 of the peripheral area AN differs from that at positions far from the peripheral area AN (e.g., the middle position of the auxiliary signal line 25a, or the position near the first border area B1 of the peripheral area AN). This results in uneven transmission of the first initialization signals Vinit1, the second initialization signals Vinit2, and the third initialization signals Vinit3 at different positions of the multiple auxiliary signal lines 25a (i.e., the first auxiliary signal line 251, the second auxiliary signal line 252, and the third auxiliary signal line 253). The inconsistency of the first initialization signals Vinit1, the second initialization signals Vinit2, and the third initialization signals Vinit3 provided to the pixel circuit 9a in each sub-pixel 9 can easily lead to uneven display brightness of the display panel 10, potentially causing display defects such as horizontal lines and affecting the display effect of the display panel 10.

[0277] Please refer to Figures 7B, 7C, and 7D. When the first initialization signal bus 61, the second initialization signal bus 62, and the third initialization signal bus 63 within the display panel 10 are at least located in the first frame area B1 and the second frame area B2 within the peripheral area AN of the display panel 10, the multiple auxiliary signal lines 25a (i.e., the first auxiliary signal line 251, the second auxiliary signal line 252, and the third auxiliary signal line 253) within the display panel 10 are connected to the first initialization signal bus 61, the second initialization signal bus 62, and the third initialization signal bus 63 located in the first frame area B1 and the second frame area B2 of the peripheral area AN. The first initialization signal bus 61, the second initialization signal bus 62, and the third initialization signal bus 63 transmit the first initialization signal Vinit1, the second initialization signal bus 62, and the third initialization signal bus 63. The second initialization signal Vinit2 and the third initialization signal Vinit3 are transmitted from both sides of the display area AA of the display panel 10 along the first direction X (i.e., the row direction in which the multiple pixel circuits 9a are arranged) to multiple auxiliary signal lines 25a (i.e., the first auxiliary signal line 251, the second auxiliary signal line 252, and the third auxiliary signal line 253). Because there is resistance on the multiple auxiliary signal lines 25a (i.e., the first auxiliary signal line 251, the second auxiliary signal line 252, and the third auxiliary signal line 253), a voltage drop (IR) will occur during the transmission of the first initialization signal Vinit1, the second initialization signal Vinit2, and the third initialization signal Vinit3 within the multiple auxiliary signal lines 25a (i.e., the first auxiliary signal line 251, the second auxiliary signal line 252, and the third auxiliary signal line 253). Furthermore, the voltage drop (IR Drop) of multiple auxiliary signal lines 25a (i.e., the first auxiliary signal line 251, the second auxiliary signal line 252, and the third auxiliary signal line 253) at positions near the first border area B1 and the second border area B2 of the peripheral area AN differs from the voltage drop (IR Drop) at positions far from the peripheral area AN (e.g., the middle position of the auxiliary signal line 25a). This results in uneven transmission of the first initialization signal Vinit1, the second initialization signal Vinit2, and the third initialization signal Vinit3 at different positions of the multiple auxiliary signal lines 25a (i.e., the first auxiliary signal line 251, the second auxiliary signal line 252, and the third auxiliary signal line 253). The inconsistency of the first initialization signal Vinit1, the second initialization signal Vinit2, and the third initialization signal Vinit3 provided to the pixel circuit 9a in each sub-pixel 9 can easily lead to uneven display brightness of the display panel 10, which may produce display defects such as horizontal lines and affect the display effect of the display panel 10.

[0278] Based on this, in some embodiments, as shown in Figures 8A and 8B, which are both planar structural diagrams of the display device 100 according to some embodiments, the display panel 10 within the display device 100 also includes a plurality of initialization signal lines 8. The initialization signal lines 8 extend along a second direction Y (i.e., the column direction in which the plurality of pixel circuits 9a are arranged).

[0279] The multiple initialization signal lines 8 may include a first initialization signal line 81, a second initialization signal line 82, and a third initialization signal line 83. The first initialization signal line 81 is configured to transmit a first initialization signal Vinit1, the second initialization signal line 82 is configured to transmit a second initialization signal Vinit2, and the third initialization signal line 83 is configured to transmit a third initialization signal Vinit3.

[0280] When the display panel 10 includes multiple initialization signal lines 8, and the multiple initialization signal lines 8 include a first initialization signal line 81, a second initialization signal line 82 and a third initialization signal line 83, the multiple auxiliary signal lines 25a in the display panel 10 include at least a second auxiliary signal line 252 and a third auxiliary signal line 253.

[0281] For example, please continue to refer to FIG8A. When the display panel 10 includes multiple initialization signal lines 8, and the multiple initialization signal lines 8 include a first initialization signal line 81, a second initialization signal line 82 and a third initialization signal line 83, the multiple auxiliary signal lines 25a in the display panel 10 may include a second auxiliary signal line 252 and a third auxiliary signal line 253, and the multiple auxiliary signal lines 25a in the display panel 10 do not include the first auxiliary signal line 251.

[0282] The second initialization signal line 82 in the multiple initialization signal lines 8 is connected to the second auxiliary signal line 252 in the multiple auxiliary signal lines 25a, and the third initialization signal line 83 in the multiple initialization signal lines 8 is connected to the third auxiliary signal line 253 in the multiple auxiliary signal lines 25a.

[0283] Since the initialization signal line 8 extends along the second direction Y (i.e., the column direction in which the multiple pixel circuits 9a are arranged) and the auxiliary signal line 25a extends along the first direction X (i.e., the row direction in which the multiple pixel circuits 9a are arranged), the second initialization signal line 82 in the multiple initialization signal lines 8 and the second auxiliary signal line 252 in the multiple auxiliary signal lines 25a together form a mesh structure, and the third initialization signal line 83 in the multiple initialization signal lines 8 and the third auxiliary signal line 253 in the multiple auxiliary signal lines 25a together form a mesh structure.

[0284] By forming a mesh structure with the second initialization signal line 82 in the multiple initialization signal lines 8 and the second auxiliary signal line 252 in the multiple auxiliary signal lines 25a, the second initialization signal Vinit2 provided by the second initialization signal bus 62 can be distributed and transmitted through the mesh structure formed by the second initialization signal line 82 in the multiple initialization signal lines 8 and the second auxiliary signal line 252 in the multiple auxiliary signal lines 25a. This reduces the voltage drop (IR Drop) of the second initialization signal Vinit2 on the transmission path and improves the uniformity of the second initialization signal Vinit2, thereby improving the display uniformity of the display panel 10, avoiding display defects such as horizontal lines on the display panel 10, and improving the display effect of the display panel 10.

[0285] By forming a mesh structure with the third initialization signal line 83 in the multiple initialization signal lines 8 and the third auxiliary signal line 253 in the multiple auxiliary signal lines 25a, the third initialization signal Vinit3 provided by the third initialization signal bus 63 can be distributed and transmitted through the mesh structure formed by the third initialization signal line 83 in the multiple initialization signal lines 8 and the third auxiliary signal line 253 in the multiple auxiliary signal lines 25a. This reduces the voltage drop (IR Drop) of the third initialization signal Vinit3 on the transmission path and improves the uniformity of the third initialization signal Vinit3, thereby improving the display uniformity of the display panel 10, avoiding display defects such as horizontal lines on the display panel 10, and improving the display effect of the display panel 10.

[0286] Alternatively, please refer to Figure 8B. In the case where the display panel 10 includes multiple initialization signal lines 8, and the multiple initialization signal lines 8 include a first initialization signal line 81, a second initialization signal line 82, and a third initialization signal line 83, the multiple auxiliary signal lines 25a in the display panel 10 may include a first auxiliary signal line 251, a second auxiliary signal line 252, and a third auxiliary signal line 253.

[0287] The first initialization signal line 81 in the multiple initialization signal lines 8 is connected to the first auxiliary signal line 251 in the multiple auxiliary signal lines 25a, the second initialization signal line 82 in the multiple initialization signal lines 8 is connected to the second auxiliary signal line 252 in the multiple auxiliary signal lines 25a, and the third initialization signal line 83 in the multiple initialization signal lines 8 is connected to the third auxiliary signal line 253 in the multiple auxiliary signal lines 25a.

[0288] Since the initialization signal line 8 extends along the second direction Y (i.e., the column direction in which the multiple pixel circuits 9a are arranged) and the auxiliary signal line 25a extends along the first direction X (i.e., the row direction in which the multiple pixel circuits 9a are arranged), the multiple initialization signal lines 8 and the multiple auxiliary signal lines 25a together form a mesh structure.

[0289] By having multiple initialization signal lines 8 (i.e., the first initialization signal line 81, the second initialization signal line 82, and the third initialization signal line 83) and multiple auxiliary signal lines 25a (i.e., the first auxiliary signal line 251, the second auxiliary signal line 252, and the third auxiliary signal line 253) jointly form a mesh structure, the first initialization signal Vinit1 provided by the first initialization signal bus 61, the second initialization signal Vinit2 provided by the second initialization signal bus 62, and the third initialization signal Vinit3 provided by the third initialization signal bus 63 can be distributed and transmitted through the mesh structure formed by the multiple initialization signal lines 8 and the multiple auxiliary signal lines 25a. This can reduce the voltage drop (IR Drop) of the first initialization signal Vinit1, the second initialization signal Vinit2, and the third initialization signal Vinit3 on the transmission path, improve the uniformity of the first initialization signal Vinit1, the second initialization signal Vinit2, and the third initialization signal Vinit3, thereby further improving the display uniformity of the display panel 10, avoiding display defects such as horizontal lines on the display panel 10, and helping to further improve the display effect of the display panel 10.

[0290] In some embodiments, please continue to refer to Figures 8A and 8B. The multiple initialization signal lines 8 in the display panel 10 include multiple initialization signal line groups 8a arranged along the first direction X (i.e., the row direction in which the multiple pixel circuits 9a are arranged). Each initialization signal line group 8a includes at least one first initialization signal line 81, at least one second initialization signal line 82 and at least one third initialization signal line 83.

[0291] For example, each initialization signal line group 8a may include at least three initialization signal lines 8. For instance, continuing to refer to Figures 8A and 8B, each initialization signal line group 8a may include four initialization signal lines 8.

[0292] The following describes some embodiments of the present disclosure using the example of each initialization signal line group 8a in the display panel 10 comprising four initialization signal lines 8.

[0293] For example, referring to Figure 8A, when each initialization signal line group 8a in the display panel 10 includes four initialization signal lines 8, each initialization signal line group 8a may include two first initialization signal lines 81, one second initialization signal line 82, and one third initialization signal line 83. That is, the number of first initialization signal lines 81 in each initialization signal line group 8a is relatively large, which is beneficial to the transmission of the first initialization signal Vinit1 in the first initialization signal lines 81. It can reduce the voltage drop (IR Drop) of the first initialization signal Vinit1 on the transmission path, improve the uniformity of the first initialization signal Vinit1, and thus improve the display uniformity of the display panel 10.

[0294] Alternatively, referring to Figure 8B, when each initialization signal line group 8a within the display panel 10 includes four initialization signal lines 8, each initialization signal line group 8a may include one first initialization signal line 81, two second initialization signal lines 82, and one third initialization signal line 83. That is, the larger number of second initialization signal lines 82 within each initialization signal line group 8a is beneficial for the transmission of the second initialization signal Vinit2 within the second initialization signal lines 82. This reduces the voltage drop (IR Drop) of the second initialization signal Vinit2 on the transmission path, improves the uniformity of the second initialization signal Vinit2, and thus improves the display uniformity of the display panel 10.

[0295] Alternatively, if each initialization signal line group 8a within the display panel 10 includes four initialization signal lines 8, each initialization signal line group 8a may include one first initialization signal line 81, one second initialization signal line 82, and two third initialization signal lines 83. That is, the larger number of third initialization signal lines 83 within each initialization signal line group 8a is beneficial for the transmission of the third initialization signal Vinit3 within the third initialization signal lines 83, reducing the voltage drop (IR Drop) of the third initialization signal Vinit3 on the transmission path, improving the uniformity of the third initialization signal Vinit3, and thus improving the display uniformity of the display panel 10.

[0296] Alternatively, in the case where each initialization signal line group 8a within the display panel 10 includes four initialization signal lines 8, some initialization signal line groups 8a within the display panel 10 include two first initialization signal lines 81, one second initialization signal line 82, and one third initialization signal line 83; some partial initialization signal line groups 8a include one first initialization signal line 81, two second initialization signal lines 82, and one third initialization signal line 83; and some partial initialization signal line groups 8a include one first initialization signal line 81, one second initialization signal line 82, and two third initialization signal lines 83. That is, the number of first initialization signal lines 81, second initialization signal lines 82, and third initialization signal lines 83 within the display panel 10 is approximately the same.

[0297] In some embodiments, when the display panel 10 includes multiple initialization signal lines 8 and multiple auxiliary signal lines 25a, and the multiple initialization signal lines 8 include a first initialization signal line 81, a second initialization signal line 82, and a third initialization signal line 83, and the multiple auxiliary signal lines 25a include a first auxiliary signal line 251, a second auxiliary signal line 252, and a third auxiliary signal line 253, the configuration of the first initialization signal bus 61, the second initialization signal bus 62, and the third initialization signal bus 63 in the display panel 10 can be the same as the configuration of the first initialization signal bus 61, the second initialization signal bus 62, and the third initialization signal bus 63 in the embodiments shown in FIG7A, FIG7B, FIG7C, and FIG7D, and will not be described again here.

[0298] In some embodiments, please continue to refer to FIG8A and in conjunction with FIG9, which is a plan view of a display device 100 according to some embodiments. When the display panel 10 includes multiple initialization signal lines 8 and multiple auxiliary signal lines 25a, and the multiple initialization signal lines 8 include a first initialization signal line 81, a second initialization signal line 82, and a third initialization signal line 83, and the multiple auxiliary signal lines 25a include a second auxiliary signal line 252 and a third auxiliary signal line 253, the arrangement of the second initialization signal bus 62 and the third initialization signal bus 63 within the display panel 10 can be the same as the arrangement of the second initialization signal bus 62 and the third initialization signal bus 63 in the embodiments shown in FIG7A, FIG7B, FIG7C, and FIG7D, and will not be repeated here. The following only describes the arrangement of the first initialization signal bus 61 within the display panel 10.

[0299] The first initialization signal bus 61 within the display panel 10 is at least located in the fourth border area B4 within the peripheral area AN of the display panel 10, and the first initialization signal line 81 among the multiple initialization signal lines 8 is connected to the first initialization signal bus 61.

[0300] For example, referring to Figure 8A, the first initialization signal bus 61 within the display panel 10 can be located in the fourth border area B4 within the peripheral area AN of the display panel 10. That is, if the first initialization signal bus 61 within the display panel 10 is not located in the first border area B1, the second border area B2, and the third border area B3 within the peripheral area AN of the display panel 10, the size of the first border area B1, the second border area B2, and the third border area B3 within the peripheral area AN of the display panel 10 can be reduced, which is beneficial for further achieving a narrower bezel design for the display panel 10.

[0301] Alternatively, please refer to Figure 9. The first initialization signal bus 61 in the display panel 10 can also be set in the first border area B1, the second border area B2, the third border area B3 and the fourth border area B4 in the peripheral area AN of the display panel 10.

[0302] The following is a detailed description of how the initialization signal line 8 in the above-mentioned display panel 10 is configured.

[0303] With the continuous development of display panels, large-size, ultra-high definition (QHD) display panels are increasingly favored by users. From 720P to 1080P, from 2K to 4K and then to 8K, the resolution of display panels is constantly being upgraded. PPI (pixels per inch) is a unit of image resolution, representing the number of pixels per inch. Therefore, the higher the PPI value, the higher the density at which the display panel can display images. The higher the display density, the higher the realism, thus achieving high-definition and ultra-high-definition display.

[0304] The higher the PPI (pixels per inch) value of the display panel 10, the more pixels it has per inch, and the more difficult it is to wire the display panel 10.

[0305] Based on this, in some embodiments, as shown in Figures 10A, 10B, and 10C, Figure 10A is a planar structural diagram of a partial region of the pixel driving layer 2 in the display panel 10 according to some embodiments; Figure 10B is a planar structural diagram of a partial region of the fourth conductive layer 26 in the pixel driving layer 2 in the display panel 10 according to some embodiments; and Figure 10C is a planar structural diagram of a partial region of the second conductive layer 23 and the fourth conductive layer 26 in the pixel driving layer 2 in the display panel 10 according to some embodiments. It should be noted that Figure 10A only shows the first semiconductor layer 21, the first conductive layer 22, the second conductive layer 23, the second semiconductor layer 24, the third conductive layer 25, and the fourth conductive layer 26 in the pixel driving layer 2, omitting other film layers in the pixel driving layer 2. For example, Figure 10A omits the insulating layer between two adjacent film layers in the pixel driving layer 2, which is located between the first semiconductor layer 21, the first conductive layer 22, the second conductive layer 23, the second semiconductor layer 24, the third conductive layer 25, and the fourth conductive layer 26; the fifth conductive layer 27 located on the side of the fourth conductive layer 26 away from the substrate 1; and the bottom shield metal (BSM) layer located on the side of the first semiconductor layer 21 close to the substrate 1.

[0306] To facilitate the explanation of the embodiments shown in Figures 10A and 10C, the first conductive layer 22, the second conductive layer 23, the second semiconductor layer 24, the third conductive layer 25, and the fourth conductive layer 26 in Figure 10A are made transparent to expose the other film layers (i.e., the first semiconductor layer 21, the first conductive layer 22, the second conductive layer 23, the second semiconductor layer 24, and the third conductive layer 25) in the pixel driving layer 2 within the display panel 10, located on the side of the fourth conductive layer 26 closest to the substrate 1. The fourth conductive layer 26 in Figure 10C is made transparent to expose the second conductive layer 23 in the pixel driving layer 2 within the display panel 10.

[0307] The multiple initialization signal lines 8 within the display panel 10 can be located within the fourth conductive layer 26 of the pixel driving layer 2. That is, the fourth conductive layer 26 of the pixel driving layer 2 includes multiple initialization signal lines 8.

[0308] The orthographic projection of the initialization signal line 8 on the substrate 1 overlaps with the orthographic projection of the second plate C2 of the multiple storage capacitors C of a column of pixel circuits 9a (i.e., multiple pixel circuits 9a arranged along the second direction Y) on the substrate 1.

[0309] By overlapping the orthographic projection of the initialization signal line 8 onto the substrate 1 with the orthographic projection of the second plates C2 of the multiple storage capacitors C of a column of pixel circuits 9a (i.e., multiple pixel circuits 9a arranged along the second direction Y) onto the substrate 1, the initialization signal line 8 is mostly located within the area where the pixel circuits 9a are located in the orthographic projection onto the substrate 1. Furthermore, along the first direction X (i.e., the row direction in which the multiple pixel circuits 9a are arranged), the orthographic projection of the initialization signal line 8 onto the substrate 1 is not located between two adjacent pixel circuits 9a. This avoids the initialization signal line 8 occupying the gap between two adjacent pixel circuits 9a, resulting in a smaller gap between two adjacent pixel circuits 9a. Consequently, the display panel 10 has a larger number of pixels per inch, which is beneficial for achieving a high PPI (pixels per inch) in the display panel 10.

[0310] In other words, by overlapping the orthographic projection of the initialization signal line 8 on the substrate 1 with the orthographic projection of the second plate C2 of the multiple storage capacitors C of a column of pixel circuits 9a (i.e., multiple pixel circuits 9a arranged along the second direction Y) on the substrate 1, a mesh structure is formed by multiple initialization signal lines 8 and multiple auxiliary signal lines 25a. This improves the display uniformity of the display panel 10 while ensuring that the display panel 10 achieves a high PPI (Pixels Per Inch).

[0311] In order to make the orthographic projection of the initialization signal line 8 on the substrate 1 overlap with the orthographic projection of the second plate C2 of the multiple storage capacitors C of a column of pixel circuits 9a (i.e., multiple pixel circuits 9a arranged along the second direction Y) on the substrate 1, it is necessary to set some conductive structures in the fourth conductive layer 26 of the pixel driving layer 2. The following is a detailed description of the setting method of some conductive structures in the fourth conductive layer 26 of the pixel driving layer 2.

[0312] In some embodiments, as shown in Figures 11A, 11B, and 11C, Figure 11A is a planar structural diagram of a partial region of the pixel driving layer 2 in the display panel 10 according to some embodiments; Figure 11B is a planar structural diagram of a partial region of the fourth conductive layer 26 in the pixel driving layer 2 in the display panel 10 according to some embodiments; and Figure 11C is a planar structural diagram of a partial region of the first semiconductor layer 21, the second conductive layer 23, and the fourth conductive layer 26 in the pixel driving layer 2 in the display panel 10 according to some embodiments. It should be noted that Figure 11A only shows the first semiconductor layer 21, the first conductive layer 22, the second conductive layer 23, the second semiconductor layer 24, the third conductive layer 25, and the fourth conductive layer 26 in the pixel driving layer 2, omitting other film layers in the pixel driving layer 2. For example, Figure 11A omits the insulating layer between two adjacent film layers in the pixel driving layer 2, including the first semiconductor layer 21, the first conductive layer 22, the second conductive layer 23, the second semiconductor layer 24, the third conductive layer 25, and the fourth conductive layer 26; the fifth conductive layer 27 located on the side of the fourth conductive layer 26 away from the substrate 1; and the bottom shield metal (BSM) layer located on the side of the first semiconductor layer 21 close to the substrate 1.

[0313] To facilitate the explanation of the embodiments shown in Figures 11A and 11C, the first conductive layer 22, the second conductive layer 23, the second semiconductor layer 24, the third conductive layer 25, and the fourth conductive layer 26 in Figure 11A are made transparent to expose the other film layers (i.e., the first semiconductor layer 21, the first conductive layer 22, the second conductive layer 23, the second semiconductor layer 24, and the third conductive layer 25) located on the side of the fourth conductive layer 26 near the substrate 1 in the pixel driving layer 2 within the display panel 10. The fourth conductive layer 26 and the second conductive layer 23 in Figure 11C are made transparent to expose the second conductive layer 23 and the first semiconductor layer 21 in the pixel driving layer 2 within the display panel 10.

[0314] Please refer to Figures 11B and 11C. The fourth conductive layer 26 within the pixel driving layer 2 includes a first transition pattern 261. The first connection portion 231 located within the second conductive layer 23 can be connected to the first voltage signal line VDD (not shown) within the display panel 10 via the first transition pattern 261. Since the two second plates C2 belonging to one second plate pair CD in the storage capacitor C of the plurality of pixel circuits 9a are connected via the first connection portion 231, the first voltage signal transmitted by the first voltage signal line VDD within the display panel 10 can be transmitted to the second plate C2 of the storage capacitor C via the first transition pattern 261 and the first connection portion 231.

[0315] In the orthographic projection onto the substrate 1, the first transition pattern 261 within the fourth conductive layer 26 is located between the two second plates CD within the second plate pair CD.

[0316] Please continue to refer to Figures 6J and 6K, and in conjunction with Figures 11B and 11C. In the embodiments shown in Figures 6J and 6K, the first connection portion 231 located in the second conductive layer 23 is connected to the first voltage signal line VDD in the display panel 10 through the first adapter portion 26a. On the orthographic projection onto the substrate 1, the first adapter portion 26a and the second electrode plate C2 of the storage capacitor C overlap.

[0317] In the embodiments shown in Figures 11B and 11C, the first transition portion 26a in the embodiments shown in Figures 6J and 6K is replaced with a first transition pattern 261. The first connection portion 231 located in the second conductive layer 23 is connected to the first voltage signal line VDD in the display panel 10 through the first transition pattern 261, and in the orthographic projection onto the substrate 1, the first transition pattern 261 in the fourth conductive layer 26 is located between the two second plates CD in the second plate pair CD. In the orthographic projection onto the substrate 1, the first transition pattern 261 in the fourth conductive layer 26 and the second electrode C2 of the storage capacitor C do not overlap. This is beneficial to increase the wiring space in the overlapping area of ​​the second electrode C2 of the storage capacitor C in the fourth conductive layer 26. It is also convenient to set an initialization signal line 8 extending along the second direction Y (i.e., the column direction in which the multiple pixel circuits 9a are arranged) in the overlapping area of ​​the second electrode C2 of the storage capacitor C in the fourth conductive layer 26. This makes the orthographic projection of the initialization signal line 8 on the substrate 1 overlap with the orthographic projection of the second electrode C2 of the multiple storage capacitors C of a column of pixel circuits 9a (i.e., multiple pixel circuits 9a arranged along the second direction Y) on the substrate 1.

[0318] In some embodiments, referring to FIG11C and in conjunction with FIG11B, the fourth conductive layer 26 within the pixel driving layer 2 further includes a second transition pattern 262 and a third transition pattern 263. The first voltage signal line VDD (not shown) within the display panel 10 is connected to the active layer pattern T51 of the first light-emitting control transistor T5 via the second transition pattern 262. The active layer pattern T81 of the third reset transistor T8 within the pixel circuit 9a is connected to the active layer pattern T51 of the first light-emitting control transistor T5 via the third transition pattern 263.

[0319] Specifically, when the first light-emitting control transistor T5 is a P-type transistor, the source region T51a of the active layer pattern T51 of the first light-emitting control transistor T5 in the pixel circuit 9a is connected to the first voltage signal line VDD in the display panel 10 through the second transition pattern 262 in the fourth conductive layer 26. (Figure 11C shows this situation).

[0320] When the first light-emitting control transistor T5 is an N-type transistor, the drain region T51b of the active layer pattern T51 of the first light-emitting control transistor T5 in the pixel circuit 9a is connected to the first voltage signal line VDD in the display panel 10 through the second transition pattern 262 in the fourth conductive layer 26.

[0321] Specifically, please continue to refer to Figure 11C. Taking the example that the third reset transistor T8 and the first light-emitting control transistor T5 in the pixel circuit 9a are both P-type transistors, the drain region T81b in the active layer pattern T81 of the third reset transistor T8 is connected to the drain region T51b in the active layer pattern T51 of the first light-emitting control transistor T5 through the third transition pattern 263 in the fourth conductive layer 26.

[0322] Please refer to Figures 11B and 11C. The first transition pattern 261 and the second transition pattern 262 in the fourth conductive layer 26 are spaced apart. That is, there is a gap between the first transition pattern 261 and the second transition pattern 262 in the fourth conductive layer 26.

[0323] Please continue to refer to Figures 11B and 11C. Along the first direction X (i.e., the row direction in which the multiple pixel circuits 9a are arranged), the second transition pattern 262 in the fourth conductive layer 26 is located between two adjacent initialization signal lines 8.

[0324] Please continue to refer to Figures 11B and 11C. Along the first direction X (i.e., the row direction in which the multiple pixel circuits 9a are arranged), the second transition pattern 262 in the fourth conductive layer 26 is located between two adjacent third transition patterns 263.

[0325] Please continue to refer to Figures 6J and 6K, and in conjunction with Figures 11B and 11C. In the embodiments shown in Figures 6J and 6K, the first transition portion 26a located in the fourth conductive layer 26 is connected to the active layer pattern T51 of the first light-emitting control transistor T5 through the second transition portion 26b. Since the first transition portion 26a is connected to the first voltage signal line VDD (not shown in the figure) in the display panel 10, the first voltage signal transmitted by the first voltage signal line VDD in the display panel 10 can be transmitted to the source region T51a or drain region T51b in the active layer pattern T51 of the first light-emitting control transistor T5 through the first transition portion 26a and the second transition portion 26b. On the orthographic projection onto the substrate 1, the second transition portion 26b is located between the active layer patterns T51 of the first light-emitting control transistor T5 in two adjacent pixel circuits 9a, and is located between the ends of the active layer patterns T51 of the first light-emitting control transistor T5 of two adjacent third transition portions 26c (the third transition portion 26c is used to connect the active layer pattern T81 of the third reset transistor T8 and the active layer pattern T51 of the first light-emitting control transistor T5). Since both the second transition portion 26b and the third transition portion 26c are located within the fourth conductive layer 26 in the pixel driving layer 2, and the second transition portion 26b is located between the ends of the active layer pattern T51 of the first light-emitting control transistor T5 of the two adjacent third transition portions 26c, in order to avoid a short circuit in the display panel 10 caused by the connection between the second transition portion 26b and the third transition portion 26c, there needs to be a sufficient gap between the second transition portion 26b and the third transition portion 26c. Therefore, in the orthographic projection onto the substrate 1, the third transition portion 26c and the main body T511 of the active layer pattern T51 of the first light-emitting control transistor T5 do not overlap.

[0326] In the embodiments shown in Figures 11B and 11C, the second transition portion 26b in the embodiments shown in Figures 6J and 6K is removed. The first voltage signal line VDD in the display panel 10 is directly connected to the active layer pattern T51 of the first light-emitting control transistor T5 through the second transition pattern 262. The first transition pattern 261 and the second transition pattern 262 are spaced apart, so that the second transition pattern 262 in the fourth conductive layer 26 is not located between the ends of two adjacent third transition patterns 263 that are close to the active layer pattern T51 of the first light-emitting control transistor T5. That is, within the fourth conductive layer 26, no conductive structure is provided between the ends of the two adjacent third transition patterns 263 located on opposite sides of the second transition pattern 262 that are close to the active layer pattern T51 of the first light-emitting control transistor T5. This can appropriately reduce the spacing between the ends of the two adjacent third transition patterns 263 located on opposite sides of the second transition pattern 262 that are close to the active layer pattern T51 of the first light-emitting control transistor T5, so that the end of the third transition pattern 263 that is close to the active layer pattern T51 of the first light-emitting control transistor T5 moves closer to the main body T511 of the active layer pattern T51 of the first light-emitting control transistor T5. Thus, in the orthogonal projection onto the substrate 1, the end of the third transition pattern 263 that is close to the active layer pattern T51 of the first light-emitting control transistor T5 can overlap with the main body T511 of the active layer pattern T51 of the first light-emitting control transistor T5.

[0327] Because, in the orthographic projection onto the substrate 1, one end of the third transition pattern 263 near the active layer pattern T51 of the first light-emitting control transistor T5 is located between the main body T511 of the active layer pattern T51 of the first light-emitting control transistor T5 and the second plate C2 of the storage capacitor C, by making the orthographic projection of the end of the third transition pattern 263 near the active layer pattern T51 of the first light-emitting control transistor T5 on the substrate 1 overlap with the orthographic projection of the main body T511 of the active layer pattern T51 of the first light-emitting control transistor T5 on the substrate 1, the third transition pattern 263 is closer to the main body T511 of the active layer pattern T51 of the first light-emitting control transistor T5 compared to the third transition portion 26c in the embodiments shown in FIG. 6J and FIG. 6K. This is beneficial to increase the distance between the third transition pattern 263 and the first light-emitting control transistor T5 in the fourth conductive layer 26. The wiring space in a portion of the active layer pattern T51 of the control transistor T5 (i.e., the side of the third transition pattern 263 near the second plate C2 of the storage capacitor C) facilitates the provision of an initialization signal line 8 extending along the second direction Y (i.e., the column direction in which the multiple pixel circuits 9a are arranged) in a portion of the third transition pattern 26 away from the active layer pattern T51 of the first light-emitting control transistor T5 (i.e., the side of the third transition pattern 263 near the second plate C2 of the storage capacitor C) within the fourth conductive layer 26. This allows the orthogonal projection of the initialization signal line 8 onto the substrate 1 and the orthogonal projection of the second plate C2 of the multiple storage capacitors C of a column of pixel circuits 9a (i.e., the multiple pixel circuits 9a arranged along the second direction Y) onto the substrate 1 to overlap.

[0328] In some embodiments, please continue to refer to FIG11B and in conjunction with FIG11D, FIG11D being a planar structural view of a partial region of the first semiconductor layer 21, the third conductive layer 25, and the fourth conductive layer 26 in the pixel driving layer 2 within the display panel 10 according to some embodiments. It should be noted that, for the convenience of explaining the embodiment shown in FIG11D, the third conductive layer 25 and the fourth conductive layer 26 in FIG11D are made transparent to expose the first semiconductor layer 21 and the third conductive layer 25 in the pixel driving layer 2 within the display panel 10.

[0329] The orthographic projection of the active layer pattern T81 of the third reset transistor T8 of the pixel circuit 9a onto the substrate 1 and the orthographic projection of the third auxiliary signal line 253 of the multiple auxiliary signal lines 25a located in the third conductive layer 25 onto the substrate 1 overlap.

[0330] The fourth conductive layer 26 in the pixel driving layer 2 also includes a fourth transition pattern 264. The third auxiliary signal line 253, one of the multiple auxiliary signal lines 25a located in the third conductive layer 25, is connected to the active layer pattern T81 of the third reset transistor T8 of the pixel circuit 9a through the fourth transition pattern 264.

[0331] Specifically, when the third reset transistor T8 is a P-type transistor, the source region T81a of the active layer pattern T81 of the third reset transistor T8 in the pixel circuit 9a is connected to the third auxiliary signal line 253 in the third conductive layer 25 through the fourth transition pattern 264 in the fourth conductive layer 26. (Figure 11D shows this situation).

[0332] When the third reset transistor T8 is an N-type transistor, the drain region T81b of the active layer pattern T81 of the third reset transistor T8 in the pixel circuit 9a is connected to the third auxiliary signal line 253 in the third conductive layer 25 through the fourth transition pattern 264 in the fourth conductive layer 26.

[0333] By making the orthographic projection of the active layer pattern T81 of the third reset transistor T8 of the pixel circuit 9a onto the substrate 1 and the orthographic projection of the third auxiliary signal line 253 of the multiple auxiliary signal lines 25a located in the third conductive layer 25 onto the substrate 1, the spacing between the third auxiliary signal line 253 and the source region T81a or drain region T81b of the active layer pattern T81 of the third reset transistor T8 is smaller. When the third auxiliary signal line 253 and the source region T81a or drain region T81b of the active layer pattern T81 of the third reset transistor T8 are connected through the fourth transition pattern 264 in the fourth conductive layer 26, the size of the fourth transition pattern 264 in the fourth conductive layer 26 can be reduced, which is beneficial to increase the wiring space of the fourth conductive layer 26 and facilitates the setting of the initialization signal line 8 extending along the second direction Y (i.e., the column direction in which the multiple pixel circuits 9a are arranged) in the display panel 10.

[0334] For example, as shown in FIG11E, FIG11E is a planar structural diagram of a partial region of the first semiconductor layer 21, the first conductive layer 22, the third conductive layer 25, and the fourth conductive layer 26 in the pixel driving layer 2 of the display panel 10 according to some embodiments. It should be noted that, for the convenience of explaining the embodiment shown in FIG11E, the first conductive layer 22, the third conductive layer 25, and the fourth conductive layer 26 in FIG11E are made transparent to expose the first semiconductor layer 21, the first conductive layer 22, and the third conductive layer 25 in the pixel driving layer 2 of the display panel 10.

[0335] The orthographic projection of the second reset control signal line Reset2 located in the first conductive layer 22 onto the substrate 1 and the orthographic projection of the third auxiliary signal line 253, one of the multiple auxiliary signal lines 25a located in the third conductive layer 25, onto the substrate 1 at least partially overlap.

[0336] In some embodiments, as shown in Figures 12A, 12B, and 12C, Figure 12A is a planar structural diagram of a partial region of the pixel driving layer 2 in the display panel 10 according to some embodiments, Figure 12B is a planar structural diagram of a partial region of the first semiconductor layer 21, the first conductive layer 22, the second conductive layer 23, and the third conductive layer 25 in the pixel driving layer 2 in the display panel 10 according to some embodiments, and Figure 12C is a planar structural diagram of a partial region of the first semiconductor layer 21, the second conductive layer 23, and the third conductive layer 25 in the pixel driving layer 2 in the display panel 10 according to some embodiments.

[0337] In the case where the multiple auxiliary signal lines 25a in the display panel 10 include a first auxiliary signal line 251, a second auxiliary signal line 252, and a third auxiliary signal line 253, in the orthogonal projection onto the substrate 1, the first auxiliary signal line 251 of the multiple auxiliary signal lines 25a is located between the second plate C2 of the storage capacitor C and the third auxiliary signal line 253 of the multiple auxiliary signal lines 25a, and is spaced apart from the active layer pattern T81 of the third reset transistor T8 in the pixel circuit 9a.

[0338] For example, as shown in FIG12D and in conjunction with FIG12B, FIG12D is a planar structural view of a partial region of the first conductive layer 22 and the third conductive layer 25 in the pixel driving layer 2 of the display panel 10 according to some embodiments. In the case where the plurality of auxiliary signal lines 25a in the display panel 10 include the first auxiliary signal line 251, in the orthographic projection onto the substrate 1, the light emission control signal line EM located in the first conductive layer 22 and the first auxiliary signal line 251 located in the third conductive layer 25 at least partially overlap.

[0339] In some embodiments, as shown in Figures 12E and 12F, Figure 12E is a planar structural diagram of a partial region of the fourth conductive layer 26 in the pixel driving layer 2 of the display panel 10 according to some embodiments, and Figure 12F is a planar structural diagram of a partial region of the first semiconductor layer 21, the third conductive layer 25 and the fourth conductive layer 26 in the pixel driving layer 2 of the display panel 10 according to some embodiments.

[0340] The fourth conductive layer 26 in the pixel driving layer 2 also includes a sixth transition pattern 266, and the first initialization signal line 81 is connected to the active layer pattern T11 of the first reset transistor T1 in the pixel circuit 9a through the sixth transition pattern 266.

[0341] Specifically, when the first reset transistor T1 is a P-type transistor, the first initialization signal line 81 is connected to the source region T11a in the active layer pattern T11 of the first reset transistor T1 in the pixel circuit 9a through the sixth transition pattern 266 in the fourth conductive layer 26. (Figure 12F shows this situation).

[0342] When the first reset transistor T1 is an N-type transistor, the first initialization signal line 81 is connected to the drain region T11b in the active layer pattern T11 of the first reset transistor T1 in the pixel circuit 9a through the sixth transition pattern 266 in the fourth conductive layer 26.

[0343] In some embodiments, referring further to Figures 12E and 12F, the fourth conductive layer 26 in the pixel driving layer 2 also includes a seventh transition pattern 267. The second auxiliary signal line 252 is connected via the seventh transition pattern 267 and the second initialization signal line 82.

[0344] In some embodiments, referring further to Figures 12E and 12F, the fourth conductive layer 26 in the pixel driving layer 2 also includes an eighth transition pattern 268. The third auxiliary signal line 253 is connected to the third initialization signal line 83 via the eighth transition pattern 268.

[0345] For example, please continue to refer to Figures 12E and 12F. The third auxiliary signal line 253 can first be connected through the fourth transition pattern 264 and the eighth transition pattern 268 in the fourth conductive layer 26. The eighth transition pattern 268 is then connected to the third initialization signal line 83 to realize the connection between the third auxiliary signal line 253 and the third initialization signal line 83.

[0346] In some embodiments, please continue to refer to Figures 12E and 12F. In the case where the multiple auxiliary signal lines 25a include the first auxiliary signal line 251, the fourth conductive layer 26 in the pixel driving layer 2 also includes a fifth transition pattern 265. The first auxiliary signal line 251 is connected to the active layer pattern T11 of the first reset transistor T1 through the fifth transition pattern 265.

[0347] Specifically, when the first reset transistor T1 is a P-type transistor, the first auxiliary signal line 251 is connected to the source region T11a in the active layer pattern T11 of the first reset transistor T1 in the pixel circuit 9a through the fifth transition pattern 265. (Figure 12F shows this situation).

[0348] When the first reset transistor T1 is an N-type transistor, the first auxiliary signal line 251 is connected to the drain region T11b in the active layer pattern T11 of the first reset transistor T1 in the pixel circuit 9a through the fifth transition pattern 265.

[0349] As can be understood, as shown in Figures 13A, 13B, and 13C, Figure 13A is a planar structural diagram of a partial region of the pixel driving layer 2 in the display panel 10 according to some embodiments, Figure 13B is a planar structural diagram of a partial region of the fourth conductive layer 26 in the pixel driving layer 2 in the display panel 10 according to some embodiments, and Figure 13C is a planar structural diagram of a partial region of the first semiconductor layer 21, the third conductive layer 25, and the fourth conductive layer 26 in the pixel driving layer 2 in the display panel 10 according to some embodiments.

[0350] In the case where multiple auxiliary signal lines 25a include a second auxiliary signal line 252 and a third auxiliary signal line 253, but do not include a first auxiliary signal line 251, the fourth conductive layer 26 in the pixel driving layer 2 does not include a fifth transition pattern 265 connection for connecting the first auxiliary signal line 251 and the active layer pattern T11 of the first reset transistor T1.

[0351] The connection methods of the first initialization signal line 81 and the active layer pattern T11 of the first reset transistor T1 in the pixel circuit 9a, the connection methods of the second auxiliary signal line 252 and the second initialization signal line 82, and the connection methods of the third auxiliary signal line 253 and the third initialization signal line 83 are the same as or similar to those shown in the embodiments of FIG12A, FIG12E and FIG12F, and will not be described again here.

[0352] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A display panel comprising a plurality of pixel circuits arranged in an array, the pixel circuits including a storage capacitor, the storage capacitor including a second plate; The display panel also includes: Substrate; A fourth conductive layer is located on the substrate; the fourth conductive layer includes multiple initialization signal lines, which extend along a second direction, the second direction being the column direction of the multiple pixel circuits; The second conductive layer is located on the side of the fourth conductive layer closest to the substrate; the second electrode of the storage capacitor is located on the second conductive layer; The orthographic projection of the initialization signal line on the substrate and the orthographic projection of the second plates of the multiple storage capacitors of the pixel circuit on the substrate overlap.

2. The display panel according to claim 1, wherein, The display panel further includes a fifth conductive layer located on the side of the fourth conductive layer away from the substrate; the fifth conductive layer includes a first voltage signal line; The second electrode of the storage capacitor of the plurality of pixel circuits includes a plurality of second electrode pairs, and a second electrode pair includes two adjacent second electrodes in a first direction, the first direction being the row direction in which the plurality of pixel circuits are arranged; the second conductive layer also includes a first connection portion, and two second electrodes belonging to a second electrode pair are connected through the first connection portion; The fourth conductive layer further includes a first transition pattern, and the first connection portion is connected to the first voltage signal line through the first transition pattern; in the orthographic projection onto the substrate, the first transition pattern is located between the two second plates inside the second plate pair.

3. The display panel according to claim 1, wherein, The display panel further includes a first semiconductor layer located on the side of the second conductive layer near the substrate; The pixel circuit further includes a first light-emitting control transistor, the first light-emitting control transistor including an active layer pattern located on the first semiconductor layer; The fourth conductive layer further includes a second transition pattern, and the first voltage signal line in the display panel is connected to the active layer pattern of the first light-emitting control transistor through the second transition pattern; In the first direction, the second transition pattern is located between two adjacent initialization signal lines.

4. The display panel according to claim 3, wherein, The first adapter pattern and the second adapter pattern are set at intervals.

5. The display panel according to claim 3, wherein, The pixel circuit further includes a third reset transistor, the third reset transistor including an active layer pattern located on the first semiconductor layer; The fourth conductive layer further includes a third transition pattern, and the active layer pattern of the third reset transistor is connected to the active layer pattern of the first light-emitting control transistor through the third transition pattern. Wherein, along the first direction, the second transition pattern is located between two adjacent third transition patterns.

6. The display panel according to claim 5, wherein, The active layer pattern of the first light-emitting control transistor includes a main body extending along the second direction; In the projection onto the substrate, the third transition pattern overlaps with the main body near one end of the active layer pattern of the first light-emitting control transistor.

7. The display panel according to claim 1, wherein, The display panel further includes a third conductive layer located between the fourth conductive layer and the second conductive layer; the third conductive layer includes a plurality of auxiliary signal lines extending along a first direction. The plurality of auxiliary signal lines include a third auxiliary signal line, and the fourth conductive layer further includes a fourth transition pattern. The third auxiliary signal line is connected to the active layer pattern of the third reset transistor of the pixel circuit through the fourth transition pattern. The orthographic projection of the active layer pattern of the third reset transistor onto the substrate and the orthographic projection of the third auxiliary signal line onto the substrate overlap.

8. The display panel according to claim 7, wherein, The display panel further includes a first conductive layer located on the side of the second conductive layer near the substrate; The first conductive layer includes a second reset control signal line, which extends along the first direction; The orthographic projection of the second reset control signal line on the substrate and the orthographic projection of the third auxiliary signal line on the substrate at least partially overlap; And / or, The first conductive layer further includes a light-emitting control signal line, which extends along the first direction; The plurality of auxiliary signal lines also includes a first auxiliary signal line, which, in a positive projection onto the substrate, is located between the second plate of the storage capacitor and the third auxiliary signal line, and at least partially overlaps with the light emission control signal line.

9. The display panel according to claim 8, wherein, The pixel circuit further includes a first reset transistor, the first reset transistor including an active layer pattern located within a first semiconductor layer of the display panel; The fourth conductive layer further includes a fifth transition pattern, through which the first auxiliary signal line is connected to the active layer pattern of the first reset transistor.

10. The display panel according to claim 1, wherein, The initialization signal line includes multiple initialization signal line groups arranged along the first direction, and each initialization signal line group includes at least one first initialization signal line, at least one second initialization signal line, and at least one third initialization signal line; The first initialization signal line is configured to transmit a first initialization signal, the second initialization signal line is configured to transmit a second initialization signal, and the third initialization signal line is configured to transmit a third initialization signal.

11. The display panel according to claim 10, wherein, The fourth conductive layer also includes a sixth transition pattern; The first initialization signal line is connected to the active layer pattern of the first reset transistor in the pixel circuit through the sixth adapter pattern.

12. The display panel according to claim 10, wherein, The display panel also includes multiple auxiliary signal lines, including a second auxiliary signal line and a third auxiliary signal line; The second auxiliary signal line is connected to the second initialization signal line, and the third auxiliary signal line is connected to the third initialization signal line.

13. The display panel according to claim 12, wherein, The fourth conductive layer also includes a seventh transition pattern and an eighth transition pattern; The second auxiliary signal line is connected to the second initialization signal line through the seventh adapter pattern, and the third auxiliary signal line is connected to the third initialization signal line through the eighth adapter pattern.

14. The display panel according to claim 12, wherein, The display panel includes a display area and a peripheral area surrounding the display area; the peripheral area includes a first border area, a second border area, a third border area and a fourth border area, the first border area and the second border area are disposed on both sides of the display area along the first direction, and the third border area and the fourth border area are disposed on both sides of the display area along the second direction. The display panel further includes a second initialization signal bus and a third initialization signal bus, wherein the second initialization signal bus and the third initialization signal bus are at least disposed in the first border area and / or the second border area; The second auxiliary signal line is connected to the second initialization signal bus, and the third auxiliary signal line is connected to the third initialization signal bus.

15. The display panel according to claim 12, wherein, The plurality of auxiliary signal lines also includes a first auxiliary signal line; The first auxiliary signal line is connected to the first initialization signal line.

16. The display panel according to claim 15, wherein, The display panel further includes a first initialization signal bus, which is at least located in the first border area and / or the second border area of ​​the display panel; the first auxiliary signal line is connected to the first initialization signal bus.

17. The display panel according to any one of claims 10 to 14, wherein, The fourth border area of ​​the display panel is close to the bonding side of the display panel; The display panel further includes a first initialization signal bus, which is at least located in the fourth border area; The first initialization signal line is connected to the first initialization signal bus.

18. A display device, comprising: The display panel as described in any one of claims 1 to 17; The driver chip is electrically connected to the display panel.

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