Display panel and display device

Abstract

A display panel. Two adjacent sub-pixels among a row of sub-pixels form a pixel group; a pixel driving circuit comprises a specified transistor, at least one signal line comprises a specified signal line, and the specified transistor is coupled to the specified signal line; the display panel comprises a substrate, a first active layer, a specified gate metal layer, and a first source-drain metal layer; the first active layer comprises an active layer first electrode pattern of the specified transistor; the specified gate metal layer comprises a specified signal line pattern; the first source-drain metal layer comprises a specified signal line bridging pattern, and in one pixel group, the active layer first electrode pattern of the specified transistor of one sub-pixel is connected to the active layer first electrode pattern of the specified transistor of the other sub-pixel; and the specified signal line bridging pattern is located in an area where one sub-pixel is located, and the specified signal line bridging pattern is connected to the active layer first electrode pattern of the specified transistor of one of the sub-pixels and is also connected to the specified signal line pattern.

Description

Display panel and display device

[0001] This application claims priority to Chinese patent application No. 202410814707.X, filed on June 21, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of display technology, and more particularly to a display panel and display device. Background Technology

[0003] With the rapid development of modern electronic information technology, the display industry is also constantly progressing, and display products are being used in a wider range of fields.

[0004] For example, OLED (Organic Light-Emitting Diode) display products have gradually gained an important position in the market due to their advantages such as thinness, high brightness, low power consumption, good flexibility, and fast response. OLED display products have allowed more users to enjoy a wonderful visual experience, while users have also put forward higher requirements for OLED display products; however, dark spots on the screen of OLED display products have greatly affected the user experience. Summary of the Invention

[0005] On one hand, a display panel is provided, comprising a plurality of sub-pixels arranged in multiple rows along a first direction, wherein two adjacent sub-pixels in a row form a pixel group; one of the sub-pixels includes a pixel driving circuit coupled to at least one signal line, the pixel driving circuit including a designated transistor, the at least one signal line including a designated signal line, and the designated transistor coupled to the designated signal line; the display panel includes a substrate, a first active layer disposed on one side of the substrate, a designated gate metal layer disposed on the side of the first active layer away from the substrate, and a first source / drain metal layer disposed on the side of the designated gate metal layer away from the substrate. The first active layer includes an active layer pattern of a designated transistor, the active layer pattern of the designated transistor including an active layer first electrode pattern. In a pixel group, the active layer first electrode pattern of the designated transistor of one sub-pixel is connected to the active layer first electrode pattern of the designated transistor of another sub-pixel. The designated gate metal layer includes a designated signal line pattern of a designated signal line. The first source-drain metal layer includes a designated signal line bridging pattern. In a pixel group, the designated signal line bridging pattern is located in the area of ​​a sub-pixel, and the designated signal line bridging pattern is connected to the active layer first electrode pattern of the designated transistor of one of the sub-pixels, and also connected to the designated signal line pattern.

[0006] In some embodiments, in a pixel group, the active layer first electrode pattern of a designated transistor of one sub-pixel is connected to the active layer first electrode pattern of a designated transistor of another sub-pixel at a designated connection point, and a designated signal line bridging pattern is connected to the designated connection point.

[0007] In some embodiments, in a pixel group, the active layer patterns of designated transistors of two sub-pixels are mirror-symmetrical, and the designated connection point is located on the mirror symmetry axis of the active layer patterns of designated transistors of the two sub-pixels; the designated signal line pattern extends along a first direction and passes through the area where the two sub-pixels are located.

[0008] In some embodiments, the width of the specified signal line bridging pattern is greater than a set width.

[0009] In some embodiments, the pixel driving circuit further includes other transistors besides the designated transistor; the first active layer also includes active layer patterns of other transistors; the active layer patterns of other transistors include active layer channel patterns; the active layer pattern of the designated transistor includes an active layer channel pattern, and the aspect ratio of the active layer channel pattern of the designated transistor is greater than the aspect ratio of the active layer channel patterns of the other transistors.

[0010] In some embodiments, the designated transistor includes a third reset transistor, the designated signal line includes a third initialization signal line, and the third reset transistor is coupled to the third initialization signal line; the first active layer includes an active layer pattern of the third reset transistor, and the active layer pattern of the third reset transistor includes an active layer first electrode pattern; the designated gate metal layer includes a third initialization signal line pattern of the third initialization signal line; the designated signal line bridging pattern includes a third initialization signal line bridging pattern, and the first source-drain metal layer includes a third initialization signal line bridging pattern.

[0011] In some embodiments, the signal line further includes a first initialization signal line; the designated gate metal layer further includes a first initialization signal line pattern of the first initialization signal line; the first initialization signal line pattern extends along a first direction and passes through the region where two sub-pixels are located in a pixel group; the third initialization signal line bridging pattern overlaps with the first initialization signal line pattern.

[0012] In some embodiments, the pixel driving circuit further includes a compensation transistor, and the signal line further includes a first power signal line; the display panel further includes a second active layer disposed between the first active layer and the designated gate metal layer, and a second source drain metal layer disposed on the side of the first source drain metal layer away from the substrate; the second active layer includes an active layer pattern of the compensation transistor; the second source drain metal layer includes a first power signal line pattern of the first power signal line, the first power signal line pattern including a block pattern, and the orthographic projection of the active layer pattern of the compensation transistor on the substrate is located within the orthographic projection of the block pattern of the first power signal line pattern on the substrate.

[0013] In some embodiments, the first power signal line pattern further includes a strip pattern connected to the block pattern, the width of which is 3.5µm to 5µm.

[0014] In some embodiments, the pixel driving circuit further includes a driving transistor, and the first active layer includes an active layer pattern of the driving transistor; the display panel further includes a bottom metal layer disposed on the side of the first active layer near the substrate; the bottom metal layer includes a bottom metal protection pattern, and the orthographic projection of the active layer pattern of the driving transistor on the substrate is located within the orthographic projection of the bottom metal protection pattern on the substrate; the bottom metal protection pattern is connected to a first power signal line pattern of the second source / drain metal layer.

[0015] In some embodiments, the display panel further includes an anode layer disposed on the side of the driving circuit layer away from the substrate; the anode layer includes a first anode and a second anode, the first anode is connected to the pixel driving circuit of a sub-pixel in the pixel group, and the second anode is connected to the pixel driving circuit of another sub-pixel in the pixel group; the first anode is disposed above the block pattern of the first power signal line pattern, and the ratio of the overlapping area of ​​the first anode and the block pattern to the area of ​​the first anode is greater than a set threshold.

[0016] In some embodiments, the substrate includes at least two flexible substrate layers and at least two buffer layers.

[0017] On the other hand, a display device is provided, including a display panel as described in any of the above embodiments. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in this application, the accompanying drawings used in some embodiments of this application will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this application, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this application.

[0019] Figure 1 is a plan view of a display panel according to some embodiments;

[0020] Figure 2 is a cross-sectional view of a display panel according to some embodiments;

[0021] Figure 3 is a pixel driving circuit diagram of some embodiments;

[0022] Figure 4 is a plan view of the film layer stacking of a display panel according to some embodiments;

[0023] Figure 5 is a plan view of the film layer stacking of another display panel according to some embodiments;

[0024] Figure 6 is a plan view of the film layer stacking of another display panel according to some embodiments;

[0025] Figure 7 is a plan view of the film layer stacking of another display panel according to some embodiments;

[0026] Figure 8 is a plan view of the film layer stacking of another display panel according to some embodiments;

[0027] Figure 9 is a plan view of the film layer stacking of another display panel according to some embodiments;

[0028] Figure 10 is a plan view of the film layer stacking of another display panel according to some embodiments;

[0029] Figure 11 is a plan view of the film layer stacking of another display panel according to some embodiments;

[0030] Figure 12 is a plan view of the film layer stacking of another display panel according to some embodiments;

[0031] Figure 13 is a plan view of the film layer stacking of another display panel according to some embodiments;

[0032] Figure 14 is a plan view of the film layer stacking of another display panel according to some embodiments;

[0033] Figure 15 is a layout diagram of the Aging process in some embodiments;

[0034] Figure 16 is a plan view of the film layer stacking of another display panel according to some embodiments;

[0035] Figure 17 is a plan view of the film layer stacking of another display panel according to some embodiments;

[0036] Figure 18 is a cross-sectional view of the film stacking in Figure 17;

[0037] Figure 19 is a plan view of the film layer stacking of another display panel according to some embodiments;

[0038] Figure 20 is a cross-sectional view of the film stacking in Figure 19;

[0039] Figure 21 is a plan view of the film layer stacking of another display panel according to some embodiments;

[0040] Figure 22 is a cross-sectional view of the film stacking in Figure 21;

[0041] Figure 23 is a plan view of the film layer stacking of another display panel according to some embodiments;

[0042] Figure 24 is a cross-sectional view of the film stacking in Figure 23;

[0043] Figure 25 is a plan view of the film layer stacking of another display panel according to some embodiments;

[0044] Figure 26 is a cross-sectional view of the film stacking in Figure 25;

[0045] Figure 27 is a plan view of the film layer stacking of another display panel according to some embodiments;

[0046] Figure 28 is a cross-sectional view of the film stacking in Figure 27;

[0047] Figure 29 is a plan view of the film layer stacking of another display panel according to some embodiments;

[0048] Figure 30 is a cross-sectional view of the film stacking in Figure 29;

[0049] Figure 31 is a plan view of the film layer stacking of another display panel according to some embodiments;

[0050] Figure 32 is a cross-sectional view of the film stacking in Figure 31;

[0051] Figure 33 is a cross-sectional view along section line AA in Figure 31;

[0052] Figure 34 is a cross-sectional view along section line BB in Figure 31;

[0053] Figure 35 is a plan view of the film layer stacking of another display panel according to some embodiments;

[0054] Figure 36 is a cross-sectional view of the film stacking in Figure 35;

[0055] Figure 37 is a plan view of the film layer stacking of another display panel according to some embodiments;

[0056] Figure 38 is a cross-sectional view of the film stacking in Figure 37;

[0057] Figure 39 is a plan view of the film layer stacking of another display panel according to some embodiments;

[0058] Figure 40 is a cross-sectional view of the film stacking in Figure 39;

[0059] Figure 41 is a plan view of the film layer stacking of another display panel according to some embodiments;

[0060] Figure 42 is a cross-sectional view of the film stacking in Figure 41;

[0061] Figure 43 is a plan view of the film layer stacking of another display panel according to some embodiments;

[0062] Figure 44 is a cross-sectional view of the film stacking in Figure 43;

[0063] Figure 45 is a plan view of the film layer stacking of another display panel according to some embodiments;

[0064] Figure 46 is a plan view of the film layer stacking of another display panel according to some embodiments;

[0065] Figure 47 is a stacked cross-sectional view of the substrates in some embodiments;

[0066] Figure 48 is a plan view of a display device according to some embodiments. Detailed Implementation

[0067] The technical solutions in some embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this application are within the scope of protection of this application.

[0068] Unless the context otherwise requires, throughout the specification and claims, the term "comprise" and its other forms, such as the third-person singular "comprises" and the present participle "comprising," are interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiments," "example," "specific example," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this application. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0069] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this application, unless otherwise stated, "a plurality of" means two or more.

[0070] In describing some embodiments, the terms "coupled" and "connected," and their derivative expressions, may be used. For example, the term "connected" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact with each other. Similarly, the term "coupled" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact. However, the terms "coupled" or "communicatively coupled" may also refer to two or more components that do not have direct contact with each other but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content of this document.

[0071] "At least one of A, B and C" has the same meaning as "at least one of A, B or C", both including the following combinations of A, B and C: only A, only B, only C, combinations of A and B, combinations of A and C, combinations of B and C, and combinations of A, B and C.

[0072] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0073] It should be understood that when a layer or element is referred to as being on another layer or substrate, it can mean that the layer or element is directly on the other layer or substrate, or that there is an intermediate layer between the layer or element and the other layer or substrate.

[0074] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as being limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched areas shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the areas of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0075] With the development of display technology, there are many types of display panels. For example, display panels can be organic light-emitting diode (OLED) display panels, micro organic light-emitting diode (Micro OLED) display panels, quantum dot light-emitting diode (QLED) display panels, mini light-emitting diode (Mini LED) display panels, or micro light-emitting diode (Micro LED) display panels, etc. Some embodiments of this application are described using OLED display panels as examples.

[0076] OLEDs are current-driven organic light-emitting devices that emit light through the injection and recombination of charge carriers. The luminous intensity is directly proportional to the injected current. Under the influence of an electric field, holes generated at the anode and electrons at the cathode move and are injected into the hole transport layer and electron transport layer, respectively, migrating to the emissive layer. When these two electrons meet in the emissive layer, they generate excitons, which excite the light-emitting molecules to produce visible light. Depending on their formulation, these molecules produce the three primary colors of red, green, and blue (RGB), constituting the basic colors. OLED display panels 1000 have advantages such as high brightness, high efficiency, wide viewing angle, self-emissive nature, all-solid-state operation, ultra-thin and ultra-lightweight design, simple manufacturing process, fast response speed, full-color display capability, and good machinability. They are increasingly widely used in display products such as mobile phones, tablets, computers, and televisions. With the increasing application of OLED display panels in mobile phones, computers, and tablets, the requirements for their display performance are becoming increasingly stringent.

[0077] In order to achieve better display effects, the pixel driving circuit 10 used to drive OLED light emission in the OLED display panel 1000 is constantly optimized. However, the increasingly complex and dense pixel driving circuit 10 has also brought many problems, such as pixel defects such as non-extinguishing points (bright spots) and / or non-emitting points (dark spots) in the OLED display panel 1000.

[0078] For example, in a full-color display with red, green, and blue LEDs, a sub-pixel in one area may not emit light, appearing as a dark spot in each LED display.

[0079] The following describes the specific settings for display panel 1000.

[0080] In some embodiments, as shown in FIG1, the display panel 1000 includes a plurality of sub-pixels P, and each sub-pixel P includes a pixel driving circuit 10 and a driven element 20 coupled to the pixel driving circuit 10. In some examples, as shown in FIG3, the pixel driving circuit 10 includes a first transistor T1 (first reset transistor), a second transistor T2 (compensation transistor), a third transistor T3 (driving transistor), a fourth transistor T4 (writing transistor), a fifth transistor T5 (first light-emitting control transistor), a sixth transistor T6 (second light-emitting control transistor), a seventh transistor T7 (second reset transistor), and a coupling capacitor Cst. In some examples, the pixel driving circuit 10 further includes an eighth transistor T8 (third reset transistor).

[0081] The first transistor T1 is a P-type transistor. The first terminal T11 of the first transistor T1 is coupled to the first initialization signal line Vinit1, the gate T13 of the first transistor T1 is coupled to the first reset signal line Reset1, and the second terminal T12 of the first transistor T1 is coupled to the third node N3.

[0082] The second transistor T2 is an N-type transistor. The first terminal T21 of the second transistor T2 is coupled to the first node N1. The first gate T23 of the second transistor T2 is coupled to the first gate signal line Gate1. The second gate T24 of the second transistor T2 is coupled to the second gate signal line Gate2. The second terminal T22 of the second transistor T2 is coupled to the third node N3.

[0083] The third transistor T3 is a P-type transistor. The first terminal T31 of the third transistor T3 is coupled to the second node N2, the gate T33 of the third transistor T3 is coupled to the first node N1, and the second terminal T32 of the third transistor T3 is coupled to the third node N3.

[0084] The fourth transistor T4 is a P-type transistor. The first terminal T41 of the fourth transistor T4 is coupled to the data signal line Data, the gate T43 of the fourth transistor T4 is coupled to the third gate signal line Gate3, and the second terminal T42 of the fourth transistor T4 is coupled to the second node N2.

[0085] The fifth transistor T5 is a P-type transistor. The first terminal T51 of the fifth transistor T5 is coupled to the first power supply signal line VDD, the gate T53 of the fifth transistor T5 is coupled to the light emission control signal line EM, and the second terminal T52 of the fifth transistor T5 is coupled to the second node N2.

[0086] The sixth transistor T6 is a P-type transistor. The first terminal T61 of the sixth transistor T6 is coupled to the third node N3. The gate T63 of the sixth transistor T6 is coupled to the light emission control signal line EM. The second terminal T62 of the sixth transistor T6 is coupled to the fourth node N4.

[0087] The seventh transistor T7 is a P-type transistor. The first terminal T71 of the seventh transistor T7 is coupled to the second initialization signal line Vinit2, the gate T73 of the seventh transistor T7 is coupled to the second reset signal line Reset2, and the second terminal T72 of the seventh transistor T7 is coupled to the fourth node N4.

[0088] The eighth transistor T8 is a P-type transistor. The first terminal T81 of the eighth transistor T8 is coupled to the third initialization signal line Vinit3, the gate T83 of the eighth transistor T8 is coupled to the second reset signal line Reset2, and the second terminal T82 of the eighth transistor T8 is coupled to the second node N2.

[0089] The first plate Cst1 of the coupling capacitor Cst is coupled to the first power signal line VDD, and the second plate Cst2 of the coupling capacitor Cst is coupled to the first node N1.

[0090] The first end 21 of the driven element 20 is coupled to the fourth node N4 to realize the coupling between the driven element 20 and the pixel driving circuit 10, and the second end 22 of the driven element 20 is coupled to the second power signal line VSS.

[0091] The following describes the specific film layer settings of the pixel driving circuit 10 in the display panel 1000 as shown in FIG3 in some embodiments.

[0092] In some embodiments, as shown in FIG1, the display panel 1000 includes a display area AA and a peripheral area BB located on at least one side of the display area AA. The display area AA is provided with a plurality of sub-pixels P. Each sub-pixel P includes a pixel driving circuit 10 and a driveable element 20 coupled to the pixel driving circuit 10.

[0093] For example, as shown in FIG1, the display panel 1000 includes a plurality of sub-pixels P, which are the smallest units for displaying images on the display panel 1000. Each sub-pixel P can display a single color, such as red (R), green (G), or blue (B). The plurality of sub-pixels P can be arranged in an array, for example, the plurality of sub-pixels P are arranged in multiple rows along a first direction X, or the plurality of sub-pixels P are arranged in multiple columns along a second direction Y. Each sub-pixel P includes a driven element 20 and a pixel driving circuit 10 for driving the driven element 20 to emit light. 10 can be composed of multiple transistors and at least one capacitor connected together; in each sub-pixel P, the element to be driven 20 is electrically connected to the corresponding pixel driving circuit 10 below it. Specifically, the anode of the element to be driven 20 is electrically connected to the corresponding pixel driving circuit 10. In this way, the first power signal input to the display panel 1000 is transmitted to the anode of the element to be driven 20 through the pixel driving circuit 10. At the same time, the second power signal is transmitted to the cathode of the element to be driven 20, thereby forming an electric field between the anode and cathode of the element to be driven 20, causing the element to be driven 20 to emit light.

[0094] In some embodiments, as shown in FIG2, the display panel 1000 may include, for example, a substrate 100, a driving circuit layer 200, a driving element layer 300, and an encapsulation layer 400 stacked sequentially. The substrate 100 provides a support base for other film layer structures of the display panel 1000; that is, other film layer structures in the display panel 1000, such as the driving circuit layer 200, the driving element layer 300, and the encapsulation layer 400, are fabricated on the substrate 100. The substrate 100 can be a rigid substrate, and the material of the rigid substrate can be, for example, a rigid material such as glass, quartz, or sapphire. The substrate 100 can also be a flexible substrate, and the material of the flexible substrate can be, for example, a flexible material such as polyimide (PI) or saturated polyester (PET). The driving circuit layer 200 is used to house the pixel driving circuit 10. The driving element layer 300 is used to house the element to be driven 20, which is, for example, a light-emitting device. The encapsulation layer 400 is used to protect the display panel 1000 and prevent moisture in the air from entering the interior of the display panel 1000 and damaging it.

[0095] In some embodiments, the driving circuit layer 200 of the display panel 1000 includes a first active layer 201, a first gate insulating layer 202, a first gate metal layer 203, a second gate insulating layer 204, a second gate metal layer 205, a first interlayer dielectric layer 206, a second active layer 207, a third gate insulating layer 208, a third gate metal layer 209, a second interlayer dielectric layer 210, a first source / drain metal layer 211, a passivation layer 212, a first planarization layer 213, a second source / drain metal layer 214, and a second planarization layer 215, which are stacked sequentially. The driving element layer 300 of the display panel 1000 includes an anode layer 301, a pixel defining layer 302, a light emitting layer 303, and a cathode layer 304, which are stacked sequentially.

[0096] The following describes the pattern of each film layer of the display panel 1000, using the structure included in a pixel driving circuit 10 as an example.

[0097] For example, as shown in FIG4, the driving circuit layer 200 of the display panel 1000 includes a first active layer 201, which is disposed on one side of the substrate 100, such as above. The first active layer 201 includes an active layer pattern of a first transistor T1, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and an eighth transistor T8.

[0098] As shown in Figure 4, the active layer pattern 2011 of the first transistor T1 includes an active layer first electrode pattern 2011-1, an active layer channel pattern 2011-3, and an active layer second electrode pattern 2011-2 connected in sequence; the active layer pattern 2013 of the third transistor T3 includes an active layer first electrode pattern 2013-1, an active layer channel pattern 2013-3, and an active layer second electrode pattern 2013-2 connected in sequence; the active layer pattern 2014 of the fourth transistor T4 includes an active layer first electrode pattern 2014-1, an active layer channel pattern 2014-3, and an active layer second electrode pattern 2014-2 connected in sequence; and the active layer pattern 2015 of the fifth transistor T5 includes an active layer first electrode pattern 2011-2, an active layer channel pattern 2011-3, and an active layer second electrode pattern 2011-2 connected in sequence. The active layer pattern 2016 of the sixth transistor T6 includes the active layer first electrode pattern 2016-1, the active layer channel pattern 2016-3, and the active layer second electrode pattern 2016-2 connected in sequence; the active layer pattern 2017 of the seventh transistor T7 includes the active layer first electrode pattern 2017-1, the active layer channel pattern 2017-3, and the active layer second electrode pattern 2017-2 connected in sequence; the active layer pattern 2018 of the eighth transistor T8 includes the active layer first electrode pattern 2018-1, the active layer channel pattern 2018-3, and the active layer second electrode pattern 2018-2 connected in sequence.

[0099] For example, as shown in FIG5, the driving circuit layer 200 of the display panel 1000 further includes a first gate metal layer 203, which is disposed on the side of the first active layer 201 away from the substrate 100. The first gate metal layer 203 includes a first reset signal line pattern 2031 extending along the first direction X, a second reset signal line pattern 2032 extending along the first direction X, a light emission control signal line pattern 2033 extending along the first direction X, a third gate signal line pattern 2034 extending along the first direction X, and a gate pattern 2035 of the third transistor T3.

[0100] As shown in Figure 5, the first reset signal line pattern 2031 and the active layer channel pattern 2011-3 of the first transistor T1 overlap in a direction perpendicular to the substrate 100. The overlapping portion of the first reset signal line pattern 2031 and the active layer channel pattern 2011-3 of the first transistor T1 serves as the gate pattern 2031-1 of the first transistor T1.

[0101] As shown in Figure 5, the second reset signal line pattern 2032 overlaps with the active layer channel pattern 2017-3 of the seventh transistor T7 and the active layer channel pattern 2018-3 of the eighth transistor T8 in a direction perpendicular to the substrate 100. The portion of the second reset signal line pattern 2032 that overlaps with the active layer channel pattern 2017-3 of the seventh transistor T7 serves as the gate pattern 2032-1 of the seventh transistor T7; the portion of the second reset signal line pattern 2032 that overlaps with the active layer channel pattern 2018-3 of the eighth transistor T8 serves as the gate pattern 2032-2 of the eighth transistor T8.

[0102] As shown in Figure 5, the light-emitting control signal line pattern 2033 overlaps with the active layer channel pattern 2015-3 of the fifth transistor T5 and the active layer channel pattern 2016-3 of the sixth transistor T6 in a direction perpendicular to the substrate 100. The portion of the light-emitting control signal line pattern 2033 that overlaps with the active layer channel pattern 2015-3 of the fifth transistor T5 serves as the gate T53 pattern 2033-2 of the fifth transistor T5; the portion of the light-emitting control signal line pattern 2033 that overlaps with the active layer channel pattern 2016-3 of the sixth transistor T6 serves as the gate T63 pattern 2033-1 of the sixth transistor T6.

[0103] As shown in Figure 5, the third gate signal line pattern 2034 and the active layer channel pattern 2014-3 of the fourth transistor T4 overlap in a direction perpendicular to the substrate 100. The overlapping portion of the third gate signal line pattern 2034 and the active layer channel pattern 2014-3 of the fourth transistor T4 serves as the gate pattern 2034-1 of the fourth transistor T4.

[0104] As shown in Figure 5, the gate pattern 2035 of the third transistor T3 and the active layer channel pattern 2013-3 of the third transistor T3 overlap in a direction perpendicular to the substrate 100.

[0105] It should be noted that the overlap mentioned in some examples refers to the fact that, in the direction perpendicular to the substrate 100, a portion of the pattern of one film layer is directly opposite to a portion of the pattern of another film layer. Directly opposite can be interpreted as the orthographic projection of a portion of the pattern of one film layer on the substrate 100 partially overlapping with the orthographic projection of a portion of the pattern of another film layer on the substrate 100. The portion directly opposite is the overlapping portion. There may be other film layers, such as insulating layers, between the portion of the pattern of one film layer and the portion of the pattern of another film layer.

[0106] For example, as shown in FIG6, the driving circuit layer 200 of the display panel 1000 further includes a second gate metal layer 205, which is disposed on the side of the first gate metal layer 203 away from the substrate 100. The second gate metal layer 205 includes a first electrode pattern 2052 of the coupling capacitor Cst and a first gate signal line pattern 2051 extending along the first direction X. The first electrode pattern 2052 of the coupling capacitor Cst is disposed opposite to the gate pattern 2035 of the third transistor T3, and the gate pattern 2035 of the third transistor T3 can serve as the second electrode pattern of the coupling capacitor Cst.

[0107] It should be noted that the orthographic arrangement can be interpreted as the orthographic projection of a portion of the pattern of one film layer onto the substrate 100 partially overlapping with the orthographic projection of a portion of the pattern of another film layer onto the substrate 100. There may be other film layers, such as insulating layers, between the portion of the pattern of one film layer and the portion of the pattern of another film layer.

[0108] For example, as shown in FIG7, the driving circuit layer 200 of the display panel 1000 further includes a second active layer 207, which is disposed on the side of the second gate metal layer 205 away from the substrate 100. The second active layer 207 includes an active layer pattern 2071 of the second transistor T2, which includes an active layer first electrode pattern 2071-1, an active layer channel pattern 2071-3, and an active layer second electrode pattern 2071-2 connected in sequence.

[0109] As shown in Figure 7, the active layer channel pattern 2071-3 of the second transistor T2 overlaps with the first gate signal line pattern 2051 of the second gate metal layer 205 in a direction perpendicular to the substrate 100. The portion of the first gate signal line pattern 2051 that overlaps with the active layer channel pattern 2071-3 of the second transistor T2 serves as the first gate pattern 2051-1 of the second transistor T2.

[0110] For example, as shown in FIG8, the driving circuit layer 200 of the display panel 1000 further includes a third gate metal layer 209, which is disposed on the side of the second active layer 207 away from the substrate 100. The third gate metal layer 209 includes a first initialization signal line pattern 2092 extending along the first direction X, a second initialization signal line pattern 2091 extending along the first direction X, a third initialization signal line pattern 2093 extending along the first direction X, and a second gate signal line pattern 2094 extending along the first direction X.

[0111] As shown in Figure 8, the first initialization signal line pattern 2092 corresponds to the second reset signal line pattern 2032; the second initialization signal line pattern 2091 corresponds to the first reset signal line pattern 2031; the third initialization signal line pattern 2093 corresponds to the light emission control signal line pattern 2033; and the second gate signal line pattern 2094 corresponds to the first gate signal line pattern 2051. The active layer channel pattern 2071-3 of the second transistor T2 overlaps with the second gate signal line pattern 2094 in a direction perpendicular to the substrate 100. The overlapping portion of the second gate signal line pattern 2094 and the active layer channel pattern 2071-3 of the second transistor T2 serves as the second gate pattern 2094-1 of the second transistor T2.

[0112] For example, as shown in FIG9, the driving circuit layer 200 of the display panel 1000 further includes a second interlayer dielectric layer 210. A drilling process is performed on the second interlayer dielectric layer 210 to form vias 2101, 2102, 2102, 2103, 2104, 2104, 2104, and 2105, respectively, penetrating the first interlayer dielectric layer 202, the second interlayer dielectric layer 204, the first interlayer dielectric layer 206, the third interlayer dielectric layer 208, and the second interlayer dielectric layer 210.

[0113] For example, as shown in FIG10, the driving circuit layer 200 of the display panel 1000 further includes a first source / drain metal layer 211, which is disposed on the side of the second interlayer dielectric layer 210 away from the substrate 100.

[0114] As shown in Figure 10, and in conjunction with Figures 4 and 9, the first source / drain metal layer 211 includes a first electrode pattern 2111-1 and a second electrode pattern 2111-2 of the first transistor T1; the first electrode pattern 2111-1 of the first transistor T1 passes through a via 2101 penetrating the first gate insulating layer 202, the second gate insulating layer 204, the first interlayer dielectric layer 206, the third gate insulating layer 208, and the second interlayer dielectric layer 210, and connects with the first electrode pattern 2111-1 of the active layer of the first transistor T1. The first electrode pattern 2111-1 of the first transistor T1 is connected to the first initialization signal line pattern 2092 through a via 2105 penetrating the second interlayer dielectric layer 210; the second electrode pattern 2111-2 of the first transistor T1 is connected to the active layer second electrode pattern 2011-2 of the first transistor T1 through a via 2101 penetrating the first gate insulating layer 202, the second gate insulating layer 204, the first interlayer dielectric layer 206, the third gate insulating layer 208, and the second interlayer dielectric layer 210.

[0115] As shown in Figure 10, and in conjunction with Figures 4 and 9, the first source / drain metal layer 211 includes a first electrode pattern 2112-1 and a second electrode pattern 2112-2 of the second transistor T2; the first electrode pattern 2112-1 of the second transistor T2 is connected to the first electrode pattern 2071-1 of the active layer of the second transistor T2 through a via 2102 penetrating the third gate insulating layer 208 and the second interlayer dielectric layer 210, and the first electrode pattern 2112-1 of the second transistor T2 is connected through a via 2102 penetrating the second gate insulating layer 204, The via 2104 of the first interlayer dielectric layer 206, the third gate insulating layer 208, and the second interlayer dielectric layer 210 is connected to the gate pattern 2035 of the third transistor T3; the second electrode pattern 2112-2 of the second transistor T2 is connected to the active layer second electrode pattern 2071-2 of the second transistor T2 through the via 2102 penetrating the third gate insulating layer 208 and the second interlayer dielectric layer 210; the second electrode pattern 2112-2 of the second transistor T2 is connected to the second electrode pattern 2111-2 of the first transistor T1.

[0116] As shown in Figure 10, and in conjunction with Figures 4 and 9, the first source / drain metal layer 211 includes a first electrode pattern 2113-1 and a second electrode pattern 2113-2 of the third transistor T3. The first electrode pattern 2113-1 of the third transistor T3 is connected to the first electrode pattern 2013-1 of the active layer of the third transistor T3 through a via 2101 penetrating the first gate insulating layer 202, the second gate insulating layer 204, the first interlayer dielectric layer 206, the third gate insulating layer 208, and the second interlayer dielectric layer 210. The second electrode pattern 2113-2 of the third transistor T3 is connected to the second electrode pattern 2013-2 of the active layer of the third transistor T3 through a via 2101 penetrating the first gate insulating layer 202, the second gate insulating layer 204, the first interlayer dielectric layer 206, the third gate insulating layer 208, and the second interlayer dielectric layer 210. The second electrode pattern 2113-2 of the third transistor T3 is connected to the second electrode pattern 2112-2 of the second transistor T2.

[0117] As shown in Figure 10, and in conjunction with Figures 4 and 9, the first source / drain metal layer 211 includes a first electrode pattern 2114-1 and a second electrode pattern 2114-2 of the fourth transistor T4. The first electrode pattern 2114-1 of the fourth transistor T4 is connected to the first electrode pattern 2014-1 of the active layer of the fourth transistor T4 through a via 2101 penetrating the first gate insulating layer 202, the second gate insulating layer 204, the first interlayer dielectric layer 206, the third gate insulating layer 208, and the second interlayer dielectric layer 210. The second electrode pattern 2114-2 of the fourth transistor T4 is connected to the second electrode pattern 2014-2 of the active layer of the fourth transistor T4 through a via 2101 penetrating the first gate insulating layer 202, the second gate insulating layer 204, the first interlayer dielectric layer 206, the third gate insulating layer 208, and the second interlayer dielectric layer 210. The second electrode pattern 2114-2 of the fourth transistor T4 is connected to the first electrode pattern 2113-1 of the third transistor T3.

[0118] As shown in Figure 10, and in conjunction with Figures 4 and 9, the first source / drain metal layer 211 includes a first electrode pattern 2115-1 and a second electrode pattern 2115-2 of the fifth transistor T5. The first electrode pattern 2115-1 of the fifth transistor T5 is connected to the first electrode pattern 2015-1 of the active layer of the fifth transistor T5 through a via 2101 penetrating the first gate insulating layer 202, the second gate insulating layer 204, the first interlayer dielectric layer 206, the third gate insulating layer 208, and the second interlayer dielectric layer 210. The second electrode pattern 2115-2 of the fifth transistor T5 is connected to the second electrode pattern 2015-2 of the active layer of the fifth transistor T5 through a via 2101 penetrating the first gate insulating layer 202, the second gate insulating layer 204, the first interlayer dielectric layer 206, the third gate insulating layer 208, and the second interlayer dielectric layer 210. The second electrode pattern 2115-2 of the fifth transistor T5 is connected to the second electrode pattern 2114-2 of the fourth transistor T4.

[0119] As shown in Figure 10, and in conjunction with Figures 4 and 9, the first source / drain metal layer 211 includes a first electrode pattern 2116-1 and a second electrode pattern 2116-2 of the sixth transistor T6. The first electrode pattern 2116-1 of the sixth transistor T6 is connected to the first electrode pattern 2016-1 of the active layer of the sixth transistor T6 through a via 2101 penetrating the first gate insulating layer 202, the second gate insulating layer 204, the first interlayer dielectric layer 206, the third gate insulating layer 208, and the second interlayer dielectric layer 210, and the first electrode pattern 2116-1 of the sixth transistor T6 is connected to the second electrode pattern 2113-2 of the third transistor T3. The second electrode pattern 2116-2 of the sixth transistor T6 is connected to the second electrode pattern 2016-2 of the active layer of the sixth transistor T6 through a via 2101 penetrating the first gate insulating layer 202, the second gate insulating layer 204, the first interlayer dielectric layer 206, the third gate insulating layer 208, and the second interlayer dielectric layer 210.

[0120] As shown in Figure 10, and in conjunction with Figures 4 and 9, the first source / drain metal layer 211 includes a first electrode pattern 2117-1 and a second electrode pattern 2117-2 of the seventh transistor T7. The first electrode pattern 2117-1 of the seventh transistor T7 is connected to the first electrode pattern 2117-1 of the active layer of the seventh transistor T7 through a via 2101 penetrating the first gate insulating layer 202, the second gate insulating layer 204, the first interlayer dielectric layer 206, the third gate insulating layer 208, and the second interlayer dielectric layer 210. -1 is connected to the second initialization signal line pattern 2091 through a via 2105 penetrating the second interlayer dielectric layer 210; the second electrode pattern 2117-2 of the seventh transistor T7 is connected to the active layer second electrode pattern 2017-2 of the seventh transistor T7 through a via 2101 penetrating the first gate insulating layer 202, the second gate insulating layer 204, the first interlayer dielectric layer 206, the third gate insulating layer 208, and the second interlayer dielectric layer 210; the second electrode pattern 2117-2 of the seventh transistor T7 is connected to the second electrode pattern 2116-2 of the sixth transistor T6.

[0121] As shown in Figure 10, and in conjunction with Figures 4 and 9, the first source / drain metal layer 211 includes a first electrode pattern 2118-1 and a second electrode pattern 2118-2 of the eighth transistor T8. The first electrode pattern 2118-1 of the eighth transistor T8 is connected to the first electrode pattern 2018-1 of the active layer of the eighth transistor T8 through a via 2101 penetrating the first gate insulating layer 202, the second gate insulating layer 204, the first interlayer dielectric layer 206, the third gate insulating layer 208, and the second interlayer dielectric layer 210. The second electrode pattern 2118-2 of the eighth transistor T8 is connected to the second electrode pattern 2018-2 of the active layer of the eighth transistor T8 through a via 2101 penetrating the first gate insulating layer 202, the second gate insulating layer 204, the first interlayer dielectric layer 206, the third gate insulating layer 208, and the second interlayer dielectric layer 210. The second electrode pattern 2118-2 of the eighth transistor T8 is connected to the second electrode pattern 2115-2 of the fifth transistor T5.

[0122] As shown in Figure 10 and in conjunction with Figure 9, the first source / drain metal layer 211 includes a first power signal line bridging pattern 2119; the first power signal line bridging pattern 2119 is connected to the first electrode pattern 2115-1 of the fifth transistor T5, and the first power signal line bridging pattern 2119 is connected to the first electrode pattern 2052 of the coupling capacitor Cst through a via 2103 penetrating the first interlayer dielectric layer 206, the third gate insulating layer 208, and the second interlayer dielectric layer 210.

[0123] As shown in Figure 10 and in conjunction with Figure 9, the first source / drain metal layer 211 includes a third initialization signal line bridging pattern 21110; the first pole pattern 2118-1 of the eighth transistor T8 is connected to the third initialization signal line bridging pattern 21110, and the third initialization signal line bridging pattern 21110 is connected to the third initialization signal line pattern 2093 through a via 2105 penetrating the second interlayer dielectric layer 210.

[0124] As shown in Figure 10 and in conjunction with Figure 9, the first source / drain metal layer 211 includes a vertical third initialization signal line pattern 21111 extending along the second direction Y; the vertical third initialization signal line pattern 21111 is connected to the third initialization signal line pattern 2093 through a via 2105 penetrating the second interlayer dielectric layer 210.

[0125] It should be noted that when one pattern in a certain film layer is connected to another pattern, the two patterns can be regarded as the same pattern. For example, if the first electrode pattern 2118-1 of the eighth transistor T8 on the first source-drain metal layer 211 is connected to the third initialization signal line bridging pattern 21110, it can be understood that the first electrode pattern 2118-1 of the eighth transistor T8 on the first source-drain metal layer 211 and the third initialization signal line bridging pattern 21110 are the same pattern.

[0126] For example, as shown in FIG11, the driving circuit layer 200 of the display panel 1000 further includes a passivation layer 212 and a first planarization layer 213. A drilling process is performed on the first planarization layer 213 to form a via 2131 that penetrates the passivation layer 212 and the first planarization layer 213.

[0127] For example, as shown in FIG12, the driving circuit layer 200 of the display panel 1000 further includes a second source / drain metal layer 214, which is disposed on the side of the first source / drain metal layer 211 away from the substrate 100. The second source / drain metal layer 214 includes a data signal line pattern 2143 extending along the second direction Y, a first power signal line pattern 2141 extending along the second direction Y, and an anode conductor pattern 2142.

[0128] As shown in Figure 12, and in conjunction with Figures 10 and 11, the data signal line pattern 2143 is connected to the first electrode pattern 2114-1 of the fourth transistor T4 through a via 2131 penetrating the passivation layer 212 and the first planarization layer 213; the first power signal line pattern 2141 is connected to the first power signal line bridging pattern 2119 through a via 2131 penetrating the passivation layer 212 and the first planarization layer 213; and the anode conductor pattern 2142 is connected to the second electrode pattern 2116-2 of the sixth transistor T6 through a via 2131 penetrating the passivation layer 212 and the first planarization layer 213.

[0129] For example, as shown in FIG13, the driving element layer 300 of the display panel 1000 includes an anode layer 301; the anode layer 301 includes a plurality of anode patterns 3010, and an anode pattern 3010 is connected to an anode guide pattern 2142 through a via through the second planar layer 215.

[0130] For example, as shown in FIG14, the driving element layer 300 of the display panel 1000 further includes a pixel defining layer 302; the pixel defining layer 302 includes a plurality of openings 3021, one opening 3021 exposing an anode pattern 3010.

[0131] For example, the driving element layer 300 of the display panel 1000 also includes a light-emitting layer 303, which includes a plurality of light-emitting patterns, one of which is located within an opening 3021.

[0132] For example, the driving element layer 300 of the display panel 1000 also includes a cathode layer 304, which is deposited on the side of the light-emitting layer 303 away from the substrate 100.

[0133] The above settings allow the pixel driving circuit 10, as shown in Figure 3, to be placed in the display panel 1000.

[0134] It should be noted that the film layer configuration of the display panel 1000 is not limited to the film layers described above. In some embodiments, multiple insulating layers may be included between adjacent metal layers; in other embodiments, one or more of the aforementioned metal layers may be deleted, or one or more metal layers may be added; in still other embodiments, as shown in FIG44, the driving element layer 300 of the display panel 1000 may further include spacers 305 disposed on the side of the pixel defining layer 302 away from the substrate 100. The film layer configuration of the display panel 1000 can be designed according to specific circumstances, and this application does not limit it.

[0135] When the display panel 1000 is not displaying an image, the driven element 20 in the sub-pixel P of the display panel 1000 is required to stop working. That is, the pixel driving circuit 10 in the sub-pixel P of the display panel 1000 is disconnected, and no current flows through the driven element 20 coupled to the pixel driving circuit 10. The pixel driving circuit 10 is controlled by the conduction or cutoff of the transistor. However, the transistor, such as the P-type transistor, may have leakage current in the cutoff state, that is, current still flows through the transistor in the cutoff state. When the leakage current is large enough to make the driven element 20 of the sub-pixel P work, the sub-pixel P of the display panel 1000 will be lit, forming a non-extinguishing point (bright spot) on the display panel 1000.

[0136] For example, as shown in Figure 3, when the display panel 1000 is not displaying an image, that is, when the pixel driving circuit 10 is in the non-light-emitting stage, the second transistor T2 and the sixth transistor T6 are cut off, the first node N1 is at a high voltage level, and the fourth node N4 is at a low voltage level. When the leakage current of the second transistor T2 and the sixth transistor T6 is too large, the current will flow through the driven element 20, causing the driven element 20 to start working, and the sub-pixel P will be lit, forming a bright spot on the display panel 1000; or when the leakage current of the fifth transistor T5, the third transistor T3 and the sixth transistor T6 is too large, the current will flow through the driven element 20, causing the driven element 20 to start working, and the sub-pixel P will be lit, forming an inextinguishable point (bright spot) on the display panel 1000.

[0137] In some embodiments, to avoid bright spots when the display panel 1000 is not displaying an image, an electrical aging process can be used to reduce the leakage current of the transistors, for example, reducing the leakage current of the P-type transistors so that the leakage current is not high enough to make the driven element 20 of the sub-pixel P work, thereby eliminating bright spots caused by excessive leakage current of the transistors and improving the stability of the transistors.

[0138] For example, the principle of reducing transistor leakage current using the Aging process is as follows: In the display panel 1000, the active layer, gate metal layer, and source / drain metal layers of the display panel 1000 are combined to form a transistor, such as a P-type transistor. The active layer includes an active layer source, an active layer channel region, and an active layer drain; the gate metal layer includes a gate, which is correspondingly disposed with the active layer channel region; the source / drain metal layer includes a source and a drain, with the source connected to the active layer source and the drain connected to the active layer drain. By applying a negative voltage to the drain of the transistor, such as a P-type transistor, and a positive voltage to the gate, electrons at the transistor drain are captured by the gate of the gate metal layer. Therefore, holes are induced in the active layer channel region to form a lightly doped drain (LDD) region, thereby reducing the gate-drain electric field and reducing the transistor leakage current.

[0139] For example, an Aging process can be used to reduce the leakage current of the P-type transistors in the pixel driving circuit 10 shown in FIG3, and the specific Aging process layout is shown in FIG15.

[0140] As shown in Figure 15, where Pattern represents the process layout, Vgh / Vgh-N represents the voltage of the high voltage signal, Vgl / Vgl-N represents the voltage of the low voltage signal, Vdd represents the voltage of the first power supply signal, Vss represents the voltage of the second power supply signal, Vint1 represents the voltage of the first initialization signal, Vint2 represents the voltage of the second initialization signal, Vint3 represents the voltage of the third initialization signal, Vdata represents the voltage of the data signal, and Time represents the time taken for the Aging process.

[0141] Specifically, row 1 in Figure 15 represents: performing the first Aging process on the first transistor T1 and the seventh transistor T7 respectively; the voltage Vgh / Vgh-N of the high voltage signal applied to the gate T13 of the first transistor T1 and the gate T73 of the seventh transistor T7 is 15V; the voltage Vgl / Vgl-N of the low voltage signal applied to the drain of the first transistor T1 and the drain of the seventh transistor T7 is -7V; the voltage Vdd of the first power supply signal is 7V; the voltage Vss of the second power supply signal is 7V; the voltage Vint1 of the first initialization signal is -15V; the voltage Vint2 of the second initialization signal is -15V; the voltage Vint3 of the third initialization signal is 4V; the voltage Vdata of the data signal is 4V; and the time taken for the Aging process is 15s.

[0142] The meaning of the rows containing numbers 2 to 10 in Figure 15 is the same as that of the row containing number 1, and will not be repeated here.

[0143] After performing an aging process on the relevant P-type transistors in the pixel driving circuit 10 shown in Figure 3, the leakage current in the pixel driving circuit 10 shown in Figure 3 is greatly reduced, the probability of bright spots in the display panel 1000 when no image is displayed is reduced, and the stability of the pixel driving circuit 10 shown in Figure 3 is improved. At the same time, when performing image display testing on the display panel 1000, the inventors of this disclosure discovered that non-light-emitting points (dark spots) appeared on the display panel 1000 when displaying an image. When observing the location of the non-light-emitting points (dark spots) on the display panel 1000 using an optical microscope, it can be clearly seen that the pixels at the location of the non-light-emitting points (dark spots) are obviously burned, thus causing burn-in type dark spots on the display panel 1000.

[0144] Regarding the cause of burn-in type dark spots, the inventors of this disclosure have discovered through research that the cause of pixel burn-in is likely a short circuit in the signal line of the pixel driving circuit 10, which leads to burn-in type dark spots appearing on the pixels of the display panel 1000.

[0145] The inventors of this disclosure analyzed the signal lines of each film layer in the driving circuit layer 200 of the display panel 1000. The analysis revealed that, as shown in Figure 3 and in conjunction with Figure 10, the first electrode T81 of the eighth transistor T8 is coupled to the third initialization signal line Vinit3. In the design of the driving circuit layer 200 of the display panel 1000, the third gate metal layer 209 includes a first initialization signal line pattern 2092 extending along the first direction X and a third initialization signal line pattern 2093 extending along the first direction X. The first source / drain metal layer 211 includes a first electrode pattern 2118-1 of the eighth transistor T8 and a third initialization signal line bridging pattern 21110. The first electrode pattern 2118-1 of the eighth transistor T8 is connected to the third initialization signal line bridging pattern 21110. The third initialization signal line bridging pattern 21110 is connected to the third initialization signal line pattern 2093 through a via 2105 penetrating the second interlayer dielectric layer 210, thereby achieving coupling between the first electrode T81 of the eighth transistor T8 and the third initialization signal line Vinit3.

[0146] However, the third initialization signal line bridging pattern 21110 overlaps with the first initialization signal line pattern 2092, and there is only one second interlayer dielectric layer 210 between the first source / drain metal layer 211 where the third initialization signal line bridging pattern 21110 is located and the third gate metal layer 209 where the first initialization signal line pattern 2092 is located. If small particles or dust are present during the fabrication of the second interlayer dielectric layer 210 of the display panel 1000, the small particles or dust will penetrate the second interlayer dielectric layer 210, for example, by penetrating the third initialization signal line bridging pattern 21110 and the first initialization signal line pattern 2092. The second interlayer dielectric layer 210 at the overlapping position of the initialization signal line pattern 2092, or small particles or dust, prevents the successful deposition of the second interlayer dielectric layer 210, thus rendering the second interlayer dielectric layer 210 ineffective. During magnetron sputtering of the first source / drain metal layer 211, material from the first source / drain metal layer 211 may enter the gaps between small particles or dust, causing the third initialization signal line bridging pattern 21110 to conduct electricity or directly connect with the first initialization signal line pattern 2092, resulting in a short circuit between the first initialization signal line Vinit1 and the third initialization signal line Vinit3. According to the FIB diagram, it can be further determined that the presence of small particles or dust PT at the overlapping position of the third initialization signal line bridging pattern 21110 and the first initialization signal line pattern 2092 causes a short circuit between the first initialization signal line Vinit1 and the third initialization signal line Vinit3.

[0147] As shown in Figure 15, during the aging process of the P-type transistors in the pixel driving circuit 10 shown in Figure 3, the voltage difference between the first initialization signal voltage Vint1 and the third initialization signal voltage Vint3 can reach 22V. When the first initialization signal line Vint1 and the third initialization signal line Vint3 of the display panel 1000 are short-circuited, the voltage difference between the first initialization signal voltage Vint1 and the third initialization signal voltage Vint3 is large during the aging process of the display panel 1000, for example, 22V. This can cause the signal lines and pixels of the display panel 1000 to be burned, resulting in burn-in dark spots, which in turn greatly reduces the yield of the display panel 1000.

[0148] To avoid burn-in type dark spots, in some embodiments, a display panel 1000 is provided, as shown in FIG1. ​​The display panel 1000 includes a plurality of sub-pixels P, the plurality of sub-pixels P are arranged in multiple rows along a first direction X, and two adjacent sub-pixels P in a row of sub-pixels P form a pixel group PP; a sub-pixel P includes a pixel driving circuit 10, and the pixel driving circuit 10 is coupled to at least one signal line 30.

[0149] As shown in Figure 3, the pixel driving circuit 10 includes a designated transistor 11, and at least one signal line 30 includes a designated signal line 31. The designated transistor 11 is coupled to the designated signal line 31. The designated transistor 11 is one of the multiple transistors included in the pixel driving circuit 10, and the designated signal line 31 is one of the multiple signal lines 30 connected to the pixel driving circuit 10. The designated signal line 31 is connected to the designated transistor 11.

[0150] The following describes the pattern of each film layer of the display panel 1000, taking the structure included in two adjacent sub-pixels P (i.e., a pixel group PP) along the first direction X as an example.

[0151] As shown in Figure 2, the display panel 1000 includes a substrate 100 and a driving circuit layer 200 disposed on one side of the substrate 100, and a pixel driving circuit 10 is disposed on the driving circuit layer 200. As shown in Figure 16, the driving circuit layer 200 includes a first active layer 201 disposed on one side of the substrate 100, a designated gate metal layer 2001 disposed on the side of the first active layer 201 away from the substrate 100, and a first source / drain metal layer 211 disposed on the side of the designated gate metal layer 2001 away from the substrate 100; the first active layer 201 includes an active layer pattern 2010 of a designated transistor 11, and the active layer pattern 2010 of the designated transistor 11 includes an active layer first electrode pattern 2010-1. In a pixel group PP, the active layer first electrode pattern 2010-1 of the designated transistor 11 of a sub-pixel P is... 10-1 is connected to the active layer first pole pattern 2010-1' of the designated transistor 11 of another sub-pixel P'; the designated gate metal layer 2001 includes the designated signal line pattern 20010 of the designated signal line 31; the first source-drain metal layer 211 includes the designated signal line bridging pattern 2110. In a pixel group PP, the designated signal line bridging pattern 2110 is located in the area where a sub-pixel P is located. The designated signal line bridging pattern 2110 is connected to the active layer first pole pattern 2010-1 of the designated transistor 11 of one of the sub-pixels P, and is also connected to the designated signal line pattern 20010.

[0152] For example, as shown in FIG1, two adjacent sub-pixels P in a row of sub-pixels P can be used as a pixel group PP. The display panel 1000 includes multiple pixel groups PP. The pixel group PP is the smallest repeating unit of the display panel 1000, that is, the film layer settings of the multiple pixel groups PP in the display panel 1000 are consistent.

[0153] For example, as shown in FIG1, the pixel driving circuit 10 is coupled to the signal line in the display panel 1000. As shown in FIG3, the pixel driving circuit 10 includes a designated transistor 11, and the signal line includes a designated signal line 31. The designated transistor 11 is coupled to the designated signal line 31.

[0154] It should be noted that the number of designated transistors 11 is not limited here; there can be only one or more designated transistors 11. Similarly, the number of designated signal lines 31 is not limited here; there can be only one or more designated signal lines 31. When there is only one designated transistor 11 and one designated signal line 31, the designated transistor 11 is coupled to the designated signal line 31. When there are multiple designated transistors 11 and multiple designated signal lines 31, one designated transistor 11 is coupled to one designated signal line 31.

[0155] For example, as shown in FIG2, the display panel 1000 includes a substrate 100 and a driving circuit layer 200 disposed on one side of the substrate 100. The driving circuit layer 200 is a general term for the film layer where the pixel driving circuits 10 of all sub-pixels P in the display panel 1000 are located, that is, the pixel driving circuits 10 are disposed on the driving circuit layer 200.

[0156] For example, as shown in FIG16, the driving circuit layer 200 includes a first active layer 201 disposed on one side of the substrate 100, a designated gate metal layer 2001 disposed on the side of the first active layer 201 away from the substrate 100, and a first source / drain metal layer 211 disposed on the side of the designated gate metal layer 2001 away from the substrate 100. An insulating layer is disposed between the first active layer 201 and the designated gate metal layer 2001, and an insulating layer is disposed between the designated gate metal layer 2001 and the first source / drain metal layer 211.

[0157] For example, as shown in FIG16, the first active layer 201 includes an active layer pattern 2010 of a designated transistor 11; the active layer pattern 2010 of the designated transistor 11 includes an active layer first pole pattern 2010-1, an active layer channel pattern 2010-3, and an active layer second pole pattern 2010-2 connected in sequence; the active layer first pole pattern 2010-1 of the designated transistor 11 of a sub-pixel P in a pixel group PP is connected to the active layer first pole pattern 2010-1' of the designated transistor 11 of another sub-pixel P'.

[0158] It should be noted that when there are multiple designated transistors 11 in the pixel driving circuit 10, the active layer first electrode patterns 2010-1 of the designated transistors 11 corresponding to two sub-pixels P in a pixel group PP are connected. Specifically, for example, a sub-pixel P includes three designated transistors 11, namely a first designated transistor, a second designated transistor, and a third designated transistor; in a pixel group PP, the active layer first electrode pattern 2010-1 of the first designated transistor of one sub-pixel P is connected to the active layer first electrode pattern 2010-1' of the first designated transistor of another sub-pixel P', the active layer first electrode pattern 2010-1 of the second designated transistor of one sub-pixel P is connected to the active layer first electrode pattern 2010-1' of the second designated transistor of another sub-pixel P', and the active layer first electrode pattern 2010-1 of the third designated transistor of one sub-pixel P is connected to the active layer first electrode pattern 2010-1' of the third designated transistor of another sub-pixel P'.

[0159] For example, as shown in FIG16, the designated gate metal layer 2001 includes a designated signal line pattern 20010 of the designated signal line 31.

[0160] For example, as shown in FIG16, the first source-drain metal layer 211 includes a designated signal line bridging pattern 2110; in a pixel group PP, the designated signal line bridging pattern 2110 is located in the area where a sub-pixel P is located. It can be understood that the area where the other sub-pixel P' is located does not include the designated signal line bridging pattern 2110. That is, among the two sub-pixels P in a pixel group PP, only one sub-pixel P includes the designated signal line bridging pattern 2110; the designated signal line bridging pattern 2110 is connected to the active layer first pole pattern 2010-1 of the designated transistor 11 of one of the sub-pixels P through a via penetrating the insulating layer between the first source-drain metal layer 211 and the first active layer 201; and the designated signal line bridging pattern 2110 is also connected to the designated signal line pattern 20010 through a via penetrating the insulating layer between the first source-drain metal layer 211 and the designated gate metal layer 2001.

[0161] It should be noted that the number of designated signal line bridging patterns 2110 within the area where a sub-pixel P is located is not limited here. There can be only one designated signal line bridging pattern 2110 or multiple designated signal line bridging patterns 2110. When there is only one designated signal line bridging pattern 2010-1 of the active layer of the designated transistor 11 and only one designated signal line pattern 20010, there is also only one designated signal line bridging pattern 2110. When there are multiple designated signal line bridging patterns 2010-1 of the active layer of the designated transistor 11 and multiple designated signal line patterns 20010, there can also be multiple designated signal line bridging patterns 2110. The designated signal line bridging pattern 2010-1 of the active layer of the designated transistor 11, the designated signal line pattern 20010, and the designated signal line bridging pattern 2110 correspond to each other. Specifically, for example, a sub-pixel P includes two designated transistors 11, namely a first designated transistor and a second designated transistor, that is, a sub-pixel P includes the active layer first electrode pattern of the first designated transistor and the active layer first electrode pattern of the second designated transistor; a sub-pixel P includes two designated signal line patterns 20010, namely the first designated signal line pattern and the second designated signal line pattern; a sub-pixel P includes two designated signal line bridging patterns 2110, namely the first designated signal line bridging pattern and the second designated signal line bridging pattern; the first designated signal line bridging pattern of a sub-pixel P connects the active layer first electrode pattern of the first designated transistor and the first designated signal line pattern respectively, and the second designated signal line bridging pattern of a sub-pixel P connects the active layer first electrode pattern of the second designated transistor and the second designated signal line pattern respectively.

[0162] Although in a pixel group PP, only one of the two sub-pixels P is provided with a designated signal line bridging pattern 2110, and the designated signal line bridging pattern 2110 is connected to the active layer first electrode pattern 2010-1 of the designated transistor 11 of one of the sub-pixels P through a via penetrating the insulating layer between the first source / drain metal layer 211 and the first active layer 201, thereby transmitting the signal transmitted by the designated signal line pattern 20010 to the active layer first electrode pattern 2010-1 of the designated transistor 11 of one of the sub-pixels P through the designated signal line bridging pattern 2110; however, because the active layer first electrode pattern 2010-1 of the designated transistor 11 of one sub-pixel P in a pixel group PP is connected to the active layer first electrode pattern 2010-1 of the designated transistor 11 of the other sub-pixel P; The active layer first pole pattern 2010-1' of the designated transistor 11 of each sub-pixel P' is connected. Therefore, the signal transmitted by the designated signal line pattern 20010 is transmitted to the active layer first pole pattern 2010-1 of the designated transistor 11 of one sub-pixel P through the designated signal line bridging pattern 2110. At the same time, the signal transmitted by the designated signal line pattern 20010 is also transmitted to the active layer first pole pattern 2010-1' of the designated transistor 11 of the other sub-pixel P' through the designated signal line bridging pattern 2110. This ensures that the active layer first pole patterns 2010-1 of the designated transistor 11 of both sub-pixels P of a pixel group PP receive the signal transmitted by the designated signal line pattern 20010.

[0163] Therefore, a designated signal line bridging pattern 2110 is set in a sub-pixel P of a pixel group PP, and the designated signal line bridging pattern 2110 connects the active layer first electrode pattern 2010-1 of the designated transistor 11 of one sub-pixel P and the designated signal line pattern 20010; since the active layer first electrode patterns 2010-1 of the designated transistor 11 in two sub-pixels P of a pixel group PP are connected, it can be realized that the active layer first electrode patterns 2010-1 of the designated transistor 11 in both sub-pixels P of a pixel group PP can be connected to the designated signal line pattern 20010 through the designated signal line bridging pattern 2110, without affecting This configuration reduces the number of designated signal line bridging patterns 2110 of a sub-pixel P in the pixel group PP, thereby reducing the overlap between the designated signal line bridging patterns 2110 and other signal line patterns. This reduces the probability of short circuits caused by the overlap between the designated signal line bridging patterns 2110 and other signal line patterns, thereby reducing the probability of burn-in type dark spots. This greatly improves the burn-in type dark spot defects of the display panel 1000, improves the yield rate, and significantly improves the Y-line defects caused by burn-in. It also significantly reduces the market risk caused by burn-in of the pixel driving circuit 10.

[0164] In some embodiments, as shown in FIG16, in a pixel group PP, the active layer first pole pattern 2010-1 of the designated transistor 11 of one sub-pixel P and the active layer first pole pattern 2010-1' of the designated transistor 11 of another sub-pixel P' are connected at a designated connection point 1, and the designated signal line bridging pattern 2110 is connected to the designated connection point 1.

[0165] For example, the designated connection point 1 can be set at a position where its orthogonal projection on the substrate 100 is closer to the orthogonal projection of the designated signal line pattern 20010 on the substrate 100; this setting helps to reduce the length of the designated signal line bridging pattern 2110, reduce the probability of defects in the designated signal line bridging pattern 2110 during the fabrication process, and at the same time reduce the impedance of the designated signal line bridging pattern 2110.

[0166] In some embodiments, as shown in FIG16, in a pixel group PP, the active layer patterns 2010 of the designated transistors 11 of the two sub-pixels P are mirror symmetrical, and the designated connection point 1 is located on the mirror symmetry axis 2 of the active layer patterns 2010 of the designated transistors 11 of the two sub-pixels P; the designated signal line pattern 20010 extends along the first direction X and passes through the area where the two sub-pixels P are located.

[0167] For example, as shown in FIG16, the active layer patterns 2010 of the designated transistors 11 of two sub-pixels P in a pixel group PP are mirror symmetrical. The designated connection point 1 is set on the mirror symmetry axis 2 of the active layer patterns 2010 of the designated transistors 11 of the two sub-pixels P. That is, the size and shape of the first pole patterns 2010-1 of the active layer of the designated transistors 11 of the two sub-pixels P are the same. The transmission path length of the signal from the designated connection point 1 to the first pole patterns 2010-1 of the active layer of the designated transistors 11 of the two sub-pixels P is the same. This can ensure that the first pole patterns 2010-1 of the active layer of the designated transistors 11 of the two sub-pixels P in a pixel group PP simultaneously receive the signal transmitted by the designated signal line pattern 20010, and the loss of the received signal is consistent. Synchronous transmission can be performed to ensure the uniformity of sub-pixels P in the display panel 1000.

[0168] In some embodiments, as shown in FIG16, the width of the specified signal line bridging pattern 2110 is greater than a set width.

[0169] For example, as shown in FIG16, setting a specified signal line bridging pattern 2110 in one of the sub-pixels P of a pixel group PP results in an increase in the impedance of the specified signal line bridging pattern 2110 due to the reduction of one specified signal line bridging pattern 2110, which in turn leads to an increase in the write impedance of the specified signal line 31.

[0170] In some embodiments, a designated signal line bridging pattern 2110 is provided in each sub-pixel P, and the width of the designated signal line bridging pattern 2110 can be, for example, a set width of 1.8 μm. In order to reduce the impedance of the designated signal line bridging pattern 2110 when it is provided in one of the sub-pixels P of a pixel group PP as shown in FIG. 16, the width of the designated signal line bridging pattern 2110 can be set to, for example, 1.8 μm to 3 μm, such as 2 μm, 2.1 μm, 2.2 μm, 2.3 μm, 2.4 μm, 2.5 μm, 2.6 μm, 2.7 μm, 2.8 μm, 2.9 μm, or 3 μm, thereby compensating for the write capability of the designated signal line 31.

[0171] It should be noted that "set width" refers to the width of the specified signal line bridging pattern 2110 when each sub-pixel P is set with a specified signal line bridging pattern 2110. The "set width 1.8um" mentioned above is only an exemplary width, and the set width is not necessarily 1.8um. ​​The "set width" can be set according to the actual product process, and this disclosure does not make such a setting.

[0172] In some embodiments, as shown in FIG16, the pixel driving circuit 10 further includes other transistors besides the designated transistor 11; the first active layer 201 further includes active layer patterns of other transistors; the active layer patterns of other transistors include active layer channel patterns; the active layer pattern 2010 of the designated transistor 11 includes an active layer channel pattern 2010-3, and the aspect ratio of the active layer channel pattern 2010-3 of the designated transistor 11 is greater than the aspect ratio of the active layer channel patterns of other transistors.

[0173] For example, as shown in FIG16, setting a specified signal line bridging pattern 2110 in one of the sub-pixels P of a pixel group PP increases the impedance of the specified signal line bridging pattern 2110 compared to setting a specified signal line bridging pattern 2110 in each sub-pixel P, thereby increasing the write impedance of the specified signal line 31; the write capability of the specified signal line 31 can be compensated by increasing the aspect ratio of the active layer channel pattern 2010-3 of the specified transistor 11.

[0174] For example, a designated signal line bridging pattern 2110 is provided in each sub-pixel P. The aspect ratio of the active layer channel pattern of the transistor in sub-pixel P can be the same, for example, 2 / 4. In order to compensate for the writing capability of the designated signal line 31 when the designated signal line bridging pattern 2110 is provided in one of the sub-pixels P in a pixel group PP as shown in FIG16, the aspect ratio of the active layer channel pattern 2010-3 of the designated transistor 11 can be increased, while the aspect ratio of the active layer channel pattern of other transistors remains unchanged. The aspect ratio of the active layer channel pattern 2010-3 of the designated transistor 11 can be, for example, 2.4 / 4.

[0175] In some embodiments, the display panel 1000 includes a plurality of sub-pixels P, and each sub-pixel P includes a pixel driving circuit 10 as shown in FIG3; the plurality of sub-pixels P are arranged in multiple rows along a first direction X, and two adjacent sub-pixels P in a row of sub-pixels form a pixel group PP. The film layer settings of the two sub-pixels in a pixel group PP are the same as those of a single sub-pixel, except that the settings of the first active layer 201 and the first source / drain metal layer 211 are different. For details of the film layer settings of the two sub-pixels in a pixel group PP, please refer to FIG16 to FIG44, which will not be repeated here.

[0176] In some embodiments, as shown in FIG3, the designated transistor 11 includes a third reset transistor, namely the eighth transistor T8, and the designated signal line 31 includes a third initialization signal line Vinit3. The third reset transistor, namely the eighth transistor T8, is coupled to the third initialization signal line Vinit3. As shown in FIG31, the first active layer 201 includes the active layer pattern 2018 of the third reset transistor, namely the eighth transistor T8. The active layer pattern 2018 of the third reset transistor, namely the eighth transistor T8, includes the active layer first pole pattern 2018-1. The designated gate metal layer 2001 includes the third initialization signal line pattern 2093 of the third initialization signal line Vinit3. The designated signal line bridging pattern 2110 includes the third initialization signal line bridging pattern 21110, and the first source-drain metal layer 211 includes the third initialization signal line bridging pattern 21110.

[0177] For example, as shown in FIG17, the first active layer 201 includes an active layer pattern 2018 of an eighth transistor T8. The active layer pattern 2018 of the eighth transistor T8 includes an active layer first pole pattern 2018-1, an active layer channel pattern 2018-3, and an active layer second pole pattern 2018-2 connected in sequence. The active layer first pole pattern 2018-1 of the eighth transistor T8 of one sub-pixel P in a pixel group PP is connected to the active layer first pole pattern 2018-1' of the eighth transistor T8 of another sub-pixel P'.

[0178] For example, as shown in FIG25, the designated gate metal layer 2001 may be, for example, a third gate metal layer 209. The designated gate metal layer 2001, for example, the third gate metal layer 209 includes a third initialization signal line pattern 2093 of the third initialization signal line Vinit3.

[0179] For example, as shown in FIG31, the specified signal line bridging pattern 2110 includes a third initialization signal line bridging pattern 21110, and the first source / drain metal layer 211 includes the third initialization signal line bridging pattern 21110. In a pixel group PP, the third initialization signal line bridging pattern 21110 is located in the area of ​​one sub-pixel P. It can be understood that the area of ​​the other sub-pixel P' does not include the third initialization signal line bridging pattern 21110. That is, among the two sub-pixels P in a pixel group PP, only one sub-pixel P includes the third initialization signal line bridging pattern 21110. The third initialization signal line bridging pattern 21110 is connected to the first active layer pattern 2018-1 of the eighth transistor T8 of one of the sub-pixels P through a via penetrating the insulating layer between the first source / drain metal layer 211 and the first active layer 201. The third initialization signal line bridging pattern 21110 is also connected to the third initialization signal line pattern 2093 through a via penetrating the insulating layer between the first source / drain metal layer 211 and the designated gate metal layer 2001.

[0180] In some embodiments, as shown in FIG3, the signal line further includes a first initialization signal line Vinit1; as shown in FIG25, the designated gate metal layer 2001, for example, the third gate metal layer 209, further includes a first initialization signal line pattern 2092 of the first initialization signal line Vinit1; the first initialization signal line pattern 2092 extends along the first direction X and passes through the region where two sub-pixels P are located in a pixel group PP; as shown in FIG31, the third initialization signal line bridging pattern 21110 overlaps with the first initialization signal line pattern 2092.

[0181] For example, as shown in FIG31, when the third initialization signal line bridging pattern 21110 is connected to the active layer first pole pattern 2018-1 of the eighth transistor T8 of one of the sub-pixels P, and is also connected to the third initialization signal line pattern 2093, although the third initialization signal line bridging pattern 21110 overlaps with the first initialization signal line pattern 2092, the third initialization signal line bridging pattern 21110 is only set in one sub-pixel P in a pixel group PP, thus reducing the number of third initialization signal line bridging patterns 21110 in one sub-pixel P in the pixel group PP, i.e., reducing... The reduction in the number of third initialization signal line bridging patterns 21110 reduces the overlap between the third initialization signal line bridging patterns 21110 and the first initialization signal line pattern 2092, thereby reducing the probability of short circuits caused by the overlap between the third initialization signal line bridging patterns 21110 and the first initialization signal line pattern 2092. This reduces the probability of burn-in type dark spots, greatly improves the burn-in type dark spot defects of the display panel 1000, improves the yield rate, and significantly improves the Y-line defects caused by burn-in, significantly reducing the market risk caused by burn-in of the pixel driving circuit 10.

[0182] In some embodiments, as shown in FIG45 and referring to FIG10, the width of the third initialization signal line bridging pattern 21110 is greater than the set width.

[0183] For example, as shown in FIG45, in a pixel group PP, two sub-pixels P share a third initialization signal line bridging pattern 21110. The initialization signal transmitted by the third initialization signal line Vinit3 reaches the eighth transistor T8 of the two sub-pixels P through one third initialization signal line bridging pattern 21110. At this time, the impedance of the third initialization signal line bridging pattern 21110 is increased compared with the impedance of the initialization signal transmitted by the third initialization signal line Vinit3 in some previous embodiments, which reaches the eighth transistor T8 of the two sub-pixels P through two third initialization signal line bridging patterns 21110, thereby increasing the write impedance of the third initialization signal line Vinit3.

[0184] For example, as shown in FIG45, in order to reduce the impedance of the third initialization signal line bridging pattern 21110 when it is set in one of the sub-pixels P of a pixel group PP, the width of the third initialization signal line bridging pattern 21110 can be greater than the width of other patterns on the first source-drain metal layer 211. Other patterns can be, for example, the first power signal line bridging pattern 2119, the first pole pattern 2112-1 of the second transistor T2, etc.

[0185] For example, as shown in FIG10, a third initialization signal line bridging pattern 21110 is provided in each sub-pixel P. The width of the third initialization signal line bridging pattern 21110 can be, for example, 1.8µm. In order to reduce the impedance of the third initialization signal line bridging pattern 21110 when it is provided in one of the sub-pixels P of a pixel group PP as shown in FIG45, the width of the third initialization signal line bridging pattern 21110 can be set to, for example, 1.8µm to 3µm, such as 2µm, 2.1µm, 2.2µm, 2.3µm, 2.4µm, 2.5µm, 2.6µm, 2.7µm, 2.8µm, 2.9µm, or 3µm, thereby compensating for the write capability of the third initialization signal line Vinit3.

[0186] In some embodiments, as shown in FIG46, the first active layer 201 further includes an active layer pattern of a first transistor T1, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7. The active layer patterns of the first transistor T1, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 all include active layer channel patterns; the active layer pattern 2018 of the eighth transistor T8 includes an active layer channel pattern 2018-3. In some examples, the aspect ratio of the active layer channel pattern 2018-3 of the eighth transistor T8 is greater than that of the active layer channel pattern of the first transistor T1; in some examples, the aspect ratio of the active layer channel pattern 2018-3 of the eighth transistor T8 is greater than that of the active layer channel pattern of the seventh transistor T7; in other examples, the aspect ratio of the active layer channel pattern 2018-3 of the eighth transistor T8 is greater than that of the active layer channel patterns of the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6.

[0187] For example, the first transistor T1 is a first reset transistor, the second transistor T2 is a compensation transistor, the third transistor T3 is a driving transistor, the fourth transistor T4 is a writing transistor, the fifth transistor T5 is a first light-emitting control transistor, the sixth transistor T6 is a second light-emitting control transistor, the seventh transistor T7 is a second reset transistor, and the eighth transistor T8 is a third reset transistor.

[0188] The channel width-to-length ratio of a transistor is the ratio of the width to the length of the conductive channel. The larger the width-to-length ratio, the larger the conduction current Id through the transistor when it is turned on. In other words, the width-to-length ratio is directly proportional to the conduction current Id. The width-to-length ratio of a transistor reflects its conduction capability, i.e., its signal writing capability.

[0189] For example, as shown in FIG10, the aspect ratio of the active layer channel pattern of the transistor in the sub-pixel P can all be the same, for example, the aspect ratio can all be 2 / 4; in order to compensate for the writing capability of the third initialization signal line Vinit3 when the third initialization signal line bridging pattern 21110 is set in one of the sub-pixels P of a pixel group PP as shown in FIG46, the aspect ratio of the active layer channel pattern 2018-3 of the eighth transistor T8 can be increased to enhance the signal writing capability of the eighth transistor T8, while the aspect ratio of the active layer channel patterns of the first transistor T1, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 remains unchanged; the aspect ratio of the active layer channel pattern 2018-3 of the eighth transistor T8 can be, for example, 2.4 / 4.

[0190] The first transistor T1, the eighth transistor T8, and the seventh transistor T7 are all reset transistors, all implementing the reset function. The aspect ratio of the active layer channel pattern 2018-3 of the eighth transistor T8 is set to be greater than that of the active layer channel pattern of the first transistor T1 and also greater than that of the active layer channel pattern of the seventh transistor T1. This improves the signal writing capability of the eighth transistor T8, ensuring that the writing capability of the initialization signal of the three reset transistors remains consistent, improving the uniformity of the corresponding node potential of the pixel driving circuit, and avoiding the impact of the setting of the third initialization signal line bridging pattern 21110 on the reset function of the eighth transistor T8.

[0191] In some embodiments, as shown in FIG3, the pixel driving circuit 10 further includes a compensation transistor, namely a second transistor T2, and the signal line further includes a first power supply signal line VDD; as shown in FIG37, the driving circuit layer 200 of the display panel 1000 further includes a second active layer 207 disposed between the first active layer 201 and the designated gate metal layer 2001, such as the third gate metal layer 209, and a second source drain metal layer 214 disposed on the side of the first source drain metal layer 211 away from the substrate 100; as shown in FIG23, the second active layer 207 is disposed between the first active layer 201 and the designated gate metal layer 2001, such as the third gate metal layer 209, and a second source drain metal layer 214 disposed on the side of the first source drain metal layer 211 away from the substrate 100; The source layer 207 includes a compensation transistor, namely the active layer pattern 2071 of the second transistor T2; as shown in FIG37, the second source-drain metal layer 214 includes a first power signal line pattern 2141 of the first power signal line VDD, the first power signal line pattern 2141 includes a block pattern 2141-1, and the orthographic projection of the active layer pattern 2071 of the compensation transistor, namely the second transistor T2, on the substrate 100 is located within the orthographic projection of the block pattern 2141-1 of the first power signal line pattern 2141 on the substrate 100.

[0192] For example, as shown in FIG37, the orthographic projection of the active layer pattern 2071 of the second transistor T2 onto the substrate 100 lies within the orthographic projection of the block pattern 2141-1 of the first power signal line pattern 2141 onto the substrate 100. That is, the area of ​​the block pattern 2141-1 of the first power signal line pattern 2141 is larger than the area of ​​the active layer pattern 2071 of the second transistor T2, and the block pattern 2141-1 of the first power signal line pattern 2141 is located above the active layer pattern 2071 of the second transistor T2 and can cover the active layer pattern 2071 of the second transistor T2 in a direction perpendicular to the substrate 100. The block pattern 2141-1 of the first power signal line pattern 2141 can be used to shield the active layer pattern 2071 of the second transistor T2 from light penetrating into the display panel 1000 from the environment, preventing changes in the material properties of the active layer pattern 2071 of the second transistor T2 under the influence of natural light, thus affecting the performance of the display panel 1000.

[0193] In some embodiments, as shown in FIG37, the first power signal line pattern 2141 further includes a strip pattern 2141-2 connected to the block pattern 2141-1, the width of the strip pattern 2141-2 being 3.5um to 5um.

[0194] For example, the bar pattern 2141-2 of the first power signal line pattern 2141 is mainly used to transmit the first power signal. In order to reduce the impedance of the bar pattern 2141-2, the width of the bar pattern 2141-2 can be set to 3.5um to 5um, such as 3.5um, 3.6um, 3.7um, 3.8um, 3.9um, 4um, 4.1um, 4.2um, 4.3um, 4.4um, 4.5um, 4.6um, 4.7um, 4.8um, 4.9um, and 5um.

[0195] For example, as shown in FIG37, the bar pattern 2141-2 can be set as two bars, and the two bars 2141-2 are respectively connected to the block pattern 2141-1, and the bars 2141-2 are kept symmetrical. This setting can ensure that power can be supplied at the same time, which is beneficial to improving the flatness of the display panel 1000 and reducing color deviation.

[0196] In some embodiments, as shown in FIG3, the pixel driving circuit 10 further includes a driving transistor, namely a third transistor T3. As shown in FIG17, the first active layer 201 includes the active layer pattern 2013 of the driving transistor, namely the third transistor T3. As shown in FIG18, the driving circuit layer 200 of the display panel 1000 further includes a bottom metal layer 219 disposed on the side of the first active layer 201 near the substrate 100. The bottom metal layer 219 includes a bottom metal protection pattern 2191. The orthographic projection of the active layer pattern 2013 of the driving transistor, namely the third transistor T3, on the substrate 100 is located within the orthographic projection of the bottom metal protection pattern 2191 on the substrate 100. The bottom metal protection pattern 2191 is connected to the first power signal line pattern 2141 of the second source-drain metal layer 214.

[0197] For example, as shown in FIG17, the active layer pattern 2013 of the third transistor T3 includes an active layer first electrode pattern 2013-1, an active layer channel pattern 2013-3, and an active layer second electrode pattern 2013-2 connected in sequence; as shown in FIG18, the orthographic projection of the active layer pattern 2013 of the third transistor T3 on the substrate 100 is located within the orthographic projection of the bottom metal protection pattern 2191 on the substrate 100, that is, the bottom metal protection pattern 2191 is located below the active layer pattern of the third transistor T3 and can cover the active layer pattern of the third transistor T3 in a direction perpendicular to the substrate 100, and the bottom metal protection pattern 2191 and the second The first power signal line pattern 2141 of the source-drain metal layer 214 is connected. This arrangement can protect the third transistor T3 and prevent impurities in the lower layer from moving upward and affecting the performance of the third transistor T3. At the same time, the bottom metal protection pattern 2191 is connected to the first power signal line pattern 2141. For example, the bottom metal protection pattern 2191 and the first power signal line pattern 2141 are connected through a via in the peripheral area BB of the display panel 1000. After the signal is turned on, the bottom metal protection pattern 2191 and the active layer pattern of the third transistor T3 form a balanced electric field, making the channel electric field of the active layer channel pattern of the third transistor T3 more stable and less susceptible to interference from the electric field at the bottom of the display panel 1000.

[0198] In some embodiments, as shown in FIG43, the display panel 1000 further includes an anode layer 301 disposed on the side of the driving circuit layer 200 away from the substrate 100; the anode layer 301 includes a first anode 3011 and a second anode 3012, the first anode 3011 is connected to the pixel driving circuit 10 of a sub-pixel P in the pixel group PP, and the second anode 3012 is connected to the pixel driving circuit 10 of another sub-pixel P' in the pixel group PP; the first anode 3011 is disposed above the block pattern 2141-1 of the first power signal line pattern 2141, and the ratio of the overlapping area of ​​the first anode 3011 and the block pattern 2141-1 to the area of ​​the first anode 3011 is greater than a set threshold.

[0199] For example, the first anode 3011 is disposed above the block pattern 2141-1 of the first power signal line pattern 2141. The ratio of the overlapping area of ​​the first anode 3011 and the block pattern 2141-1 to the area of ​​the first anode 3011 is greater than a set threshold, such as 60%. This can ensure the flatness of the first anode 3011, improve the uniformity of the sub-pixels P of the display panel 1000, and improve the yield of the display panel 1000.

[0200] It should be noted that the "set threshold" can be set according to the actual product process, and this disclosure does not specify a threshold. The "set threshold for example, 60%" mentioned above is only an exemplary value and does not mean that the set threshold is always 60%.

[0201] In some embodiments, as shown in FIG47, the substrate 100 includes at least two flexible substrates 101 and at least two buffer layers 102.

[0202] For example, when fabricating the display panel 1000, a glass support is typically disposed below the substrate 100.

[0203] For example, the material of the buffer layer 102 can be silicon nitride and / or silicon oxide. Silicon nitride has good density, which can prevent metal ions carried by the glass under the substrate 100 from diffusing to the active layer region. Silicon oxide has good insulation, which can prevent static electricity outside the display panel 1000 from affecting the pixel driving circuit 10 inside the display panel 1000. Silicon oxide also has good heat insulation, which can reduce the heat conduction rate and help form larger crystal grains. It plays a role in absorbing heat when the glass is laser-lifted in the later stage, blocking heat from penetrating to the film layer on the substrate 100. At the same time, when the substrate 100 includes at least two flexible substrates 101 and at least two buffer layers 102, it can better protect the bottom of the display panel 1000, while reducing the impact of small particles or dust, and preventing small particles or dust from entering the interior of the display panel 1000 from below.

[0204] On the other hand, a display device 10000 is provided, as shown in FIG48, including a display panel 1000 as described in any of the above embodiments.

[0205] For example, the display device 10000 can display images, such as static images or moving images.

[0206] For example, the display device 10000 may be (but is not limited to) a mobile phone, wireless device, personal digital assistant (PDA), handheld or portable computer, GPS receiver / navigator, camera, MP4 video player, camcorder, game console, watch, clock, calculator, television monitor, flat panel display, computer monitor, automotive display (e.g., odometer display, etc.), navigator, cockpit controller and / or display, display of camera view (e.g., display of a rearview camera in a vehicle), electronic photograph, electronic billboard or sign, projector, architectural structure, packaging and aesthetic structure (e.g., display of an image of a piece of jewelry), etc.

[0207] In the description of this specification, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.

[0208] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A display panel, wherein, It includes multiple sub-pixels, which are arranged in multiple rows along a first direction, with two adjacent sub-pixels in a row forming a pixel group; one of the multiple sub-pixels includes a pixel driving circuit, which is coupled to at least one signal line, the pixel driving circuit includes a designated transistor, the at least one signal line includes a designated signal line, and the designated transistor is coupled to the designated signal line; The display panel includes: Substrate; A first active layer is disposed on one side of the substrate, the first active layer includes an active layer pattern of the designated transistor, the active layer pattern of the designated transistor includes an active layer first pole pattern; in a pixel group, the active layer first pole pattern of the designated transistor of one sub-pixel is connected to the active layer first pole pattern of the designated transistor of another sub-pixel. A designated gate metal layer is disposed on the side of the first active layer away from the substrate, the designated gate metal layer including a designated signal line pattern of the designated signal line; A first source / drain metal layer is disposed on the side of the designated gate metal layer away from the substrate, the first source / drain metal layer including a designated signal line bridging pattern; in a pixel group, the designated signal line bridging pattern is located in the region of a sub-pixel, the designated signal line bridging pattern is connected to the active layer first electrode pattern of the designated transistor of one of the sub-pixels, and is also connected to the designated signal line pattern.

2. The display panel according to claim 1, wherein, In one pixel group, the active layer first electrode pattern of the designated transistor of one sub-pixel is connected to the active layer first electrode pattern of the designated transistor of another sub-pixel at a designated connection point, and the designated signal line bridging pattern is connected to the designated connection point.

3. The display panel according to claim 2, wherein, In one pixel group, the active layer patterns of the designated transistors of the two sub-pixels are mirror-symmetrical, and the designated connection point is located on the mirror symmetry axis of the active layer patterns of the designated transistors of the two sub-pixels; the designated signal line pattern extends along the first direction and passes through the area where the two sub-pixels are located.

4. The display panel according to any one of claims 1 to 3, wherein, The width of the specified signal line bridging pattern is greater than the set width.

5. The display panel according to any one of claims 1 to 4, wherein, The pixel driving circuit also includes other transistors besides the specified transistor; The first active layer further includes active layer patterns of the other transistors; the active layer patterns of the other transistors include active layer channel patterns; The active layer pattern of the specified transistor includes an active layer channel pattern, and the aspect ratio of the active layer channel pattern of the specified transistor is greater than the aspect ratio of the active layer channel patterns of the other transistors.

6. The display panel according to any one of claims 1 to 5, wherein, The designated transistor includes a third reset transistor, the designated signal line includes a third initialization signal line, and the third reset transistor is coupled to the third initialization signal line; The first active layer includes the active layer pattern of the third reset transistor, and the active layer pattern of the third reset transistor includes the active layer first electrode pattern. The designated gate metal layer includes the third initialization signal line pattern of the third initialization signal line; The specified signal line bridging pattern includes a third initialization signal line bridging pattern, and the first source / drain metal layer includes the third initialization signal line bridging pattern.

7. The display panel according to claim 6, wherein, The signal line also includes a first initialization signal line; The designated gate metal layer further includes a first initialization signal line pattern of the first initialization signal line; the first initialization signal line pattern extends along the first direction and passes through the region where two of the sub-pixels are located in a pixel group; The third initialization signal line bridging pattern overlaps with the first initialization signal line pattern.

8. The display panel according to any one of claims 1 to 7, wherein, The pixel driving circuit further includes a compensation transistor, and the signal line further includes a first power supply signal line; the display panel further includes: A second active layer is disposed between the first active layer and the designated gate metal layer; the second active layer includes the active layer pattern of the compensation transistor; A second source / drain metal layer is disposed on the side of the first source / drain metal layer away from the substrate; the second source / drain metal layer includes a first power signal line pattern of the first power signal line, the first power signal line pattern including a block pattern, and the orthographic projection of the active layer pattern of the compensation transistor on the substrate is located within the orthographic projection of the block pattern of the first power signal line pattern on the substrate.

9. The display panel according to claim 8, wherein, The first power signal line pattern also includes a strip pattern connected to the block pattern, the width of which is 3.5µm to 5µm.

10. The display panel according to claim 8 or 9, wherein, The pixel driving circuit further includes a driving transistor, and the first active layer includes the active layer pattern of the driving transistor. The display panel also includes: A bottom metal layer is disposed on the side of the first active layer near the substrate; the bottom metal layer includes a bottom metal protection pattern, and the orthographic projection of the active layer pattern of the driving transistor on the substrate is located within the orthographic projection of the bottom metal protection pattern on the substrate; the bottom metal protection pattern is connected to the first power signal line pattern of the second source-drain metal layer.

11. The display panel according to any one of claims 8 to 10, wherein, The display panel also includes: An anode layer disposed on the side of the driving circuit layer away from the substrate; The anode layer includes a first anode and a second anode, the first anode being connected to the pixel driving circuit of one of the sub-pixels in the pixel group, and the second anode being connected to the pixel driving circuit of another sub-pixel in the pixel group; The first anode is disposed above the block pattern of the first power signal line pattern, and the ratio of the overlapping area of ​​the first anode and the block pattern to the area of ​​the first anode is greater than a set threshold.

12. The display panel according to any one of claims 1 to 11, wherein, The substrate includes at least two flexible substrate layers and at least two buffer layers.

13. A display device, wherein, Includes the display panel as described in any one of claims 1 to 12.

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