Display panel and display device

Abstract

A display panel. Two adjacent sub-pixels among a row of sub-pixels form a pixel group; a pixel driving circuit comprises a specified transistor, at least one signal line comprises a specified signal line, and the specified transistor is coupled to the specified signal line; the display panel comprises a substrate, a first active layer, a specified gate metal layer, and a first source-drain metal layer; the first active layer comprises an active layer first electrode pattern of the specified transistor; the specified gate metal layer comprises a specified signal line pattern; the first source-drain metal layer comprises a specified signal line bridging pattern, and in one pixel group, the active layer first electrode pattern of the specified transistor of one sub-pixel is connected to the active layer first electrode pattern of the specified transistor of the other sub-pixel; and the specified signal line bridging pattern is located in an area where one sub-pixel is located, and the specified signal line bridging pattern is connected to the active layer first electrode pattern of the specified transistor of one of the sub-pixels and is also connected to the specified signal line pattern.

Description

Display panel and display device

[0001] The present application claims priority to Chinese Patent Application No. 202410814707.X, filed on June 21, 2024, the entire contents of which are incorporated herein by reference. TECHNICAL FIELD

[0002] The present application relates to the technical field of display, in particular to a display panel and a display device. BACKGROUND

[0003] With the rapid development of modern electronic information technology, the display industry is also constantly progressing, and display products are increasingly widely used in various fields.

[0004] For example, OLED (Organic Light-Emitting Diode) display products gradually occupy an important position in the market due to their advantages such as thinness, high brightness, low power consumption, good flexibility, fast response, etc. OLED display products allow more users to enjoy a good visual sensory experience, and users also have higher requirements for OLED display products. However, the screen dark spots of OLED display products greatly affect the user experience effect. SUMMARY

[0005] In one aspect, a display panel is provided, the display panel includes a plurality of sub-pixels, the plurality of sub-pixels are arranged into a plurality of rows along a first direction, and adjacent two sub-pixels in a row of sub-pixels serve as a pixel group; one sub-pixel in the plurality of sub-pixels includes a pixel driving circuit, the pixel driving circuit is coupled with at least one signal line, the pixel driving circuit includes a specified transistor, the at least one signal line includes a specified signal line, and the specified transistor is coupled with the specified signal line; the display panel includes a substrate, a first active layer disposed on one side of the substrate, a specified gate metal layer disposed on a side of the first active layer away from the substrate, and a first source-drain metal layer disposed on a side of the specified gate metal layer away from the substrate; the first active layer includes an active layer pattern of the specified transistor, the active layer pattern of the specified transistor includes an active layer first pole pattern, in a pixel group, the active layer first pole pattern of the specified transistor of one sub-pixel is connected with the active layer first pole pattern of the specified transistor of another sub-pixel; the specified gate metal layer includes a specified signal line pattern of the specified signal line; the first source-drain metal layer includes a specified signal line bridge pattern, in a pixel group, the specified signal line bridge pattern is located in a region of one sub-pixel, the specified signal line bridge pattern is connected with the active layer first pole pattern of the specified transistor of one of the sub-pixels, and is also connected with the specified signal line pattern.

[0006] In some embodiments, in one pixel group, the active layer first pole pattern of a designated transistor of one sub-pixel is connected to a designated connection point with the active layer first pole pattern of a designated transistor of another sub-pixel, and the designated signal line bridging pattern is connected to the designated connection point.

[0007] In some embodiments, in one pixel group, the active layer patterns of the designated transistors of two sub-pixels are mirror symmetrical, the designated connection point is located on the mirror symmetry axis of the active layer patterns of the designated transistors of the two sub-pixels, and the designated signal line pattern extends along a first direction and passes through the regions where the two sub-pixels are located.

[0008] In some embodiments, the width of the designated signal line bridging pattern is greater than a set width.

[0009] In some embodiments, the pixel driving circuit further comprises other transistors in addition to the designated transistors, the first active layer further comprises active layer patterns of the other transistors, the active layer patterns of the other transistors comprise active layer channel patterns, the active layer patterns of the designated transistors comprise active layer channel patterns, and the width-length ratio of the active layer channel patterns of the designated transistors is greater than the width-length ratio of the active layer channel patterns of the other transistors.

[0010] In some embodiments, the designated transistors comprise a third reset transistor, the designated signal lines comprise a third initialization signal line, the third reset transistor is coupled to the third initialization signal line, the first active layer comprises an active layer pattern of the third reset transistor, the active layer pattern of the third reset transistor comprises an active layer first pole pattern, the designated gate metal layer comprises a third initialization signal line pattern of the third initialization signal line, and the designated signal line bridging pattern comprises a third initialization signal line bridging pattern, and the first source-drain metal layer comprises the third initialization signal line bridging pattern.

[0011] In some embodiments, the signal lines further comprise a first initialization signal line, the designated gate metal layer further comprises a first initialization signal line pattern of the first initialization signal line, the first initialization signal line pattern extends along a first direction and passes through the regions where the two sub-pixels in one pixel group are located, and the third initialization signal line bridging pattern overlaps the first initialization signal line pattern.

[0012] In some embodiments, the pixel driving circuit further comprises a compensation transistor, the signal lines further comprise a first power supply signal line, the display panel further comprises a second active layer arranged between the first active layer and the designated gate metal layer and a second source-drain metal layer arranged on the side of the first source-drain metal layer away from the substrate, the second active layer comprises an active layer pattern of the compensation transistor, the second source-drain metal layer comprises a first power supply signal line pattern of the first power supply signal line, the first power supply signal line pattern comprises a block pattern, and the orthographic projection of the active layer pattern of the compensation transistor on the substrate is located within the orthographic projection of the block pattern of the first power supply signal line pattern on the substrate.

[0013] In some embodiments, the first power signal line pattern further comprises a strip pattern connected with the block pattern, and a width of the strip pattern is 3.5um-5um.

[0014] In some embodiments, the pixel driving circuit further comprises a driving transistor, the first active layer comprises an active layer pattern of the driving transistor; the display panel further comprises a bottom metal layer disposed on a side of the first active layer close to the substrate; the bottom metal layer comprises a bottom metal protection pattern, a normal projection of the active layer pattern of the driving transistor on the substrate is located within a normal projection of the bottom metal protection pattern on the substrate; and the bottom metal protection pattern is connected with the first power signal line pattern of the second source-drain metal layer.

[0015] In some embodiments, the display panel further comprises an anode layer disposed on a side of the driving circuit layer away from the substrate; the anode layer comprises a first anode and a second anode, the first anode is connected with the pixel driving circuit of one sub-pixel in the pixel group, and the second anode is connected with the pixel driving circuit of another sub-pixel in the pixel group; the first anode is disposed above the block pattern of the first power signal line pattern, and a ratio of an overlapping area of the first anode and the block pattern to an area of the first anode is greater than a set threshold value.

[0016] In some embodiments, the substrate comprises at least two flexible substrates and at least two buffer layers.

[0017] In another aspect, a display device is provided, comprising the display panel according to any one of the above embodiments. BRIEF DESCRIPTION OF DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the present application, the following will briefly introduce the drawings needed to be used in some embodiments of the present application. Obviously, the drawings in the following description are only the drawings of some embodiments of the present application, and other drawings can also be obtained by those skilled in the art according to these drawings. In addition, the drawings in the following description can be regarded as schematic diagrams, and are not limited to the actual size of the product, the actual process of the method, the actual timing of the signal, etc. involved in the embodiments of the present application.

[0019] FIG. 1 is a plan view of a display panel according to some embodiments;

[0020] FIG. 2 is a cross-sectional view of a display panel according to some embodiments;

[0021] FIG. 3 is a pixel driving circuit according to some embodiments;

[0022] FIG. 4 is a film layer stacking plan view of a display panel according to some embodiments;

[0023] FIG. 5 is another film layer stacking plan view of a display panel according to some embodiments;

[0024] Figure 6 is a film layer stack plan view of yet another display panel of some embodiments;

[0025] Figure 7 is a film layer stack plan view of yet another display panel of some embodiments;

[0026] Figure 8 is a film layer stack plan view of yet another display panel of some embodiments;

[0027] Figure 9 is a film layer stack plan view of yet another display panel of some embodiments;

[0028] Figure 10 is a film layer stack plan view of yet another display panel of some embodiments;

[0029] Figure 11 is a film layer stack plan view of yet another display panel of some embodiments;

[0030] Figure 12 is a film layer stack plan view of yet another display panel of some embodiments;

[0031] Figure 13 is a film layer stack plan view of yet another display panel of some embodiments;

[0032] Figure 14 is a film layer stack plan view of yet another display panel of some embodiments;

[0033] Figure 15 is an Aging process layout of some embodiments;

[0034] Figure 16 is a film layer stack plan view of yet another display panel of some embodiments;

[0035] Figure 17 is a film layer stack plan view of yet another display panel of some embodiments;

[0036] Figure 18 is a film layer stack cross-sectional view of Figure 17;

[0037] Figure 19 is a film layer stack plan view of yet another display panel of some embodiments;

[0038] Figure 20 is a film layer stack cross-sectional view of Figure 19;

[0039] Figure 21 is a film layer stack plan view of yet another display panel of some embodiments;

[0040] Figure 22 is a film layer stack cross-sectional view of Figure 21;

[0041] Figure 23 is a film layer stack plan view of yet another display panel of some embodiments;

[0042] Figure 24 is a film layer stack cross-sectional view of Figure 23;

[0043] Figure 25 is a film layer stack plan view of yet another display panel of some embodiments;

[0044] Figure 26 is a cross-sectional view of the film layer stack of Figure 25;

[0045] Figure 27 is a plan view of a film layer stack of yet another display panel, in accordance with some embodiments;

[0046] Figure 28 is a cross-sectional view of the film layer stack of Figure 27;

[0047] Figure 29 is a plan view of a film layer stack of yet another display panel, in accordance with some embodiments;

[0048] Figure 30 is a cross-sectional view of the film layer stack of Figure 29;

[0049] Figure 31 is a plan view of a film layer stack of yet another display panel, in accordance with some embodiments;

[0050] Figure 32 is a cross-sectional view of the film layer stack of Figure 31;

[0051] Figure 33 is a cross-sectional view of Figure 31 along section line A-A;

[0052] Figure 34 is a cross-sectional view of Figure 31 along section line B-B;

[0053] Figure 35 is a plan view of a film layer stack of yet another display panel, in accordance with some embodiments;

[0054] Figure 36 is a cross-sectional view of the film layer stack of Figure 35;

[0055] Figure 37 is a plan view of a film layer stack of yet another display panel, in accordance with some embodiments;

[0056] Figure 38 is a cross-sectional view of the film layer stack of Figure 37;

[0057] Figure 39 is a plan view of a film layer stack of yet another display panel, in accordance with some embodiments;

[0058] Figure 40 is a cross-sectional view of the film layer stack of Figure 39;

[0059] Figure 41 is a plan view of a film layer stack of yet another display panel, in accordance with some embodiments;

[0060] Figure 42 is a cross-sectional view of the film layer stack of Figure 41;

[0061] Figure 43 is a plan view of a film layer stack of yet another display panel, in accordance with some embodiments;

[0062] Figure 44 is a cross-sectional view of the film layer stack of Figure 43;

[0063] Figure 45 is a plan view of a film layer stack of yet another display panel, in accordance with some embodiments;

[0064] Figure 46 is a plan view of a film layer stack of yet another display panel, in accordance with some embodiments;

[0065] Figure 47 is a stacked cross-sectional view of the substrates in some embodiments;

[0066] Figure 48 is a plan view of a display device according to some embodiments. Detailed Implementation

[0067] The technical solutions in some embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this application are within the scope of protection of this application.

[0068] Unless the context otherwise requires, throughout the specification and claims, the term "comprise" and its other forms, such as the third-person singular "comprises" and the present participle "comprising," are interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiments," "example," "specific example," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this application. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0069] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this application, unless otherwise stated, "a plurality of" means two or more.

[0070] In describing some embodiments, "coupled" and "connected," and variations thereof, can be used. For example, the phrase "connected to" can be used to indicate that two or more elements are in direct physical or electrical contact with one another. As another example, the phrase "coupled to" can be used to indicate that two or more elements are in direct physical or electrical contact with one another. However, "coupled" or "communicatively coupled" can also mean that two or more elements are not in direct contact with one another, but yet still co-operate or interact with one another. The embodiments disclosed herein are not necessarily limited in scope by the contents herein.

[0071] "at least one of A, B, and C" has the same meaning as "at least one of A, B, or C" and includes the following combinations: only A, only B, only C, a combination of A and B, a combination of A and C, a combination of B and C, and a combination of A, B, and C.

[0072] "A and / or B" includes the following three combinations: only A, only B, and a combination of A and B.

[0073] It will be understood that when a layer or element is referred to as being "on" another layer or substrate, it can be directly on the other layer or substrate, or intervening layers can also be present.

[0074] Exemplary embodiments are described herein with reference to cross-sectional and / or plan view illustrations that are idealized illustrations. In the interest of clarity, not all of the scale of the layers and regions can be shown in the drawings, which can distort the representation of the actual sizes of the layers and regions. Thus, the exemplary embodiments should not be construed as limited to the precise shapes and dimensions illustrated in the drawings. In particular, the exemplary embodiments are not limited to the precise shapes and dimensions illustrated in the drawings, and can include shapes and dimensions that are different from those illustrated in the drawings. For example, an etched region that is illustrated as a rectangle will typically have curved features. Thus, the regions illustrated in the drawings are schematic and not intended to be limiting of the actual shapes of the regions of the devices, and are not intended to limit the scope of the exemplary embodiments.

[0075] With the development of display technology, there are various types of display panels, such as an organic light-emitting diode (OLED) display panel, a micro organic light-emitting diode (Micro OLED) display panel, a quantum dot light emitting diode (QLED) display panel, a mini light-emitting diode (Mini LED) display panel, or a micro light-emitting diode (Micro LED) display panel, etc. Some embodiments of the present application take the OLED display panel as an example for illustration.

[0076] OLED is a current type of organic light-emitting device, which is a phenomenon of light emission by injection and recombination of carriers. The light emission intensity is proportional to the injected current. Under the action of an electric field, holes generated by the anode and electrons generated by the cathode will move and be injected into the hole transport layer and the electron transport layer, respectively, and migrate to the light-emitting layer. When the two meet in the light-emitting layer, energy excitons are generated, which excite light-emitting molecules to produce visible light. Light-emitting molecules produce red, green and blue three primary colors (RGB three primary colors) depending on their formulations, which constitute the basic colors. The OLED display panel 1000 made of OLED has the advantages of high brightness, high efficiency, wide viewing angle, self-luminous, full solid, ultra-thin and ultra-light, simple manufacturing process, fast response speed, full-color display, and good mechanical processing performance, etc. It has been more and more widely used in display products such as mobile phones, tablets, computers, and televisions. With the application of OLED display panel 1000 in display products such as mobile phones, computers, and tablets, the requirements for the display effect of OLED display panel 1000 are becoming higher and higher.

[0077] In order to achieve better display effect, the pixel driving circuit 10 for driving OLED light emission in the OLED display panel 1000 is constantly optimized. However, the increasingly complex and dense pixel driving circuit 10 also brings many problems, such as the appearance of non-extinguishing points (bright spots) and / or non-light-emitting points (dark spots) in the OLED display panel 1000.

[0078] For example, in the full-color, red, green, and blue point light display screen, it can be seen that the sub-pixels in a certain area do not emit light, and in each point light display screen, a non-light-emitting point (dark spot) is presented.

[0079] The specific settings of the display panel 1000 are introduced below.

[0080] In some embodiments, as shown in FIG. 1, the display panel 1000 includes a plurality of sub-pixels P, one of which includes one pixel driving circuit 10 and one to-be-driven element 20 coupled with the pixel driving circuit 10. In some examples, as shown in FIG. 3, the pixel driving circuit 10 includes a first transistor T1 (first reset transistor), a second transistor T2 (compensation transistor), a third transistor T3 (driving transistor), a fourth transistor T4 (write transistor), a fifth transistor T5 (first light-emitting control transistor), a sixth transistor T6 (second light-emitting control transistor), a seventh transistor T7 (second reset transistor), and a coupling capacitor Cst. In some examples, the pixel driving circuit 10 further includes an eighth transistor T8 (third reset transistor).

[0081] The first transistor T1 is a P-type transistor, the first electrode T11 of the first transistor T1 is coupled with the first initialization signal line Vinit1, the gate electrode T13 of the first transistor T1 is coupled with the first reset signal line Reset1, and the second electrode T12 of the first transistor T1 is coupled with the third node N3.

[0082] The second transistor T2 is an N-type transistor, the first electrode T21 of the second transistor T2 is coupled with the first node N1, the first gate electrode T23 of the second transistor T2 is coupled with the first gate signal line Gate1, the second gate electrode T24 of the second transistor T2 is coupled with the second gate signal line Gate2, and the second electrode T22 of the second transistor T2 is coupled with the third node N3.

[0083] The third transistor T3 is a P-type transistor, the first electrode T31 of the third transistor T3 is coupled with the second node N2, the gate electrode T33 of the third transistor T3 is coupled with the first node N1, and the second electrode T32 of the third transistor T3 is coupled with the third node N3.

[0084] The fourth transistor T4 is a P-type transistor, the first electrode T41 of the fourth transistor T4 is coupled with the data signal line Data, the gate electrode T43 of the fourth transistor T4 is coupled with the third gate signal line Gate3, and the second electrode T42 of the fourth transistor T4 is coupled with the second node N2.

[0085] The fifth transistor T5 is a P-type transistor, the first electrode T51 of the fifth transistor T5 is coupled with the first power signal line VDD, the gate electrode T53 of the fifth transistor T5 is coupled with the light-emitting control signal line EM, and the second electrode T52 of the fifth transistor T5 is coupled with the second node N2.

[0086] The sixth transistor T6 is a P-type transistor, a first electrode T61 of the sixth transistor T6 is coupled with the third node N3, a gate electrode T63 of the sixth transistor T6 is coupled with the light-emitting control signal line EM, and a second electrode T62 of the sixth transistor T6 is coupled with the fourth node N4.

[0087] The seventh transistor T7 is a P-type transistor, a first electrode T71 of the seventh transistor T7 is coupled with the second initialization signal line Vinit2, a gate electrode T73 of the seventh transistor T7 is coupled with the second reset signal line Reset2, and a second electrode T72 of the seventh transistor T7 is coupled with the fourth node N4.

[0088] The eighth transistor T8 is a P-type transistor, a first electrode T81 of the eighth transistor T8 is coupled with the third initialization signal line Vinit3, a gate electrode T83 of the eighth transistor T8 is coupled with the second reset signal line Reset2, and a second electrode T82 of the eighth transistor T8 is coupled with the second node N2.

[0089] A first plate Cst1 of the coupling capacitor Cst is coupled with the first power supply signal line VDD, and a second plate Cst2 of the coupling capacitor Cst is coupled with the first node N1.

[0090] The first end 21 of the to-be-driven element 20 is coupled with the fourth node N4, so as to realize the coupling of the to-be-driven element 20 and the pixel driving circuit 10, and the second end 22 of the to-be-driven element 20 is coupled with the second power supply signal line VSS.

[0091] The following introduces the specific film layer setting of the pixel driving circuit 10 as shown in FIG. 3 in the display panel 1000 in some embodiments.

[0092] In some embodiments, as shown in FIG. 1, the display panel 1000 includes a display area AA and a peripheral area BB located at least one side of the display area AA, the display area AA is provided with a plurality of sub-pixels P, one sub-pixel P includes one pixel driving circuit 10 and one to-be-driven element 20 coupled with the pixel driving circuit 10.

[0093] Exemplarily, as shown in FIG. 1, a display panel 1000 includes a plurality of sub-pixels P, the sub-pixel P is the smallest unit for the display panel 1000 to display a picture, each sub-pixel P can display a single color, for example, red (R), green (G) or blue (B); the plurality of sub-pixels P can be arranged in an array, for example, the plurality of sub-pixels P are arranged into multiple rows along a first direction X, and the plurality of sub-pixels P are arranged into multiple columns along a second direction Y; each sub-pixel P includes a to-be-driven element 20 and a pixel driving circuit 10 for driving the to-be-driven element 20 to emit light; the pixel driving circuit 10 can be constituted by a plurality of transistors and at least one capacitor; in each sub-pixel P, the to-be-driven element 20 is electrically connected with the corresponding pixel driving circuit 10 below, specifically, an anode of the to-be-driven element 20 is electrically connected with the corresponding pixel driving circuit 10, so that a first power signal input into the inside of the display panel 1000 is transmitted to the anode of the to-be-driven element 20 through the pixel driving circuit 10, and a second power signal is transmitted to a cathode of the to-be-driven element 20 at the same time, so as to form an electric field between the anode and the cathode of the to-be-driven element 20, and make the to-be-driven element 20 emit light.

[0094] In some embodiments, as shown in FIG. 2, the display panel 1000 can include, for example, a substrate 100, a driving circuit layer 200, a driving element layer 300 and an encapsulation layer 400 which are sequentially stacked. The substrate 100 provides a bearing basis for other film layer structures of the display panel 1000, that is, other film layer structures of the display panel 1000, for example, the driving circuit layer 200, the driving element layer 300 and the encapsulation layer 400 are made on the substrate 100; the substrate 100 can be a rigid substrate, and the material of the rigid substrate can be, for example, a rigid material such as glass material, quartz material or sapphire material; the substrate 100 can also be a flexible substrate, and the material of the flexible substrate can be, for example, a flexible material such as polyimide (PI) or saturated polyester (PET). The driving circuit layer 200 is used for arranging the pixel driving circuit 10. The driving element layer 300 is used for arranging the to-be-driven element 20, and the to-be-driven element 20 is, for example, a light emitting device. The encapsulation layer 400 is used for protecting the display panel 1000, preventing water vapor in the air from entering the inside of the display panel 1000 and damaging the display panel 1000.

[0095] In some embodiments, the driving circuit layer 200 of the display panel 1000 comprises a first active layer 201, a first gate insulating layer 202, a first gate metal layer 203, a second gate insulating layer 204, a second gate metal layer 205, a first interlayer dielectric layer 206, a second active layer 207, a third gate insulating layer 208, a third gate metal layer 209, a second interlayer dielectric layer 210, a first source-drain metal layer 211, a passivation layer 212, a first planarization layer 213, a second source-drain metal layer 214, a second planarization layer 215, which are sequentially stacked.

[0096] The following takes the structure included in a pixel driving circuit 10 as an example to introduce the patterns of each film layer of the display panel 1000.

[0097] Exemplarily, as shown in FIG. 4, the driving circuit layer 200 of the display panel 1000 comprises a first active layer 201, which is disposed on one side, for example, the upper side of the substrate 100. The first active layer 201 comprises the active layer patterns of the first transistor T1, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8.

[0098] As shown in FIG. 4, the active layer pattern 2011 of the first transistor T1 comprises a first active layer electrode pattern 2011-1, an active layer channel pattern 2011-3, and a second active layer electrode pattern 2011-2, which are sequentially connected; the active layer pattern 2013 of the third transistor T3 comprises a first active layer electrode pattern 2013-1, an active layer channel pattern 2013-3, and a second active layer electrode pattern 2013-2, which are sequentially connected; the active layer pattern 2014 of the fourth transistor T4 comprises a first active layer electrode pattern 2014-1, an active layer channel pattern 2014-3, and a second active layer electrode pattern 2014-2, which are sequentially connected; the active layer pattern 2015 of the fifth transistor T5 comprises a first active layer electrode pattern 2015-1, an active layer channel pattern 2015-3, and a second active layer electrode pattern 2015-2, which are sequentially connected; the active layer pattern 2016 of the sixth transistor T6 comprises a first active layer electrode pattern 2016-1, an active layer channel pattern 2016-3, and a second active layer electrode pattern 2016-2, which are sequentially connected; the active layer pattern 2017 of the seventh transistor T7 comprises a first active layer electrode pattern 2017-1, an active layer channel pattern 2017-3, and a second active layer electrode pattern 2017-2, which are sequentially connected; and the active layer pattern 2018 of the eighth transistor T8 comprises a first active layer electrode pattern 2018-1, an active layer channel pattern 2018-3, and a second active layer electrode pattern 2018-2, which are sequentially connected.

[0099] Exemplarily, as shown in FIG. 5, the driving circuit layer 200 of the display panel 1000 further comprises a first gate metal layer 203, which is arranged on the side of the first active layer 201 away from the substrate 100. The first gate metal layer 203 comprises a first reset signal line pattern 2031 extending along the first direction X, a second reset signal line pattern 2032 extending along the first direction X, a light-emitting control signal line pattern 2033 extending along the first direction X, a third gate signal line pattern 2034 extending along the first direction X, and a gate pattern 2035 of the third transistor T3.

[0100] As shown in FIG. 5, the first reset signal line pattern 2031 overlaps with the active layer channel pattern 2011-3 of the first transistor T1 in the direction perpendicular to the substrate 100, and the part of the first reset signal line pattern 2031 overlapping with the active layer channel pattern 2011-3 of the first transistor T1 serves as the gate pattern 2031-1 of the first transistor T1.

[0101] As shown in FIG. 5, the second reset signal line pattern 2032 respectively overlaps with the active layer channel pattern 2017-3 of the seventh transistor T7 and the active layer channel pattern 2018-3 of the eighth transistor T8 in the direction perpendicular to the substrate 100, and the part of the second reset signal line pattern 2032 overlapping with the active layer channel pattern 2017-3 of the seventh transistor T7 serves as the gate pattern 2032-1 of the seventh transistor T7; the part of the second reset signal line pattern 2032 overlapping with the active layer channel pattern 2018-3 of the eighth transistor T8 serves as the gate pattern 2032-2 of the eighth transistor T8.

[0102] As shown in FIG. 5, the light-emitting control signal line pattern 2033 respectively overlaps with the active layer channel pattern 2015-3 of the fifth transistor T5 and the active layer channel pattern 2016-3 of the sixth transistor T6 in the direction perpendicular to the substrate 100, and the part of the light-emitting control signal line pattern 2033 overlapping with the active layer channel pattern 2015-3 of the fifth transistor T5 serves as the gate pattern T53 of the fifth transistor T5; the part of the light-emitting control signal line pattern 2033 overlapping with the active layer channel pattern 2016-3 of the sixth transistor T6 serves as the gate pattern T63 of the sixth transistor T6.

[0103] As shown in FIG. 5, the third gate signal line pattern 2034 overlaps with the active layer channel pattern 2014-3 of the fourth transistor T4 in the direction perpendicular to the substrate 100, and the part of the third gate signal line pattern 2034 overlapping with the active layer channel pattern 2014-3 of the fourth transistor T4 serves as the gate pattern 2034-1 of the fourth transistor T4.

[0104] In some examples, the overlap means that a part of a pattern of one film layer is arranged opposite to a part of a pattern of another film layer in a direction perpendicular to the substrate 100. The arrangement opposite can be explained as that a part of a pattern of one film layer has a partial overlap with a part of a pattern of another film layer in a direction perpendicular to the substrate 100. There can be other film layers, such as insulating layers, between the part of the pattern of one film layer and the part of the pattern of another film layer.

[0105] In some examples, the overlap means that a part of a pattern of one film layer is arranged opposite to a part of a pattern of another film layer in a direction perpendicular to the substrate 100. The arrangement opposite can be explained as that a part of a pattern of one film layer has a partial overlap with a part of a pattern of another film layer in a direction perpendicular to the substrate 100. There can be other film layers, such as insulating layers, between the part of the pattern of one film layer and the part of the pattern of another film layer.

[0106] In some examples, the overlap means that a part of a pattern of one film layer is arranged opposite to a part of a pattern of another film layer in a direction perpendicular to the substrate 100. The arrangement opposite can be explained as that a part of a pattern of one film layer has a partial overlap with a part of a pattern of another film layer in a direction perpendicular to the substrate 100. There can be other film layers, such as insulating layers, between the part of the pattern of one film layer and the part of the pattern of another film layer.

[0107] In some examples, the overlap means that a part of a pattern of one film layer is arranged opposite to a part of a pattern of another film layer in a direction perpendicular to the substrate 100. The arrangement opposite can be explained as that a part of a pattern of one film layer has a partial overlap with a part of a pattern of another film layer in a direction perpendicular to the substrate 100. There can be other film layers, such as insulating layers, between the part of the pattern of one film layer and the part of the pattern of another film layer.

[0108] In some examples, the overlap means that a part of a pattern of one film layer is arranged opposite to a part of a pattern of another film layer in a direction perpendicular to the substrate 100. The arrangement opposite can be explained as that a part of a pattern of one film layer has a partial overlap with a part of a pattern of another film layer in a direction perpendicular to the substrate 100. There can be other film layers, such as insulating layers, between the part of the pattern of one film layer and the part of the pattern of another film layer.

[0109] In some examples, the overlap means that a part of a pattern of one film layer is arranged opposite to a part of a pattern of another film layer in a direction perpendicular to the substrate 100. The arrangement opposite can be explained as that a part of a pattern of one film layer has a partial overlap with a part of a pattern of another film layer in a direction perpendicular to the substrate 100. There can be other film layers, such as insulating layers, between the part of the pattern of one film layer and the part of the pattern of another film layer.

[0110] Exemplarily, as shown in FIG. 8, the driving circuit layer 200 of the display panel 1000 further comprises a third gate metal layer 209, which is arranged on the side of the second active layer 207 away from the substrate 100. The third gate metal layer 209 comprises a first initialization signal line pattern 2092 extending along the first direction X, a second initialization signal line pattern 2091 extending along the first direction X, a third initialization signal line pattern 2093 extending along the first direction X, and a second gate signal line pattern 2094 extending along the first direction X.

[0111] As shown in FIG. 8, the first initialization signal line pattern 2092 is arranged corresponding to the second reset signal line pattern 2032; the second initialization signal line pattern 2091 is arranged corresponding to the first reset signal line pattern 2031; the third initialization signal line pattern 2093 is arranged corresponding to the light-emitting control signal line pattern 2033; and the second gate signal line pattern 2094 is arranged corresponding to the first gate signal line pattern 2051. The active layer channel pattern 2071-3 of the second transistor T2 overlaps the second gate signal line pattern 2094 in the direction perpendicular to the substrate 100, and the part of the second gate signal line pattern 2094 overlapping the active layer channel pattern 2071-3 of the second transistor T2 serves as the second gate pattern 2094-1 of the second transistor T2.

[0112] Exemplarily, as shown in FIG. 9, the driving circuit layer 200 of the display panel 1000 further comprises a second interlayer dielectric layer 210. A via hole process is performed on the second interlayer dielectric layer 210 to form a via hole 2101 penetrating through the first gate insulating layer 202, the second gate insulating layer 204, the first interlayer dielectric layer 206, the third gate insulating layer 208, and the second interlayer dielectric layer 210, a via hole 2102 penetrating through the third gate insulating layer 208 and the second interlayer dielectric layer 210, a via hole 2103 penetrating through the first interlayer dielectric layer 206, the third gate insulating layer 208, and the second interlayer dielectric layer 210, a via hole 2104 penetrating through the second gate insulating layer 204, the first interlayer dielectric layer 206, the third gate insulating layer 208, and the second interlayer dielectric layer 210, and a via hole 2105 penetrating through the second interlayer dielectric layer 210.

[0113] Exemplarily, as shown in FIG. 10, the driving circuit layer 200 of the display panel 1000 further comprises a first source-drain metal layer 211, which is arranged on the side of the second interlayer dielectric layer 210 away from the substrate 100.

[0114] As shown in FIG. 10, and in combination with FIG. 4, FIG. 9, the first source-drain metal layer 211 includes a first electrode pattern 2111-1 of the first transistor T1 and a second electrode pattern 2111-2 of the first transistor T1; the first electrode pattern 2111-1 of the first transistor T1 is connected with the active layer first electrode pattern 2011-1 of the first transistor T1 through the via 2101 penetrating through the first gate insulating layer 202, the second gate insulating layer 204, the first interlayer dielectric layer 206, the third gate insulating layer 208, and the second interlayer dielectric layer 210, and the first electrode pattern 2111-1 of the first transistor T1 is connected with the first initialization signal line pattern 2092 through the via 2105 penetrating through the second interlayer dielectric layer 210; the second electrode pattern 2111-2 of the first transistor T1 is connected with the active layer second electrode pattern 2011-2 of the first transistor T1 through the via 2101 penetrating through the first gate insulating layer 202, the second gate insulating layer 204, the first interlayer dielectric layer 206, the third gate insulating layer 208, and the second interlayer dielectric layer 210.

[0115] As shown in FIG. 10, and in combination with FIG. 4, FIG. 9, the first source-drain metal layer 211 includes a first electrode pattern 2112-1 of the second transistor T2 and a second electrode pattern 2112-2 of the second transistor T2; the first electrode pattern 2112-1 of the second transistor T2 is connected with the active layer first electrode pattern 2071-1 of the second transistor T2 through the via 2102 penetrating through the third gate insulating layer 208 and the second interlayer dielectric layer 210, and the first electrode pattern 2112-1 of the second transistor T2 is connected with the gate pattern 2035 of the third transistor T3 through the via 2104 penetrating through the second gate insulating layer 204, the first interlayer dielectric layer 206, the third gate insulating layer 208, and the second interlayer dielectric layer 210; the second electrode pattern 2112-2 of the second transistor T2 is connected with the active layer second electrode pattern 2071-2 of the second transistor T2 through the via 2102 penetrating through the third gate insulating layer 208 and the second interlayer dielectric layer 210; the second electrode pattern 2112-2 of the second transistor T2 is connected with the second electrode pattern 2111-2 of the first transistor T1.

[0116] As shown in FIG. 10, and in combination with FIGS. 4 and 9, the first source-drain metal layer 211 includes a first electrode pattern 2113-1 of the third transistor T3 and a second electrode pattern 2113-2 of the third transistor T3; the first electrode pattern 2113-1 of the third transistor T3 is connected to the active layer first electrode pattern 2013-1 of the third transistor T3 through the via 2101 penetrating the first gate insulating layer 202, the second gate insulating layer 204, the first interlayer dielectric layer 206, the third gate insulating layer 208, and the second interlayer dielectric layer 210; the second electrode pattern 2113-2 of the third transistor T3 is connected to the active layer second electrode pattern 2013-2 of the third transistor T3 through the via 2101 penetrating the first gate insulating layer 202, the second gate insulating layer 204, the first interlayer dielectric layer 206, the third gate insulating layer 208, and the second interlayer dielectric layer 210; and the second electrode pattern 2113-2 of the third transistor T3 is connected to the second electrode pattern 2112-2 of the second transistor T2.

[0117] As shown in FIG. 10, and in combination with FIGS. 4 and 9, the first source-drain metal layer 211 includes a first electrode pattern 2114-1 of the fourth transistor T4 and a second electrode pattern 2114-2 of the fourth transistor T4; the first electrode pattern 2114-1 of the fourth transistor T4 is connected to the active layer first electrode pattern 2014-1 of the fourth transistor T4 through the via 2101 penetrating the first gate insulating layer 202, the second gate insulating layer 204, the first interlayer dielectric layer 206, the third gate insulating layer 208, and the second interlayer dielectric layer 210; the second electrode pattern 2114-2 of the fourth transistor T4 is connected to the active layer second electrode pattern 2014-2 of the fourth transistor T4 through the via 2101 penetrating the first gate insulating layer 202, the second gate insulating layer 204, the first interlayer dielectric layer 206, the third gate insulating layer 208, and the second interlayer dielectric layer 210; and the second electrode pattern 2114-2 of the fourth transistor T4 is connected to the first electrode pattern 2113-1 of the third transistor T3.

[0118] As shown in FIG. 10, and in combination with FIGS. 4 and 9, the first source-drain metal layer 211 includes a first electrode pattern 2115-1 of the fifth transistor T5 and a second electrode pattern 2115-2 of the fifth transistor T5; the first electrode pattern 2115-1 of the fifth transistor T5 is connected with the active layer first electrode pattern 2015-1 of the fifth transistor T5 through the via 2101 penetrating the first gate insulating layer 202, the second gate insulating layer 204, the first interlayer dielectric layer 206, the third gate insulating layer 208, and the second interlayer dielectric layer 210; the second electrode pattern 2115-2 of the fifth transistor T5 is connected with the active layer second electrode pattern 2015-2 of the fifth transistor T5 through the via 2101 penetrating the first gate insulating layer 202, the second gate insulating layer 204, the first interlayer dielectric layer 206, the third gate insulating layer 208, and the second interlayer dielectric layer 210; and the second electrode pattern 2115-2 of the fifth transistor T5 is connected with the second electrode pattern 2114-2 of the fourth transistor T4.

[0119] As shown in FIG. 10, and in combination with FIGS. 4 and 9, the first source-drain metal layer 211 includes a first electrode pattern 2116-1 of the sixth transistor T6 and a second electrode pattern 2116-2 of the sixth transistor T6; the first electrode pattern 2116-1 of the sixth transistor T6 is connected with the active layer first electrode pattern 2016-1 of the sixth transistor T6 through the via 2101 penetrating the first gate insulating layer 202, the second gate insulating layer 204, the first interlayer dielectric layer 206, the third gate insulating layer 208, and the second interlayer dielectric layer 210, and the first electrode pattern 2116-1 of the sixth transistor T6 is connected with the second electrode pattern 2113-2 of the third transistor T3; the second electrode pattern 2116-2 of the sixth transistor T6 is connected with the active layer second electrode pattern 2016-2 of the sixth transistor T6 through the via 2101 penetrating the first gate insulating layer 202, the second gate insulating layer 204, the first interlayer dielectric layer 206, the third gate insulating layer 208, and the second interlayer dielectric layer 210.

[0120] As shown in FIG. 10, and in combination with FIG. 4, FIG. 9, the first source-drain metal layer 211 includes a first electrode pattern 2117-1 of the seventh transistor T7 and a second electrode pattern 2117-2 of the seventh transistor T7; the first electrode pattern 2117-1 of the seventh transistor T7 is connected with the active layer first electrode pattern 2017-1 of the seventh transistor T7 through the via 2101 penetrating through the first gate insulating layer 202, the second gate insulating layer 204, the first interlayer dielectric layer 206, the third gate insulating layer 208, and the second interlayer dielectric layer 210, and the first electrode pattern 2117-1 of the seventh transistor T7 is connected with the second initialization signal line pattern 2091 through the via 2105 penetrating through the second interlayer dielectric layer 210; the second electrode pattern 2117-2 of the seventh transistor T7 is connected with the active layer second electrode pattern 2017-2 of the seventh transistor T7 through the via 2101 penetrating through the first gate insulating layer 202, the second gate insulating layer 204, the first interlayer dielectric layer 206, the third gate insulating layer 208, and the second interlayer dielectric layer 210; and the second electrode pattern 2117-2 of the seventh transistor T7 is connected with the second electrode pattern 2116-2 of the sixth transistor T6.

[0121] As shown in FIG. 10, and in combination with FIG. 4, FIG. 9, the first source-drain metal layer 211 includes a first electrode pattern 2118-1 of the eighth transistor T8 and a second electrode pattern 2118-2 of the eighth transistor T8; the first electrode pattern 2118-1 of the eighth transistor T8 is connected with the active layer first electrode pattern 2018-1 of the eighth transistor T8 through the via 2101 penetrating through the first gate insulating layer 202, the second gate insulating layer 204, the first interlayer dielectric layer 206, the third gate insulating layer 208, and the second interlayer dielectric layer 210; and the second electrode pattern 2118-2 of the eighth transistor T8 is connected with the active layer second electrode pattern 2018-2 of the eighth transistor T8 through the via 2101 penetrating through the first gate insulating layer 202, the second gate insulating layer 204, the first interlayer dielectric layer 206, the third gate insulating layer 208, and the second interlayer dielectric layer 210; and the second electrode pattern 2118-2 of the eighth transistor T8 is connected with the second electrode pattern 2115-2 of the fifth transistor T5.

[0122] As shown in FIG. 10, and in combination with FIG. 9, the first source-drain metal layer 211 includes a first power signal line bridging pattern 2119; the first power signal line bridging pattern 2119 is connected with the first electrode pattern 2115-1 of the fifth transistor T5, and the first power signal line bridging pattern 2119 is connected with the first plate pattern 2052 of the coupling capacitor Cst through the via 2103 penetrating through the first interlayer dielectric layer 206, the third gate insulating layer 208, and the second interlayer dielectric layer 210.

[0123] As shown in FIG. 10, and in combination with FIG. 9, the first source-drain metal layer 211 includes a third initialization signal line bridging pattern 21110; the first electrode pattern 2118-1 of the eighth transistor T8 is connected with the third initialization signal line bridging pattern 21110, and the third initialization signal line bridging pattern 21110 is connected with the third initialization signal line pattern 2093 through the via 2105 penetrating the second interlayer dielectric layer 210.

[0124] As shown in FIG. 10, and in combination with FIG. 9, the first source-drain metal layer 211 includes a third initialization signal line bridging pattern 21110; the first electrode pattern 2118-1 of the eighth transistor T8 is connected with the third initialization signal line bridging pattern 21110, and the third initialization signal line bridging pattern 21110 is connected with the third initialization signal line pattern 2093 through the via 2105 penetrating the second interlayer dielectric layer 210.

[0125] It should be noted that one pattern of a film layer is connected with another pattern, which can be regarded as the two patterns being the same pattern, for example, the first electrode pattern 2118-1 of the eighth transistor T8 on the first source-drain metal layer 211 is connected with the third initialization signal line bridging pattern 21110, which can be understood as the first electrode pattern 2118-1 of the eighth transistor T8 on the first source-drain metal layer 211 and the third initialization signal line bridging pattern 21110 being the same pattern.

[0126] As shown in FIG. 11, the driving circuit layer 200 of the display panel 1000 further includes a passivation layer 212 and a first planarization layer 213, and a via 2131 penetrating the passivation layer 212 and the first planarization layer 213 is formed by a punching process on the first planarization layer 213.

[0127] As shown in FIG. 12, the driving circuit layer 200 of the display panel 1000 further includes a second source-drain metal layer 214, which is disposed on the side of the first source-drain metal layer 211 away from the substrate 100. The second source-drain metal layer 214 includes a data signal line pattern 2143 extending along the second direction Y, a first power signal line pattern 2141 extending along the second direction Y, and an anode tab pattern 2142.

[0128] As shown in FIG. 12, and in combination with FIG. 10 and FIG. 11, the data signal line pattern 2143 is connected with the first electrode pattern 2114-1 of the fourth transistor T4 through the via 2131 penetrating the passivation layer 212 and the first planarization layer 213; the first power signal line pattern 2141 is connected with the first power signal line bridging pattern 2119 through the via 2131 penetrating the passivation layer 212 and the first planarization layer 213; and the anode tab pattern 2142 is connected with the second electrode pattern 2116-2 of the sixth transistor T6 through the via 2131 penetrating the passivation layer 212 and the first planarization layer 213.

[0129] Exemplarily, as shown in FIG. 13, the driving element layer 300 of the display panel 1000 includes an anode layer 301; the anode layer 301 includes a plurality of anode patterns 3010, one anode pattern 3010 is connected with one anode lead pattern 2142 through a via hole penetrating through the second planar layer 215.

[0130] Exemplarily, as shown in FIG. 14, the driving element layer 300 of the display panel 1000 further includes a pixel definition layer 302; the pixel definition layer 302 includes a plurality of openings 3021, one opening 3021 exposes one anode pattern 3010.

[0131] Exemplarily, the driving element layer 300 of the display panel 1000 further includes a light emitting layer 303, the light emitting layer 303 includes a plurality of light emitting patterns, one light emitting pattern is located in one opening 3021.

[0132] Exemplarily, the driving element layer 300 of the display panel 1000 further includes a cathode layer 304, the cathode layer 304 is entirely laid on the side of the light emitting layer 303 away from the substrate 100.

[0133] Through the above setting, the pixel driving circuit 10 as shown in FIG. 3 can be arranged in the display panel 1000.

[0134] It should be noted that the film layer arrangement of the display panel 1000 is not limited to including the above-described film layers. In some embodiments, a plurality of insulating layers can be included between adjacent metal layers; in other embodiments, one or more of the above-described metal layers can be deleted, or one or more metal layers can be added; in still other embodiments, as shown in FIG. 44, the driving element layer 300 of the display panel 1000 can further include a spacer 305 arranged on the side of the pixel definition layer 302 away from the substrate 100. The arrangement of the film layers of the display panel 1000 can be designed according to specific circumstances, which is not limited herein.

[0135] When the display panel 1000 does not display a picture, it is required that the to-be-driven element 20 in the sub-pixel P of the display panel 1000 stops working, i.e., the pixel driving circuit 10 in the sub-pixel P of the display panel 1000 is disconnected, and no current passes through the to-be-driven element 20 coupled with the pixel driving circuit 10. The conduction or disconnection of the pixel driving circuit 10 is controlled by the conduction or disconnection of the transistor in the pixel driving circuit 10, but the transistor, for example, a P-type transistor, may have a leakage current in the off state, i.e., the transistor still has a current passing through in the off state; when the passing leakage current is large enough to make the to-be-driven element 20 of the sub-pixel P work, the sub-pixel P of the display panel 1000 will be lit up, forming a non-extinguishing point (bright spot) on the display panel 1000.

[0136] Exemplarily, as shown in FIG. 3, when the display panel 1000 does not display a picture, i.e. the pixel driving circuit 10 is in a non-emitting stage, the second transistor T2 and the sixth transistor T6 are turned off, the first node N1 is at a high voltage level, and the fourth node N4 is at a low voltage level. When the drain current of the second transistor T2 and the sixth transistor T6 is too large, current will flow through the to-be-driven element 20, causing the to-be-driven element 20 to start working, the sub-pixel P is lit, and a bright spot is formed on the display panel 1000; or when the drain current of the fifth transistor T5, the third transistor T3 and the sixth transistor T6 is too large, current will flow through the to-be-driven element 20, causing the to-be-driven element 20 to start working, the sub-pixel P is lit, and a non-extinguishing point (bright spot) is formed on the display panel 1000.

[0137] In some embodiments, in order to avoid the bright spot defect of the display panel 1000 when it does not display a picture, an electrical aging process (Aging process) can be used to reduce the drain current of the transistor, for example, to reduce the drain current of the P-type transistor, so that the drain current does not reach a level that can cause the to-be-driven element 20 of the sub-pixel P to work, thereby eliminating the bright spot defect caused by the excessively high drain current of the transistor and improving the stability of the transistor.

[0138] Exemplarily, the principle of the Aging process for reducing the drain current of the transistor is as follows: in the display panel 1000, the active layer, the gate metal layer and the source-drain metal layer of the display panel 1000 are combined to form a transistor, for example, a P-type transistor. The active layer includes an active layer source, an active layer channel region and an active layer drain; the gate metal layer includes a gate electrode, which is arranged corresponding to the active layer channel region; the source-drain metal layer includes a source electrode and a drain electrode, the source electrode is connected to the active layer source, and the drain electrode is connected to the active layer drain. The drain electrode of the transistor, for example, the P-type transistor, is given a negative voltage, and the gate electrode is given a positive voltage, so that the electrons in the drain electrode of the transistor are captured by the gate electrode of the gate metal layer. Therefore, holes are induced in the active layer channel region to form a light doped drain (LDD), thereby reducing the electric field between the gate electrode and the drain electrode and reducing the drain current of the transistor.

[0139] Exemplarily, the Aging process can be used to reduce the drain current of the P-type transistor in the pixel driving circuit 10 shown in FIG. 3. The specific Aging process layout is shown in FIG. 15.

[0140] As shown in Fig. 15, wherein, Pattern represents the process layout, Vgh / Vgh-N represents the voltage of high voltage signal, Vgl / Vgl-N represents the voltage of low voltage signal, Vdd represents the voltage of first power signal, Vss represents the voltage of second power signal, Vint1 represents the voltage of first initialization signal, Vint2 represents the voltage of second initialization signal, Vint3 represents the voltage of third initialization signal, Vdata represents the voltage of data signal, Time represents the time used for Aging process.

[0141] Specifically, the line with serial number 1 in Fig. 15 represents: the first Aging process is performed on the first transistor T1 and the seventh transistor T7 respectively; the voltage Vgh / Vgh-N of high voltage signal given to the gate T13 of the first transistor T1 and the gate T73 of the seventh transistor T7 is 15V; the voltage Vgl / Vgl-N of low voltage signal given to the drain of the first transistor T1 and the drain of the seventh transistor T7 is -7V; the voltage Vdd of first power signal is 7V; the voltage Vss of second power signal is 7V; the voltage Vint1 of first initialization signal is -15V; the voltage Vint2 of second initialization signal is -15V; the voltage Vint3 of third initialization signal is 4V; the voltage Vdata of data signal is 4V; and the time Time used for Aging process is 15s.

[0142] The lines with serial numbers 2-10 in Fig. 15 represent the same meaning as the line with serial number 1, which will not be described here.

[0143] After the Aging process is performed on the related P-type transistors in the pixel driving circuit 10 shown in Fig. 3, the leakage current in the pixel driving circuit 10 shown in Fig. 3 is greatly reduced, the probability of bright spot defect of the display panel 1000 when not displaying a picture is reduced, and the stability of the pixel driving circuit 10 shown in Fig. 3 is improved. At the same time, when the display panel 1000 is detected for displaying a picture, the inventors of the present application find that the display panel 1000 has a non-emitting point (dark spot) when displaying a picture. When the position of the non-emitting point (dark spot) of the display panel 1000 is observed using an optical microscope, it can be clearly seen that the pixel at the position of the non-emitting point (dark spot) is obviously burned, so that the display panel 1000 has a burn-type dark spot.

[0144] For the reason of forming the burn-type dark spot, the inventors of the present application find through research that the reason of the pixel being burned is likely that the signal line of the pixel driving circuit 10 is short-circuited, so that the pixel of the display panel 1000 is burned to form a burn-type dark spot.

[0145] The present inventors analyze the signal lines of each film layer in the driving circuit layer 200 of the display panel 1000, and find that, as shown in FIG. 3 and in combination with FIG. 10, the first electrode T81 of the eighth transistor T8 is coupled with the third initialization signal line Vinit3; in the design of the driving circuit layer 200 of the display panel 1000, the third gate metal layer 209 includes a first initialization signal line pattern 2092 extending along the first direction X and a third initialization signal line pattern 2093 extending along the first direction X, and the first source-drain metal layer 211 includes a first electrode pattern 2118-1 of the eighth transistor T8 and a third initialization signal line bridge pattern 21110; the first electrode pattern 2118-1 of the eighth transistor T8 is connected with the third initialization signal line bridge pattern 21110, and the third initialization signal line bridge pattern 21110 is connected with the third initialization signal line pattern 2093 through a via 2105 penetrating through the second interlayer dielectric layer 210, so as to realize the coupling of the first electrode T81 of the eighth transistor T8 with the third initialization signal line Vinit3.

[0146] However, the third initialization signal line bridge pattern 21110 overlaps with the first initialization signal line pattern 2092, and there is only one second interlayer dielectric layer 210 between the first source-drain metal layer 211 where the third initialization signal line bridge pattern 21110 is located and the third gate metal layer 209 where the first initialization signal line pattern 2092 is located; if there is a small particle or a small dust in the process of preparing the second interlayer dielectric layer 210 of the display panel 1000, the small particle or the small dust can penetrate through the second interlayer dielectric layer 210, for example, the second interlayer dielectric layer 210 at the overlapping position of the third initialization signal line bridge pattern 21110 and the first initialization signal line pattern 2092, or the small particle or the small dust fails to deposit the second interlayer dielectric layer 210 successfully, so as to cause the second interlayer dielectric layer 210 to fail to take effect; when the first source-drain metal layer 211 is sputtered by a magnetron, the material of the first source-drain metal layer 211 can enter the gap of the small particle or the small dust, so as to cause the third initialization signal line bridge pattern 21110 and the first initialization signal line pattern 2092 to be conductive or directly connected, thereby causing the first initialization signal line Vinit1 and the third initialization signal line Vinit3 to be short-circuited. According to the FIB figure, it can be further determined that the small particle or the small dust PT at the overlapping position of the third initialization signal line bridge pattern 21110 and the first initialization signal line pattern 2092 causes the first initialization signal line Vinit1 and the third initialization signal line Vinit3 to be short-circuited.

[0147] As can be seen from FIG. 15, when the P-type transistor in the pixel driving circuit 10 as shown in FIG. 3 is subjected to the aging process, the voltage difference between the voltage Vint1 of the first initialization signal and the voltage Vint3 of the third initialization signal can reach 22 V. When the first initialization signal line Vinit1 and the third initialization signal line Vinit3 of the display panel 1000 are short-circuited, the voltage difference between the voltage Vint1 of the first initialization signal and the voltage Vint3 of the third initialization signal is large, for example, 22 V, during the aging process of the display panel 1000, which can cause the signal lines and the pixels of the display panel 1000 to be burnt, resulting in burnt dark spots, and thus greatly reducing the yield of the display panel 1000.

[0148] To avoid the burnt dark spots, in some embodiments, a display panel 1000 is provided, as shown in FIG. 1, which includes a plurality of sub-pixels P arranged in multiple rows along a first direction X, and adjacent two sub-pixels P in a row of the sub-pixels P form a pixel group PP; one sub-pixel P includes one pixel driving circuit 10, and the pixel driving circuit 10 is coupled with at least one signal line 30.

[0149] As shown in FIG. 3, the pixel driving circuit 10 includes a specified transistor 11, the at least one signal line 30 includes a specified signal line 31, and the specified transistor 11 is coupled with the specified signal line 31; wherein the specified transistor 11 is one transistor in the plurality of transistors included in the pixel driving circuit 10, the specified signal line 31 is one signal line in the plurality of signal lines 30 connected to the pixel driving circuit 10, and the specified signal line 31 is connected to the specified transistor 11.

[0150] Hereinafter, the patterns of the film layers of the display panel 1000 are introduced by taking the structures included in adjacent two sub-pixels P (i.e., one pixel group PP) along the first direction X as an example.

[0151] As shown in FIG. 2, the display panel 1000 comprises a substrate 100 and a driving circuit layer 200 arranged on one side of the substrate 100, and the pixel driving circuit 10 is arranged on the driving circuit layer 200. As shown in FIG. 16, the driving circuit layer 200 comprises a first active layer 201 arranged on one side of the substrate 100, a designated gate metal layer 2001 arranged on the side of the first active layer 201 away from the substrate 100, and a first source-drain metal layer 211 arranged on the side of the designated gate metal layer 2001 away from the substrate 100; the first active layer 201 comprises an active layer pattern 2010 of the designated transistor 11, and the active layer pattern 2010 of the designated transistor 11 comprises an active layer first pole pattern 2010-1; in one pixel group PP, the active layer first pole pattern 2010-1 of the designated transistor 11 of one sub-pixel P is connected with the active layer first pole pattern 2010-1' of the designated transistor 11 of another sub-pixel P'; the designated gate metal layer 2001 comprises a designated signal line pattern 20010 of the designated signal line 31; and the first source-drain metal layer 211 comprises a designated signal line bridge pattern 2110, which is located in the region of one sub-pixel P in one pixel group PP, and is connected with the active layer first pole pattern 2010-1 of the designated transistor 11 of one sub-pixel P and the designated signal line pattern 20010.

[0152] Exemplarily, as shown in FIG. 1, two adjacent sub-pixels P in one row of sub-pixels P can be regarded as one pixel group PP, and the display panel 1000 comprises a plurality of pixel groups PP, and the pixel group PP is the minimum repeating unit of the display panel 1000, i.e., the film layers of the plurality of pixel groups PP in the display panel 1000 are arranged uniformly.

[0153] Exemplarily, as shown in FIG. 1, the pixel driving circuit 10 is coupled with the signal line in the display panel 1000, and as shown in FIG. 3, the pixel driving circuit 10 comprises the designated transistor 11, the signal line comprises the designated signal line 31, and the designated transistor 11 is coupled with the designated signal line 31.

[0154] It should be noted that the number of the designated transistor 11 is not limited herein, and the designated transistor 11 can be only one or a plurality of; the number of the designated signal line 31 is not limited herein, and the designated signal line 31 can be only one or a plurality of. When the designated transistor 11 and the designated signal line 31 are both only one, the designated transistor 11 is coupled with the designated signal line 31; when the designated transistor 11 and the designated signal line 31 are both a plurality of, one designated transistor 11 is coupled with one designated signal line 31.

[0155] Exemplarily, as shown in FIG. 2, the display panel 1000 includes a substrate 100 and a driving circuit layer 200 arranged on one side of the substrate 100, the driving circuit layer 200 being a general term of a film layer where the pixel driving circuit 10 of all the sub-pixels P in the display panel 1000 is arranged, i.e., the pixel driving circuit 10 is arranged on the driving circuit layer 200.

[0156] Exemplarily, as shown in FIG. 16, the driving circuit layer 200 includes a first active layer 201 arranged on one side of the substrate 100, a designated gate metal layer 2001 arranged on a side of the first active layer 201 away from the substrate 100, a first source-drain metal layer 211 arranged on a side of the designated gate metal layer 2001 away from the substrate 100, and an insulating layer arranged between the first active layer 201 and the designated gate metal layer 2001, and an insulating layer arranged between the designated gate metal layer 2001 and the first source-drain metal layer 211.

[0157] Exemplarily, as shown in FIG. 16, the first active layer 201 includes an active layer pattern 2010 of the designated transistor 11; the active layer pattern 2010 of the designated transistor 11 includes an active layer first pole pattern 2010-1, an active layer channel pattern 2010-3, and an active layer second pole pattern 2010-2 connected in sequence; the active layer first pole pattern 2010-1 of the designated transistor 11 of one sub-pixel P in one pixel group PP is connected with the active layer first pole pattern 2010-1' of the designated transistor 11 of another sub-pixel P'.

[0158] It should be noted that when there are multiple designated transistors 11 of the pixel driving circuit 10, the active layer first pole patterns 2010-1 of the corresponding designated transistors 11 of the two sub-pixels P in one pixel group PP are connected. Specifically, for example, one sub-pixel P includes three designated transistors 11, which are a first designated transistor, a second designated transistor, and a third designated transistor; in one pixel group PP, the active layer first pole pattern 2010-1 of the first designated transistor of one sub-pixel P is connected with the active layer first pole pattern 2010-1' of the first designated transistor of another sub-pixel P', the active layer first pole pattern 2010-1 of the second designated transistor of one sub-pixel P is connected with the active layer first pole pattern 2010-1' of the second designated transistor of another sub-pixel P', and the active layer first pole pattern 2010-1 of the third designated transistor of one sub-pixel P is connected with the active layer first pole pattern 2010-1' of the third designated transistor of another sub-pixel P'.

[0159] Exemplarily, as shown in FIG. 16, the designated gate metal layer 2001 includes a designated signal line pattern 20010 of the designated signal line 31.

[0160] Exemplarily, as shown in FIG. 16, the first source-drain metal layer 211 includes a designated signal line bridging pattern 2110; in one pixel group PP, the designated signal line bridging pattern 2110 is located in the region of one sub-pixel P, and it can be understood that the region of another sub-pixel P' does not include the designated signal line bridging pattern 2110, that is, only one of the two sub-pixels P of one pixel group PP includes the designated signal line bridging pattern 2110; the designated signal line bridging pattern 2110 is connected with the active layer first electrode pattern 2010-1 of the designated transistor 11 of one sub-pixel P through a via hole penetrating through the insulating layer between the first source-drain metal layer 211 and the first active layer 201; and the designated signal line bridging pattern 2110 is also connected with the designated signal line pattern 20010 through a via hole penetrating through the insulating layer between the first source-drain metal layer 211 and the designated gate metal layer 2001.

[0161] It should be noted that the number of designated signal line bridging patterns 2110 in the region of one sub-pixel P is not limited herein, and the designated signal line bridging pattern 2110 can be only one or multiple; when the active layer first electrode pattern 2010-1 of the designated transistor 11 and the designated signal line pattern 20010 are both only one, the designated signal line bridging pattern 2110 is also only one; when the active layer first electrode pattern 2010-1 of the designated transistor 11 and the designated signal line pattern 20010 are both multiple, the designated signal line bridging pattern 2110 can also be multiple; the active layer first electrode pattern 2010-1 of the designated transistor 11, the designated signal line pattern 20010, and the designated signal line bridging pattern 2110 correspond to each other. Specifically, for example, one sub-pixel P includes two designated transistors 11, which are a first designated transistor and a second designated transistor, that is, one sub-pixel P includes the active layer first electrode pattern of the first designated transistor and the active layer first electrode pattern of the second designated transistor; one sub-pixel P includes two designated signal line patterns 20010, which are a first designated signal line pattern and a second designated signal line pattern; one sub-pixel P includes two designated signal line bridging patterns 2110, which are a first designated signal line bridging pattern and a second designated signal line bridging pattern; the first designated signal line bridging pattern of one sub-pixel P is connected with the active layer first electrode pattern of the first designated transistor and the first designated signal line pattern, respectively, and the second designated signal line bridging pattern of one sub-pixel P is connected with the active layer first electrode pattern of the second designated transistor and the second designated signal line pattern, respectively.

[0162] Although only one of the two sub-pixels P in one pixel group PP is provided with the designated signal line bridging pattern 2110, and the designated signal line bridging pattern 2110 is connected to the active layer first electrode pattern 2010-1 of the designated transistor 11 in one of the sub-pixels P through a via hole penetrating through the insulating layer between the first source-drain metal layer 211 and the first active layer 201, so that the signal transmitted by the designated signal line pattern 20010 is transmitted to the active layer first electrode pattern 2010-1 of the designated transistor 11 in one of the sub-pixels P through the designated signal line bridging pattern 2110; but since the active layer first electrode pattern 2010-1 of the designated transistor 11 in one of the sub-pixels P in one pixel group PP is connected to the active layer first electrode pattern 2010-1' of the designated transistor 11 in the other sub-pixel P', the signal transmitted by the designated signal line pattern 20010 is transmitted to the active layer first electrode pattern 2010-1 of the designated transistor 11 in one of the sub-pixels P through the designated signal line bridging pattern 2110 at the same time, and the signal transmitted by the designated signal line pattern 20010 is also transmitted to the active layer first electrode pattern 2010-1' of the designated transistor 11 in the other sub-pixel P' through the designated signal line bridging pattern 2110, so that the active layer first electrode pattern 2010-1 of the designated transistor 11 in both of the sub-pixels P in one pixel group PP can receive the signal transmitted by the designated signal line pattern 20010.

[0163] Therefore, the designated signal line bridging pattern 2110 is provided in one of the sub-pixels P in one pixel group PP, and the designated signal line bridging pattern 2110 is connected to the active layer first electrode pattern 2010-1 of the designated transistor 11 in one of the sub-pixels P and the designated signal line pattern 20010; since the active layer first electrode pattern 2010-1 of the designated transistor 11 in both of the sub-pixels P in one pixel group PP is connected, so that the active layer first electrode pattern 2010-1 of the designated transistor 11 in both of the sub-pixels P in one pixel group PP can be connected to the designated signal line pattern 20010 through the designated signal line bridging pattern 2110, without affecting the operation of the pixel driving circuit 10; this setting reduces the designated signal line bridging pattern 2110 in one of the sub-pixels P in one pixel group PP, i.e. reduces the number of designated signal line bridging patterns 2110, thereby reducing the overlap between the designated signal line bridging pattern 2110 and other signal line patterns, reducing the probability of short circuit between the designated signal line bridging pattern 2110 and other signal line patterns from the source, thereby reducing the probability of burn-in dark spots, greatly improving the burn-in dark spot defect of the display panel 1000, improving the yield, and significantly improving the Y line defect caused by burn-in, significantly reducing the market risk caused by burn-in of the pixel driving circuit 10.

[0164] In some embodiments, as shown in FIG. 16, in one pixel group PP, the active layer first electrode pattern 2010-1 of the designated transistor 11 of one sub-pixel P is connected to the active layer first electrode pattern 2010-1' of the designated transistor 11 of another sub-pixel P' at a designated connection point 1, and the designated signal line bridging pattern 2110 is connected to the designated connection point 1.

[0165] Exemplarily, the designated connection point 1 can be arranged at a position where its orthographic projection on the substrate 100 is closer to the orthographic projection of the designated signal line pattern 20010 on the substrate 100; such arrangement is conducive to reducing the length of the designated signal line bridging pattern 2110, reducing the probability of defects of the designated signal line bridging pattern 2110 in the manufacturing process, and reducing the impedance of the designated signal line bridging pattern 2110.

[0166] In some embodiments, as shown in FIG. 16, in one pixel group PP, the active layer patterns 2010 of the designated transistors 11 of two sub-pixels P are mirror-symmetrical, and the designated connection point 1 is located on the mirror-symmetry axis 2 of the active layer patterns 2010 of the designated transistors 11 of the two sub-pixels P; the designated signal line pattern 20010 extends along the first direction X and passes through the regions where the two sub-pixels P are located.

[0167] Exemplarily, as shown in FIG. 16, in one pixel group PP, the active layer patterns 2010 of the designated transistors 11 of two sub-pixels P are mirror-symmetrical, and the designated connection point 1 is arranged on the mirror-symmetry axis 2 of the active layer patterns 2010 of the designated transistors 11 of the two sub-pixels P, i.e., the active layer first electrode patterns 2010-1 of the designated transistors 11 of the two sub-pixels P are the same in size and shape, the transmission path lengths of the signals from the designated connection point 1 to the active layer first electrode patterns 2010-1 of the designated transistors 11 of the two sub-pixels P are the same, which can ensure that the active layer first electrode patterns 2010-1 of the designated transistors 11 of the two sub-pixels P in one pixel group PP simultaneously receive the signals transmitted by the designated signal line pattern 20010, and the loss of the received signals is consistent, so that synchronous transmission can be performed and the uniformity of the sub-pixels P in the display panel 1000 can be ensured.

[0168] In some embodiments, as shown in FIG. 16, the width of the designated signal line bridging pattern 2110 is greater than a set width.

[0169] Exemplarily, as shown in FIG. 16, compared with arranging the designated signal line bridging pattern 2110 in each sub-pixel P, arranging the designated signal line bridging pattern 2110 in one sub-pixel P in one pixel group PP reduces one designated signal line bridging pattern 2110, which increases the impedance of the designated signal line bridging pattern 2110 and thus increases the write impedance of the designated signal line 31.

[0170] In some embodiments, the specified signal line bridge pattern 2110 is arranged in each sub-pixel P, and the width of the specified signal line bridge pattern 2110 can be, for example, a set width of 1.8 um. In order to reduce the impedance of the specified signal line bridge pattern 2110 when the specified signal line bridge pattern 2110 is arranged in one of the sub-pixels P of one pixel group PP as shown in FIG. 16, the width of the specified signal line bridge pattern 2110 can be set to, for example, 1.8 um to 3 um, such as 2 um, 2.1 um, 2.2 um, 2.3 um, 2.4 um, 2.5 um, 2.6 um, 2.7 um, 2.8 um, 2.9 um, 3 um, so as to compensate for the write ability of the specified signal line 31.

[0171] It should be noted that the "set width" refers to the width of the specified signal line bridge pattern 2110 when the specified signal line bridge pattern 2110 is arranged in each sub-pixel P. The "set width of 1.8 um" described above is only an example of a width, and the set width is not necessarily 1.8 um. The "set width" can be set according to the actual product process, and the present disclosure does not make any settings.

[0172] In some embodiments, as shown in FIG. 16, the pixel driving circuit 10 further includes other transistors in addition to the specified transistor 11; the first active layer 201 further includes an active layer pattern of the other transistors; the active layer pattern of the other transistors includes an active layer channel pattern; the active layer pattern 2010 of the specified transistor 11 includes an active layer channel pattern 2010-3, and the width-length ratio of the active layer channel pattern 2010-3 of the specified transistor 11 is greater than the width-length ratio of the active layer channel pattern of the other transistors.

[0173] For example, as shown in FIG. 16, the arrangement of the specified signal line bridge pattern 2110 in one of the sub-pixels P of one pixel group PP increases the impedance of the specified signal line bridge pattern 2110 compared to the arrangement of the specified signal line bridge pattern 2110 in each sub-pixel P, thereby increasing the write impedance of the specified signal line 31; the write ability of the specified signal line 31 can be compensated by increasing the width-length ratio of the active layer channel pattern 2010-3 of the specified transistor 11.

[0174] Exemplarily, the designated signal line bridging pattern 2110 is arranged in each of the sub-pixels P, and the width-length ratio of the active layer channel pattern of the transistor in the sub-pixel P may, for example, be the same, and may, for example, be 2 / 4; in order to compensate for the writing ability of the designated signal line 31 when the designated signal line bridging pattern 2110 is arranged in one of the sub-pixels P of one pixel group PP as shown in FIG. 16, the width-length ratio of the active layer channel pattern 2010-3 of the designated transistor 11 can be increased, and the width-length ratio of the active layer channel pattern of the other transistors remains unchanged; the width-length ratio of the active layer channel pattern 2010-3 of the designated transistor 11 may, for example, be 2.4 / 4.

[0175] In some embodiments, the display panel 1000 includes a plurality of sub-pixels P, one sub-pixel P includes one pixel driving circuit 10 as shown in FIG. 3; the plurality of sub-pixels P are arranged into a plurality of rows along the first direction X, and two adjacent sub-pixels P in one row of sub-pixels P form one pixel group PP. The film layer arrangement of the two sub-pixels in one pixel group PP is different from the arrangement of the first active layer 201 and the first source-drain metal layer 211, and the film layer arrangement of the two sub-pixels in one pixel group PP is consistent with the film layer arrangement of one sub-pixel described above, and the film layer arrangement of the two sub-pixels in one pixel group PP is described in detail in FIGS. 16-44, which will not be described here.

[0176] In some embodiments, as shown in FIG. 3, the designated transistor 11 includes a third reset transistor, i.e., an eighth transistor T8, the designated signal line 31 includes a third initialization signal line Vinit3, and the third reset transistor, i.e., the eighth transistor T8 is coupled to the third initialization signal line Vinit3; as shown in FIG. 31, the first active layer 201 includes an active layer pattern 2018 of the third reset transistor, i.e., the eighth transistor T8, and the active layer pattern 2018 of the third reset transistor, i.e., the eighth transistor T8 includes an active layer first electrode pattern 2018-1; the designated gate metal layer 2001 includes a third initialization signal line pattern 2093 of the third initialization signal line Vinit3; and the designated signal line bridging pattern 2110 includes a third initialization signal line bridging pattern 21110, and the first source-drain metal layer 211 includes the third initialization signal line bridging pattern 21110.

[0177] Exemplarily, as shown in FIG. 17, the first active layer 201 includes an active layer pattern 2018 of the eighth transistor T8, and the active layer pattern 2018 of the eighth transistor T8 includes an active layer first electrode pattern 2018-1, an active layer channel pattern 2018-3, and an active layer second electrode pattern 2018-2 connected in sequence, and the active layer first electrode pattern 2018-1 of the eighth transistor T8 of one sub-pixel P in one pixel group PP is connected to the active layer first electrode pattern 2018-1' of the eighth transistor T8 of another sub-pixel P'.

[0178] Exemplarily, as shown in FIG. 25, the specified gate metal layer 2001, for example, the third gate metal layer 209, includes a third initialization signal line pattern 2093 of a third initialization signal line Vinit3.

[0179] Exemplarily, as shown in FIG. 31, the specified signal line bridge pattern 2110 includes a third initialization signal line bridge pattern 21110, and the first source-drain metal layer 211 includes the third initialization signal line bridge pattern 21110. In one pixel group PP, the third initialization signal line bridge pattern 21110 is located in the region of one sub-pixel P. It can be understood that the region of another sub-pixel P' does not include the third initialization signal line bridge pattern 21110, that is, only one of the two sub-pixels P of one pixel group PP includes the third initialization signal line bridge pattern 21110; the third initialization signal line bridge pattern 21110 is connected with the active layer first electrode pattern 2018-1 of one of the sub-pixels P through a via hole penetrating through the insulating layer between the first source-drain metal layer 211 and the first active layer 201; and the third initialization signal line bridge pattern 21110 is also connected with the third initialization signal line pattern 2093 through a via hole penetrating through the insulating layer between the first source-drain metal layer 211 and the specified gate metal layer 2001.

[0180] In some embodiments, as shown in FIG. 3, the signal line further includes a first initialization signal line Vinit1; as shown in FIG. 25, the specified gate metal layer 2001, for example, the third gate metal layer 209, further includes a first initialization signal line pattern 2092 of the first initialization signal line Vinit1; the first initialization signal line pattern 2092 extends along the first direction X and passes through the regions of the two sub-pixels P in one pixel group PP; as shown in FIG. 31, the third initialization signal line bridge pattern 21110 overlaps with the first initialization signal line pattern 2092.

[0181] Exemplarily, as shown in FIG. 31, when the third initialization signal line bridging pattern 21110 is connected with the active layer first electrode pattern 2018-1 of the eighth transistor T8 of one of the sub-pixels P and also connected with the third initialization signal line pattern 2093, although the third initialization signal line bridging pattern 21110 will overlap with the first initialization signal line pattern 2092, the third initialization signal line bridging pattern 21110 is arranged in only one of the sub-pixels P in one pixel group PP, which reduces the third initialization signal line bridging pattern 21110 in one of the sub-pixels P in one pixel group PP, i.e., reduces the number of the third initialization signal line bridging pattern 21110, thereby reducing the overlap between the third initialization signal line bridging pattern 21110 and the first initialization signal line pattern 2092, reducing the probability of short circuit between the third initialization signal line bridging pattern 21110 and the first initialization signal line pattern 2092 from the source, thereby reducing the probability of occurrence of burn-in type dark spots, greatly improving the burn-in type dark spot defect of the display panel 1000, improving the yield, and significantly improving the Y line defect caused by burn-in, significantly reducing the market risk caused by burn-in of the pixel driving circuit 10.

[0182] In some embodiments, as shown in FIG. 45, and with reference to FIG. 10, the width of the third initialization signal line bridging pattern 21110 is greater than the set width.

[0183] Exemplarily, as shown in FIG. 45, two sub-pixels P in one pixel group PP share one third initialization signal line bridging pattern 21110, and the initialization signal transmitted by the third initialization signal line Vinit3 reaches the eighth transistor T8 of the two sub-pixels P through one third initialization signal line bridging pattern 21110, at this time, the impedance of the third initialization signal line bridging pattern 21110 is increased compared with the impedance of the initialization signal transmitted by the third initialization signal line Vinit3 reaching the eighth transistor T8 of the two sub-pixels P through two third initialization signal line bridging patterns 21110, thereby causing the write impedance of the third initialization signal line Vinit3 to increase.

[0184] Exemplarily, as shown in FIG. 45, in order to reduce the impedance of the third initialization signal line bridging pattern 21110 when the third initialization signal line bridging pattern 21110 is arranged in one of the sub-pixels P in one pixel group PP, the width of the third initialization signal line bridging pattern 21110 can be greater than the width of other patterns on the first source-drain metal layer 211, which can be, for example, the first power signal line bridging pattern 2119, the first electrode pattern 2112-1 of the second transistor T2, etc.

[0185] Exemplarily, a third initialization signal line bridge pattern 21110 is arranged in each sub-pixel P as shown in FIG. 10, and the width of the third initialization signal line bridge pattern 21110 can be, for example, 1.8 um. In order to reduce the impedance of the third initialization signal line bridge pattern 21110 when the third initialization signal line bridge pattern 21110 is arranged in one of the sub-pixels P of one pixel group PP as shown in FIG. 45, the width of the third initialization signal line bridge pattern 21110 can be set to, for example, 1.8 um to 3 um, such as 2 um, 2.1 um, 2.2 um, 2.3 um, 2.4 um, 2.5 um, 2.6 um, 2.7 um, 2.8 um, 2.9 um, 3 um, so as to compensate the writing ability of the third initialization signal line Vinit3.

[0186] In some embodiments, as shown in FIG. 46, the first active layer 201 further includes active layer patterns of the first transistor T1, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7. The active layer patterns of the first transistor T1, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 each include an active layer channel pattern; the active layer pattern 2018 of the eighth transistor T8 includes an active layer channel pattern 2018-3, and in some examples, the width-length ratio of the active layer channel pattern 2018-3 of the eighth transistor T8 is greater than the width-length ratio of the active layer channel pattern of the first transistor T1; in some examples, the width-length ratio of the active layer channel pattern 2018-3 of the eighth transistor T8 is greater than the width-length ratio of the active layer channel pattern of the seventh transistor T7; in other examples, the width-length ratio of the active layer channel pattern 2018-3 of the eighth transistor T8 is greater than the width-length ratio of the active layer channel patterns of the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6.

[0187] Exemplarily, the first transistor T1 is a first reset transistor, the second transistor T2 is a compensation transistor, the third transistor T3 is a driving transistor, the fourth transistor T4 is a writing transistor, the fifth transistor T5 is a first light-emitting control transistor, the sixth transistor T6 is a second light-emitting control transistor, the seventh transistor T7 is a second reset transistor, and the eighth transistor T8 is a third reset transistor.

[0188] The channel width-length ratio of a transistor is the ratio of the width and length of the conductive channel of the transistor, and the greater the width-length ratio, the greater the on-current Id of the transistor when the transistor is turned on, that is, the width-length ratio is proportional to the on-current Id, and the width-length ratio of the transistor reflects the on-capability of the transistor, that is, the signal writing capability.

[0189] Exemplarily, as shown in FIG. 10, the width-length ratios of the active layer channel patterns of the transistors in the sub-pixel P can all be the same, for example, each can be 2 / 4; in order to compensate for the writing ability of the third initialization signal line Vinit3 when the third initialization signal line bridge pattern 21110 is arranged in one of the sub-pixels P of one pixel group PP as shown in FIG. 46, the width-length ratio of the active layer channel pattern 2018-3 of the eighth transistor T8 can be increased, so that the signal writing ability of the eighth transistor T8 is enhanced, while the width-length ratios of the active layer channel patterns of the first transistor T1, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 remain unchanged; for example, the width-length ratio of the active layer channel pattern 2018-3 of the eighth transistor T8 can be 2.4 / 4.

[0190] The first transistor T1, the eighth transistor T8 and the seventh transistor T7 are all reset transistors, all realizing reset functions, and the width-length ratio of the active layer channel pattern 2018-3 of the eighth transistor T8 is greater than the width-length ratio of the active layer channel pattern of the first transistor T1 and greater than the width-length ratio of the active layer channel pattern of the seventh transistor T1, so as to improve the signal writing ability of the eighth transistor T8, to ensure that the writing abilities of the initialization signals of the three reset transistors remain consistent, to improve the uniformity of the node potentials of the pixel driving circuit, and to avoid the setting of the third initialization signal line bridge pattern 21110 from affecting the reset function of the eighth transistor T8.

[0191] In some embodiments, as shown in FIG. 3, the pixel driving circuit 10 further includes a compensation transistor, i.e., the second transistor T2, and the signal line further includes a first power signal line VDD; as shown in FIG. 37, the driving circuit layer 200 of the display panel 1000 further includes a second active layer 207 arranged between the first active layer 201 and a specified gate metal layer 2001, for example, the third gate metal layer 209, and a second source-drain metal layer 214 arranged away from the substrate 100 on one side of the first source-drain metal layer 211; as shown in FIG. 23, the second active layer 207 includes an active layer pattern 2071 of the compensation transistor, i.e., the second transistor T2; as shown in FIG. 37, the second source-drain metal layer 214 includes a first power signal line pattern 2141 of the first power signal line VDD, and the first power signal line pattern 2141 includes a block pattern 2141-1, and a normal projection of the active layer pattern 2071 of the compensation transistor, i.e., the second transistor T2 on the substrate 100 is located within a normal projection of the block pattern 2141-1 of the first power signal line pattern 2141 on the substrate 100.

[0192] Exemplarily, as shown in FIG. 37, the orthogonal projection of the active layer pattern 2071 of the second transistor T2 on the substrate 100 is located in the orthogonal projection of the block pattern 2141-1 of the first power signal line pattern 2141 on the substrate 100, that is, the area of the block pattern 2141-1 of the first power signal line pattern 2141 is greater than the area of the active layer pattern 2071 of the second transistor T2, and the block pattern 2141-1 of the first power signal line pattern 2141 is located above the active layer pattern 2071 of the second transistor T2 and can cover the active layer pattern 2071 of the second transistor T2 in the direction perpendicular to the substrate 100. The block pattern 2141-1 of the first power signal line pattern 2141 can be used to shield the active layer pattern 2071 of the second transistor T2 from the light from the nature into the display panel 1000, prevent the material of the active layer pattern 2071 of the second transistor T2 from changing in property under the influence of the natural light, and affect the performance of the display panel 1000.

[0193] In some embodiments, as shown in FIG. 37, the first power signal line pattern 2141 further includes a strip pattern 2141-2 connected with the block pattern 2141-1, and the width of the strip pattern 2141-2 is 3.5um-5um.

[0194] Exemplarily, the strip pattern 2141-2 of the first power signal line pattern 2141 is mainly used for transmitting the first power signal, in order to reduce the impedance of the strip pattern 2141-2, the width of the strip pattern 2141-2 can be set to 3.5um-5um, for example, 3.5um, 3.6um, 3.7um, 3.8um, 3.9um, 4um, 4.1um, 4.2um, 4.3um, 4.4um, 4.5um, 4.6um, 4.7um, 4.8um, 4.9um, 5um.

[0195] Exemplarily, as shown in FIG. 37, the strip pattern 2141-2 can be provided in two, and the two strip patterns 2141-2 are respectively connected with the block pattern 2141-1, and the strip patterns 2141-2 are kept symmetrical, which can ensure that the power can be supplied at the same time, is conducive to the improvement of the flatness of the display panel 1000, and reduces the color deviation.

[0196] In some embodiments, as shown in FIG. 3, the pixel driving circuit 10 further includes a driving transistor, i.e., a third transistor T3, as shown in FIG. 17, the first active layer 201 includes an active layer pattern 2013 of the driving transistor, i.e., the third transistor T3; as shown in FIG. 18, the driving circuit layer 200 of the display panel 1000 further includes a bottom metal layer 219 disposed on the side of the first active layer 201 close to the substrate 100; the bottom metal layer 219 includes a bottom metal protection pattern 2191, and a normal projection of the active layer pattern 2013 of the driving transistor, i.e., the third transistor T3, on the substrate 100 is located within a normal projection of the bottom metal protection pattern 2191 on the substrate 100; the bottom metal protection pattern 2191 is connected with the first power signal line pattern 2141 of the second source-drain metal layer 214.

[0197] Exemplarily, as shown in FIG. 17, the active layer pattern 2013 of the third transistor T3 includes an active layer first electrode pattern 2013-1, an active layer channel pattern 2013-3 and an active layer second electrode pattern 2013-2 connected in sequence; as shown in FIG. 18, the normal projection of the active layer pattern 2013 of the third transistor T3 on the substrate 100 is located within the normal projection of the bottom metal protection pattern 2191 on the substrate 100, that is, the bottom metal protection pattern 2191 is located below the active layer pattern of the third transistor T3 and can cover the active layer pattern of the third transistor T3 in the direction perpendicular to the substrate 100, and the bottom metal protection pattern 2191 is connected with the first power signal line pattern 2141 of the second source-drain metal layer 214, which can protect the third transistor T3 and block the upward migration of impurities in the lower layer to affect the performance of the third transistor T3, and at the same time, the bottom metal protection pattern 2191 is connected with the first power signal line pattern 2141, for example, the bottom metal protection pattern 2191 is connected with the first power signal line pattern 2141 through a via in the peripheral area BB of the display panel 1000, and after the signal is connected, the bottom metal protection pattern 2191 and the active layer pattern of the third transistor T3 form a balanced electric field, so that the channel electric field of the active layer channel pattern of the third transistor T3 is more stable and is not easily disturbed by the electric field at the bottom of the display panel 1000.

[0198] In some embodiments, as shown in FIG. 43, the display panel 1000 further includes an anode layer 301 disposed on the side of the driving circuit layer 200 away from the substrate 100; the anode layer 301 includes a first anode 3011 and a second anode 3012, the first anode 3011 is connected with the pixel driving circuit 10 of one sub-pixel P in the pixel group PP, and the second anode 3012 is connected with the pixel driving circuit 10 of another sub-pixel P' in the pixel group PP; the first anode 3011 is disposed above the block pattern 2141-1 of the first power signal line pattern 2141, and the ratio of the overlapping area of the first anode 3011 and the block pattern 2141-1 to the area of the first anode 3011 is greater than a set threshold.

[0199] Exemplarily, the first anode 3011 is arranged above the block-shaped pattern 2141-1 of the first power signal line pattern 2141, and a ratio of an overlapping area of the first anode 3011 and the block-shaped pattern 2141-1 to an area of the first anode 3011 is greater than a set threshold value, for example, 60%, which can ensure the flatness of the first anode 3011, improve the uniformity of the sub-pixel P of the display panel 1000, and improve the yield of the display panel 1000.

[0200] It should be noted that the “set threshold value” can be set according to the actual product process, and the disclosure does not set the “set threshold value”. The “set threshold value is, for example, 60%” described above is only an example value, and the set threshold value is not 60%.

[0201] In some embodiments, as shown in FIG. 47, the substrate 100 includes at least two layers of flexible substrates 101 and at least two layers of buffer layers 102.

[0202] Exemplarily, when the display panel 1000 is prepared, a glass carrier is usually arranged below the substrate 100.

[0203] Exemplarily, the material of the buffer layer 102 can be, for example, silicon nitride and / or silicon oxide. The silicon nitride material has good compactness, which can prevent metal ions of the glass carrier below the substrate 100 from diffusing to the active layer region. The silicon oxide material has good insulation, which can avoid the influence of static electricity outside the display panel 1000 on the pixel driving circuit 10 inside the display panel 1000. The silicon oxide material has good heat insulation, which can reduce the heat conduction rate, help to form larger crystal grains, and play a role in absorbing heat when the glass carrier is laser peeled off in the later stage, thereby blocking the penetration of heat to the film layer above the substrate 100. At the same time, when the substrate 100 includes at least two layers of flexible substrates 101 and at least two layers of buffer layers 102, the bottom of the display panel 1000 can be better protected, the influence of small particles or small dust can be reduced, and small particles or small dust can be prevented from entering the inside of the display panel 1000 from below the display panel 1000.

[0204] On the other hand, a display device 10000 is provided, as shown in FIG. 48, which includes the display panel 1000 according to any of the above embodiments.

[0205] Exemplarily, the display device 10000 can display images, for example, static images or dynamic images, etc.

[0206] Exemplarily, the display device 10000 can be, but is not limited to, a mobile phone, a wireless device, a Personal Digital Assistant (PDA), a handheld or portable computer, a GPS receiver / navigator, a camera, an MP4 video player, a camcorder, a game console, a watch, a clock, a calculator, a TV monitor, a flat panel display, a computer monitor, an automobile display (e.g., a speedometer display, etc.), a navigator, a cockpit controller and / or display, a display of a camera view (e.g., a display of a rear view camera in a vehicle), an electronic photo, an electronic billboard or sign, a projector, an architectural structure, a packaging and aesthetic structure (e.g., a display of an image for a piece of jewelry), etc.

[0207] In the description of the present specification, a specific feature, structure, material or characteristic can be combined in any one or more embodiments or examples in a suitable manner.

[0208] The above description is merely illustrative of the application, and the scope of the application is not limited thereto. Any variations and modifications of the application, which would occur to those skilled in the art, are to be considered within the scope of the application. Therefore, the scope of the application should be determined by the appended claims.

Claims

1. A display panel, wherein, The display panel comprises a plurality of sub-pixels arranged in a plurality of rows along a first direction, and two adjacent sub-pixels in a row of the sub-pixels form a pixel group; one sub-pixel of the plurality of sub-pixels comprises a pixel driving circuit, the pixel driving circuit is coupled with at least one signal line, the pixel driving circuit comprises a specified transistor, the at least one signal line comprises a specified signal line, and the specified transistor is coupled with the specified signal line; The display panel comprises: a substrate; a first active layer disposed on one side of the substrate, the first active layer comprising an active layer pattern of the specified transistor, the active layer pattern of the specified transistor comprising an active layer first electrode pattern; in one pixel group, the active layer first electrode pattern of the specified transistor of one sub-pixel is connected with the active layer first electrode pattern of the specified transistor of another sub-pixel; a specified gate metal layer disposed on the side of the first active layer away from the substrate, the specified gate metal layer comprising a specified signal line pattern of the specified signal line; a first source-drain metal layer disposed on the side of the specified gate metal layer away from the substrate, the first source-drain metal layer comprising a specified signal line bridge pattern; in one pixel group, the specified signal line bridge pattern is located in the region of one sub-pixel, the specified signal line bridge pattern is connected with the active layer first electrode pattern of the specified transistor of one of the sub-pixels, and is also connected with the specified signal line pattern.

2. The display panel of claim 1, wherein, In one pixel group, the active layer first electrode pattern of the specified transistor of one sub-pixel is connected with the active layer first electrode pattern of the specified transistor of another sub-pixel at a specified connection point, and the specified signal line bridge pattern is connected with the specified connection point.

3. The display panel of claim 2, wherein, In one pixel group, the active layer patterns of the specified transistors of the two sub-pixels are mirror-symmetrical, the specified connection point is located on the mirror-symmetrical axis of the active layer patterns of the specified transistors of the two sub-pixels; the specified signal line pattern extends along the first direction and passes through the regions of the two sub-pixels.

4. The display panel according to any one of claims 1 to 3, wherein The width of the specified signal line bridge pattern is greater than a set width.

5. The display panel according to any one of claims 1 to 4, wherein The pixel driving circuit further comprises other transistors in addition to the specified transistor; The first active layer further comprises an active layer pattern of the other transistors; the active layer pattern of the other transistors comprises an active layer channel pattern; The active layer pattern of the specified transistor comprises an active layer channel pattern, and the width-length ratio of the active layer channel pattern of the specified transistor is greater than the width-length ratio of the active layer channel pattern of the other transistors.

6. The display panel according to any one of claims 1 to 5, wherein The specified transistor comprises a third reset transistor, the specified signal line comprises a third initialization signal line, and the third reset transistor is coupled with the third initialization signal line; The first active layer comprises an active layer pattern of the third reset transistor, and the active layer pattern of the third reset transistor comprises an active layer first electrode pattern; The specified gate metal layer includes a third initialization signal line pattern of the third initialization signal line; The specified signal line bridge pattern includes a third initialization signal line bridge pattern, and the first source-drain metal layer includes the third initialization signal line bridge pattern.

7. The display panel of claim 6, wherein, The signal line further includes a first initialization signal line; The specified gate metal layer further includes a first initialization signal line pattern of the first initialization signal line; the first initialization signal line pattern extends along the first direction and passes through regions where two of the sub-pixels in one of the pixel groups are located; The third initialization signal line bridge pattern overlaps the first initialization signal line pattern.

8. The display panel according to any one of claims 1 to 7, wherein The pixel driving circuit further includes a compensation transistor, and the signal line further includes a first power supply signal line; the display panel further includes: a second active layer disposed between the first active layer and the specified gate metal layer; the second active layer includes an active layer pattern of the compensation transistor; a second source-drain metal layer disposed on a side of the first source-drain metal layer away from the substrate; the second source-drain metal layer includes a first power supply signal line pattern of the first power supply signal line, the first power supply signal line pattern includes a block pattern, and a normal projection of the active layer pattern of the compensation transistor on the substrate is located within a normal projection of the block pattern of the first power supply signal line pattern on the substrate.

9. The display panel of claim 8, wherein, The first power supply signal line pattern further includes a strip pattern connected to the block pattern, and a width of the strip pattern is 3.5um-5um.

10. The display panel of claim 8 or 9, wherein, The pixel driving circuit further includes a driving transistor, and the first active layer includes an active layer pattern of the driving transistor; The display panel further includes: a bottom metal layer disposed on a side of the first active layer close to the substrate; the bottom metal layer includes a bottom metal protection pattern, a normal projection of the active layer pattern of the driving transistor on the substrate is located within a normal projection of the bottom metal protection pattern on the substrate, and the bottom metal protection pattern is connected to the first power supply signal line pattern of the second source-drain metal layer.

11. The display panel according to any one of claims 8 to 10, wherein The display panel further includes: an anode layer disposed on a side of the driving circuit layer away from the substrate; The anode layer includes a first anode and a second anode, the first anode is connected to the pixel driving circuit of one of the sub-pixels in the pixel group, and the second anode is connected to the pixel driving circuit of another of the sub-pixels in the pixel group; The first anode is disposed above the block pattern of the first power supply signal line pattern, and a ratio of an overlapping area of the first anode and the block pattern to an area of the first anode is greater than a set threshold value.

12. The display panel according to any one of claims 1 to 11, wherein, The substrate includes at least two flexible substrates and at least two buffer layers.

13. A display device, wherein, The display panel includes any one of claims 1-12.

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