Pixel circuit and display apparatus

Abstract

A pixel circuit and a display apparatus. The pixel circuit comprises: a driving circuit (10) and a data writing circuit (20), wherein the data writing circuit (20) comprises a first control circuit (11), a second control circuit (12) and a third control circuit (13); under the control of a first scanning signal, the first control circuit (11) controls the connection or disconnection between a first node (G) and a first intermediate node (N1); under the control of the first scanning signal, the second control circuit (12) controls the connection or disconnection between the first intermediate node (N1) and a data line (DL); under the control of the potential of the first node (G), the third control circuit (13) controls the potential of the first intermediate node (N1); or, the transistor comprised in the data writing circuit (20) is a dual-gate transistor, a first gate electrode of the transistor comprised in the data writing circuit (20) is electrically connected to a first scanning end (G1), and a second gate electrode of the transistor comprised in the data writing circuit (20) is electrically connected to a first constant-voltage end (VG1). The electric leakage of the first node (G) can be reduced, thereby improving the compensation precision.

Description

Pixel circuits and display devices

[0001] Cross-references to related applications

[0002] This application claims priority to Chinese Patent Application No. 202410798536.6, filed in China on June 19, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to the field of display technology, and more particularly to a pixel circuit and a display device. Background Technology

[0004] In the display industry, LTPS (Low Temperature Polycrystalline Silicon) transistors are widely used due to their high mobility, which allows for smaller bezels. Source-follower internally compensated pixel circuits are commonly used for accurate compensation because they have low requirements for integrated circuits (ICs). However, n-type LTPS transistors in source-follower internally compensated pixel circuits can experience leakage current, affecting the compensation accuracy. Summary of the Invention

[0005] The main objective of this disclosure is to provide a pixel circuit and a display device that solves the problem in the prior art where leakage current in the transistors of the pixel circuit affects the compensation accuracy.

[0006] In one aspect, embodiments of this disclosure provide a pixel circuit, including a driving circuit and a data writing circuit;

[0007] The control terminal of the driving circuit is electrically connected to the first node, and the driving circuit is used to generate a driving current under the control of the potential of the first node.

[0008] The data writing circuit includes a first control circuit, a second control circuit, and a third control circuit. The first control circuit is electrically connected to a first scanning end, a first node, and a first intermediate node, respectively, and is used to control the connection or disconnection between the first node and the first intermediate node under the control of a first scanning signal provided by the first scanning end. The second control circuit is electrically connected to the first scanning end, the first intermediate node, and a data line, respectively, and is used to control the connection or disconnection between the first intermediate node and the data line under the control of the first scanning signal. The third control circuit is electrically connected to the first node and the first intermediate node, respectively, and is used to control the potential of the first intermediate node under the control of the potential of the first node; or...

[0009] The data writing circuit is electrically connected to the first scanning terminal, the data line, and the first node, respectively, and is used to write the data voltage provided by the data line into the first node under the control of the first scanning signal provided by the first scanning terminal. The transistor included in the data writing circuit is a dual-gate transistor. The first gate of the transistor included in the data writing circuit is electrically connected to the first scanning terminal, and the second gate of the transistor included in the data writing circuit is electrically connected to the first fixed voltage terminal.

[0010] Optionally, the third control circuit is used to control the potential of the first intermediate node to be an effective voltage when the potential of the first node is an effective voltage.

[0011] Optionally, the data writing circuit includes a dual-gate transistor;

[0012] The first gate is a top gate and the second gate is a bottom gate; or, the first gate is a bottom gate and the second gate is a top gate.

[0013] The data writing circuit includes an n-type transistor, and the first fixed voltage terminal is a low voltage terminal; or, the data writing circuit includes a p-type transistor, and the first fixed voltage terminal is a high voltage terminal.

[0014] Optionally, the pixel circuit described in at least one embodiment of this disclosure further includes an initialization circuit;

[0015] The initialization circuit is connected to the fourth control circuit, the fifth control circuit and the sixth control circuit respectively;

[0016] The fourth control circuit is electrically connected to the second scanning end, the first node, and the second intermediate node, respectively, and is used to control the connection or disconnection between the first node and the second intermediate node under the control of the second scanning signal provided by the second scanning end.

[0017] The fifth control circuit is electrically connected to the second scanning terminal, the second intermediate node, and the reference voltage terminal respectively, and is used to control the connection or disconnection between the second intermediate node and the reference voltage terminal under the control of the second scanning signal.

[0018] The sixth control circuit is electrically connected to the first node and the second intermediate node respectively, and is used to control the potential of the second intermediate node under the control of the potential of the first node.

[0019] Optionally, the sixth control circuit is used to control the potential of the second intermediate node to be an effective voltage when the potential of the first node is an effective voltage.

[0020] Optionally, the pixel circuit described in at least one embodiment of this disclosure further includes an initialization circuit;

[0021] The initialization circuit is electrically connected to the second scan terminal, the reference voltage terminal, and the first node, respectively, and is used to write the reference voltage provided by the reference voltage terminal into the first node under the control of the second scan signal provided by the second scan terminal; the transistor included in the initialization circuit is a dual-gate transistor, the first gate of the transistor included in the initialization circuit is electrically connected to the second scan terminal, and the second gate of the transistor included in the initialization circuit is electrically connected to the second fixed voltage terminal.

[0022] Optionally, the first gate is a top gate and the second gate is a bottom gate; or, the first gate is a bottom gate and the second gate is a top gate.

[0023] The initialization circuit includes an n-type transistor, and the second fixed voltage terminal is a low voltage terminal; or, the initialization circuit includes a p-type transistor, and the second fixed voltage terminal is a high voltage terminal.

[0024] Optionally, the first control circuit includes a first transistor, and the second control circuit includes a second transistor;

[0025] The gate of the first transistor is electrically connected to the first scan terminal, the first electrode of the first transistor is electrically connected to the first node, and the second electrode of the first transistor is electrically connected to the first intermediate node.

[0026] The gate of the second transistor is electrically connected to the first scan terminal, the first terminal of the second transistor is electrically connected to the first intermediate node, and the second terminal of the second transistor is electrically connected to the data line.

[0027] Optionally, the third control circuit includes a third transistor;

[0028] The gate of the third transistor is electrically connected to the first node, the first terminal of the third transistor is electrically connected to the first voltage terminal, and the second terminal of the third transistor is electrically connected to the first intermediate node; or,

[0029] The gate and the first electrode of the third transistor are both electrically connected to the first node, and the second electrode of the third transistor is electrically connected to the first intermediate node.

[0030] Optionally, the fourth control circuit includes a fourth transistor, and the fifth control circuit includes a fifth transistor;

[0031] The gate of the fourth transistor is electrically connected to the second scan terminal, the first terminal of the fourth transistor is electrically connected to the first node, and the second terminal of the fourth transistor is electrically connected to the second intermediate node.

[0032] The gate of the fifth transistor is electrically connected to the second scan terminal, the first terminal of the fifth transistor is electrically connected to the second intermediate node, and the second terminal of the fifth transistor is electrically connected to the reference voltage terminal.

[0033] Optionally, the sixth control circuit includes a sixth transistor;

[0034] The gate of the sixth transistor is electrically connected to the first node, the first terminal of the sixth transistor is electrically connected to the second voltage terminal, and the second terminal of the sixth transistor is electrically connected to the second intermediate node; or,

[0035] The gate and the first electrode of the sixth transistor are both electrically connected to the first node, and the second electrode of the sixth transistor is electrically connected to the second intermediate node.

[0036] Optionally, the pixel circuit described in at least one embodiment of this disclosure further includes a first energy storage circuit; the first terminal of the driving circuit is electrically connected to the second node, and the second terminal of the driving circuit is electrically connected to the third node;

[0037] The first end of the first energy storage circuit is electrically connected to the first node, and the second end of the first energy storage circuit is electrically connected to the third node. The first energy storage circuit is used to store electrical energy.

[0038] Optionally, the pixel circuit described in at least one embodiment of this disclosure further includes a light-emitting element, an initial control circuit, and a second energy storage circuit;

[0039] The second node is electrically connected to the power supply voltage terminal, the third node is electrically connected to the first electrode of the light-emitting element, and the second electrode of the light-emitting element is electrically connected to the third voltage terminal;

[0040] The initial control circuit is electrically connected to the third scanning terminal, the initial voltage terminal, and the third node, respectively, and is used to write the initial voltage provided by the initial voltage terminal into the third node under the control of the third scanning signal provided by the third scanning terminal;

[0041] The first end of the second energy storage circuit is electrically connected to the third node, and the second end of the second energy storage circuit is electrically connected to the third voltage terminal. The second energy storage circuit is used to store electrical energy.

[0042] Optionally, the pixel circuit described in at least one embodiment of this disclosure further includes a light-emitting element, a first light-emitting control circuit, a second light-emitting control circuit, an initial control circuit, and a second energy storage circuit;

[0043] The first light-emitting control circuit is electrically connected to the first light-emitting control terminal, the power supply voltage terminal, and the second node, respectively, and is used to control the connection or disconnection between the power supply voltage terminal and the second node under the control of the first light-emitting control signal provided by the first light-emitting control terminal.

[0044] The second light-emitting control circuit is electrically connected to the second light-emitting control terminal, the third node, and the first electrode of the light-emitting element, respectively, and is used to control the connection or disconnection between the third node and the first electrode of the light-emitting element under the control of the second light-emitting control signal provided by the second light-emitting control terminal; the second electrode of the light-emitting element is electrically connected to the third voltage terminal.

[0045] The initial control circuit is electrically connected to the third scanning terminal, the initial voltage terminal, and the first electrode of the light-emitting element, respectively, and is used to write the initial voltage provided by the initial voltage terminal into the first electrode of the light-emitting element under the control of the third scanning signal provided by the third scanning terminal;

[0046] The first end of the second energy storage circuit is electrically connected to the third node, and the second end of the second energy storage circuit is electrically connected to the first electrode of the light-emitting element. The second energy storage circuit is used to store electrical energy.

[0047] Optionally, the initial control circuit includes a seventh transistor, the first energy storage circuit includes a first capacitor, and the second energy storage circuit includes a second capacitor;

[0048] The gate of the seventh transistor is electrically connected to the third scan terminal, the first terminal of the seventh transistor is electrically connected to the initial voltage terminal, and the second terminal of the seventh transistor is electrically connected to the third node;

[0049] The first terminal of the first capacitor is electrically connected to the first node, and the second terminal of the first capacitor is electrically connected to the third node; the first terminal of the second capacitor is electrically connected to the third node, and the second terminal of the second capacitor is electrically connected to the third voltage terminal.

[0050] Optionally, the first light-emitting control circuit includes an eighth transistor, the second light-emitting control circuit includes a ninth transistor; the initial control circuit includes a seventh transistor, the first energy storage circuit includes a first capacitor, and the second energy storage circuit includes a second capacitor.

[0051] The gate of the eighth transistor is electrically connected to the first light-emitting control terminal, the first electrode of the eighth transistor is electrically connected to the power supply voltage terminal, and the second electrode of the eighth transistor is electrically connected to the second node.

[0052] The gate of the ninth transistor is electrically connected to the second light-emitting control terminal, the first terminal of the ninth transistor is electrically connected to the third node, and the second terminal of the ninth transistor is electrically connected to the first terminal of the light-emitting element.

[0053] The gate of the seventh transistor is electrically connected to the third scanning terminal, the first terminal of the seventh transistor is electrically connected to the initial voltage terminal, and the second terminal of the seventh transistor is electrically connected to the first terminal of the light-emitting element.

[0054] The first terminal of the first capacitor is electrically connected to the first node, and the second terminal of the first capacitor is electrically connected to the third node;

[0055] The first end of the second capacitor is electrically connected to the third node, and the second end of the second capacitor is electrically connected to the first electrode of the light-emitting element.

[0056] In a second aspect, embodiments of this disclosure provide a display device including the pixel circuit described above.

[0057] The pixel circuit and display device described in at least one embodiment of this disclosure can reduce leakage current in the first node, thereby improving compensation accuracy. Attached Figure Description

[0058] Figure 1 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0059] Figure 2 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0060] Figure 3 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0061] Figure 4 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0062] Figure 5 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0063] Figure 6 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0064] Figure 7 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0065] Figure 8 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0066] Figure 9A is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0067] Figure 9B is a timing diagram of at least one embodiment of the pixel circuit shown in Figure 9A;

[0068] Figure 10 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0069] Figure 11 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0070] Figure 12 is a timing diagram of at least one embodiment of the pixel circuit shown in Figure 11;

[0071] Figure 13 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0072] Figure 14 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0073] Figure 15 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure. Detailed Implementation

[0074] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this disclosure.

[0075] In all embodiments of this disclosure, the transistors used can be thin-film transistors, field-effect transistors, or other devices with similar characteristics. In the embodiments of this disclosure, to distinguish the two terminals of the transistor other than the gate, one terminal is referred to as the first terminal and the other as the second terminal.

[0076] In actual operation, when the transistor is a thin-film transistor or a field-effect transistor, the first electrode can be the drain and the second electrode can be the source; or, the first electrode can be the source and the second electrode can be the drain.

[0077] The pixel circuit described in this embodiment includes a driving circuit and a data writing circuit;

[0078] The control terminal of the driving circuit is electrically connected to the first node, and the driving circuit is used to generate a driving current under the control of the potential of the first node.

[0079] The data writing circuit includes a first control circuit, a second control circuit, and a third control circuit. The first control circuit is electrically connected to a first scanning end, a first node, and a first intermediate node, respectively, and is used to control the connection or disconnection between the first node and the first intermediate node under the control of a first scanning signal provided by the first scanning end. The second control circuit is electrically connected to the first scanning end, the first intermediate node, and a data line, respectively, and is used to control the connection or disconnection between the first intermediate node and the data line under the control of the first scanning signal. The third control circuit is electrically connected to the first node, the first intermediate node, and a first voltage terminal, respectively, and is used to control the connection or disconnection between the first intermediate node and the first voltage terminal under the control of the potential of the first node. Alternatively,

[0080] The data writing circuit is electrically connected to the first scanning terminal, the data line, and the first node, respectively, and is used to write the data voltage provided by the data line into the first node under the control of the first scanning signal provided by the first scanning terminal. The transistor included in the data writing circuit is a dual-gate transistor. The first gate of the transistor included in the data writing circuit is electrically connected to the first scanning terminal, and the second gate of the transistor included in the data writing circuit is electrically connected to the first fixed voltage terminal.

[0081] In at least one embodiment of this disclosure, the third control circuit is used to control the potential of the first intermediate node to be an effective voltage when the potential of the first node is an effective voltage.

[0082] Optionally, the first gate can be a top gate and the second gate can be a bottom gate; or, the first gate can be a bottom gate and the second gate can be a top gate.

[0083] Optionally, the data writing circuit includes an n-type transistor, and the first fixed voltage terminal is a low voltage terminal; or, the data writing circuit includes a p-type transistor, and the first fixed voltage terminal is a high voltage terminal.

[0084] The pixel circuit described in at least one embodiment of this disclosure incorporates a leakage protection scheme to counteract transistor leakage, thereby improving compensation accuracy.

[0085] As shown in Figure 1, the pixel circuit of at least one embodiment of this disclosure includes a driving circuit 10 and a data writing circuit;

[0086] The control terminal of the driving circuit 10 is electrically connected to the first node G, and the driving circuit 10 is used to generate a driving current under the control of the potential of the first node G.

[0087] The data writing circuit includes a first control circuit 11, a second control circuit 12, and a third control circuit 13;

[0088] The first control circuit 11 is electrically connected to the first scanning end G1, the first node G and the first intermediate node N1 respectively, and is used to control the connection or disconnection between the first node G and the first intermediate node N1 under the control of the first scanning signal provided by the first scanning end G1.

[0089] The second control circuit 12 is electrically connected to the first scanning terminal G1, the first intermediate node N1, and the data line DL, respectively, and is used to control the connection or disconnection between the first intermediate node N1 and the data line DL under the control of the first scanning signal.

[0090] The third control circuit 13 is electrically connected to the first node G and the first intermediate node N1 respectively, and is used to control the potential of the first intermediate node N1 under the control of the potential of the first node G.

[0091] In at least one embodiment of the pixel circuit shown in FIG1 of this disclosure, when in operation, the third control circuit 13 is used to control the potential of the first intermediate node N1 to be an effective voltage when the potential of the first node G is an effective voltage.

[0092] Optionally, when the driving circuit includes an n-type transistor, the effective voltage can be a high voltage.

[0093] In at least one embodiment of the pixel circuit shown in FIG1 of this disclosure, when the potential of the first node G is an effective voltage, the third control circuit 13 controls the potential of the first intermediate node N1 to be an effective voltage, thereby reducing the leakage current of the first node G.

[0094] As shown in Figure 2, the pixel circuit of at least one embodiment of the present disclosure includes a driving circuit 10 and a data writing circuit 20;

[0095] The control terminal of the driving circuit 10 is electrically connected to the first node G, and the driving circuit 10 is used to generate a driving current under the control of the potential of the first node G.

[0096] The data writing circuit 20 is electrically connected to the first scanning terminal G1, the data line DL and the first node G respectively, and is used to write the data voltage Vdata provided by the data line DL into the first node G under the control of the first scanning signal provided by the first scanning terminal G1.

[0097] The data writing circuit includes a dual-gate transistor. The first gate of the transistor in the data writing circuit is electrically connected to the first scan terminal, and the second gate of the transistor in the data writing circuit is electrically connected to the first fixed voltage terminal, so as to reduce the leakage current of the transistor in the data writing circuit.

[0098] As shown in Figure 3, based on at least one embodiment shown in Figure 1, the pixel circuit of at least one embodiment of this disclosure further includes an initialization circuit;

[0099] The initialization circuit is connected to the fourth control circuit 14, the fifth control circuit 15 and the sixth control circuit 16 respectively;

[0100] The fourth control circuit 14 is electrically connected to the second scanning terminal G2, the first node G, and the second intermediate node N2, respectively, and is used to control the connection or disconnection between the first node G and the second intermediate node N2 under the control of the second scanning signal provided by the second scanning terminal G2.

[0101] The fifth control circuit 15 is electrically connected to the second scanning terminal G2, the second intermediate node N2 and the reference voltage terminal REF respectively, and is used to control the connection or disconnection between the second intermediate node N2 and the reference voltage terminal REF under the control of the second scanning signal.

[0102] The sixth control circuit 16 is electrically connected to the first node G and the second intermediate node N2 respectively, and is used to control the potential of the second intermediate node N2 under the control of the potential of the first node G.

[0103] In at least one embodiment of this disclosure, the sixth control circuit 16 is used to control the potential of the second intermediate node N2 to be an effective voltage when the potential of the first node G is an effective voltage.

[0104] As shown in Figure 4, based on at least one embodiment of the pixel circuit shown in Figure 2, the pixel circuit of at least one embodiment of this disclosure further includes an initialization circuit 30;

[0105] The initialization circuit 30 is electrically connected to the second scan terminal G2, the reference voltage terminal REF, and the first node G, respectively, and is used to write the reference voltage provided by the reference voltage terminal REF into the first node G under the control of the second scan signal provided by the second scan terminal G2.

[0106] The initialization circuit includes a dual-gate transistor, the first gate of the transistor in the initialization circuit is electrically connected to the second scan terminal, and the second gate of the transistor in the initialization circuit is electrically connected to the second fixed voltage terminal.

[0107] Optionally, the first gate is a top gate and the second gate is a bottom gate; or, the first gate is a bottom gate and the second gate is a top gate.

[0108] The initialization circuit includes an n-type transistor, and the second fixed voltage terminal is a low voltage terminal; or, the initialization circuit includes a p-type transistor, and the second fixed voltage terminal is a high voltage terminal.

[0109] Optionally, the first control circuit includes a first transistor, and the second control circuit includes a second transistor;

[0110] The gate of the first transistor is electrically connected to the first scan terminal, the first electrode of the first transistor is electrically connected to the first node, and the second electrode of the first transistor is electrically connected to the first intermediate node.

[0111] The gate of the second transistor is electrically connected to the first scan terminal, the first terminal of the second transistor is electrically connected to the first intermediate node, and the second terminal of the second transistor is electrically connected to the data line.

[0112] Optionally, the third control circuit includes a third transistor;

[0113] The gate of the third transistor is electrically connected to the first node, the first terminal of the third transistor is electrically connected to the first voltage terminal, and the second terminal of the third transistor is electrically connected to the first intermediate node; or,

[0114] The gate and the first electrode of the third transistor are both electrically connected to the first node, and the second electrode of the third transistor is electrically connected to the first intermediate node.

[0115] Optionally, the first voltage terminal can be a high voltage terminal.

[0116] Optionally, the fourth control circuit includes a fourth transistor, and the fifth control circuit includes a fifth transistor;

[0117] The gate of the fourth transistor is electrically connected to the second scan terminal, the first terminal of the fourth transistor is electrically connected to the first node, and the second terminal of the fourth transistor is electrically connected to the second intermediate node.

[0118] The gate of the fifth transistor is electrically connected to the second scan terminal, the first terminal of the fifth transistor is electrically connected to the second intermediate node, and the second terminal of the fifth transistor is electrically connected to the reference voltage terminal.

[0119] Optionally, the sixth control circuit includes a sixth transistor;

[0120] The gate of the sixth transistor is electrically connected to the first node, the first terminal of the sixth transistor is electrically connected to the second voltage terminal, and the second terminal of the sixth transistor is electrically connected to the second intermediate node; or,

[0121] The gate and the first electrode of the sixth transistor are both electrically connected to the first node, and the second electrode of the sixth transistor is electrically connected to the second intermediate node.

[0122] Optionally, the second voltage terminal can be a high voltage terminal.

[0123] The pixel circuit described in at least one embodiment of this disclosure further includes a first energy storage circuit; the first terminal of the driving circuit is electrically connected to the second node, and the second terminal of the driving circuit is electrically connected to the third node;

[0124] The first end of the first energy storage circuit is electrically connected to the first node, and the second end of the first energy storage circuit is electrically connected to the third node. The first energy storage circuit is used to store electrical energy.

[0125] In a specific implementation, the first energy storage circuit can control the potential of the third node under the control of the potential of the first node.

[0126] The pixel circuit described in at least one embodiment of this disclosure further includes a light-emitting element, an initial control circuit, and a second energy storage circuit;

[0127] The second node is electrically connected to the power supply voltage terminal, the third node is electrically connected to the first electrode of the light-emitting element, and the second electrode of the light-emitting element is electrically connected to the third voltage terminal;

[0128] The initial control circuit is electrically connected to the third scanning terminal, the initial voltage terminal, and the third node, respectively, and is used to write the initial voltage provided by the initial voltage terminal into the third node under the control of the third scanning signal provided by the third scanning terminal;

[0129] The first end of the second energy storage circuit is electrically connected to the third node, and the second end of the second energy storage circuit is electrically connected to the third voltage terminal. The second energy storage circuit is used to store electrical energy.

[0130] In a specific implementation, the pixel circuit may include a light-emitting element, an initial control circuit, and a second energy storage circuit. Under the control of a third scan signal, the initial control circuit writes an initial voltage into a third node to clear the residual charge on the first electrode of the light-emitting element. The second energy storage circuit can maintain the potential of the third node.

[0131] Optionally, the third voltage terminal can be a low voltage terminal.

[0132] As shown in Figure 5, based on at least one embodiment of the pixel circuit shown in Figure 3, the pixel circuit described in at least one embodiment of this disclosure may further include a first energy storage circuit 51.

[0133] The first end of the driving circuit 10 is electrically connected to the second node D, and the second end of the driving circuit is electrically connected to the third node S.

[0134] The first end of the first energy storage circuit 51 is electrically connected to the first node G, and the second end of the first energy storage circuit 51 is electrically connected to the third node S. The first energy storage circuit 51 is used to store electrical energy.

[0135] The pixel circuit described in at least one embodiment of this disclosure further includes a light-emitting element E1, an initial control circuit 50, and a second energy storage circuit 52;

[0136] The second node D is electrically connected to the power supply voltage terminal ELVDD, the third node S is electrically connected to the first electrode of the light-emitting element E1, and the second electrode of the light-emitting element E1 is electrically connected to the third voltage terminal V3;

[0137] The initial control circuit 50 is electrically connected to the third scan terminal G3, the initial voltage terminal VAR, and the third node S, respectively, and is used to write the initial voltage Var provided by the initial voltage terminal VAR into the third node S under the control of the third scan signal provided by the third scan terminal G3.

[0138] The first end of the second energy storage circuit 52 is electrically connected to the third node S, and the second end of the second energy storage circuit 52 is electrically connected to the third voltage terminal V3. The second energy storage circuit 52 is used to store electrical energy.

[0139] As shown in Figure 6, based on at least one embodiment of the pixel circuit shown in Figure 4, the pixel circuit described in at least one embodiment of this disclosure may further include a first energy storage circuit 51.

[0140] The first end of the driving circuit 10 is electrically connected to the second node D, and the second end of the driving circuit is electrically connected to the third node S.

[0141] The first end of the first energy storage circuit 51 is electrically connected to the first node G, and the second end of the first energy storage circuit 51 is electrically connected to the third node S. The first energy storage circuit 51 is used to store electrical energy.

[0142] The pixel circuit described in at least one embodiment of this disclosure further includes a light-emitting element E1, an initial control circuit 50, and a second energy storage circuit 52;

[0143] The second node D is electrically connected to the power supply voltage terminal ELVDD, the third node S is electrically connected to the first electrode of the light-emitting element E1, and the second electrode of the light-emitting element E1 is electrically connected to the third voltage terminal V3;

[0144] The initial control circuit 50 is electrically connected to the third scan terminal G3, the initial voltage terminal VAR, and the third node S, respectively, and is used to write the initial voltage Var provided by the initial voltage terminal VAR into the third node S under the control of the third scan signal provided by the third scan terminal G3.

[0145] The first end of the second energy storage circuit 52 is electrically connected to the third node S, and the second end of the second energy storage circuit 52 is electrically connected to the third voltage terminal V3. The second energy storage circuit 52 is used to store electrical energy.

[0146] The pixel circuit described in at least one embodiment of this disclosure further includes a light-emitting element, a first light-emitting control circuit, a second light-emitting control circuit, an initial control circuit, and a second energy storage circuit;

[0147] The first light-emitting control circuit is electrically connected to the first light-emitting control terminal, the power supply voltage terminal, and the second node, respectively, and is used to control the connection or disconnection between the power supply voltage terminal and the second node under the control of the first light-emitting control signal provided by the first light-emitting control terminal.

[0148] The second light-emitting control circuit is electrically connected to the second light-emitting control terminal, the third node, and the first electrode of the light-emitting element, respectively, and is used to control the connection or disconnection between the third node and the first electrode of the light-emitting element under the control of the second light-emitting control signal provided by the second light-emitting control terminal; the second electrode of the light-emitting element is electrically connected to the third voltage terminal.

[0149] The initial control circuit is electrically connected to the third scanning terminal, the initial voltage terminal, and the first electrode of the light-emitting element, respectively, and is used to write the initial voltage provided by the initial voltage terminal into the first electrode of the light-emitting element under the control of the third scanning signal provided by the third scanning terminal;

[0150] The first end of the second energy storage circuit is electrically connected to the third node, and the second end of the second energy storage circuit is electrically connected to the first electrode of the light-emitting element. The second energy storage circuit is used to store electrical energy.

[0151] In a specific implementation, the pixel circuit may further include a light-emitting element, a first light-emitting control circuit, a second light-emitting control circuit, an initial control circuit, and a second energy storage circuit; the first light-emitting control circuit and the second light-emitting control circuit are used to control the on / off state of the light-emitting path, and the initial control circuit initializes the first electrode of the light-emitting element under the control of the third scanning signal, clearing the residual charge on the first electrode of the light-emitting element.

[0152] As shown in Figure 7, based on at least one embodiment of the pixel circuit shown in Figure 3, the pixel circuit described in at least one embodiment of this disclosure may further include a light-emitting element E1, a first light-emitting control circuit 71, a second light-emitting control circuit 72, an initial control circuit 50, and a second energy storage circuit 52.

[0153] The pixel circuit described in at least one embodiment of this disclosure may further include a first energy storage circuit 51;

[0154] The first end of the driving circuit 10 is electrically connected to the second node D, and the second end of the driving circuit is electrically connected to the third node S.

[0155] The first end of the first energy storage circuit 51 is electrically connected to the first node G, and the second end of the first energy storage circuit 51 is electrically connected to the third node S. The first energy storage circuit 51 is used to store electrical energy.

[0156] The first light-emitting control circuit 71 is electrically connected to the first light-emitting control terminal EM1, the power supply voltage terminal ELVDD, and the second node D, respectively, and is used to control the connection or disconnection between the power supply voltage terminal ELVDD and the second node D under the control of the first light-emitting control signal provided by the first light-emitting control terminal EM1.

[0157] The second light-emitting control circuit 72 is electrically connected to the second light-emitting control terminal EM2, the third node S, and the first electrode of the light-emitting element E1, respectively. It is used to control the connection or disconnection between the third node S and the first electrode of the light-emitting element E1 under the control of the second light-emitting control signal provided by the second light-emitting control terminal EM2; the second electrode of the light-emitting element E1 is electrically connected to the third voltage terminal V3.

[0158] The initial control circuit 50 is electrically connected to the third scanning terminal G3, the initial voltage terminal VAR, and the first electrode of the light-emitting element E1, respectively, and is used to write the initial voltage Var provided by the initial voltage terminal VAR into the first electrode of the light-emitting element E1 under the control of the third scanning signal provided by the third scanning terminal G3.

[0159] The first end of the second energy storage circuit 52 is electrically connected to the third node S, and the second end of the second energy storage circuit 52 is electrically connected to the first electrode of the light-emitting element E1. The second energy storage circuit 52 is used to store electrical energy.

[0160] As shown in Figure 8, based on at least one embodiment of the pixel circuit shown in Figure 4, the pixel circuit described in at least one embodiment of this disclosure may further include a first energy storage circuit 51.

[0161] The first end of the driving circuit 10 is electrically connected to the second node D, and the second end of the driving circuit is electrically connected to the third node S.

[0162] The first end of the first energy storage circuit 51 is electrically connected to the first node G, and the second end of the first energy storage circuit 51 is electrically connected to the third node S. The first energy storage circuit 51 is used to store electrical energy.

[0163] The pixel circuit described in at least one embodiment of this disclosure may further include a light-emitting element E1, a first light-emitting control circuit 71, a second light-emitting control circuit 72, an initial control circuit 50, and a second energy storage circuit 52.

[0164] The first light-emitting control circuit 71 is electrically connected to the first light-emitting control terminal EM1, the power supply voltage terminal ELVDD, and the second node D, respectively, and is used to control the connection or disconnection between the power supply voltage terminal ELVDD and the second node D under the control of the first light-emitting control signal provided by the first light-emitting control terminal EM1.

[0165] The second light-emitting control circuit 72 is electrically connected to the second light-emitting control terminal EM2, the third node S, and the first electrode of the light-emitting element E1, respectively. It is used to control the connection or disconnection between the third node S and the first electrode of the light-emitting element E1 under the control of the second light-emitting control signal provided by the second light-emitting control terminal EM2; the second electrode of the light-emitting element E1 is electrically connected to the third voltage terminal V3.

[0166] The initial control circuit 50 is electrically connected to the third scanning terminal G3, the initial voltage terminal VAR, and the first electrode of the light-emitting element E1, respectively, and is used to write the initial voltage Var provided by the initial voltage terminal VAR into the first electrode of the light-emitting element E1 under the control of the third scanning signal provided by the third scanning terminal G3.

[0167] The first end of the second energy storage circuit 52 is electrically connected to the third node S, and the second end of the second energy storage circuit 52 is electrically connected to the first electrode of the light-emitting element E1. The second energy storage circuit 52 is used to store electrical energy.

[0168] Optionally, the initial control circuit includes a seventh transistor, the first energy storage circuit includes a first capacitor, and the second energy storage circuit includes a second capacitor;

[0169] The gate of the seventh transistor is electrically connected to the third scan terminal, the first terminal of the seventh transistor is electrically connected to the initial voltage terminal, and the second terminal of the seventh transistor is electrically connected to the third node;

[0170] The first terminal of the first capacitor is electrically connected to the first node, and the second terminal of the first capacitor is electrically connected to the third node;

[0171] The first terminal of the second capacitor is electrically connected to the third node, and the second terminal of the second capacitor is electrically connected to the third voltage terminal.

[0172] Optionally, the first light-emitting control circuit includes an eighth transistor, the second light-emitting control circuit includes a ninth transistor; the initial control circuit includes a seventh transistor, the first energy storage circuit includes a first capacitor, and the second energy storage circuit includes a second capacitor.

[0173] The gate of the eighth transistor is electrically connected to the first light-emitting control terminal, the first electrode of the eighth transistor is electrically connected to the power supply voltage terminal, and the second electrode of the eighth transistor is electrically connected to the second node.

[0174] The gate of the ninth transistor is electrically connected to the second light-emitting control terminal, the first terminal of the ninth transistor is electrically connected to the third node, and the second terminal of the ninth transistor is electrically connected to the first terminal of the light-emitting element.

[0175] The gate of the seventh transistor is electrically connected to the third scanning terminal, the first terminal of the seventh transistor is electrically connected to the initial voltage terminal, and the second terminal of the seventh transistor is electrically connected to the first terminal of the light-emitting element.

[0176] The first terminal of the first capacitor is electrically connected to the first node, and the second terminal of the first capacitor is electrically connected to the third node;

[0177] The first end of the second capacitor is electrically connected to the third node, and the second end of the second capacitor is electrically connected to the first electrode of the light-emitting element.

[0178] As shown in Figure 9A, based on at least one embodiment of the pixel circuit shown in Figure 5, the light-emitting element is an organic light-emitting diode O1;

[0179] The first control circuit includes a first transistor T1, and the second control circuit includes a second transistor T2;

[0180] The gate of the first transistor T1 is electrically connected to the first scan terminal G1, the drain of the first transistor T1 is electrically connected to the first node G, and the source of the first transistor T1 is electrically connected to the first intermediate node N1.

[0181] The gate of the second transistor T2 is electrically connected to the first scan terminal G1, the drain of the second transistor T2 is electrically connected to the first intermediate node N1, and the source of the second transistor T2 is electrically connected to the data line DL.

[0182] The third control circuit includes a third transistor T3;

[0183] The gate of the third transistor T3 is electrically connected to the first node G, the drain of the third transistor T3 is electrically connected to the high voltage terminal VGH, and the source of the third transistor T3 is electrically connected to the first intermediate node N1.

[0184] The fourth control circuit includes a fourth transistor T4, and the fifth control circuit includes a fifth transistor T5;

[0185] The gate of the fourth transistor T4 is electrically connected to the second scan terminal G2, the drain of the fourth transistor T4 is electrically connected to the first node G, and the source of the fourth transistor T4 is electrically connected to the second intermediate node N2.

[0186] The gate of the fifth transistor T5 is electrically connected to the second scan terminal G2, the drain of the fifth transistor T5 is electrically connected to the second intermediate node N2, and the source of the fifth transistor T5 is electrically connected to the reference voltage terminal REF.

[0187] The sixth control circuit includes a sixth transistor T6;

[0188] The gate of the sixth transistor T6 is electrically connected to the first node G, the drain of the sixth transistor T6 is electrically connected to the high voltage terminal VGH, and the source of the sixth transistor T6 is electrically connected to the second intermediate node N2.

[0189] The driving circuit includes a driving transistor DT;

[0190] The gate of the driving transistor DT is electrically connected to the first node G, the drain of the driving transistor DT is electrically connected to the power supply voltage terminal ELVDD, and the drain of the driving transistor DT is electrically connected to the third node S.

[0191] The initial control circuit includes a seventh transistor T7, the first energy storage circuit includes a first capacitor C1, and the second energy storage circuit includes a second capacitor C2.

[0192] The gate of the seventh transistor T7 is electrically connected to the third scan terminal G3, the drain of the seventh transistor T7 is electrically connected to the initial voltage terminal VAR, and the source of the seventh transistor T7 is electrically connected to the third node S.

[0193] The first terminal of the first capacitor C1 is electrically connected to the first node G, and the second terminal of the first capacitor C1 is electrically connected to the third node S.

[0194] The first terminal of the second capacitor C2 is electrically connected to the third node S, and the second terminal of the second capacitor C2 is electrically connected to the low voltage terminal ELVSS.

[0195] The anode of O1 is electrically connected to the third node S, and the cathode of O1 is electrically connected to the low voltage terminal ELVSS.

[0196] In at least one embodiment of the pixel circuit shown in Figure 9A, all transistors are n-type transistors.

[0197] In at least one embodiment of this disclosure, the pixel circuit may include an n-type LTPS (low-temperature polysilicon) transistor.

[0198] In the display industry, LTPS transistors are widely used due to their high mobility, which allows for smaller bezels. Source-follower internally compensated pixel circuits are commonly used for accurate compensation because they have low requirements for integrated circuits (ICs). However, n-type LTPS transistors in source-follower internally compensated pixel circuits can leak current, affecting compensation accuracy. At least one embodiment of this disclosure describes a scheme to add leakage protection to the pixel circuit to counteract the leakage current of the n-type LTPS transistors, thereby improving compensation accuracy.

[0199] In at least one embodiment of the pixel circuit shown in FIG9A of this disclosure, T2, T3, T5 and T6 are added. When the potential of the first node G is high voltage, T3 is turned on, and N1 is connected to VGH so that the potential of N1 is high voltage, thus allowing T1 to be completely turned off without leakage. When the potential of the first node G is high voltage, T6 is turned on, and N2 is connected to VGH so that the potential of N2 is high voltage, thus allowing T2 to be completely turned off without leakage. This can reduce the leakage of the first node G.

[0200] As shown in FIG9B, when at least one embodiment of the pixel circuit shown in FIG9A of this disclosure is in operation, the display cycle may include a reset phase S1, a compensation phase S2, a data writing phase S3 and a light emission phase S4 arranged sequentially.

[0201] During the reset phase S1, G2 and G3 provide high voltage signals, G1 provides a low voltage signal, T4 and T5 are both turned on, T7 is turned on, VAR provides an initial voltage Var to the anode of O1 to clear the residual charge on the anode of O1; VAR provides an initial voltage Var to the third node S; REF provides a reference voltage Vref to the first node G, so that DT can be turned on at the beginning of the compensation phase S2.

[0202] During the compensation phase S2, G1 provides a low voltage signal, G2 and G3 provide high voltage signals, T4 and T5 are both turned on, and T7 is turned on.

[0203] At the start of the compensation phase S2, DT is turned on, charging C1 through the power supply voltage signal provided by ELVDD, changing the potential of the third node S until the potential of the third node S becomes Vref-Vth, at which point DT is turned off; Vth is the threshold voltage of DT.

[0204] During the data writing phase S3, G1 provides a high voltage signal, G2 provides a low voltage signal, and G3 provides a high voltage signal. T1 and T2 are turned on. DL provides the data voltage Vdata to the first node G, and VAR provides the initial voltage Var to the anode of O1 to clear the residual charge on the anode of O1. The potential of the third node S becomes Vref-Vth+(Vdata-Vref)×(C1z / (C1z+C2z)) due to the voltage division effect of C1 and C2, where C1z is the capacitance value of C1 and C2z is the capacitance value of C2.

[0205] During the light-emitting stage S4, G1, G2, and G3 all provide low-voltage signals. DT drives O1 to emit light, and the driving current Id generated by DT is equal to K×((Vdata-Vref)×(C2z / (C1z+C2z))). 2 Id is independent of Vth; K is the current coefficient of DT.

[0206] As shown in Figure 10, based on at least one embodiment of the pixel circuit shown in Figure 5, the light-emitting element is an organic light-emitting diode O1;

[0207] The first control circuit includes a first transistor T1, and the second control circuit includes a second transistor T2;

[0208] The gate of the first transistor T1 is electrically connected to the first scan terminal G1, the drain of the first transistor T1 is electrically connected to the first node G, and the source of the first transistor T1 is electrically connected to the first intermediate node N1.

[0209] The gate of the second transistor T2 is electrically connected to the first scan terminal G1, the drain of the second transistor T2 is electrically connected to the first intermediate node N1, and the source of the second transistor T2 is electrically connected to the data line DL.

[0210] The third control circuit includes a third transistor T3;

[0211] The gate and drain of the third transistor T3 are both electrically connected to the first node G, and the source of the third transistor T3 is electrically connected to the first intermediate node N1.

[0212] The fourth control circuit includes a fourth transistor T4, and the fifth control circuit includes a fifth transistor T5;

[0213] The gate of the fourth transistor T4 is electrically connected to the second scan terminal G2, the drain of the fourth transistor T4 is electrically connected to the first node G, and the source of the fourth transistor T4 is electrically connected to the second intermediate node N2.

[0214] The gate of the fifth transistor T5 is electrically connected to the second scan terminal G2, the drain of the fifth transistor T5 is electrically connected to the second intermediate node N2, and the source of the fifth transistor T5 is electrically connected to the reference voltage terminal REF.

[0215] The sixth control circuit includes a sixth transistor T6;

[0216] The gate and drain of the sixth transistor T6 are both electrically connected to the first node G, and the source of the sixth transistor T6 is electrically connected to the second intermediate node N2.

[0217] The driving circuit includes a driving transistor DT;

[0218] The gate of the driving transistor DT is electrically connected to the first node G, the drain of the driving transistor DT is electrically connected to the power supply voltage terminal ELVDD, and the drain of the driving transistor DT is electrically connected to the third node S.

[0219] The initial control circuit includes a seventh transistor T7, the first energy storage circuit includes a first capacitor C1, and the second energy storage circuit includes a second capacitor C2.

[0220] The gate of the seventh transistor T7 is electrically connected to the third scan terminal G3, the drain of the seventh transistor T7 is electrically connected to the initial voltage terminal VAR, and the source of the seventh transistor T7 is electrically connected to the third node S.

[0221] The first terminal of the first capacitor C1 is electrically connected to the first node G, and the second terminal of the first capacitor C1 is electrically connected to the third node S.

[0222] The first terminal of the second capacitor C2 is electrically connected to the third node S, and the second terminal of the second capacitor C2 is electrically connected to the low voltage terminal ELVSS.

[0223] The anode of O1 is electrically connected to the third node S, and the cathode of O1 is electrically connected to the low voltage terminal ELVSS.

[0224] In at least one embodiment of the pixel circuit shown in Figure 10, all transistors are n-type transistors.

[0225] In at least one embodiment of the pixel circuit shown in FIG10 of this disclosure, T2, T3, T5 and T6 are added. When the potential of the first node G is high voltage, T3 is turned on, and N1 is connected to G, so that the potential of N1 is high voltage, thus allowing T1 to be completely turned off without leakage. When the potential of the first node G is high voltage, T6 is turned on, and N2 is connected to G, so that the potential of N2 is high voltage, thus allowing T2 to be completely turned off without leakage. This can reduce the leakage of the first node G.

[0226] As shown in Figure 11, based on at least one embodiment of the pixel circuit shown in Figure 7, the light-emitting element is an organic light-emitting diode O1;

[0227] The first control circuit includes a first transistor T1, and the second control circuit includes a second transistor T2;

[0228] The gate of the first transistor T1 is electrically connected to the first scan terminal G1, the drain of the first transistor T1 is electrically connected to the first node G, and the source of the first transistor T1 is electrically connected to the first intermediate node N1.

[0229] The gate of the second transistor T2 is electrically connected to the first scan terminal G1, the drain of the second transistor T2 is electrically connected to the first intermediate node N1, and the source of the second transistor T2 is electrically connected to the data line DL.

[0230] The third control circuit includes a third transistor T3;

[0231] The gate of the third transistor T3 is electrically connected to the first node G, the drain of the third transistor T3 is electrically connected to the high voltage terminal VGH, and the source of the third transistor T3 is electrically connected to the first intermediate node N1.

[0232] The fourth control circuit includes a fourth transistor T4, and the fifth control circuit includes a fifth transistor T5;

[0233] The gate of the fourth transistor T4 is electrically connected to the second scan terminal G2, the drain of the fourth transistor T4 is electrically connected to the first node G, and the source of the fourth transistor T4 is electrically connected to the second intermediate node N2.

[0234] The gate of the fifth transistor T5 is electrically connected to the second scan terminal G2, the drain of the fifth transistor T5 is electrically connected to the second intermediate node N2, and the source of the fifth transistor T5 is electrically connected to the reference voltage terminal REF.

[0235] The sixth control circuit includes a sixth transistor T6;

[0236] The gate of the sixth transistor T6 is electrically connected to the first node G, the drain of the sixth transistor T6 is electrically connected to the high voltage terminal VGH, and the source of the sixth transistor T6 is electrically connected to the second intermediate node N2.

[0237] The driving circuit includes a driving transistor DT;

[0238] The gate of the driving transistor DT is electrically connected to the first node G, the drain of the driving transistor DT is electrically connected to the second node D, and the source of the driving transistor DT is electrically connected to the third node S.

[0239] The first light-emitting control circuit includes an eighth transistor T8, the second light-emitting control circuit includes a ninth transistor T9; the initial control circuit includes a seventh transistor T7, the first energy storage circuit includes a first capacitor C1, and the second energy storage circuit includes a second capacitor C2.

[0240] The gate of the eighth transistor T8 is electrically connected to the first light-emitting control terminal EM1, the drain of the eighth transistor T8 is electrically connected to the power supply voltage terminal ELVDD, and the source of the eighth transistor T8 is electrically connected to the second node D.

[0241] The gate of the ninth transistor T9 is electrically connected to the second light-emitting control terminal EM2, the drain of the ninth transistor T9 is electrically connected to the third node S, the source of the ninth transistor T9 is electrically connected to the anode of O1, and the cathode of O1 is electrically connected to the low-voltage terminal ELVSS.

[0242] The gate of the seventh transistor T7 is electrically connected to the third scan terminal G3, the drain of the seventh transistor T7 is electrically connected to the initial voltage terminal VAR, and the source of the seventh transistor T7 is electrically connected to the anode of O1.

[0243] The first terminal of the first capacitor C1 is electrically connected to the first node G, and the second terminal of the first capacitor C1 is electrically connected to the third node S.

[0244] The first end of the second capacitor C2 is electrically connected to the third node S, and the second end of the second capacitor C2 is electrically connected to the anode of O1.

[0245] In at least one embodiment of the pixel circuit shown in Figure 11, all transistors are n-type transistors.

[0246] Figure 12 is a timing diagram of at least one embodiment of the pixel circuit shown in Figure 11.

[0247] As shown in FIG12, when at least one embodiment of the pixel circuit shown in FIG11 of this disclosure is in operation, the display cycle may include a reset stage S1, a compensation stage S2, a data writing stage S3 and a light emission stage S4 arranged sequentially.

[0248] During the reset phase S1, EM1 provides a low voltage signal, EM2, G2, and G3 provide high voltage signals, G1 provides a low voltage signal, T9 is turned on, T4 and T5 are both turned on, T7 is turned on, VAR provides an initial voltage Var to the anode of O1 to clear residual charge on the anode of O1; VAR provides an initial voltage Var to the third node S; REF provides a reference voltage Vref to the first node G, so that DT can be turned on at the beginning of the compensation phase S2.

[0249] During the compensation phase S2, EM1 provides a high voltage signal, EM2 provides a low voltage signal, G1 provides a low voltage signal, G2 and G3 provide high voltage signals, T8 is turned on, T4 and T5 are both turned on, and T7 is turned on.

[0250] At the start of the compensation phase S2, DT is turned on, charging C1 through the power supply voltage signal provided by ELVDD, changing the potential of the third node S until the potential of the third node S becomes Vref-Vth, at which point DT is turned off; Vth is the threshold voltage of DT.

[0251] During the data writing phase S3, EM1 and EM2 provide low voltage signals, G1 provides a high voltage signal, G2 provides a low voltage signal, and G3 provides a high voltage signal. T1 and T2 are turned on. DL provides the data voltage Vdata to the first node G, and VAR provides the initial voltage Var to the anode of O1 to clear the residual charge on the anode of O1. The potential of the third node S becomes Vref-Vth+(Vdata-Vref)×(C1z / (C1z+C2z)) due to the voltage division effect of C1 and C2, where C1z is the capacitance value of C1 and C2z is the capacitance value of C2.

[0252] During the light-emitting stage S4, EM1 and EM2 provide high-voltage signals, while G1, G2, and G3 provide low-voltage signals. T8 and T9 are both turned on, and DT drives O1 to emit light. The driving current Id generated by DT is equal to K×((Vdata-Vref)×(C2z / (C1z+C2z))). 2 Id is independent of Vth; K is the current coefficient of DT.

[0253] As shown in Figure 13, based on at least one embodiment of the pixel circuit shown in Figure 6,

[0254] The data writing circuit includes a first transistor T1;

[0255] The first transistor T1 is a dual-gate transistor;

[0256] The top gate of the first transistor T1 is electrically connected to the first scan terminal G1, and the bottom gate of the first transistor T1 is electrically connected to the first fixed voltage terminal VG1; the drain of T1 is electrically connected to the data line DL, and the source of T1 is electrically connected to the first node G.

[0257] The initialization circuit includes a fourth transistor T4;

[0258] The top gate of the fourth transistor T4 is electrically connected to the second scan terminal G2, the bottom gate of the fourth transistor T4 is electrically connected to the second fixed voltage terminal VG2, the drain of the fourth transistor T4 is electrically connected to the reference voltage terminal REF, and the source of the fourth transistor T4 is electrically connected to the first node G.

[0259] The driving circuit includes a driving transistor DT;

[0260] The gate of the driving transistor DT is electrically connected to the first node G, the drain of the driving transistor DT is electrically connected to the power supply voltage terminal ELVDD, and the drain of the driving transistor DT is electrically connected to the third node S.

[0261] The initial control circuit includes a seventh transistor T7, the first energy storage circuit includes a first capacitor C1, and the second energy storage circuit includes a second capacitor C2.

[0262] The gate of the seventh transistor T7 is electrically connected to the third scan terminal G3, the drain of the seventh transistor T7 is electrically connected to the initial voltage terminal VAR, and the source of the seventh transistor T7 is electrically connected to the third node S.

[0263] The first terminal of the first capacitor C1 is electrically connected to the first node G, and the second terminal of the first capacitor C1 is electrically connected to the third node S.

[0264] The first terminal of the second capacitor C2 is electrically connected to the third node S, and the second terminal of the second capacitor C2 is electrically connected to the low voltage terminal ELVSS.

[0265] The anode of O1 is electrically connected to the third node S, and the cathode of O1 is electrically connected to the low voltage terminal ELVSS.

[0266] In at least one embodiment of the pixel circuit shown in Figure 13, all transistors are n-type transistors.

[0267] In at least one embodiment of the pixel circuit shown in Figure 13, T1 and T4 are dual-gate transistors. The bottom gate of T1 is electrically connected to the first fixed voltage terminal VG1, and the bottom gate of T4 is electrically connected to the second fixed voltage terminal VG2, so as to reduce the leakage current of T1 and T4 and eliminate the risk of leakage current.

[0268] In at least one embodiment of the pixel circuit shown in Figure 13, the first fixed voltage terminal VG1 can be a low voltage terminal, and the second fixed voltage terminal VG2 can be a low voltage terminal.

[0269] The voltage value of the low voltage signal provided by VG1 can be greater than or equal to -10V and less than or equal to -6V, and the voltage value of the low voltage signal provided by VG2 can be greater than or equal to -10V and less than or equal to -6V.

[0270] In at least one embodiment of this disclosure, when T1 and T4 are replaced with p-type transistors, VG1 and VG2 can provide high-voltage signals, the voltage values ​​of which can be greater than or equal to 2V and less than or equal to 6V.

[0271] Optionally, the first fixed voltage terminal and the second fixed voltage terminal can be the same fixed voltage terminal to reduce the number of fixed voltage terminals used.

[0272] As shown in Figure 14, based on at least one embodiment of the pixel circuit shown in Figure 6,

[0273] The data writing circuit includes a first transistor T1;

[0274] The first transistor T1 is a dual-gate transistor;

[0275] The top gate of the first transistor T1 is electrically connected to the first scan terminal G1, and the bottom gate of the first transistor T1 is electrically connected to the first fixed voltage terminal VG1; the drain of T1 is electrically connected to the data line DL, and the source of T1 is electrically connected to the first node G.

[0276] The initialization circuit includes a fourth transistor T4;

[0277] The top gate of the fourth transistor T4 is electrically connected to the second scan terminal G2, the bottom gate of the fourth transistor T4 is electrically connected to the first fixed voltage terminal VG1, the drain of the fourth transistor T4 is electrically connected to the reference voltage terminal REF, and the source of the fourth transistor T4 is electrically connected to the first node G.

[0278] The driving circuit includes a driving transistor DT;

[0279] The gate of the driving transistor DT is electrically connected to the first node G, the drain of the driving transistor DT is electrically connected to the power supply voltage terminal ELVDD, and the drain of the driving transistor DT is electrically connected to the third node S.

[0280] The initial control circuit includes a seventh transistor T7, the first energy storage circuit includes a first capacitor C1, and the second energy storage circuit includes a second capacitor C2.

[0281] The gate of the seventh transistor T7 is electrically connected to the third scan terminal G3, the drain of the seventh transistor T7 is electrically connected to the initial voltage terminal VAR, and the source of the seventh transistor T7 is electrically connected to the third node S.

[0282] The first terminal of the first capacitor C1 is electrically connected to the first node G, and the second terminal of the first capacitor C1 is electrically connected to the third node S.

[0283] The first terminal of the second capacitor C2 is electrically connected to the third node S, and the second terminal of the second capacitor C2 is electrically connected to the low voltage terminal ELVSS.

[0284] The anode of O1 is electrically connected to the third node S, and the cathode of O1 is electrically connected to the low voltage terminal ELVSS.

[0285] In at least one embodiment of the pixel circuit shown in Figure 14, all transistors are n-type transistors.

[0286] In at least one embodiment of the pixel circuit shown in Figure 14, T1 and T4 are dual-gate transistors. The bottom gate of T1 is electrically connected to the first fixed voltage terminal VG1, and the bottom gate of T4 is electrically connected to the first fixed voltage terminal VG1, so as to reduce the leakage current of T1 and T4 and eliminate the risk of leakage current.

[0287] In at least one embodiment of the pixel circuit shown in Figure 14, the first fixed voltage terminal VG1 can be a low voltage terminal.

[0288] The low-voltage signal provided by VG1 can be greater than or equal to -10V and less than or equal to -6V.

[0289] As shown in Figure 15, based on at least one embodiment of the pixel circuit shown in Figure 8,

[0290] The data writing circuit includes a first transistor T1;

[0291] The first transistor T1 is a dual-gate transistor;

[0292] The top gate of the first transistor T1 is electrically connected to the first scan terminal G1, and the bottom gate of the first transistor T1 is electrically connected to the first fixed voltage terminal VG1; the drain of T1 is electrically connected to the data line DL, and the source of T1 is electrically connected to the first node G.

[0293] The initialization circuit includes a fourth transistor T4;

[0294] The top gate of the fourth transistor T4 is electrically connected to the second scan terminal G2, the bottom gate of the fourth transistor T4 is electrically connected to the first fixed voltage terminal VG1, the drain of the fourth transistor T4 is electrically connected to the reference voltage terminal REF, and the source of the fourth transistor T4 is electrically connected to the first node G.

[0295] The driving circuit includes a driving transistor DT;

[0296] The gate of the driving transistor DT is electrically connected to the first node G, the drain of the driving transistor DT is electrically connected to the second node D, and the source of the driving transistor DT is electrically connected to the third node S.

[0297] The first light-emitting control circuit includes an eighth transistor T8, the second light-emitting control circuit includes a ninth transistor T9; the initial control circuit includes a seventh transistor T7, the first energy storage circuit includes a first capacitor C1, and the second energy storage circuit includes a second capacitor C2.

[0298] The gate of the eighth transistor T8 is electrically connected to the first light-emitting control terminal EM1, the drain of the eighth transistor T8 is electrically connected to the power supply voltage terminal ELVDD, and the source of the eighth transistor T8 is electrically connected to the second node D.

[0299] The gate of the ninth transistor T9 is electrically connected to the second light-emitting control terminal EM2, the drain of the ninth transistor T9 is electrically connected to the third node S, the source of the ninth transistor T9 is electrically connected to the anode of O1, and the cathode of O1 is electrically connected to the low-voltage terminal ELVSS.

[0300] The gate of the seventh transistor T7 is electrically connected to the third scan terminal G3, the drain of the seventh transistor T7 is electrically connected to the initial voltage terminal VAR, the source of the seventh transistor T7 is electrically connected to the anode of O1, and the cathode of O1 is electrically connected to the low voltage terminal ELVSS.

[0301] The first terminal of the first capacitor C1 is electrically connected to the first node G, and the second terminal of the first capacitor C1 is electrically connected to the third node S.

[0302] The first end of the second capacitor C2 is electrically connected to the third node S, and the second end of the second capacitor C2 is electrically connected to the anode of O1.

[0303] In at least one embodiment of the pixel circuit shown in Figure 15, all transistors are n-type transistors.

[0304] In at least one embodiment of the pixel circuit shown in Figure 15, T1 and T4 are dual-gate transistors. The bottom gate of T1 is electrically connected to the first fixed voltage terminal VG1, and the bottom gate of T4 is electrically connected to the first fixed voltage terminal VG1, so as to reduce the leakage current of T1 and T4 and eliminate the risk of leakage current.

[0305] In at least one embodiment of the pixel circuit shown in Figure 15, the first fixed voltage terminal VG1 can be a low voltage terminal.

[0306] The low-voltage signal provided by VG1 can be greater than or equal to -10V and less than or equal to -6V.

[0307] The display device described in this disclosure includes the pixel circuit described above.

[0308] The above description represents the preferred embodiments of this disclosure. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles described herein, and these improvements and modifications should also be considered within the scope of protection of this disclosure.

Claims

1. A pixel circuit, comprising a driving circuit and a data writing circuit; The control terminal of the driving circuit is electrically connected to the first node, and the driving circuit is used to generate a driving current under the control of the potential of the first node. The data writing circuit includes a first control circuit, a second control circuit, and a third control circuit. The first control circuit is electrically connected to a first scanning end, a first node, and a first intermediate node, respectively, and is used to control the connection or disconnection between the first node and the first intermediate node under the control of a first scanning signal provided by the first scanning end. The second control circuit is electrically connected to the first scanning end, the first intermediate node, and a data line, respectively, and is used to control the connection or disconnection between the first intermediate node and the data line under the control of the first scanning signal. The third control circuit is electrically connected to the first node and the first intermediate node, respectively, and is used to control the potential of the first intermediate node under the control of the potential of the first node; or... The data writing circuit is electrically connected to the first scanning terminal, the data line, and the first node, respectively, and is used to write the data voltage provided by the data line into the first node under the control of the first scanning signal provided by the first scanning terminal. The transistor included in the data writing circuit is a dual-gate transistor. The first gate of the transistor included in the data writing circuit is electrically connected to the first scanning terminal, and the second gate of the transistor included in the data writing circuit is electrically connected to the first fixed voltage terminal.

2. The pixel circuit as described in claim 1, wherein, The third control circuit is used to control the potential of the first intermediate node to be an effective voltage when the potential of the first node is an effective voltage.

3. The pixel circuit as described in claim 1, wherein, The data writing circuit includes dual-gate transistors; The first gate is a top gate and the second gate is a bottom gate; or, the first gate is a bottom gate and the second gate is a top gate. The data writing circuit includes an n-type transistor, and the first fixed voltage terminal is a low voltage terminal; or, the data writing circuit includes a p-type transistor, and the first fixed voltage terminal is a high voltage terminal.

4. The pixel circuit as described in claim 1, wherein, It also includes an initialization circuit; The initialization circuit is connected to the fourth control circuit, the fifth control circuit and the sixth control circuit respectively; The fourth control circuit is electrically connected to the second scanning end, the first node, and the second intermediate node, respectively, and is used to control the connection or disconnection between the first node and the second intermediate node under the control of the second scanning signal provided by the second scanning end. The fifth control circuit is electrically connected to the second scanning terminal, the second intermediate node, and the reference voltage terminal respectively, and is used to control the connection or disconnection between the second intermediate node and the reference voltage terminal under the control of the second scanning signal. The sixth control circuit is electrically connected to the first node and the second intermediate node respectively, and is used to control the potential of the second intermediate node under the control of the potential of the first node.

5. The pixel circuit as described in claim 4, wherein, The sixth control circuit is used to control the potential of the second intermediate node to be an effective voltage when the potential of the first node is an effective voltage.

6. The pixel circuit as described in claim 1, wherein, It also includes an initialization circuit; The initialization circuit is electrically connected to the second scan terminal, the reference voltage terminal, and the first node, respectively, and is used to write the reference voltage provided by the reference voltage terminal into the first node under the control of the second scan signal provided by the second scan terminal; the transistor included in the initialization circuit is a dual-gate transistor, the first gate of the transistor included in the initialization circuit is electrically connected to the second scan terminal, and the second gate of the transistor included in the initialization circuit is electrically connected to the second fixed voltage terminal.

7. The pixel circuit as described in claim 6, wherein, The first gate is a top gate and the second gate is a bottom gate; or, the first gate is a bottom gate and the second gate is a top gate. The initialization circuit includes an n-type transistor, and the second fixed voltage terminal is a low voltage terminal; or, the initialization circuit includes a p-type transistor, and the second fixed voltage terminal is a high voltage terminal.

8. The pixel circuit as described in claim 1, wherein, The first control circuit includes a first transistor, and the second control circuit includes a second transistor; The gate of the first transistor is electrically connected to the first scan terminal, the first electrode of the first transistor is electrically connected to the first node, and the second electrode of the first transistor is electrically connected to the first intermediate node. The gate of the second transistor is electrically connected to the first scan terminal, the first terminal of the second transistor is electrically connected to the first intermediate node, and the second terminal of the second transistor is electrically connected to the data line.

9. The pixel circuit as described in claim 1, wherein, The third control circuit includes a third transistor; The gate of the third transistor is electrically connected to the first node, the first terminal of the third transistor is electrically connected to the first voltage terminal, and the second terminal of the third transistor is electrically connected to the first intermediate node. or, The gate and the first electrode of the third transistor are both electrically connected to the first node, and the second electrode of the third transistor is electrically connected to the first intermediate node.

10. The pixel circuit as claimed in claim 4, wherein, The fourth control circuit includes a fourth transistor, and the fifth control circuit includes a fifth transistor; The gate of the fourth transistor is electrically connected to the second scan terminal, the first terminal of the fourth transistor is electrically connected to the first node, and the second terminal of the fourth transistor is electrically connected to the second intermediate node. The gate of the fifth transistor is electrically connected to the second scan terminal, the first terminal of the fifth transistor is electrically connected to the second intermediate node, and the second terminal of the fifth transistor is electrically connected to the reference voltage terminal.

11. The pixel circuit as claimed in claim 4, wherein, The sixth control circuit includes a sixth transistor; The gate of the sixth transistor is electrically connected to the first node, the first terminal of the sixth transistor is electrically connected to the second voltage terminal, and the second terminal of the sixth transistor is electrically connected to the second intermediate node; or, The gate and the first electrode of the sixth transistor are both electrically connected to the first node, and the second electrode of the sixth transistor is electrically connected to the second intermediate node.

12. The pixel circuit according to any one of claims 1 to 11, wherein, It also includes a first energy storage circuit; the first end of the drive circuit is electrically connected to the second node, and the second end of the drive circuit is electrically connected to the third node; The first end of the first energy storage circuit is electrically connected to the first node, and the second end of the first energy storage circuit is electrically connected to the third node. The first energy storage circuit is used to store electrical energy.

13. The pixel circuit as claimed in claim 12, wherein, It also includes a light-emitting element, an initial control circuit, and a second energy storage circuit; The second node is electrically connected to the power supply voltage terminal, the third node is electrically connected to the first electrode of the light-emitting element, and the second electrode of the light-emitting element is electrically connected to the third voltage terminal; The initial control circuit is electrically connected to the third scanning terminal, the initial voltage terminal, and the third node, respectively, and is used to write the initial voltage provided by the initial voltage terminal into the third node under the control of the third scanning signal provided by the third scanning terminal; The first end of the second energy storage circuit is electrically connected to the third node, and the second end of the second energy storage circuit is electrically connected to the third voltage terminal. The second energy storage circuit is used to store electrical energy.

14. The pixel circuit as claimed in claim 12, wherein, It also includes a light-emitting element, a first light-emitting control circuit, a second light-emitting control circuit, an initial control circuit, and a second energy storage circuit; The first light-emitting control circuit is electrically connected to the first light-emitting control terminal, the power supply voltage terminal, and the second node, respectively, and is used to control the connection or disconnection between the power supply voltage terminal and the second node under the control of the first light-emitting control signal provided by the first light-emitting control terminal. The second light-emitting control circuit is electrically connected to the second light-emitting control terminal, the third node, and the first electrode of the light-emitting element, respectively, and is used to control the connection or disconnection between the third node and the first electrode of the light-emitting element under the control of the second light-emitting control signal provided by the second light-emitting control terminal; the second electrode of the light-emitting element is electrically connected to the third voltage terminal. The initial control circuit is electrically connected to the third scanning terminal, the initial voltage terminal, and the first electrode of the light-emitting element, respectively, and is used to write the initial voltage provided by the initial voltage terminal into the first electrode of the light-emitting element under the control of the third scanning signal provided by the third scanning terminal; The first end of the second energy storage circuit is electrically connected to the third node, and the second end of the second energy storage circuit is electrically connected to the first electrode of the light-emitting element. The second energy storage circuit is used to store electrical energy.

15. The pixel circuit as claimed in claim 13, wherein, The initial control circuit includes a seventh transistor, the first energy storage circuit includes a first capacitor, and the second energy storage circuit includes a second capacitor. The gate of the seventh transistor is electrically connected to the third scan terminal, the first terminal of the seventh transistor is electrically connected to the initial voltage terminal, and the second terminal of the seventh transistor is electrically connected to the third node; The first terminal of the first capacitor is electrically connected to the first node, and the second terminal of the first capacitor is electrically connected to the third node; the first terminal of the second capacitor is electrically connected to the third node, and the second terminal of the second capacitor is electrically connected to the third voltage terminal.

16. The pixel circuit as claimed in claim 14, wherein, The first light-emitting control circuit includes an eighth transistor, the second light-emitting control circuit includes a ninth transistor; the initial control circuit includes a seventh transistor, the first energy storage circuit includes a first capacitor, and the second energy storage circuit includes a second capacitor. The gate of the eighth transistor is electrically connected to the first light-emitting control terminal, the first electrode of the eighth transistor is electrically connected to the power supply voltage terminal, and the second electrode of the eighth transistor is electrically connected to the second node. The gate of the ninth transistor is electrically connected to the second light-emitting control terminal, the first electrode of the ninth transistor is electrically connected to the third node, and the second electrode of the ninth transistor is electrically connected to the first electrode of the light-emitting element. The gate of the seventh transistor is electrically connected to the third scanning terminal, the first terminal of the seventh transistor is electrically connected to the initial voltage terminal, and the second terminal of the seventh transistor is electrically connected to the first terminal of the light-emitting element. The first terminal of the first capacitor is electrically connected to the first node, and the second terminal of the first capacitor is electrically connected to the third node; The first end of the second capacitor is electrically connected to the third node, and the second end of the second capacitor is electrically connected to the first electrode of the light-emitting element.

17. A display device comprising a pixel circuit as claimed in any one of claims 1 to 16.

Images