Power supply circuit for low-power double-data-rate random-access memory, and personal computer

Abstract

The embodiments of the present application relate to the technical field of power circuits. Provided are a power supply circuit for a low-power double-data-rate random-access memory, and a personal computer. The embodiments of the present application can reduce the power consumption of a computer, alleviate the problem of heat accumulation, and increase the battery endurance. Moreover, the embodiments of the present application are conducive to the miniaturization and lightweight of computers. The power supply circuit for a low-power double-data-rate random-access memory comprises: a buck chip, which comprises a power input pin, a power output pin, a power bias pin and a feedback pin; a bootstrap capacitor, wherein a first end of the bootstrap capacitor is connected to the power bias pin, and a second end of the bootstrap capacitor is connected to the power output pin; an energy storage inductor, wherein a first end of the energy storage inductor is connected to the power output pin, and a second end thereof is connected to a power input end of at least one low-power double-data-rate random-access memory, so as to supply power to the low-power double-data-rate random-access memory; and a feedback voltage collection sub-circuit, which is used for providing a feedback voltage to the feedback pin on the basis of a voltage at the second end of the energy storage inductor.

Description

Low power double data rate random access memory power supply circuit and personal computer

[0001] The present application claims priority to the Chinese patent application No. 202410796914.7, filed on June 19, 2024, and titled "Low power double data rate random access memory power supply circuit and personal computer", the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0002] The present application relates to the technical field of power supply circuit, and in particular to a low power double data rate random access memory power supply circuit and a personal computer. BACKGROUND

[0003] In recent years, with the rapid development and rapid popularization of personal computer (PC) products, people's demand for personal computers is also slowly changing. For example, computers that are small in size and do not have internal heat problems are gradually favored by consumers. Especially in the field of portable computers (such as notebook computers), computers with high endurance time are more favored by consumers.

[0004] In the related art, in order to reduce the working temperature of the computer, solve the problem of heat accumulation caused by the heat generated by the internal devices of the computer in the working state and the inability to discharge in time, the volume and scale of the heat dissipation device are generally increased to improve the heat dissipation performance of the computer. However, this will make the volume of the computer larger and the weight heavier, which is not conducive to the miniaturization and light weight of the computer. For portable computers with batteries, the battery capacity of the computer is often increased to improve the endurance time of the computer. However, this is also not conducive to the miniaturization and light weight of the computer. SUMMARY

[0005] In order to solve the above technical problems, the present application provides a low power double data rate random access memory power supply circuit and a personal computer, which can reduce the power consumption of the computer, alleviate the heat accumulation problem, and improve the endurance time. At the same time, it is conducive to the miniaturization and light weight of the computer.

[0006] In a first aspect, the embodiments of the present application provide a low power double data rate random access memory power supply circuit, comprising:

[0007] A step-down chip, the step-down chip comprising a power input pin, a power output pin, a power bias pin and a feedback pin; the power input pin is connected to an external power supply, and the external power supply supplies power to the step-down chip;

[0008] A bootstrap capacitor, a first end of the bootstrap capacitor is connected to the power bias pin, and a second end of the bootstrap capacitor is connected to the power output pin;

[0009] The first end of the energy storage inductor is connected to the power output pin, and the second end of the energy storage inductor is connected to the power input end of at least one low-power double data rate random access memory, for supplying power to the low-power double data rate random access memory;

[0010] The feedback voltage acquisition sub-circuit is configured to provide a feedback voltage to the feedback pin according to the voltage at the second end of the energy storage inductor.

[0011] The voltage output pin is configured to output a voltage according to the feedback voltage, so as to keep the voltage at the second end of the energy storage inductor within a preset range.

[0012] Since the Buck chip internally integrates a MOS tube, it is not necessary to externally set a MOS tube to work cooperatively with the Buck chip. It can be seen that the Buck chip has high integration, which makes the board area of the LPDDR power supply circuit 10 smaller. At the same time, since the Buck chip has high integration, it is not necessary to externally set a MOS tube, which makes the cost of the LPDDR power supply circuit 10 lower. In addition, since the Buck chip has high integration, it has higher power efficiency, which can make the battery endurance time of the notebook computer 100 longer. Or under the same endurance time, the battery has a smaller size and a lighter weight, which is beneficial to reducing the size and weight of the notebook computer. Moreover, since the Buck chip has higher power efficiency, it generates less heat, so the size and scale of the heat dissipation system of the notebook computer can be reduced, which is further beneficial to reducing the size and weight of the notebook computer.

[0013] In some possible implementations, the feedback voltage acquisition sub-circuit includes a pull-up resistor and a pull-down resistor. The first end of the pull-up resistor is connected to the second end of the energy storage inductor, and the second end of the pull-up resistor is connected to the feedback pin. The first end of the pull-down resistor is connected to the feedback pin, and the second end of the pull-down resistor is grounded. Through the cooperation of the pull-up resistor and the pull-down resistor, the feedback pin can obtain a suitable feedback voltage, so that the Buck chip can correct the voltage of the power output pin.

[0014] In some possible implementations, the resistance value of the pull-up resistor is 93.1kΩ, and the resistance value of the pull-down resistor is 120kΩ. Such a setting can make the LPDDR power supply circuit output a working voltage suitable for the LPDDR.

[0015] In some possible implementations, the feedback voltage acquisition sub-circuit includes a feedback voltage filtering module configured to stabilize the voltage of the feedback pin.

[0016] In some possible implementation manners, the feedback voltage filtering module comprises a feedback voltage filtering resistor and a feedback voltage filtering capacitor, a first end of the feedback voltage filtering resistor is connected to the second end of the energy storage inductor, a second end of the feedback voltage filtering resistor is connected to a first end of the feedback voltage filtering capacitor, and a second end of the feedback voltage filtering capacitor is connected to the feedback pin. The RC filtering circuit can improve the stability of the voltage at the feedback pin and reduce voltage fluctuation.

[0017] In some possible implementation manners, the buck chip further comprises a bypass capacitor and a bypass voltage providing end, and the buck chip further comprises a bypass capacitor pin, a first end of the bypass capacitor is connected to the bypass capacitor pin and the bypass voltage providing end, and a second end of the bypass capacitor is grounded. The high-frequency noise in the front-stage power supply can be filtered out through the bypass capacitor, thereby avoiding interference of the high-frequency noise.

[0018] In some possible implementation manners, the buck chip further comprises an internal power supply filtering capacitor, and the buck chip further comprises an internal power supply pin, a first end of the internal power supply filtering capacitor is connected to the internal power supply pin, and a second end of the internal power supply filtering capacitor is grounded. The internal power supply filtering capacitor can improve the power supply quality of the internal power supply module of the buck chip and reduce power supply voltage fluctuation.

[0019] In some possible implementation manners, the buck chip further comprises a current limiting resistor, and the buck chip further comprises a power supply state feedback pin, a first end of the current limiting resistor is connected to the power supply state feedback pin, and a second end of the current limiting resistor is connected to an external controller. The buck chip sends information about the current working state of the chip to the external controller through the power supply state feedback pin, and the external controller can learn whether the buck chip is in a normal working state, thereby completing state monitoring of the buck chip. For example, when the buck chip is in an abnormal state, the buck chip can be powered off in a timely manner, thereby improving the safety of the circuit.

[0020] In some possible implementation manners, the buck chip further comprises a current limiting pin, the current limiting pin is configured to acquire a current limiting voltage signal, and the buck chip determines a maximum current value output by a power supply output pin according to the acquired current limiting voltage signal. The size of the output current can be adjusted through the power supply output pin, thereby avoiding excessively large output current. The maximum current adjustment flexibility of the circuit is improved, and the safety risk caused by excessively large output current of the buck chip is avoided, thereby improving the safety of the circuit.

[0021] In some possible implementation manners, the buck chip further comprises an enable pin, the enable pin is configured to receive an enable signal, and the buck chip starts running according to the enable signal. The external circuit can provide the enable signal to the buck chip when the computer is powered on. The buck chip 11 starts running according to the enable signal.

[0022] In some possible implementation manners, the input filter capacitor and the output filter capacitor are further included, and the buck chip further includes a ground pin;

[0023] A first end of the input filter capacitor is connected to the power input pin, and a second end of the input filter capacitor is grounded;

[0024] A first end of the output filter capacitor is connected to the power output pin, and a second end of the output filter capacitor is grounded;

[0025] The ground pin is grounded.

[0026] The input filter capacitor can improve the power quality of the input buck chip and reduce voltage fluctuation. The output filter capacitor can reduce the output voltage fluctuation of the LPDDR power supply circuit and improve the power supply quality of the LPDDR power supply circuit.

[0027] In a second aspect, the embodiments of the present application further provide a personal computer, including the low power double data rate random access memory power supply circuit. The personal computer has the beneficial effects corresponding to the low power double data rate random access memory power supply circuit. BRIEF DESCRIPTION OF DRAWINGS

[0028] FIG. 1 is a structural schematic diagram of a notebook computer provided by the embodiments of the present application;

[0029] FIG. 2 is a structural schematic diagram of an LPDDR power supply circuit provided by the embodiments of the present application;

[0030] FIG. 3 is a structural schematic diagram of another LPDDR power supply circuit provided by the embodiments of the present application;

[0031] FIG. 4 is a structural schematic diagram of still another LPDDR power supply circuit provided by the embodiments of the present application;

[0032] FIG. 5 is a structural schematic diagram of still another LPDDR power supply circuit provided by the embodiments of the present application;

[0033] FIG. 6 is a structural schematic diagram of still another LPDDR power supply circuit provided by the embodiments of the present application;

[0034] FIG. 7 is a structural schematic diagram of still another LPDDR power supply circuit provided by the embodiments of the present application;

[0035] FIG. 8 is a structural schematic diagram of still another LPDDR power supply circuit provided by the embodiments of the present application. DETAILED DESCRIPTION

[0036] With reference to the drawings and the embodiments of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described. Obviously, the described embodiments are some of the embodiments of the present application, but not all of them. Based on the embodiments of the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts are within the scope of the present application.

[0037] The term "and / or" used in the present application is only used to describe the association relationship of the associated objects, and means that there can be three relationships, for example, A and / or B can mean that A exists alone, A and B exist simultaneously, and B exists alone.

[0038] The terms "upper", "lower", "left", "right", and the like used in the present application are only used to clearly explain the embodiments, so as to describe a possible arrangement or arrangement form of each component. It is not a limitation on the relationship between the components or the setting direction.

[0039] The terms "first" and "second" and the like in the specification and claims of the embodiments of the present application are used to distinguish different objects, and are not used to describe the specific order of the objects. For example, the first target object and the second target object are used to distinguish different target objects, and are not used to describe the specific order of the target objects.

[0040] In the embodiments of the present application, the words such as "exemplary" or "for example" are used to mean by way of example, illustration or description. Any embodiment or design scheme described as "exemplary" or "for example" in the embodiments of the present application should not be interpreted as more preferred or more advantageous than other embodiments or design schemes. Rather, the words such as "exemplary" or "for example" are intended to present the relevant concept in a specific manner.

[0041] In the description of the embodiments of the present application, unless otherwise specified, the meaning of "a plurality of" is two or more. For example, a plurality of processing units means two or more processing units; a plurality of systems means two or more systems.

[0042] The embodiment of the present application provides a personal computer, which can be a notebook computer, a desktop computer, a notebook computer, a small notebook computer, a mini host and various computer products. FIG. 1 is a structural schematic diagram of a notebook computer provided by the embodiment of the present application, and FIG. 1 is referred to. Taking the notebook computer 100 as an example, the notebook computer 100 can include a shell 101, a display panel 102, an input device 103, a mainboard (not shown in the figure) and a battery (not shown in the figure) and the like. The shell 101 can be divided into an A surface 101A, a B surface 101B, a C surface 101C and a D surface 101D. The B surface 101B is provided with a window, and the window of the B surface 101B is used to expose one side of a display panel 102 display picture, and the A surface 101A and the B surface 101B form a first cavity, and the first cavity is used to accommodate the display panel 102. The C surface 101C is provided with a window, and the window of the C surface 101C is used to expose the input device 103, and is convenient for a user to input a control instruction. The input device 103 can be set according to actual needs, for example, including a keyboard 1031 and a touchpad 1032, or a keyboard 1031 and a trackball (not shown in the figure) and the like. The C surface 101C and the D surface 101D form a second cavity, and the second cavity is used to accommodate the input device 103, the mainboard and the battery.

[0043] The material of the shell can include engineering plastics, magnesium-aluminum alloy or carbon fiber composite material and the like.

[0044] The display panel 102 can be an LCD panel, an OLED display panel, an LED display panel and the like, for example, wherein the LED display panel includes a Micro-LED display panel, a Mini-LED display panel and the like. The embodiment of the present application does not limit the type of the display panel 102.

[0045] The mainboard can be loaded with a central processing unit (CPU), a memory, a sound card and a display card and the like through welding or plug-in and the like, and is connected with a hard disk and a battery.

[0046] The memory can be LPDDR (low power double data rate random access memory), which has better power consumption control than DDR (double data rate random access memory), can prolong the battery life and increase the endurance time. The working voltage is lower, the required current is smaller, and the power supply capacity requirement of the power supply for the power supply is lower. Therefore, it has the advantages of low power consumption and less heat generation, and reduces the heat dissipation pressure of the computer.

[0047] In order to supply power to the LPDDR, the motherboard is further provided with an LPDDR power supply circuit 10. FIG. 2 is a structural schematic diagram of an LPDDR power supply circuit according to an embodiment of the present application. The LPDDR power supply circuit 10 comprises a Buck chip 11, and a bootstrap capacitor C BST , an energy storage inductor L and a feedback voltage acquisition sub-circuit 12 connected to the Buck chip 11. The LPDDR power supply circuit 10 will be described in detail below.

[0048] The Buck chip 11 comprises a power input pin VIN, which is used to connect an external power supply on the motherboard, so that the LPDDR power supply circuit 10 obtains power.

[0049] The Buck chip 11 comprises a power output pin SW, which can be connected to a first end of the energy storage inductor L, and a second end of the energy storage inductor L can be connected to a power input end of at least one LPDDR chip, for supplying the LPDDR chip with voltage and current required for operation. Optionally, the second end of the energy storage inductor L can be connected to power input ends of at least two LPDDR chips.

[0050] The Buck chip 11 comprises a power bias pin BST, and the Buck chip 11 internally comprises a first MOS tube connected to the power input pin VIN, and a second MOS tube connected to a ground end. The first end of the bootstrap capacitor C BST is connected to the power bias pin BST, and the second end of the bootstrap capacitor C BST is connected to the power output pin SW. At the beginning of a first time sequence, components in the Buck chip 11 control the second MOS tube to be turned on, at which time the second end of the bootstrap capacitor C BST is grounded, and the Buck chip 11 charges the bootstrap capacitor C BST through the first end of the bootstrap capacitor C BST , at which time the voltage difference between the two ends of the bootstrap capacitor C BST is X volts (V). Then, at the beginning of a second time sequence, components in the Buck chip 11 control the second MOS tube to be turned off, and at this time the voltage of the power output pin SW rises to Y volts. Due to the fact that the voltage difference between the two ends of the capacitor cannot be abruptly changed, under the action of the bootstrap capacitor C BST , the voltage of the power bias pin BST reaches X+Y volts. Such a voltage can make the first MOS tube satisfy Vgs (gate-source voltage) > power input pin VIN voltage + threshold voltage Vgs(th), and the first MOS tube is turned on.

[0051] During the second timing period, the first MOSFET is turned on and the second MOSFET is turned off. The voltage output from the power output pin SW is the same as the voltage output from the power input pin VIN. Due to the characteristic that the current flowing through an inductor cannot change abruptly, the voltage and current at the power output pin SW are slightly higher than in the previous timing period, and the energy storage inductor L charges. During the first timing period, the first MOSFET is turned off and the second MOSFET is turned on. The voltage output from the power output pin SW is 0. Due to the characteristic that the current flowing through an inductor cannot change abruptly, the voltage and current at the power output pin SW are slightly lower than in the previous timing period, and the energy storage inductor L discharges. The first and second timing periods cycle repeatedly to achieve the voltage reduction effect.

[0052] Buck chip 11 includes a feedback pin FB, and LPDDR power supply circuit 10 may further include a feedback voltage acquisition sub-circuit 12. The feedback voltage acquisition sub-circuit 12 is used to provide a feedback voltage to the feedback pin FB based on the output voltage of LPDDR power supply circuit 10, thereby enabling Buck chip 11 to correct the voltage of power output pin SW. Any circuit capable of performing the above function can serve as the feedback voltage acquisition sub-circuit 12, and this embodiment of the invention does not limit the specific configuration of the feedback voltage acquisition sub-circuit 12. Figure 3 is a schematic diagram of another LPDDR power supply circuit provided in this application embodiment. Referring to Figure 3, for example, the feedback voltage acquisition sub-circuit 12 may include a pull-up resistor R. H and pull-down resistor R L Pull-up resistor R H The first terminal is connected to the second terminal of the energy storage inductor L, and the pull-up resistor R H The second terminal is connected to the feedback pin FB. Pull-down resistor R L The first terminal is connected to the feedback pin FB, and the pull-down resistor R L The second terminal is grounded. Pull-up resistor R H and pull-down resistor R L The resistance ratio can be determined according to actual needs. For example, the pull-up resistor R H The resistance value can be 93.1kΩ, and the pull-down resistor R L The resistance can be 120kΩ. This is achieved through a pull-up resistor R. H and pull-down resistor R L Together, they can reduce the voltage at the second terminal of the energy storage inductor L by the required ratio and provide it to the feedback pin FB. The feedback pin FB can then sample the voltage. Internally, the Buck chip 11 can adjust whether the power output pin SW outputs voltage based on the level of the sampled voltage, thereby keeping the voltage at the second terminal of the energy storage inductor L stable near a preset value, i.e., within a preset range. The preset value can be determined according to actual needs.

[0053] Figure 4 is a schematic diagram of another LPDDR power supply circuit provided in an embodiment of this application. Referring to Figure 4, in some other embodiments, the feedback voltage acquisition sub-circuit 12 may further include a feedback voltage filtering module 121. The feedback voltage filtering module is used to filter voltage jitter and interference at the feedback pin FB, thereby stabilizing the voltage at the feedback pin FB and facilitating the acquisition of the feedback voltage. Any circuit capable of performing the above functions can be used as a feedback voltage filtering module. This embodiment of the invention does not limit the specific configuration of the feedback voltage filtering module. Figure 5 is a schematic diagram of yet another LPDDR power supply circuit provided in an embodiment of this application. Referring to Figure 5, for example, the feedback voltage filtering module may include a feedback voltage filtering resistor R1 and a feedback voltage filtering capacitor C1. The first end of the feedback voltage filtering resistor R1 is connected to the second end of the energy storage inductor L, the second end of the feedback voltage filtering resistor R1 is connected to the first end of the feedback voltage filtering capacitor C1, and the second end of the feedback voltage filtering capacitor C1 is connected to the feedback pin FB. The feedback voltage filtering resistor R1 and the feedback voltage filtering capacitor C1 constitute an RC filter circuit, thereby improving the stability of the voltage at the feedback pin FB and reducing voltage fluctuations.

[0054] Figure 6 is a schematic diagram of another LPDDR power supply circuit provided in an embodiment of this application. Referring to Figure 6, the Buck chip 11 may further include a bypass capacitor pin BYP, and the LPDDR power supply circuit 10 may further include a bypass capacitor C. BYP and bypass voltage supply terminal V BYP Bypass capacitor C BYP The first terminal is connected to the bypass capacitor pin BYP and the bypass voltage supply terminal V. BYP Bypass capacitor C BYP The second terminal is grounded. The bypass voltage supply terminal V... BYP It can be a bypass capacitor C BYP Power supply, bypass voltage supply terminal V BYP The voltage can be determined according to actual needs, for example, it can be 3.3 volts or 5 volts. This is achieved through the bypass capacitor C. BYP It can filter out high-frequency noise in the pre-amplifier power supply and avoid high-frequency noise interference.

[0055] Figure 7 is a schematic diagram of another LPDDR power supply circuit provided in an embodiment of this application. Referring to Figure 7, the Buck chip 11 may further include an internal power supply pin VCC, and the LPDDR power supply circuit 10 may further include an internal power supply filter capacitor C. VCC Internal power supply filter capacitor C VCC The first terminal is connected to the internal power supply pin VCC, and the internal power supply filter capacitor C. VCC The second terminal is grounded. The Buck chip 11 has an internal power module to power other modules within it, via an internal power filter capacitor C.VCC The filtering effect can improve the power supply quality of the internal power module of Buck chip 11 and reduce power supply voltage fluctuations.

[0056] Figure 8 is a schematic diagram of another LPDDR power supply circuit provided in an embodiment of this application. Referring to Figure 8, the Buck chip 11 may further include a power status feedback pin PG, and the LPDDR power supply circuit 10 may further include a current-limiting resistor R. PG Current-limiting resistor R PG The first terminal is connected to the power status feedback pin PG, and the current limiting resistor R PG The second end is connected to an external controller. The Buck chip 11 sends information about its current operating status to the external controller through the power status feedback pin PG. The external controller can then determine whether the Buck chip 11 is in normal working condition, thereby completing the status monitoring of the Buck chip 11.

[0057] Referring again to Figure 8, the Buck chip 11 may also include a current limiting pin ILMIT. The ILMIT pin acquires a current limiting voltage signal, and the Buck chip 11 limits the maximum output current of the power output pin SW based on this signal. The voltage connected to the ILMIT pin can be determined according to actual needs, thereby determining the maximum output current of the power output pin SW.

[0058] Referring again to Figure 8, the Buck chip 11 may also include an enable pin EN, which is connected to an external circuit. The external circuit can provide an enable signal to the Buck chip 11 when the computer is powered on. The Buck chip 11 then starts operating based on the enable signal.

[0059] Referring again to Figure 8, Buck chip 11 may also include a ground pin GND, which is grounded to enable grounding of the internal circuitry of Buck chip 11.

[0060] Referring again to Figure 8, the LPDDR power supply circuit 10 may also include an input filter capacitor C. IN Input filter capacitor C IN The first terminal is connected to the power input pin VIN, and the input filter capacitor C IN The second terminal is grounded. This is achieved through the input filter capacitor C. IN It can regulate and filter the voltage output from the pre-amplifier power supply, thereby improving power quality.

[0061] Referring again to Figure 8, the LPDDR power supply circuit 10 may also include an output filter capacitor C. OUT Output filter capacitor C OUT The first terminal is connected to the power output pin SW, and the output filter capacitor COUT The second terminal is grounded. This is achieved through the output filter capacitor C. OUT The voltage output from the second terminal of the energy storage inductor L can be regulated and filtered to improve power supply quality.

[0062] The input filter capacitor C mentioned above IN Output filter capacitor C OUT Internal power supply filter capacitor C VCC Bypass capacitor C BYP Bootstrap capacitor C BST The capacitance value of the feedback voltage filter capacitor C1, the inductance value of the energy storage inductor L, and the current limiting resistor R. PG Feedback voltage filter resistor R1, pull-up resistor R H and pull-down resistor R L The resistance values ​​can be determined according to actual needs. The grounding mentioned above can be connected to the neutral point in the computer power supply circuit, which can provide a reference "0" voltage in the circuit. The selection of Buck chip 11 can be determined according to actual needs; for example, an 8A Buck chip capable of providing 8 amps (A) of current can be selected. Since the Buck chip integrates a MOSFET internally, there is no need to set an external MOSFET for cooperative operation, demonstrating the high integration of the Buck chip. This results in a smaller board area for the LPDDR power supply circuit 10. At the same time, because the Buck chip has high integration and does not require an external MOSFET, the cost of the LPDDR power supply circuit 10 is lower. In addition, because the Buck chip has high integration, its power efficiency is high, which can extend the battery life of the laptop 100. Alternatively, with the same battery life, the battery can be smaller and lighter, which is beneficial for reducing the size and weight of the laptop. Furthermore, because the Buck chip has high power efficiency, it generates less heat, thus reducing the size and scale of the laptop's cooling system, which is beneficial for reducing the size and weight of the laptop.

[0063] The embodiments of this application have been described above with reference to the accompanying drawings. However, this application is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of this application without departing from the spirit and scope of the claims, and all of these forms are within the protection scope of this application.

Claims

1. A low-power double data rate random access memory power supply circuit, characterized in that, include: A step-down chip, comprising a power input pin, a power output pin, a power bias pin, and a feedback pin; the power input pin is connected to an external power supply, which supplies power to the step-down chip. A bootstrap capacitor, wherein the first end of the bootstrap capacitor is connected to the power supply bias pin, and the second end of the bootstrap capacitor is connected to the power supply output pin; An energy storage inductor, wherein a first end of the energy storage inductor is connected to the power output pin, and a second end of the energy storage inductor is connected to the power input terminal of at least one of the low-power double data rate random access memories, for supplying power to the low-power double data rate random access memories; The feedback voltage acquisition sub-circuit is used to provide a feedback voltage to the feedback pin based on the voltage at the second terminal of the energy storage inductor. The step-down chip is used to adjust whether the power output pin outputs voltage according to the feedback voltage, thereby keeping the voltage at the second terminal of the energy storage inductor within a preset range.

2. The low-power double data rate random access memory power supply circuit according to claim 1, characterized in that, The feedback voltage acquisition sub-circuit includes a pull-up resistor and a pull-down resistor; the first end of the pull-up resistor is connected to the second end of the energy storage inductor, and the second end of the pull-up resistor is connected to the feedback pin; the first end of the pull-down resistor is connected to the feedback pin, and the second end of the pull-down resistor is grounded.

3. The low-power double data rate random access memory power supply circuit according to claim 2, characterized in that, The pull-up resistor has a resistance of 93.1kΩ, and the pull-down resistor has a resistance of 120kΩ.

4. The low-power double data rate random access memory power supply circuit according to claim 1, characterized in that, The feedback voltage acquisition sub-circuit includes a feedback voltage filtering module, which is used to stabilize the voltage of the feedback pin.

5. The low-power double data rate random access memory power supply circuit according to claim 4, characterized in that, The feedback voltage filtering module includes a feedback voltage filtering resistor and a feedback voltage filtering capacitor. The first end of the feedback voltage filtering resistor is connected to the second end of the energy storage inductor, the second end of the feedback voltage filtering resistor is connected to the first end of the feedback voltage filtering capacitor, and the second end of the feedback voltage filtering capacitor is connected to the feedback pin.

6. The low-power double data rate random access memory power supply circuit according to claim 1, characterized in that, It also includes a bypass capacitor and a bypass voltage supply terminal. The buck chip also includes a bypass capacitor pin. The first end of the bypass capacitor is connected to the bypass capacitor pin and the bypass voltage supply terminal, and the second end of the bypass capacitor is grounded.

7. The low-power double data rate random access memory power supply circuit according to claim 1, characterized in that, It also includes an internal power supply filter capacitor. The step-down chip also includes an internal power supply pin. The first end of the internal power supply filter capacitor is connected to the internal power supply pin, and the second end of the internal power supply filter capacitor is grounded.

8. The low-power double data rate random access memory power supply circuit according to claim 1, characterized in that, It also includes a current-limiting resistor, and the buck chip also includes a power status feedback pin. The first end of the current-limiting resistor is connected to the power status feedback pin, and the second end of the current-limiting resistor is connected to an external controller.

9. The low-power double data rate random access memory power supply circuit according to claim 1, characterized in that, The buck chip also includes a current limiting pin, which is used to acquire a current limiting voltage signal. The buck chip determines the maximum current value output by the power output pin based on the acquired current limiting voltage signal.

10. The low-power double data rate random access memory power supply circuit according to claim 1, characterized in that, The buck chip also includes an enable pin, which is used to receive an enable signal; the buck chip starts operating according to the enable signal.

11. The low-power double data rate random access memory power supply circuit according to claim 1, characterized in that, It also includes an input filter capacitor and an output filter capacitor, and the step-down chip also includes a ground pin; The first end of the input filter capacitor is connected to the power input pin, and the second end of the input filter capacitor is grounded. The first end of the output filter capacitor is connected to the power output pin, and the second end of the output filter capacitor is grounded. The grounding pin is grounded.

12. A personal computer, characterized in that, The low-power double data rate random access memory power supply circuit includes any one of claims 1-11.

Images