Semiconductor device and manufacturing method therefor, and semiconductor device array and lidar

Abstract

Disclosed are a semiconductor device and a manufacturing method therefor, and a semiconductor device array and a LiDAR. The semiconductor device comprises a substrate, a photoelectric conversion structure, a resistive layer, a first metal structure and a second metal structure. The photoelectric conversion structure is formed in the substrate. The resistive layer, the first metal structure and the second metal structure are formed on the substrate. The first metal structure is electrically connected to a first end of the resistive layer. The second metal structure is electrically connected to a second end of the resistive layer. The first metal structure is further electrically connected to the photoelectric conversion structure. The second metal structure is electrically connected to the photoelectric conversion structure by means of the resistive layer and the first metal structure. There is a first parasitic capacitance between the first metal structure and the second metal structure. The semiconductor device can be used for a detector of a LiDAR, and the structure thereof can improve the waveform of an echo signal, such that a rising edge of the echo signal is steeper, thereby improving the accuracy of a detection result of the LiDAR.

Description

Semiconductor device and manufacturing method thereof, semiconductor device array and laser radar

[0001] The present disclosure claims priority to the Chinese patent application No. 202410799371.4, filed on June 19, 2024, and entitled "Semiconductor device and manufacturing method thereof, semiconductor device array and laser radar", the entire content of which is incorporated herein by reference. TECHNICAL FIELD

[0002] The present disclosure relates to the field of optical detection technology, and in particular to a semiconductor device and manufacturing method thereof, a semiconductor device array and a laser radar. BACKGROUND

[0003] In the field of optical detection technology, laser is applied to object detection due to its monochromaticity and good directivity. For example, laser radar is the abbreviation of light detection and ranging (LiDAR) system, which uses laser as medium for object detection. Laser radar can determine the distance of an object by using the time of flight (TOF) of laser in the process of object detection. For example, the TOF can be determined by the difference between the receiving time and the emitting time of laser. Therefore, how to accurately determine the receiving time of laser is particularly important for the detection accuracy of laser radar. SUMMARY

[0004] Embodiments of the present disclosure provide a semiconductor device and manufacturing method thereof, a semiconductor device array and a laser radar to improve the detection accuracy of the laser radar.

[0005] In a first aspect, a semiconductor device is provided, comprising a substrate, a photoelectric conversion structure, a resistance layer, a first metal structure, and a second metal structure. The photoelectric conversion structure is formed in the substrate. The resistance layer is formed on the substrate. The first metal structure and the second metal structure are formed on the substrate. The first metal structure is electrically connected to a first end of the resistance layer. The second metal structure is electrically connected to a second end of the resistance layer. The first metal structure is also electrically connected to the photoelectric conversion structure, and the second metal structure is electrically connected to the photoelectric conversion structure through the resistance layer and the first metal structure. The first metal structure and the second metal structure have a first parasitic capacitance therebetween.

[0006] Optionally, the first metal structure is formed in a first metal layer. The second metal structure is formed in a second metal layer.

[0007] Optionally, the second metal structure has an overlapping area with the first metal structure in the vertical projection of the first metal layer.

[0008] Optionally, the vertical distance between the second metal structure and the first metal structure is greater than or equal to 0.1 microns and less than or equal to 2 microns.

[0009] Optionally, the area of the overlapping region is greater than or equal to 2.5 square microns and less than or equal to 50 square microns.

[0010] Optionally, the overlapping region is located at a middle position of the surface of the first metal structure.

[0011] Optionally, a vertical projection of the first metal structure towards the substrate covers a surface of the photoelectric conversion structure.

[0012] Optionally, the first parasitic capacitance is greater than or equal to a first threshold value. The first threshold value is determined based on a junction capacitance of the photoelectric conversion structure.

[0013] Optionally, the first parasitic capacitance is less than or equal to 10 fF.

[0014] Optionally, the semiconductor device further comprises a third metal structure. The third metal structure is formed on the substrate. The second metal structure is configured to electrically connect a first doped region of the photoelectric conversion structure. The third metal structure is configured to electrically connect a second doped region of the photoelectric conversion structure. Wherein, the first doped region comprises an N-type doped region, and the second doped region comprises a P-type doped region. Or the first doped region comprises a P-type doped region, and the second doped region comprises an N-type doped region.

[0015] Optionally, the second metal structure and the third metal structure are formed in a second metal layer.

[0016] Optionally, a vertical projection of the third metal structure on the first metal layer is spaced from the first metal structure by a first distance.

[0017] Optionally, a vertical projection of the third metal structure on the first metal layer is spaced from the first metal structure by a first distance.

[0018] Optionally, the semiconductor device further comprises a fourth metal structure and a fifth metal structure. The fourth metal structure is configured to electrically connect the second metal structure and the second end of the resistance layer. The fifth metal structure is configured to electrically connect the third metal structure and the second doped region of the photoelectric conversion structure. Wherein, the fourth metal structure and the fifth metal structure are formed in the first metal layer with the first metal structure.

[0019] Optionally, the semiconductor device further comprises a sixth metal structure. The sixth metal structure is configured to electrically connect the second doped region of the photoelectric conversion structure. Wherein, the sixth metal structure is formed in a second metal layer with the third metal structure and is parallel to the third metal structure. Wherein, a vertical projection of the sixth metal structure on the metal layer where the first metal structure is located is spaced from the first metal structure by a third distance.

[0020] Optionally, the sixth metal structure and the third metal structure are spaced apart from the first metal structure by a distance equal to a vertical projection of the first metal layer.

[0021] In a second aspect, there is provided an array of semiconductor devices, comprising: a plurality of semiconductor devices as defined in the first aspect.

[0022] Optionally, the plurality of semiconductor devices comprises: a first semiconductor device as defined in the first aspect and a second semiconductor device as defined in the first aspect; wherein the first semiconductor device and the second semiconductor device are arranged adjacently, and the sixth metal structure of the first semiconductor device and the third metal structure of the second semiconductor device are shared.

[0023] In a third aspect, there is provided a light receiver, comprising at least one semiconductor device as defined in the first aspect.

[0024] In a fourth aspect, there is provided a lidar, comprising: a light emitter configured to emit a laser; a light receiver as defined in the third aspect configured to receive a return of the laser and convert the return into an electrical signal; and a processing circuit configured to process the electrical signal.

[0025] In a fifth aspect, there is provided a vehicle, comprising a lidar as defined in the fourth aspect, and a connecting device configured to mount the lidar on the vehicle. The vehicle may, for example, comprise a vehicle, a ship, an aircraft, a robot, or a surveying device.

[0026] In a sixth aspect, there is provided a method of manufacturing a semiconductor device, comprising: forming a photoelectric conversion structure in a substrate; forming a dielectric layer on the substrate, and forming a resistive layer and a metal layer in the dielectric layer, the resistive layer and the metal layer being electrically connected through an interlayer via; forming a first conductive structure and a second conductive structure on the dielectric layer, the first conductive structure being electrically connected to the metal layer through an interlayer via, and being electrically connected to a P-type doped region through the metal layer and the resistive layer, the second conductive structure being electrically connected to the metal layer through an interlayer via, and being electrically connected to an N-type doped region through the metal layer; and the first conductive structure and the metal layer having an overlapping region in a first direction. BRIEF DESCRIPTION OF DRAWINGS

[0027] The drawings used in the following description are for illustrative purposes only and are not intended to limit the scope of the disclosure in any way.

[0028] FIG. 1 shows a structural example diagram of a lidar, consistent with some embodiments of the present disclosure;

[0029] FIG. 2 shows waveform example diagrams of two return signals, consistent with some embodiments of the present disclosure;

[0030] FIG. 3 shows a structural example diagram of a semiconductor device, consistent with some embodiments of the present disclosure;

[0031] FIG. 4 shows an equivalent circuit diagram of an example of a semiconductor device, consistent with some embodiments of the present disclosure;

[0032] FIG. 5 shows an example layout of a semiconductor device, consistent with some embodiments of the present disclosure;

[0033] FIG. 6 shows an example layout of another semiconductor device, consistent with some embodiments of the present disclosure;

[0034] FIG. 7 shows a structural diagram of another semiconductor device, consistent with some embodiments of the present disclosure;

[0035] FIG. 8 shows an equivalent circuit diagram of an example of an array of semiconductor devices, consistent with some embodiments of the present disclosure;

[0036] FIGS. 9-12 show example layouts of arrays of semiconductor devices, consistent with some embodiments of the present disclosure;

[0037] FIG. 13 shows an example of an output waveform of the array of semiconductor devices shown in FIG. 9, consistent with some embodiments of the present disclosure;

[0038] FIG. 14 shows an example of an output waveform of the array of semiconductor devices shown in FIG. 12, consistent with some embodiments of the present disclosure;

[0039] FIG. 15 shows an example layout of a semiconductor device, consistent with some embodiments of the present disclosure;

[0040] FIGS. 16-21 show process diagrams of a method of manufacturing a semiconductor device, consistent with some embodiments of the present disclosure. DETAILED DESCRIPTION

[0041] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, specific embodiments of the present disclosure will be described below with reference to the drawings. The drawings described below are only some embodiments of the present disclosure, and those skilled in the art can determine other drawings and other embodiments according to these drawings without any creative effort, and any adjustment and improvement made without departing from the concept of the present disclosure shall fall within the protection scope of the present disclosure.

[0042] In order to make the drawings simple, each drawing only schematically represents the part related to the corresponding embodiment, and does not represent the actual structure of the product. In addition, in order to make the drawings simple and easy to understand, only some structures or components are schematically shown, and there can be more or less similar structures or components.

[0043] In the embodiments shown in the drawings, the indications of directions (such as up, down, left, right, front, and back, etc.) are not absolute but relative when describing each structure, and are not used to limit the direction of the actual use of the product.

[0044] In the embodiments of the present disclosure, the connection includes direct connection or indirect connection, which can be directly connected through a medium (for example, a wire, a trace, etc.), or can be indirectly connected through other elements, or can be internally connected.

[0045] With the development of optical detection technology, lidar is increasingly widely used. For example, lidar can be applied to intelligent driving, unmanned aerial vehicles, robot identification, geographic mapping, or environmental monitoring, etc. Intelligent driving can also be referred to as autonomous driving or assisted driving, including any level of autonomous driving, such as L1-L5 or any other level of autonomous driving.

[0046] In applications, the lidar can be installed on a vehicle through a connecting device to provide detection data for the vehicle, so that the vehicle uses the detection data to realize analysis, decision-making, or control, etc. The vehicle includes a vehicle, a ship, an aircraft (for example, a flying vehicle or a drone, etc.), a robot (for example, an industrial robot or a household robot, etc.), a mapping device, etc. For example, in an intelligent driving scenario, the vehicle includes a vehicle, and the lidar is installed on the vehicle. As the vehicle travels, the lidar can detect objects around the vehicle to determine detection data (for example, point cloud data) and provide the detection data to the vehicle, so that the vehicle makes decisions or controls according to the detection data.

[0047] FIG. 1 shows a structural example of a lidar consistent with some embodiments of the present disclosure. Referring to FIG. 1, the lidar 100 includes a laser emission system 110, a laser receiving system 120, and a control and processing system 130. Optionally, the lidar 100 further includes a scanning system 140, for example, a mechanical lidar or a semi-solid lidar can further include the scanning system 140. The scanning system 140 can include a rotating platform, a rotating mirror, a swing mirror, a vibrating mirror, or other devices that can make the laser shoot in different directions in the environment, etc.

[0048] The laser emission system 110 can be used to emit laser. After the laser meets the object 10, the laser is reflected by the surface of the object 10, and the reflected light back to the lidar 100 is called a return wave. The laser receiving system 120 can receive the return wave reflected back and convert the return wave into an electrical signal. After the electrical signal is processed by a pre-processing circuit, the return wave data can be obtained. The return wave data can be provided to the control and processing system 130. The control and processing system 130 can process the return wave data to obtain information of the object 10, for example, distance, position, or speed information of the object 10, and again, for example, three-dimensional structure information of the object.

[0049] The laser emission system 110 mainly includes a driving circuit, a laser, and an emission optical element. The laser can emit laser under the driving of the driving circuit. The laser passes through the emission optical element and is emitted. The laser includes, for example, a semiconductor laser, a fiber laser, or other types of lasers. The semiconductor laser includes, for example, a laser emission circuit, a vertical cavity surface emitting laser (VCSEL), an edge emitting laser (EEL), a distributed feedback laser (DFB), or the like. The above is only an example, and the embodiments of the present disclosure do not limit the type of laser.

[0050] The laser receiving system 120 includes a receiving optical element and a detector. The receiving optical element can collect the echo reflected by the object and converge it on the light-sensitive surface of the detector. The detector can convert the optical signal into an electrical signal by using the photoelectric effect. The detector includes, for example, a photoelectric detection circuit, a PIN photo diode (PIN PD), an avalanche photo diode (APD), a single photon avalanche diode (SPAD), a silicon photomultiplier (SiPM), or the like. The above is only an example, and the embodiments of the present disclosure do not limit the type of detector.

[0051] The emission optical element is on the emission path of the laser, and is used to shape the laser emitted by the laser and adjust the emission path of the laser. The receiving optical element is on the receiving path of the laser, and is used to collect the echo reflected by the object 10 and converge the echo on the light-sensitive surface of the detector. The emission optical element and the receiving optical element can be independent of each other, partially multiplexed, or fully multiplexed. For example, the emission optical element and the receiving optical element can include or not include a common optical element. For another example, the emission optical element or the receiving optical element only includes a common optical element. For example, the emission optical element includes one or more optical elements such as an emission lens, a light homogenizer, a beam splitter, and the like. For example, the receiving optical element includes one or more optical elements such as a receiving lens, a filter, and the like.

[0052] The preprocessing can be analog front-end processing, for example, one or more of amplification, filtering, digitization, etc. The preprocessing circuit can be an analog front-end circuit, for example, one or more of an amplification circuit, a filtering circuit, a digitization circuit, etc. The amplification circuit, for example, includes an amplifier for amplifying the electrical signal converted by the detector, which can improve the signal-to-noise ratio. The filtering circuit, for example, includes a filter for filtering out noise or interference. The digitization circuit, for example, includes one or more of an analog-to-digital converter (ADC) or a time-to-digital converter (TDC), etc. For example, the ADC converts the analog electrical signal into a digital signal representing the waveform of the echo by periodically sampling the output signal of the detector, obtaining echo data. For another example, the electrical signal converted by the detector can be converted (e.g., converted into a voltage and compared with a reference voltage to generate a threshold-crossing signal) and provided to the TDC, which measures the time of arrival of the echo based on the received electrical signal, obtaining echo data. The echo data can include data representing at least one of the time of the echo or the intensity of the echo.

[0053] The control and processing system 130, for example, includes a processing circuit and a light source control circuit. The processing circuit is configured to process the echo data to obtain information of the object. In some embodiments, the processing circuit can include one or more processors. The processor, for example, includes one or more of the following categories: an application specific integrated circuit (ASIC), a programmable logic device (PLD) implemented hardware circuit, a micro control unit (MCU), or a digital signal processor (DSP), a central processing unit (CPU), etc. The PLD implemented hardware circuit, for example, includes a field programmable gate array (FPGA), etc. The light source control circuit is configured to send control signaling to the driving circuit to control the driving circuit to drive the laser to emit light, realizing the emission of the laser. The light source control circuit and the processing circuit can be integrated together, for example, integrated as a master control chip of the lidar; or the light source control circuit and the processing circuit can be independent of each other, for example, arranged as independent chips, and the light source control circuit and the processing circuit can be arranged on the same circuit board or different circuit boards.

[0054] In some embodiments, the lidar 100 comprises a scanning system 140. The control and processing system 130 can further comprise a scanning control circuit for controlling the scanning system 140. The scanning control circuit can be integrated with one or all of the light source control circuit and the information processing circuit, for example, the scanning control circuit, the light source control circuit and the information processing circuit are integrated into a master control chip of the lidar; or the scanning control circuit, the light source control circuit and the information processing circuit can be independent of each other. In some embodiments, the control and processing system 130 can be implemented in the form of a system on chip (SOC) or an ASIC.

[0055] The lidar can utilize the TOF of the laser to determine the distance of the object during detection, and the TOF of the laser is determined by the difference between the emission time and the reception time of the laser. For example, referring to formula (1):

[0056] Wherein d represents the distance of the laser to the object, T1 represents the emission time, T2 represents the reception time, and c is the speed of light.

[0057] The reception time of the laser can be determined by detecting the pulse time of the echo signal. However, in actual application, the echo signal is a non-ideal pulse signal with a certain pulse width and rising and falling time. The pulse width of the echo signal can last for several nanoseconds or even longer, resulting in errors in the detection result, for example, which can cause a deviation of centimeters or even meters in the detected distance compared to the actual distance.

[0058] FIG. 2 shows waveform diagrams of two echo signals consistent with some embodiments of the present disclosure. Referring to FIG. 2, the pulse time of the echo signal is, for example, the time when the intensity of the echo signal reaches or exceeds the effective threshold. For example, the echo signal A reaches or exceeds the effective threshold at time Ta, and the pulse time of the echo signal A is Ta. The echo signal B reaches or exceeds the effective threshold at time Tb, and the pulse time of the echo signal B is Tb. The waveform of the echo signal has an impact on the reception time of the laser, and further affects the accuracy of the detected distance. For example, the rising edge of the waveform of the echo signal A is steeper, and can reach the effective threshold faster, while the waveform of the echo signal B is relatively flat, and it takes relatively long time to reach the effective threshold. For example, for the same laser emission time, the pulse times of the echo signal A and the echo signal B differ by a time Δt. It can be seen that the echo waveform can affect the accuracy of the detection result of the lidar.

[0059] Embodiments of the present disclosure design the semiconductor structure of the detector of the lidar to improve the waveform of the echo signal, so that the rising edge of the echo signal is steeper, and the deviation of the detected distance of the lidar is reduced.

[0060] The following description is described with reference to the accompanying drawings.

[0061] FIG. 3 shows a structural diagram of a semiconductor device according to some embodiments of the present disclosure. Referring to FIG. 3, the semiconductor device 300 includes, for example, a substrate 310, a photoelectric conversion structure 320, a resistance layer 330, a metal structure (for the sake of description, can be referred to as a first metal structure) 340, and a metal structure (for the sake of description, can be referred to as a second metal structure) 350. The photoelectric conversion structure 320 is formed in the substrate 310. The resistance layer 330, the metal structure 340, and the metal structure 350 are formed on the substrate 310. The metal structure 340 is electrically connected to a first end of the resistance layer 330, and the metal structure 350 is electrically connected to a second end of the resistance layer 330. The metal structure 340 is also electrically connected to the photoelectric conversion structure 320, and the metal structure 350 is electrically connected to the photoelectric conversion structure 320 through the resistance layer 330 and the metal structure 340. The metal structure 340 and the metal structure 350 have a first parasitic capacitance therebetween.

[0062] Embodiments of the present disclosure are directed to the design of a metal structure of a semiconductor device to change the output waveform of the semiconductor device, so that the output waveform of the semiconductor device is steeper. The semiconductor device can be applied to a laser radar to obtain a return signal with a steeper waveform, so that the return signal reaches the pulse moment faster, improving the accuracy of the determination of the receiving time of the laser by the laser radar, thereby more accurately determining the TOF of the laser and improving the accuracy of the detection result of the laser radar.

[0063] The above semiconductor device can be used for photoelectric conversion, for example, can be used for a detector of a laser radar, such as a SPAD, a SiPM, or the like. The resistance layer can be used as a quenching resistance of the detector. The photoelectric conversion structure can include at least one P-type doped region and at least one N-type doped region. Embodiments of the present disclosure do not limit the formation manner, position, or structure of the P-type doped region and the N-type doped region in the substrate, as long as at least one PN junction can be formed to generate a photoelectric effect after a reverse voltage is applied, for example, a photoelectric conversion structure suitable for generating an avalanche ionization effect.

[0064] The metal structure 350 can be configured to electrically connect a P-type doped region or an N-type doped region of the photoelectric conversion structure. The semiconductor device can further include a metal structure configured to electrically connect an N-type doped region or a P-type doped region of the photoelectric conversion structure. For example, please continue to refer to FIG. 3, in some embodiments of the present disclosure, the semiconductor device 300 further includes a metal structure (for the sake of description, which can be referred to as a third metal structure) 360 formed on the substrate 310. The metal structure 350 can electrically connect a first doped region of the photoelectric conversion structure. The metal structure 360 can electrically connect a second doped region of the photoelectric conversion structure 320. The first doped region can include an N-type doped region, and the second doped region can include a P-type doped region. Or the first doped region can include a P-type doped region, and the second doped region can include an N-type doped region.

[0065] In some embodiments of the present disclosure, the resistance layer 330 can be formed by depositing or doping a polysilicon material, for example, and the resistance value can also be adjusted by doping, so as to meet the requirement of the resistance value of the quenching process of the semiconductor device. In some embodiments of the present disclosure, the resistance layer 330 is formed in a different layer from the metal structure 340 and the metal structure 350, which is conducive to the manufacturing of the semiconductor device.

[0066] Please continue to refer to FIG. 3, in some embodiments of the present disclosure, the semiconductor device 300 further includes a metal structure (for the sake of description, which can be referred to as a fourth metal structure) 370 and a metal structure (for the sake of description, which can be referred to as a fifth metal structure) 380. The metal structure 370 can electrically connect the metal structure 350 and the second end of the resistance layer 330, and the metal structure 380 can electrically connect the metal structure 360 and the second doped region of the photoelectric conversion structure 320. In this way, the electrical connection between the metal structure 350 and the resistance layer 330, and the electrical connection between the metal structure 360 and the photoelectric conversion structure 320 can be achieved by a vertical wiring design, which is conducive to the miniaturization of the semiconductor device, and improves the production efficiency and yield of the semiconductor device.

[0067] Optionally, the metal structure 350 and the metal structure 360 can be formed in the same metal layer, for example, a metal layer (for the sake of description, which can be referred to as a second metal layer) L2. Optionally, the metal structure 370, the metal structure 380, and the metal structure 340 can be formed in the same metal layer, for example, a metal layer (for the sake of description, which can be referred to as a first metal layer) L1. In this way, the manufacturing of multiple metal structures can be achieved by the same process flow, which can simplify the manufacturing process of the semiconductor device, and further improve the manufacturing efficiency of the semiconductor device.

[0068] The metal structures can be electrically connected through via structures, which include vias and conductive medium filled in the vias, such as metal. For example, a via structure V1 is formed between the metal structure 350 and the metal structure 370 to achieve vertical electrical connection between the metal structure 350 and the metal structure 370. A via structure V2 is formed between the metal structure 340 and the photoelectric conversion structure 320 to achieve vertical electrical connection between the metal structure 340 and the photoelectric conversion structure 320. A via structure V3 is formed between the metal structure 370 and the resistance layer 330 to achieve vertical electrical connection between the metal structure 370 and the resistance layer 330. A via structure V4 is formed between the metal structure 340 and the resistance layer 330 to achieve vertical electrical connection between the metal structure 340 and the resistance layer 330. A via structure V5 is formed between the metal structure 360 and the metal structure 380 to achieve vertical electrical connection between the metal structure 360 and the metal structure 380. A via structure V6 is formed between the metal structure 380 and the photoelectric conversion structure 320 to achieve vertical electrical connection between the metal structure 380 and the photoelectric conversion structure 320. The electrical connection between the metal structures or between the metal structures and the photoelectric conversion structure through the via structures can be achieved in the vertical projection area of the metal structures, which reduces the size of the semiconductor device in the horizontal direction, facilitates the miniaturization of the semiconductor device, and simplifies the manufacturing process of the semiconductor device. The wiring structure can improve the performance of the semiconductor device. The photoelectric conversion structure 320 can be provided with a conductive structure, and the metal structures can be connected to the conductive structure on the photoelectric conversion structure 320 through the via structures, thereby achieving electrical connection with the corresponding doped regions.

[0069] FIG. 4 shows an equivalent circuit diagram of a semiconductor device according to some embodiments of the present disclosure. Referring to FIG. 4, the semiconductor device is taken as an example of a SPAD. q R represents the quenching resistance. D represents a diode (e.g., an avalanche diode). The function of the diode is achieved by, for example, the photoelectric conversion structure 320. The equivalent position of node A includes, for example, the metal structure 360. The equivalent position of node B includes, for example, the metal structure 340. The equivalent position of node C includes, for example, the metal structure 350. q R represents the parasitic capacitance between the metal structure 340 and the metal structure 350. d R represents the bulk resistance of the diode D. d R represents the junction capacitance of the diode D. bd R represents the breakdown voltage of the diode D. The avalanche state of the diode D is described by a switch S1, which is only used for equivalent illustration and does not represent the actual circuit structure of the diode D. There can be other parasitic capacitances in parallel with the junction capacitance C d , but their effects on the circuit are similar to the junction capacitance C d , and therefore are not described or distinguished.

[0070] In the avalanche trigger phase of diode D, switch S1 is equivalent to the closed state, the charge of junction capacitor C d is released outward, and the voltage of node B decreases. After a period of time, the voltage of node B is low enough, and the current of diode D is small enough, the avalanche process stops, and the switch S1 is equivalent to the open state. After that, the voltage of node B starts to rise, and the semiconductor device completes a waveform output. The following formula derivation shows the voltage and current parameter changes in the avalanche trigger phase and the avalanche recovery phase.

[0071] In the avalanche trigger phase starting at t0, the SPAD is triggered, and switch S1 is equivalent to the closed state. The current and voltage equations of each node in FIG. 4 can be referred to formula (2):

[0072] Solving V B , we get formula (3):

[0073] Wherein, represents the current flowing through the quenching resistor R q , represents the current flowing through the parasitic capacitor C q , represents the current flowing through the bulk resistance R d , represents the current flowing through the junction capacitor C d , is the voltage of B point before quenching in the avalanche process, and τ0 is the time constant of RC delay structure when the avalanche is triggered, and τ0 refer to formula (4):

[0074] Based on the above formula, the current q flowing through the quenching resistor R and the current q flowing through the parasitic capacitor C can be further obtained. Refer to formula (5):

[0075] V B , are the change processes of RC time constant τ0. According to the above formula, it can be seen that at t=0, is 0, and the total current is dominated by . When t is small, the amplitude of is much larger than has a significant impact on the rising edge of the total current, and The amplitude of the parasitic capacitance C q is positively correlated with the capacitance value of C

[0076] After assuming that the recovery phase starts at time t1, that is, the SPAD starts to quench, the switch S1 is equivalent to the open state, the current and voltage equations of each node in Figure 4 can be referred to formula (6):

[0077] Solving V B , we get formula (7):

[0078] Where τ1 is the time constant of the RC delay structure at the beginning of quenching, which can be referred to formula (8): τ1 = (C d +C q )R q formula (8)

[0079] Based on the above formula, we can further obtain the current q flowing through the quenching resistor R and the current q flowing through the parasitic capacitance C Refer to formula (9):

[0080] V B , are both the change process of RC time constant τ1.

[0081] Combined with the formulas 2 to 5 of the avalanche triggering phase, since R d <<R q , therefore τ0<<τ1, so we can know that the current waveform of the avalanche triggering phase is relatively steep, while the current waveform of the recovery phase is relatively slow. It can be seen that the introduction of the first parasitic capacitance C q can greatly increase the current at the initial stage of the triggering phase, which is manifested as the rising edge of the echo signal waveform is more steep. In this way, by using the structure of the semiconductor device shown in Figure 2, the first parasitic capacitance C q can be introduced through the metal structure 340 and the metal structure 350 at both ends of the resistance layer 330 to improve the waveform of the echo signal, so that the rising edge of the echo signal is more steep, and the deviation of the detection distance of the laser radar is reduced.

[0082] The metal structure 340 and the metal structure 350 can be formed in the same metal layer or in different metal layers. For example, when the metal structure 340 and the metal structure 350 are formed in the same metal layer, a coplanar capacitance model can be used for layout design to obtain the first parasitic capacitance. When the metal structure 340 and the metal structure 350 are formed in different metal layers, a biplanar capacitance model, a rectangular parallel plate capacitance model, or a circular parallel plate capacitance model can be used for layout design to obtain the first parasitic capacitance.

[0083] For example, please continue to refer to FIG. 3. In some embodiments of the present disclosure, the metal structure 340 and the metal structure 350 are formed in different metal layers, for example, the metal structure 340 is formed in the first metal layer L1, and the metal structure 350 is formed in the second metal layer L1. In this way, the first parasitic capacitance C q By means of the interlayer capacitance between different metal layers, the layout and connection of the metal structure can be realized in a limited chip area, which is more conducive to achieving the target parasitic capacitance by layout design, is conducive to the manufacturing and miniaturization of the semiconductor device, and has a better effect on the waveform improvement of the semiconductor device.

[0084] When the metal structure 340 and the metal structure 350 are located in different metal layers, the first parasitic capacitance C q The capacitance value is related to the distance and relative position between the metal layers, for example, is inversely proportional to the distance between the metal layers and is proportional to the overlapping area of the vertical projection between the metal layers. For example, for a rectangular parallel plate capacitance, the capacitance between the parallel plates is as formula (10):

[0085] Wherein, C represents the capacitance, ε0 represents the vacuum dielectric constant, ε r represents the relative dielectric constant of the dielectric between the parallel plates, d c represents the distance between the parallel plates, and S represents the overlapping area of the vertical projection between the parallel plates.

[0086] In some embodiments of the present disclosure, the metal structure 340 and the metal structure 350 have an overlapping area in the vertical projection in the same direction (for example, the direction towards the sinker 310). For example, the metal structure 350 has an overlapping area with the metal structure 340 in the vertical projection of the first metal layer L1 where the metal structure 340 is located. The design of the overlapping area is conducive to the formation of the first parasitic capacitance Cq This is to better improve the waveform of the echo signal, increase the steepness of the rising edge waveform of the echo signal, and make the rising edge reach the effective threshold quickly, so as to reduce the detection range error of the lidar and improve the detection accuracy.

[0087] In some embodiments of this disclosure, the parasitic capacitance C can be designed based on the RC time (i.e., the RC time constant τ1 mentioned above) of the lidar's SPAD recovery process. q The capacitance value. For example, the quenching resistance R that meets the quenching requirements for SPAD in the 5-50ns range. q If the resistance value is, for example, several hundred kiloohms (kohm), then the parasitic capacitance C q junction capacitance C d The value is in the tens of femtofarads (fF), and the junction capacitance C of the SPAD is... d For example, if the capacitance is several tens of femtoseconds, then the parasitic capacitance C q It can be set to no more than 10fF, i.e., parasitic capacitance C q It can be less than or equal to 10fF. During the avalanche triggering phase, The amplitude is much greater than At that time, the parasitic capacitance C q The effect on the signal waveform is more obvious. Referring to formula (5), when hour, amplitude and They are basically the same. Therefore, when At that time, the parasitic capacitance C q The impact on the echo signal will be relatively reduced. In some embodiments of this disclosure, the parasitic capacitance C can be set. q Greater than or equal to a first threshold, which is based on the junction capacitance C of the photoelectric conversion structure. d Determine, for example,

[0088] In the parasitic capacitance C q When achieved through the parasitic capacitance of the interlayer metal, refer to the above formula (10) for the parasitic capacitance C. q The size of the distance between the metal layers is inversely proportional to the distance between them and directly proportional to the area of ​​the metal layers. In some embodiments of this disclosure, the vertical distance between the metal structures 350 and 340 can be designed to be greater than or equal to 0.1 micrometers (µm) and less than or equal to 2 micrometers. This allows for implementation using complementary metal-oxide-semiconductor (CMOS) technology, eliminating the need for additional special processes, resulting in simpler manufacturing, lower cost, and better reliability.

[0089] Based on the above formula (10), the capacitance per unit overlapping area can be estimated to be approximately 0.02 fF / um.2 to 0.4 fF / um 2 For example, 0.2 fF / um 2 is used for calculation, to realize a parasitic capacitance C q of 2 fF. About 10 um 2 of overlapping area is used; 0.4 fF / um 2 is used for calculation, to realize a parasitic capacitance C q of 10 fF. About 2.5 um 2 of overlapping area is used; 0.02 fF / um 2 is used for calculation, to realize a parasitic capacitance C q of 10 fF. About 50 um 2 of overlapping area is used. With metal layers closer in distance, a larger parasitic capacitance C q can be realized by a smaller area.

[0090] The junction capacitance C d is positively correlated with the recovery time of the SPAD. By reducing the junction capacitance C d through the design of the metal structure, the recovery time of the SPAD is as small as possible. For example, in some embodiments of the present disclosure, the metal structure 360 is spaced apart from the metal structure 340 by a first distance d1 in the vertical projection of the first metal layer L1 on which the metal structure 340 is located. Since the vertical projections of the metal structure 360 and the metal structure 340 in the same direction do not overlap and are spaced apart by a certain distance, the junction capacitance C d between the node A and the node B can be reduced, thereby improving the recovery time of the semiconductor device. When the semiconductor device is used in a laser radar, the detection capability can be recovered as soon as possible during the detection process of the laser radar, further improving the detection performance of the laser radar. Embodiments of the present disclosure do not limit the size of the first distance d1, which can be designed in combination with the specification requirements of the semiconductor device. On the basis of meeting the specification requirements of the semiconductor device, the first distance d1 can be designed as large as possible.

[0091] The layout design of several metal structures is described below in combination with the accompanying drawings.

[0092] FIG. 5 shows an example layout of a semiconductor device, according to some embodiments of the present disclosure. Please refer to FIG. 5, which shows a top view of a semiconductor device, where the metal structure 340 is located in the first metal layer L1, and the metal structure 350 and the metal structure 360 are located in the second metal layer L1. The via layer 1 includes the via structures V2-V4 and the via structure V6. The via layer 2 includes the via structure V1 and the via structure V5. The metal structure 350 has an overlapping region O1 with the metal structure 340 in the vertical projection of the first metal layer L1. For example, a portion of the metal structure 350 extends towards the metal structure 340, so that the vertical projection of the metal structure 350 overlaps with the metal structure 340.

[0093] FIG. 6 shows another example layout of a semiconductor device, according to some embodiments of the present disclosure. FIG. 7 shows an example structure of a semiconductor device, according to some embodiments of the present disclosure. In the example shown in FIG. 7, the structures in different cross sections are moved to the same cross section for better clarity of the connection between layers. Please refer to FIG. 6 and FIG. 7, which show a top view of a semiconductor device, where the metal structure 340 is located in the first metal layer L1, and the metal structure 350 and the metal structure 360 are located in the second metal layer L1. The via layer 1 includes the via structures V2-V4 and the via structure V6. The via layer 2 includes the via structure V1 and the via structure V5. The metal structure 350 has an overlapping region O2 with the metal structure 340 in the vertical projection of the first metal layer L1. For example, the entire metal structure 350 is arranged towards the metal structure 340, so that the vertical projection of the metal structure 350 overlaps with the metal structure 340.

[0094] Please continue to refer to FIG. 6 and FIG. 7. In some embodiments of the present disclosure, the vertical projection of the metal structure 340 towards the substrate 310 can cover the surface of the photoelectric conversion structure 320. For a back-side illuminated (BSI) semiconductor device or semiconductor device array, the light incident from the back side will reflect once on the metal on the front side. The metal structure 340 is arranged to have a large area, which can achieve a better reflection effect, thereby having a higher detection efficiency.

[0095] The embodiments of the present disclosure do not limit the geometric shape of the overlapping region. The overlapping region includes, for example, regular shapes such as rectangles, trapezoids, semicircles, triangles, etc., or can include other irregular shapes. In FIG. 5 and FIG. 6, the rectangular overlapping region is used as an example. The design of the rectangular overlapping region can simplify the semiconductor process flow and improve the performance of the semiconductor device.

[0096] Any one of the semiconductor devices provided by the above embodiments of the present disclosure can be integrated together; for example, the embodiments of the present disclosure also provide a semiconductor device array, which includes a plurality of semiconductor devices, and the plurality of semiconductor devices are arranged, for example, can be arranged as a one-dimensional array or a two-dimensional array.

[0097] The semiconductor device array takes SiPM as an example, and the SiPM can be understood as a SPAD array. The SPAD array can be composed in a SPAD independent working mode or a SPAD parallel working mode. In the SPAD independent working mode, the parasitic capacitance C q The analysis of the influence on the output signal waveform is the same as described above. In the SPAD parallel working mode, the equivalent circuit of the SiPM takes the example shown in FIG. 8.

[0098] FIG. 8 shows an equivalent circuit example diagram of a semiconductor device array example according to some embodiments of the present disclosure. Please refer to FIG. 8, R S represents an external sampling resistor, and the echo signal waveform obtained by the outside world can be a current waveform flowing through R S C g represents the equivalent capacitance between node C and node A, which can be the sum of multiple parasitic capacitances in the semiconductor device array. R q / (n-1), C q (n-1), C d (n-1) represents the equivalent resistance and capacitance of other semiconductor devices in the semiconductor device array except for the semiconductor device 810. Among them, R q / (n-1) represents the equivalent quenching resistance of the other semiconductor devices, C q (n-1) represents the equivalent parasitic capacitance of the other semiconductor devices, C q (n-1) represents the equivalent junction capacitance of the other semiconductor devices. The resistance value of the sampling resistor R S is usually very small, and the influence on the working state of the semiconductor device can be ignored. The existence of the parasitic capacitance C g makes the current on the sampling resistor R S not equal to the current flowing through the diode D or ). The equivalent capacitance C g corresponds to providing a low-pass filtering function, and the high-frequency components in the current signal of the diode D can flow away through the parasitic capacitance C g , and the rising edge and the falling edge of the current waveform on the sampling resistor R S will be slowed down. The equivalent resistance and capacitance of the other semiconductor devices in the semiconductor array have similar influences on the current signal of the diode D as the parasitic capacitance C g , but since the impedance is significantly higher than C g branch, the influence is not great.

[0099] parasitic capacitance C g The steepness of the rising edge of the echo signal is also affected, and a larger parasitic capacitance C g will make the rising edge of the echo signal flatten. Reducing the parasitic capacitance C g , or even eliminating the parasitic capacitance C g , can determine a more steep rising edge of the echo signal to reduce the deviation of the detection distance of the lidar. In addition, reducing the parasitic capacitance C g can further make the falling edge of the echo signal more steep, and the quenching process is shortened, so that the semiconductor device can recover the detection capability as soon as possible during the lidar detection process, and the performance of the lidar is further improved.

[0100] In some embodiments of the present disclosure, please continue to refer to FIG. 3, as well as FIG. 4-FIG. 7, the metal structure 360 and the metal structure 350 are separated by a second distance d2 in the vertical projection of the first metal layer L1 where the metal structure 340 is located. Since the vertical projections of the metal structure 360 and the metal structure 350 in the same direction do not overlap and are separated by a certain distance, the parasitic capacitance C g between the node A and the node C can be reduced, thereby improving the output waveform of the semiconductor device, making the rising edge and the falling edge more steep. In this way, the more steep rising edge can make the echo signal reach the effective threshold more quickly, so as to reduce the detection distance error of the lidar and improve the detection accuracy. The more steep falling edge can shorten the quenching process, so that the semiconductor device can recover the detection capability as soon as possible during the lidar detection process. The present disclosure does not limit the size of the second distance d2, which can be designed in combination with the specification requirements of the semiconductor device. On the basis of meeting the specification requirements of the semiconductor device, the first distance d2 can be designed as large as possible. Alternatively, in the layout design, the second distance d2 is greater than the first distance d1, so that the waveform of the echo signal is more steep, and the metal structure layout design is easier to implement.

[0101] parasitic capacitance C g has a filtering effect on the output signal of the semiconductor device, and the smaller the capacitance value is, the better. However, in actual application, the parasitic capacitance C g includes a combination of various contributions, for example, the value of the parasitic capacitance caused by the process flow of the patch, packaging, etc. is about 10 pF, and the value of the parasitic capacitance caused by the metal trace in the chip is about 1 to 10 pF. For the semiconductor device array consistent with some embodiments of the present disclosure, the parasitic capacitance C gThe metal structures can be located in the same metal layer and can be calculated by a coplanar capacitance model. For example, there are two metal structures with a line width of 1 um, a pitch of 0.5 um, and a length of 20 um in a semiconductor device, the capacitance between the two metal structures can be estimated to be about 1.3 fF. For a semiconductor device array including 1000 semiconductor devices, the C g size of the metal structures is about 1.3 pF. For another example, the pitch between the two metal structures is lengthened to 5 um, the capacitance between the two metal structures is about 0.7 fF, and for a semiconductor device array including 1000 semiconductor devices, the C g size of the metal structures is about 0.7 pF. Based on the area limitation of the semiconductor device, the distance between the metal structures will not be particularly far, for example, will not be greater than the coverage of a single semiconductor device. For example, the pitch between the metal structures will not exceed 10 um, and the C g size of the metal structures is about 1 fF.

[0102] The following describes the layout design of the metal structures of several semiconductor arrays in conjunction with the accompanying drawings.

[0103] FIGS. 9-12 show example layouts of several semiconductor device arrays consistent with some embodiments of the present disclosure. Referring to FIGS. 9-12, the semiconductor array includes a plurality of semiconductor devices (as shown by the dashed boxes D in the figures), the number and arrangement of the semiconductor devices in the figures are only examples, and in practice, there can be more or fewer semiconductor devices, and the arrangement can be one-dimensional or two-dimensional.

[0104] In the example shown in FIG. 9, the same column of semiconductor devices share the metal structure 360 (e.g., share the “Node A” in FIG. 9) or the metal structure 350 (e.g., share the “Node C” in FIG. 9); and the same row of adjacent semiconductor devices share the metal structure 360 (e.g., share the “Node A” in FIG. 9) or the metal structure 350 (e.g., share the “Node C” in FIG. 9). The metal structure 340, the metal structure 350, and the metal structure 360 (e.g., the “Node A”, the “Node B”, and the “Node C” in FIG. 9) have no overlapping area in the vertical projection in the same direction (e.g., the direction facing the substrate), the parasitic capacitance between the Node A and the Node B is small, and the parasitic capacitance between the Node A and the Node C is small. In the layout design, the Node B and the Node C can be made closer to each other, the parasitic capacitance between the Node B and the Node C is increased, the waveform of the output signal is improved, the rising edge of the output signal is steeper, the echo signal reaches the effective threshold faster, the detection distance error of the lidar is reduced, and the detection accuracy is improved. The distance between the Node B and the Node A is increased, the waveform of the output signal is improved, the falling edge of the output signal is steeper, and the quenching process is shortened, so that the semiconductor device array can recover the detection capability as soon as possible during the lidar detection process. The example shown in FIG. 10 is different from that in FIG. 9 in that the same row of adjacent semiconductor devices no longer share the metal structure 360 (e.g., do not share the “Node A” in FIG. 10) or the metal structure 350 (e.g., do not share the “Node C” in FIG. 10). In the layout design, similarly, the Node B and the Node C can be made closer to each other, and the distance between the Node B and the Node A can be increased to improve the waveform of the output signal.

[0105] In the example shown in FIG. 9 or FIG. 10 above, a part of the metal structure 350 corresponding to the Node C can be extended to the metal structure 340 corresponding to the Node A partially or entirely to form an overlapping area O1 between the vertical projection of the metal structure 350 and the metal structure 340 in the same direction, so as to form a larger parasitic capacitance C q between the Node B and the Node C. For example, in the example shown in FIG. 11, a part of the metal structure 350 is extended to the metal structure 340, so that there is an overlapping area O1 between the vertical projection of the metal structure 350 and the metal structure 340 in the direction facing the substrate. For another example, in the example shown in FIG. 12, the metal structure 350 is translated to the metal structure 340, so that there is an overlapping area O2 between the vertical projection of the metal structure 350 and the metal structure 340 in the same direction. In this example, the parasitic capacitance C q between the Node B and the Node C is increased, and the parasitic capacitance C g between the Node A and the Node C is further reduced relative to the example above. The layout design can reduce the difficulty of the manufacturing process of the semiconductor device; and the metal structure is more regular, and the semiconductor device has better heat dissipation and conduction performance.

[0106] The node A can correspond to one or more metal structures. For example, in the examples shown in FIGS. 9-11, the first metal layer L1 can include a plurality of metal structures, such as the metal structure 360, the metal structure 361, and the metal structure 362, etc. The disclosed embodiments are not limited to this, and there can be more or fewer metal structures. Similarly, the node B can correspond to one or more metal structures, and the node C can also correspond to one or more metal structures. That is, the number of metal structures corresponding to the nodes A-C in the above figures is only an example, and there can be more or fewer metal structures.

[0107] FIG. 13 shows an example diagram of an output waveform of the semiconductor device array shown in FIG. 9, and FIG. 14 shows an example diagram of an output waveform of the semiconductor device array shown in FIG. 12. By comparing FIG. 13 and FIG. 14, it can be seen that the output waveform of the semiconductor device array shown in FIG. 12 has a better improvement effect, with a steeper waveform front and a higher peak value; when applied in a laser radar, the rear circuit is more likely to capture an accurate laser TOF.

[0108] Please continue to refer to FIG. 6, the metal structure 350 can be further moved to the middle position of the metal structure 340. For example, FIG. 15 shows another example layout of a semiconductor device according to some embodiments of the present disclosure. Please refer to FIG. 15, the overlapping region O2 is located at the middle position of the first metal structure 340. In this embodiment, the metal structure 350 and the metal structure 340 have an overlapping region in the vertical projection in the same direction, and the junction capacitance C q between the node B and the node C of the semiconductor device is increased. When the semiconductor array is laid out, the distance between the metal structure 350 and the metal structure 360, and the distance between the metal structure 350 and the metal structure 360 of the adjacent semiconductor device are both taken into account, the parasitic capacitance C g between the node A and the node C is reduced, and the complexity of the semiconductor device array design is reduced. In addition, the overall semiconductor device can be symmetrically laid out as much as possible, which is more conducive to the internal structure and wiring layout of the semiconductor array, and better detector performance can be achieved.

[0109] The semiconductor devices in the semiconductor device array can share the metal structures. For example, the semiconductor devices in the same column share the metal structures corresponding to node A or node C as described in the above embodiments. In some embodiments of the present disclosure, the semiconductor devices in the same row can also share the metal structures corresponding to node A or node C. Please continue to refer to FIG. 12, the semiconductor devices arranged adjacently can share the same metal structure corresponding to node A. Thus, the process flow of the semiconductor device array is simplified, and the production efficiency is improved. At this time, for a semiconductor device, the semiconductor device can also have a metal structure (for the sake of description, it can be referred to as a sixth metal structure) 390 configured to electrically connect the second doped region of the photoelectric conversion structure. The metal structure 390 is located in the same metal layer as the metal structure 360 and is parallel to the metal structure 360. The vertical projection of the metal structure 390 on the first metal layer L1 where the metal structure 340 is located is spaced apart from the metal structure 350 by a third distance d3. Similarly to the metal structure 360, since the vertical projections of the metal structure 390 and the metal structure 350 in the same direction do not overlap and are spaced apart by a certain distance, the parasitic capacitance C g Thus, the output waveform of the semiconductor device is improved, and the rising edge and the falling edge are steeper. In this way, the steeper rising edge can make the echo signal reach the effective threshold more quickly, so as to reduce the detection distance error of the lidar and improve the detection accuracy; the steeper falling edge can shorten the quenching process, and the semiconductor device can recover the detection capability as soon as possible in the lidar detection process. The embodiments of the present disclosure do not limit the size of the third distance d3, and the third distance d3 can be designed in combination with the specification requirements of the semiconductor device. On the basis that the specification requirements of the semiconductor device are met, the third distance d3 can be designed to be as large as possible.

[0110] In some embodiments of the present disclosure, the metal structure 390 and the metal structure 360 are spaced apart from the metal structure 350 by equal distances in the vertical projection of the first metal layer L1 where the metal structure 340 is located. That is, the second distance d2 is equal to the third distance d3. At this time, the horizontal distances of the metal structure 360 and the metal structure 390 from the metal structure 350 are balanced, so that the parasitic capacitance C g is reduced, and the waveform of the echo signal generated by the semiconductor device or the semiconductor device array corresponding to the quenching process is improved, and the sensitivity of the detector is improved.

[0111] FIGS. 16 to 21 show process example diagrams of a manufacturing method of a semiconductor device, which is consistent with some embodiments of the present disclosure. The manufacturing method at least includes providing a substrate 310 (as shown in FIG. 16) and forming a photoelectric conversion structure 320 in the substrate 310 (as shown in FIG. 17). For example, an initial wafer is provided, and the photoelectric conversion structure 320 is formed on the initial wafer by ion implantation. The photoelectric conversion structure 320 can include at least one P-type doped region and at least one N-type doped region.

[0112] Please continue to refer to FIG. 18, a dielectric layer (for the sake of description, can be called a first dielectric layer) 181 is formed on the substrate 310, and a resistance layer 330 is formed on the dielectric layer 181, which serves as a quenching resistance. For example, the dielectric layer 181 can be deposited, and a polysilicon layer is deposited on the dielectric layer 181, and the resistance layer 330 is formed by photolithography or etching on the polysilicon layer.

[0113] Please continue to refer to FIG. 19, a dielectric layer (for the sake of description, can be called a second dielectric layer) 191 is formed on the substrate 310, and the metal structure provided in any of the above embodiments is formed in the dielectric layer 191. For example, the metal structure 340 is electrically connected to the first end of the resistance layer 330, the metal structure 350 is electrically connected to the second end of the resistance layer 330, and the metal structure 340 is also electrically connected to the photoelectric conversion structure 320. The metal structure 350 is electrically connected to the photoelectric conversion structure 320 through the resistance layer 330 and the metal structure 340. The metal structure 340 and the metal structure 350 have a first parasitic capacitance therebetween.

[0114] Taking the metal structure shown in FIG. 3 as an example, the above manufacturing method further includes a process of forming a via structure. The conductive medium filled in the via structure V1-V6 can include, for example, metal materials such as copper, aluminum, etc. For example, the via structure filled with copper can be manufactured by using a dual damascene structure. For the via structure filled with aluminum, a deposition and etching process can be used for manufacturing. The via and the connected metal structure can be manufactured in one process flow, for example, the patterns of the metal structure 380 and the via structure V6, the patterns of the metal structure 340 and the via structures V2 and V4, and the patterns of the metal structure 370 and the via structure V3 are obtained by etching, and then the metal structures 340, 370 and 380 in the first metal layer L1 and the corresponding via structures V2-V4 and V6 are formed by depositing metal. Alternatively, the via and the connected metal structure can be manufactured in different process flows, for example, the via structures V2-V4 are first formed by a deposition and etching process. The first metal layer L1 is deposited on the via structures V2-V4, and the metal structures 340, 370 and 380 are formed by an etching process. The formation processes of the metal structures 350 and 360 and the via structures V1 and V5 are similar to the above described manner.

[0115] The semiconductor device or semiconductor device array provided by the embodiments of the present disclosure can be manufactured into a back-illuminated structure or a front-side illuminated (FSI) structure. In some embodiments of the present disclosure, for the semiconductor device or semiconductor device array of the back-illuminated structure, the initial wafer 201 can be further bonded with a carrier wafer 202 (as shown in FIG. 20). Then, the initial wafer 201 is thinned, and a surface process is performed on the back surface of the initial wafer to improve the optical transmittance, and a passivation protective layer 203 is formed on the back surface (as shown in FIG. 21), etc.

[0116] In some embodiments of the present disclosure, a light receiver is also provided. The light receiver can include at least one semiconductor device having any of the semiconductor structures provided by the above embodiments. The light receiver can be used in optical devices such as laser radar.

[0117] In the present disclosure, unless otherwise explicitly specified and limited, ordinal words such as "first", "second", etc. are only used to distinguish the description of the associated objects, and cannot be understood as indicating or implying the relative importance or order between the associated objects; in addition, it also does not represent the number of the associated objects. "Multiple" includes two or more, and other quantifiers are similar. " / " is used to describe the relationship between the associated objects, which represents the "or" relationship between the associated objects. "And / or" is used to describe the relationship between the associated objects, which includes any combination relationship between the associated objects, for example, "a and / or b" includes: "a alone", "b alone", or "a and b". "One or more" or "at least one" of a plurality of objects means any object or any combination of a plurality of objects, for example, "one or more of a1, a2, a3" or "at least one of a1, a2, a3" includes: "a1 alone", "a2 alone", "a3 alone", "a1 and a2", "a1 and a3", "a2 and a3", or "a1, a2 and a3".

[0118] In the above embodiments, the description of each embodiment has its own focus, and the parts not described or recorded in detail in a certain embodiment can be referred to the related description of other embodiments. In addition, the above embodiments can be freely combined as needed.

Claims

1. A semiconductor device, characterized by, The application includes: a substrate; a photoelectric conversion structure formed in the substrate; a resistance layer formed on the substrate; a first metal structure and a second metal structure formed on the substrate, the first metal structure electrically connected to a first end of the resistance layer, and the second metal structure electrically connected to a second end of the resistance layer; wherein the first metal structure is also electrically connected to the photoelectric conversion structure, and the second metal structure is electrically connected to the photoelectric conversion structure through the resistance layer and the first metal structure; and the first metal structure and the second metal structure have a first parasitic capacitance therebetween.

2. The semiconductor device according to claim 1, wherein The first metal structure is formed in a first metal layer, and the second metal structure is formed in a second metal layer.

3. The semiconductor device of claim 2, wherein, A vertical projection of the second metal structure on the first metal layer has an overlapping area with the first metal structure.

4. The semiconductor device according to claim 3, wherein A vertical distance between the second metal structure and the first metal structure is greater than or equal to 0.1 microns and less than or equal to 2 microns.

5. The semiconductor device according to claim 3 or 4, wherein An area of the overlapping area is greater than or equal to 2.5 square microns and less than or equal to 50 square microns.

6. The semiconductor device according to any one of claims 1 to 5, wherein A vertical projection of the first metal structure towards the substrate covers a surface of the photoelectric conversion structure.

7. The semiconductor device according to any one of claims 1 to 6, wherein The first parasitic capacitance is greater than or equal to a first threshold value, which is determined based on a junction capacitance of the photoelectric conversion structure.

8. The semiconductor device of claim 7, wherein, The first parasitic capacitance is less than or equal to 10 fF.

9. The semiconductor device according to any one of claims 1 to 8, wherein Further including: a third metal structure formed on the substrate; the second metal structure is configured to electrically connect a first doped region of the photoelectric conversion structure; the third metal structure is configured to electrically connect a second doped region of the photoelectric conversion structure; wherein the first doped region comprises an N-type doped region, and the second doped region comprises a P-type doped region; or the first doped region comprises a P-type doped region, and the second doped region comprises an N-type doped region.

10. The semiconductor device of claim 9, wherein, The second metal structure and the third metal structure are formed in a second metal layer.

11. The semiconductor device according to claim 9 or 10, characterized by The first metal structure is formed in a first metal layer, and a vertical projection of the third metal structure on the first metal layer is spaced from the first metal structure by a first distance.

12. The semiconductor device of claim 11, wherein, A vertical projection of the third metal structure on the first metal layer is spaced from a vertical projection of the second metal structure on the first metal layer by a second distance, which is greater than the first distance.

13. The semiconductor device according to any one of claims 9 to 12, wherein Further including: a fourth metal structure configured to electrically connect the second metal structure and the second end of the resistance layer; a fifth metal structure configured to electrically connect the third metal structure and the second doped region of the photoelectric conversion structure; wherein the fourth metal structure and the fifth metal structure are formed in a first metal layer with the first metal structure.

14. The semiconductor device according to any one of claims 9 to 13, wherein Further including: a sixth metal structure configured to electrically connect the second doped region; wherein the sixth metal structure is formed in a second metal layer with the third metal structure and is parallel to the third metal structure, and a vertical projection of the sixth metal structure on the first metal layer is spaced from the second metal structure by a third distance.

15. The semiconductor device of claim 14, wherein, The sixth metal structure and the third metal structure are spaced from the second metal structure by an equal distance in a vertical projection on the first metal layer.

16. An optical receiver comprising: comprising at least one semiconductor device as claimed in any of claims 1-15.

17. A lidar, comprising: comprising: a light emitter configured to emit laser light; a light receiver as claimed in claim 16, configured to receive a return of the laser light and to convert the return into an electrical signal; processing circuitry configured to process the electrical signal.

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