Semiconductor structures

Abstract

The present disclosure relates to a semiconductor structure comprising: a first channel layer; a first barrier layer configured to induce a first two-dimensional electron gas, 2DEG, in the first channel layer; a source contact and a drain contact, wherein the first 2DEG is configurable to form a channel between the source contact and the drain contact; a gate contact configured to apply a first voltage to the first 2DEG, to modulate the first 2DEG; a first bias layer; a second barrier layer configured to induce formation of a second 2DEG in the first bias layer; and a bias contact configured to apply a bias voltage to the second 2DEG, to apply an electric field to the first 2DEG.

Description

[0001] Semiconductor Structures

[0002] Technical field

[0003] The present application relates to a semiconductor structure. The present application also relates to a RF module, an electronic device and a method of forming a semiconductor structure.

[0004] Forming semiconductor devices from lll-N semiconductor materials is becoming increasingly desirable. Si has dominated the semiconductor industry for many decades. However, lll-N semiconductor materials, such as GaN, possess desirable electronic and photonic properties, outperforming Si in many aspects.

[0005] The high electron mobility transistor (HEMT) is a semiconductor device commonly formed from lll-N materials. lll-N HEMTs typically exhibit a higher breakdown voltage and greater electron mobility than Si MOSFETs. The use of lll-N HEMTs has therefore found use in power and radio frequency (RF) communications applications.

[0006] HEMTs exhibit high electron mobility due to the formation of a two-dimensional electron gas (2DEG) in the channel layer of the HEMT. Typically, an AIGaN barrier layer is formed over a GaN channel layer. The AIGaN barrier layer induces the formation of a 2D EG in the GaN channel layer. Whilst the formation of the 2DEG is a desirable property it commonly results in HEMTs exhibiting depletion mode (D-mode) behaviour where a negative bias voltage is applied to the HEMT in order to turn the HEMT to the ‘off’ state.

[0007] In some applications, the D-mode behaviour of a HEMT is typically not as desirable as an enhancement mode (E-mode) operation, where a transistor is normally in the ‘off’ state and a positive bias voltage is applied to turn the transistor to the ‘on’ state. For D- mode operation, a driver circuit or negative bias generator is typically added to a circuit to appropriately control the HEMT. Such circuitry is not commonly used for E-mode operation.

[0008] Additionally, HEMTs are commonly formed using epitaxial techniques where a relatively thick buffer layer is grown between the substrate and the channel layer. The buffer can include a number of defects. During switching, carriers can migrate from the channel layer and become trapped in the defects. The defects are thus commonly referred to as ‘traps’. The traps are a cause of drain lag, which limits the conductivity of the 2DEG.

[0009] It is an object of the disclosure to obviate or eliminate at least some of the abovedescribed disadvantages associated with existing techniques.

[0010] According to a first aspect there is provided a semiconductor structure comprising: a first channel layer; a first barrier layer configured to induce a first two-dimensional electron gas (2DEG) in the first channel layer; a source contact and a drain contact, wherein the first 2DEG is configurable to form a channel between the source contact and the drain contact; a gate contact configured to apply a first voltage to the first 2DEG, to modulate the first 2DEG; a first bias layer; a second barrier layer configured to induce formation of a second 2DEG in the first bias layer; and a bias contact configured to apply a bias voltage to the second 2DEG, to apply an electric field to the first 2DEG.

[0011] According to a second aspect there is provided a semiconductor device comprising the semiconductor structure according to the first aspect.

[0012] According to a third aspect there is provided a power management device comprising the semiconductor device according to the second aspect.

[0013] According to a fourth aspect there is provided an electronic device comprising the power management device according to the third aspect.

[0014] According to a fifth aspect there is provided a method of forming a semiconductor structure comprising: forming a first channel layer; forming a first barrier layer configured to induce a first two-dimensional electron gas (2DEG) in the first channel layer; forming a source contact and a drain contact, wherein the first 2DEG is configurable to form a channel between the source contact and the drain contact; forming a gate contact configured to apply a first voltage to the first 2DEG, to modulate the first 2DEG; forming a first bias layer; forming a second barrier layer configured to induce formation of a second 2DEG in the first bias layer; and forming a bias contact configured to apply a bias voltage to the second 2DEG, to apply an electric field to the first 2DEG. Brief of the

[0015] For a better understanding of the techniques, and to show how it may be put into effect, reference will now be made, by way of example, to the accompanying drawings, in which:

[0016] Figure 1 is an example of a semiconductor structure;

[0017] Figure 2 is an example of a semiconductor structure;

[0018] Figure 3 is another example of a semiconductor structure;

[0019] Figure 4 is an example of a semiconductor structure;

[0020] Figure 5 is an exploded view of a semiconductor structure;

[0021] Figures 6a-e are process steps in a method for manufacturing a semiconductor structure;

[0022] Figure 7 is a flowchart illustrating process steps in a method.

[0023] Detailed Description

[0024] Epitaxy or epitaxial means crystalline growth of material, usually via high temperature deposition. Epitaxy can be effected in a molecular beam epitaxy (MBE) tool in which layers are grown on a heated substrate in an ultra-high vacuum environment. Elemental sources are heated in a furnace and directed towards the substrate without carrier gases. The elemental constituents react at the substrate surface to create a deposited layer. Each layer is allowed to reach its lowest energy state before the next layer is grown so that bonds are formed between the layers. Epitaxy can also be performed in a metalorganic vapour phase epitaxy (MOVPE) tool, also known as a metal-organic chemical vapour deposition (MOCVD) tool. Compound metal-organic and hydride sources are flowed over a heated surface using a carrier gas, typically hydrogen. Epitaxial deposition occurs at much higher pressure than in an MBE tool. The compound constituents are cracked in the gas phase and then reacted at the surface to grow layers of desired composition. A compound material comprising one or more materials from group III of the periodic table with one or more materials from group V is known as a lll-V material. The compounds have a 1 :1 combination of group III and group V regardless of the number of elements from each group. Subscripts in chemical symbols of compounds refer to the proportion of that element within that group. Thus Alo.25Gao.75As means the group III part comprises 25% Al, and thus 75% Ga, whilst the group V part comprises 100% As.

[0025] Doping means that a layer or material contains a small impurity concentration of another element (dopant) which donates (donor) or extracts (acceptor) charge carriers from the parent material and therefore alters the conductivity. Charge carriers may be electrons or holes. A doped material with extra electrons is called n-type whilst a doped material with extra holes (fewer electrons) is called p-type.

[0026] A layer may be monolithic, that is comprising bulk material throughout. Alternatively it may be porous for some or all of its thickness. A porous layer includes air or vacuum pores, with the porosity defined as the proportion of the area which is occupied by the pores rather than the bulk material. The porosity can vary through the thickness of the layer. For example, the layer may be porous in one or more sublayer. The layer may include an upper portion which is porous with a lower portion that is non-porous.

[0027] A porous layer means that pores have been formed through bulk material so that voids are intentionally introduced. Porosity is expressed in percentages which refers to the volume of bulk material which has been removed so 25% porosity means that the 25% of the equivalent volume of bulk material is voided.

[0028] A fully depleted porous layer means a layer in which there are no charge carriers.

[0029] Where a device is described it should be understood that it will typically be formed on a circular substrate wafer of 4” (100mm), 6” (150mm), 8” (200mm), 12” (300mm) or greater diameter. After growth, deposition, bonding and other fabrication steps the devices are separated by dicing the wafer and layers into devices (chips) of appropriate dimensions. Typically tens, hundreds or thousands of devices are cut from a single wafer.

[0030] Throughout the present disclosure corresponding elements in the Figures are labelled with corresponding reference numerals. To provide additional context to the description of the examples according to the present disclosure, there now follows a further discussion of the drawbacks, which conventional examples suffer from.

[0031] Figure 1 is an example of a conventional HEMT 100. HEMT 100 comprises a substrate 110, a nucleation layer 120, a buffer layer 130, a channel layer 140 and a barrier layer 150 formed on the substrate 110. The nucleation layer 120, buffer layer 130, channel layer 140 and barrier layer 150 comprise semiconductor material. In one example, the nucleation layer 120, buffer layer 130, channel layer 140 and barrier layer 150 comprise lll-N semiconductor material. However, in other examples, the nucleation layer 120, buffer layer 130, channel layer 140 and barrier layer 150 may comprise other lll-V materials such as GaAs-based materials. The nucleation layer 120, buffer layer 130, channel layer 140 and barrier layer 150 may thus be epitaxially grown on the substrate 110. In some examples, the substrate 110 may comprise a material for the epitaxial growth of semiconductor material thereon, such as, Si, SiC, Sapphire, GaN or AIN.

[0032] The nucleation layer 120 is configured to transition from the substrate 110 to the semiconductor materials forming the HEMT 100. In some examples, the nucleation layer 120 may comprise AIN. The buffer layer 130, is configured to eliminate defects and provide isolation between the substrate 110 and the channel layer 140 above the buffer layer 130. In some examples, the buffer layer 130 may comprise GaN or AIGaN.

[0033] Channel layer 140 provides the channel in the HEMT for charge carriers to flow. A 2- dimensional electron gas (2DEG) 142 is formed in the channel, which confines the electrons and results in the HEMT exhibiting high electron mobility properties. The 2DEG 142 is formed in the channel layer 140 due to a polarization discontinuity between the barrier layer 150 and the channel layer 140. In some examples, the channel layer 140 comprises GaN and the barrier layer 150 comprises AIGaN.

[0034] HEMT 100 further comprises a source contact 160, a drain contact 170 and a gate contact 180. As illustrated in Figure 1 , the 2DEG 142 is continuous between the source contact 160 and the drain contact 170. As such, with no bias voltage applied to the gate contact 180, the formation of the 2DEG 142 results in current flow between the source contact 160 and drain contact 170. The HEMT 100 thus exhibit D-mode behaviour. A negative bias voltage is applied to the gate contact 180 to turn the HEMT 100 to the ‘off’ state where the formation of the 2DEG 142 is interrupted. In some examples, the buffer layer 130 may be doped, for example, with C or Fe. Doping the buffer further improves the electrical isolation properties of the buffer layer 130. However, the dopants can form ‘traps’, which trap carriers, reducing the conductivity of the 2DEG 142 and result in drain lag.

[0035] Examples according to the present disclosure provide a semiconductor structure that comprises a second 2DEG and a bias contact configured to apply a bias voltage to the second 2DEG. The second 2DEG is further configured to apply an electric field the first 2DEG of the channel layer. In such examples, the second 2DEG may thus be configured to adjust the electrical properties of the first 2DEG. The second 2DEG may thus further be configured to adjust the electric field at the first 2DEG and, in turn, adjust the threshold voltage used to modulate formation of the first 2DEG. In some examples, the second 2DEG may be configured to interrupt formation of the first 2DEG of the channel layer, when a zero bias voltage is applied to the HEMT. A positive threshold voltage may then be applied to form the 2DEG. In such examples, the HEMT is configured for E-mode operation.

[0036] Furthermore, in some examples, the second 2DEG is further configured to prevent carriers migrating from the channel layer to the buffer layer. The electric field applied to the first 2DEG by the second 2DEG confines carriers to the first 2DEG thereby improving carrier mobility and mitigating drain lag.

[0037] Figure 2 is an example of a HEMT 200. HEMT 200 comprises corresponding elements to HEMT 100 described above.

[0038] HEMT 200 further comprises a bias layer 210 and a second barrier layer 220. Bias layer 210 and a second barrier layer 220 comprise semiconductor material. In one example, the bias layer 210 and second barrier layer 220 comprise lll-N semiconductor material. However, in other examples, the bias layer 210 and second barrier layer 220 comprise other lll-V materials such as GaAs-based materials. The bias layer 210 and second barrier layer 220 may thus be epitaxially grown on the substrate 110.

[0039] The second barrier layer 220 is configured to induce a second 2DEG 212 in the bias layer 210. In a similar manner to the channel layer 140 and barrier layer 150 described above, the second 2DEG 212 may form due to a polarization discontinuity between the bias layer 210 and second barrier layer 220. In one example, the bias layer 210 may comprise GaN and the second barrier layer 220 may comprise AIGaN.

[0040] The HEMT 200 further comprises a bias contact 230. The bias contact 230 is configured to apply a bias voltage to the second 2DEG 212. The application of the bias voltage to the second 2DEG 212 is configured to, in turn, apply an electric field to the first 2DEG 142. As described above, the bias voltage may thus be configured to modify the electrical properties of the first 2DEG and therefore modify the properties and operation of the HEMT 200. In some examples, the application of the bias voltage to the second 2DEG 212 may be configured to set the threshold voltage of the HEMT 200. In such examples, the bias voltage modifies the electric field at the first 2DEG 142 to modify the threshold voltage.

[0041] In some examples, the bias voltage may be configured to set the threshold voltage to greater than 0 V. For example, the bias voltage may be configured to interrupt formation of the first 2DEG 142, when a 0 V control voltage is applied to the gate contact 180. In such examples, the first 2DEG 142 may no longer form a continuous channel between the source contact 160 and drain contact 170, when a 0 V control voltage is applied to the gate contact 180. In this state, the HEMT 200 is thus in the non-conducting or ‘off’ state. To turn the HEMT 200 to the conducting or ‘on’ state, a positive control voltage is applied to the gate contact 180, which alters the electric field in the channel layer 140 to form a continuous 2DEG 142 between the source contact 160 and drain contact 170. In such examples, the HEMT 200 thus operates with E-mode behaviour, where a positive threshold voltage is applied to switch the HEMT 200 between the conducting and nonconducting states.

[0042] In some examples, the bias voltage is configured to suppress carrier movement from the first 2DEG 142 towards the second 2DEG 212. In such examples, the application of the bias voltage confines carriers to the channel layer 140 and prevents carriers migrating towards traps in the buffer layer 130. In such examples, the bias voltage is further configured to improve the conductivity of the first 2DEG 142 and mitigate the effects of drain lag.

[0043] In some examples, the bias layer 210 may be doped n-type. In some examples, the second barrier layer 220 may be doped n-type. In some examples, the doping of the bias layer 210 or the second barrier layer 220 may increase the number carriers in the second 2DEG 212 to result in a denser second 2DEG 212.

[0044] Figure 3 is an example of a HEMT 300. HEMT 300 comprises corresponding elements to HEMT 100 and HEMT 200 described above.

[0045] HEMT 300 comprises a second channel layer 340 and a third barrier layer 350. Second channel layer 340 and third barrier layer 350 comprise semiconductor material. In one example, the second channel layer 340 and third barrier layer 350 comprise lll-N semiconductor material. However, in other examples, the second channel layer 340 and third barrier layer 350 comprise other 11 l-V materials such as GaAs-based materials. The second channel layer 340 and third barrier layer 350 may thus be epitaxially grown on the substrate 110.

[0046] The third barrier layer 350 is configured to induce a third 2DEG 342 in the second channel layer 340. In a similar manner to the channel layer 140 and barrier layer 150 described above, the third 2DEG 342 may form due to a polarization discontinuity between the channel layer 340 and the third barrier layer 350. In one example, the second channel layer 340 may comprise GaN and the third barrier layer 350 may comprise AIGaN.

[0047] The HEMT 300 further comprises a source contact 360, drain contact 370 and gate contact 380. In some examples, the first 2DEG 142 and the third 2DEG 342 may be configured to form a communicative channel between the source contact 360 and the drain contact 370. In such examples, the first 2DEG 142 and the third 2DEG 342 may be configured to result in a lower on resistance between the source contact 360 and the drain contact 370, compared to a single 2DEG formed between the source contact 360 and drain contact 370.

[0048] It will therefore be appreciated that whilst the HEMT 300 comprises two 2DEGs configured to form a communicative channel between the source contact 360 and the drain contact 370, in other examples, the HEMT 300 may comprise more than two 2DEGs configured to form a communicative channel between the source contact 360 and the drain contact 370 to lower the on resistance between the source contact 360 and the drain contact 370. In some examples, HEMT 300 may thus comprise a plurality of 2DEGs configured to form a communicative channel between the source contact 360 and the drain contact 370, where the plurality may comprise any suitable number such as two, three or four 2DEGs.

[0049] In some examples, the gate contact 380 may thus be configured to receive a control voltage to modulate the formation of the first 2DEG 142 and / or the third 2DEG 342. In some examples, the gate contact 380 may be configured to switch the HEMT 300 between a conducting or non-conducting state dependent on whether the first 2DEG 142 or the third 2DEG 342 is formed between the source contact 360 and drain contact 370. In particular, in conventional HEMT architectures where a bias layer 210 is not present, it can be difficult for a gate contact 380 to apply a control voltage to modulate “deeper” 2DEGs, such as first 2DEG 142, due to the distance between the gate contact 380 and first 2DEG 142. However, in examples, according to the present disclosure, the bias layer 210 can be configured to adjust the electric field at the first 2DEG 142 in order enable a control voltage applied to gate contact 380 to appropriately modulate the formation of first 2DEG 142.

[0050] It will be appreciated that the formation of source contact 360, drain contact 370 and gate contact 380 is for illustrative purposes and one skilled in the art would be able to configure source contact 360, drain contact 370 and gate contact 380 appropriately to control the formation of the first 2DEG 142 and the third 2DEG 342.

[0051] Figure 4 is an example of a semiconductor structure 400. Semiconductor structure 400 comprises HEMT 200 and HEMT 401. In some examples, the semiconductor structure 400 may thus comprise a semiconductor wafer comprising a plurality of HEMTs comprising HEMT 200 and HEMT 401.

[0052] HEMT 401 comprises a nucleation layer 420, buffer layer 430, bias layer 440, second barrier layer 450, channel layer 460, 2DEG 462, first barrier layer 470, source contact 492, drain contact 494 and gate contact 490. In some examples, nucleation layer 420, buffer layer 430, channel layer 460, first barrier layer 470, source contact 492, drain contact 494 and gate contact 490 may comprise corresponding materials, features and functionality to nucleation layer 120, buffer layer 130, channel layer 140, first barrier layer 150, source contact 160, drain contact 170 and gate contact 180, respectively, of HEMT 200. Bias layer 440 and barrier layer 450 may comprise similar materials to the bias layer 210 and barrier layer 220, respectively. For example, the bias layer 440 may comprise GaN and the barrier layer 450 may comprise AIGaN. However, bias layer 440 and barrier layer 450 may be configured such that a 2DEG does not form in bias layer 440. In some examples, the interface between the bias layer 440 and barrier layer 450 may be defective such that a 2DEG does not form in the bias layer 440. In some examples, one or both of the bias layer 440 and barrier layer 450 may comprise ions which defect the interface between the bias layer 440 and barrier layer 450 such that a 2DEG does not form in the bias layer 440. In some examples, the ions may be implanted into one of the bias layer 440 and barrier layer 450. In some examples, the ions may comprise H, He, B or N.

[0053] In some examples, the nucleation layer 120, buffer layer 130, bias layer 210, first barrier layer 220, channel layer 140 and first barrier layer 150 of HEMT 200 may comprise first portions of semiconductor layers formed on substrate 110, and nucleation layer 420, buffer layer 430, bias layer 440, barrier layer 450, channel layer 460 and barrier layer 470 of HEMT 401 may comprise second portions of the semiconductor layers formed on substrate 110. Thus, the bias layer 210 may comprise a first portion of a bias layer that comprises the second 2DEG 212 and bias layer 440 may comprise a second portion of the bias layer that does not comprise the 2DEG 212. The second portion of the bias layer 440 may comprise ions and the second portion of the bias layer 210 may not comprise ions. In a similar manner, in some examples, the barrier layer 220 may comprise a first portion of a barrier layer that does not comprise ions and the barrier layer 440 may comprise a second portion of the barrier layer that comprises ions.

[0054] Semiconductor structure 400 thus further comprises a dividing region 402. Dividing region 402 is configured to electrically isolate HEMT 200 and HEMT 401 from one another. The dividing region 402 is thus further configured to divide the semiconductor layers on a wafer into first and second portions, as described above. In some examples, the dividing region 402 may comprise ions implanted into the semiconductor structure 400, as will be described in more detail below. In some examples, the ions may comprise H, He, B or N.

[0055] Although dividing region 402 is illustrated as extending from the barrier layers 150, 470 to the substrate 110, in other examples, the dividing region 402 may not penetrate into the semiconductor structure 400 as far as the substrate 110. In some examples, the dividing region may sufficiently electrically isolate the HEMT 200 from the HEMT 401 if the conductive semiconductor layers are isolated. As such, in some examples, the dividing region 402 may extend through the conductive semiconductor layers which may comprise the barrier layers 150, 470, channel layers 140, 460, barrier layers 220, 450 and bias layers 210 and 440. In such examples, the dividing region 402 may not extend through the buffer layers 130, 430 or the nucleation layers 120, 420, as these layers typically are not conductive layers.

[0056] The second 2DEG 212 thus extends under the first 2DEG 142 and does not extend under the fourth 2DEG 462. Application of a bias voltage to the bias contact 230 may thus apply an electric field to affect the properties of the first 2DEG 142, but the application of the bias voltage may not substantially affect the properties of the fourth 2DEG 462. In such examples, the bias voltage may thus be configured to adjust the threshold voltage of the HEMT 200 but may not affect the threshold voltage of the HEMT 401 . In such examples, the HEMT 200 may thus comprise a different threshold voltage to HEMT 401. In some examples, the bias voltage may be configured to operate the HEMT 200 with E-mode behaviour with a positive threshold voltage, where the HEMT 401 is configured for D- mode behaviour with a negative threshold voltage. In such examples, the HEMT 200 and HEMT 401 may form part of a circuit for logic applications.

[0057] The description above presents the first 2DEG 142 and second 2DEG 212 overlying one another along axis that are substantially parallel. Similarly, the description above presents the source contact 160, drain contact 170, gate contact 180 and bias contact 230 along a single axis. However, examples according to the present disclosure may comprise the first 2DEG 142, second 2DEG 212, source contact 160, drain contact 170, gate contact 180 and bias contact 230 arranged in alternative arrangements.

[0058] Figure 5 is an exploded view of features of HEMT 200. Figure 5 illustrates a configuration of the source contact 160, drain contact 170, gate contact 180, bias contact 230, channel layer 140, first 2DEG 142, bias layer 210 and second 2DEG 212. The remaining features of the HEMT 200 are not illustrated in Figure 5 for clarity.

[0059] HEMT 200 comprises the first 2DEG 142 arranged along a first axis 510 in the channel layer 140. HEMT 200 further comprises the second 2DEG 212 arranged in the bias layer 210 along a second axis 520. The first axis 510 is in a first plane defined by the channel layer 140 and the second axis 520 is in a second plane defined by the bias layer 210. As illustrated in Figure 5, the first axis 510 is normal to the second axis 520. However, in other examples, the first axis 510 may be angled relative to the second axis 520 for any non-zero angle.

[0060] As described above, portions of the bias layer 210 may be configured to comprise the second 2DEG 212 and other portions of the bias layer 210 may not comprise the second 2DEG 212. In a similar manner, portions of the channel layer 140 may be configured to comprise the first 2DEG 142 and portions of the channel layer 140 may not comprise the first 2DEG 142. In such examples, portions of the channel layer 140 and / or portions of the barrier layer 150 may comprise implanted ions to disrupt formation of the first 2DEG 142 in portions of the channel layer 140.

[0061] The HEMT 200 further comprises a first contact axis 530 comprising the source contact 160, drain contact 170 and gate contact 180, but which does not comprise the bias contact 230. The HEMT 200 further comprises a second contact axis 540 comprising the gate contact 180 and the bias contact 230. The first contact axis 540 and the second contact axis 550 thus intersect at the gate contact 180. The first contact axis 530 is normal to the second contact axis 540. However, in other examples, the first contact axis 530 may be angled relative to the second contact axis 530 for any non-zero angle.

[0062] The first contact axis 530 is parallel to the first axis 510 and the second contact axis 540 is parallel to the second axis 520.

[0063] In some examples, configuring the bias contact 230 to run along an alternative axis to the source contact 160, drain contact 170 and gate contact 180 may provide greater design freedom for the circuit design. For example, in some circuit designs, it may be advantageous to position the bias contact away from the source contact 160 or drain contact 170, and be closer to the gate contact 180.

[0064] In some examples, configuring the first 2DEG 142 and the second 2DEG 212 to run along axis that are non-parallel may improve the formation of the first 2DEG 142. For example, where the second 2DEG 212 runs under the first 2DEG 142 along a parallel axis, the second 2DEG 212 may affect the conduction properties of the first 2DEG 142 between the sourse contact 160 and gate contact 180, as well as between the drain contact 170 and the gate contact 180, which may not be desirable in some applications. The first axis 510 of the first 2DEG 142 and the second axis 520 of the second 2DEG 212 may thus intersect a third axis 550 that comprises the gate contact 180. In such examples, in this configuration, the second 2DEG 212 may only adjust the electrical properties of the first 2DEG 142 in a portion of the channel layer 140 beneath the gate contact 180.

[0065] Figures 6a-e are example process steps 600a-e in a method of manufacturing a semiconductor structure. Process steps 600a-e are process steps for manufacturing semiconductor structure 400 described above.

[0066] Figure 6a illustrates a first process step 600a, in which nucleation layer 620, buffer layer 630, bias layer 601 , barrier layer 602, channel layer 640 and barrier layer 650 are formed on substrate 110. As described above the nucleation layer 620, buffer layer 630, bias layer 601 , barrier layer 602, channel layer 640 and barrier layer 650 comprise semiconductor material, for example, lll-N semiconductor material. In some examples, nucleation layer 620, buffer layer 630, bias layer 601 , barrier layer 602, channel layer 640 and barrier layer 650 may thus be sequentially formed on the substrate 110 using epitaxial growth techniques, such as, MOCVD or MBE. In some examples, the substrate 110 may thus comprise a material configured to permit the epitaxial growth of semiconductor material thereon. For example, the substrate 110 may comprise Si, Sic, sapphire, GaN or AIN.

[0067] First process step 600a thus illustrates that epitaxial formation of semiconductor layers on a substrate 110 to form a semiconductor wafer. The semiconductor wafer may be fabricated into a plurality of semiconductor devices, such as HEMT 200 and HEMT 401 , as will be described below.

[0068] The semiconductor wafer thus comprises a channel layer 2DEG 642 and a bias layer 2DEG 612. Channel layer 2DEG 642 is formed in the channel layer 640 across the semiconductor wafer due to a polarization discontinuity between the channel layer 640 and barrier layer 650. In a similar manner, bias layer 2DEG 612 is formed in the bias layer 601 across the semiconductor wafer due to a polarization discontinuity between the barrier layer 602 and the bias layer 601. As will be described below, channel layer 2DEG 642 and bias layer 2DEG 612 may be fabricated into separate 2DEG “portions”, forming part of semiconductor devices, such as HEMT 200 and HEMT 401. Figure 6b illustrates a second process step 600b in which second 2DEG 212 has been formed in a portion of the bias layer 601. As described above, the interface of the bias layer 601 and barrier layer 602 may be defected to provision portions of the bias layer 601 which do and do not comprise a 2DEG. For example, bias layer 601 comprises a first portion 601a comprising the 2DEG 212 and a second portion 601b, which does not comprise a 2DEG. In some examples, the interface between the barrier layer 602 and the second portion 601b of the bias layer 601 may be configured to become defective resulting in the removal of a 2DEG in the second portion 601b of the bias layer 601. In one example, ions may be implanted into the bias layer 601 or the barrier layer 602 to form defects at the interface between bias layer 601 and the barrier layer 602 at the second portion 601b. The defects formed by the ions result in a 2DEG being removed from the second portion 601 b. In some examples, the ions may comprise H, He, B or N.

[0069] As will be described in more detail below, the removal of a 2DEG from the second portion 601b may thus provision an area for the formation of a semiconductor device without a biasing 2DEG, such as HEMT 401. In some examples, a mask may thus be formed which is used to provision portions of the bias layer 601 in which the 2DEG is removed. For example, ions may be fired towards the bias layer 601 through the mask, which penetrate through the barrier layer 650 and channel layer 640, and may become implanted in either the barrier layer 602 or bias layer 601 to result in the removal of the 2DEG in a portion of the bias layer 601 , such as second portion 601b.

[0070] Figure 6c illustrates a third process step 600c in which a dividing region 402 is formed in the semiconductor wafer.

[0071] Dividing region 402 is configured to divide nucleation layer 620, buffer layer 630, bias layer 601 , barrier layer 602, channel layer 640 and barrier layer 650 into a first set of semiconductor device layers comprising nucleation layer 120, buffer layer 130, bias layer 210, barrier layer 220, channel layer 140 and barrier layer 150 for HEMT 200, and a second set of semiconductor device layers comprising nucleation layer 420, buffer layer 430, bias layer 440, barrier layer 450, channel layer 460 and barrier layer 470 for HEMT 400.

[0072] In some examples, the dividing region 402 may comprise ions implanted into a section of the nucleation layer 620, buffer layer 630, bias layer 601 , barrier layer 602, channel layer 640 and barrier layer 650. In a similar manner to that described above, a mask may be formed to provision the dividing region 402, and ions may be implanted into the semiconductor wafer, through the mask, to form the dividing region 402. In some examples, the ions may comprise H, He, B or N.

[0073] Figure 6d illustrates a fourth process step 600d in which bias contact 230 is formed. In some examples, bias contact 230 may be formed by etching a via through barrier layer 150, channel layer 140 and barrier layer 220. In some examples, a mask may be formed to form the via. Bias contact 230 may subsequently be deposited into the via. In some examples, bias contact material may be deposited through a mask to form the bias contact 230.

[0074] Figure 6e illustrates a fifth process step 600e in which source contact 160, drain contact 170 and gate contact 180 are formed to form HEMT 200. Additionally, source contact 492, drain contact 494 and gate contact 490 for formed to form HEMT 401. Source contacts 160, 492, drain contacts 170, 494 and gate contact 180, 490 may be formed using any suitable etching and deposition technique, as one skilled in the art would readily understand.

[0075] Figure 7 is a flowchart 700 illustrating process steps in a method of forming a semiconductor structure. The method 700 comprises, in a first step 710, forming a first channel layer. The method 700 further comprises, in a second step 720, forming a first barrier layer configured to induce a first two-dimensional electron gas (2DEG) in the first channel layer. The method 700 further comprises, in a third step 730, forming a source contact and a drain contact, wherein the first 2DEG is configurable to form a channel between the source contact and the drain contact. The method 700 further comprises, in a fourth step 740, forming a gate contact configured to apply a first voltage to the first 2DEG, to modulate the first 2DEG. The method 700 further comprises, in a fifth step 750, forming a first bias layer. The method 700 further comprises, in a sixth step 760, forming a second barrier layer configured to induce formation of a second 2DEG in the first bias layer. The method 700 further comprises, in a seventh step 770, forming a bias contact configured to apply a bias voltage to the second 2DEG, to apply an electric field to the first 2DEG.

[0076] The present disclosure further provides a semiconductor device comprising a semiconductor structure according to examples of the present disclosure. In some examples the semiconductor device may comprise a semiconductor device for managing or transferring power. In some examples the semiconductor device may comprise a high electron mobility transistor (HEMT).

[0077] The present disclosure further provides power management device comprising a semiconductor device according to examples of the present disclosure. In some examples the power management device may manage or transfer power for an electronic device for user operation, for example a mobile phone, cell phone, smart phone, tablet computer, wearable computer such as a watch, or similar. In some examples the power management device may comprise a charging device such as a charger, an adapter, a wireless charger, or similar for charging a battery or on-board power source of an electronic device. In some examples the power management device may comprise a power supply housed in an electronic device for user operation, such as a power converter, for example a DC-DC converter, an AC-DC converter, a DC-AC converter or similar.

[0078] The present disclosure further provides an electronic device comprising a power management device according to examples of the present disclosure. In some examples the electronic device may comprise an electronic device for user operation. In some examples the electronic device may comprise a communication device such as a mobile telephone, smartphone or similar. In some examples the electronic device may comprise handheld computing device, such as a tablet or similar. In some examples the electronic device may comprise a visual display device, such as a television, a monitor or similar. In some examples the electronic device may comprise a wearable device, such as a smartwatch, smart glasses, or similar. In some examples the electronic device may comprise a gaming device such as a games console, or similar. In some examples the electronic device may comprise a headset such as a virtual reality (VR) headset, an augmented reality (AR) headset, or similar. In some examples the electronic device may comprise an audio accessory device, such as headphones, earphones, wireless headphones, true wireless headphones, earbuds, or similar. In some examples the electronic device may comprise an appliance such as a household appliance, for example a refrigerator or a washing machine, or similar.

[0079] It should be noted that the above-mentioned embodiments illustrate rather than limit the idea, and that those skilled in the art will be able to design many alternative embodiments without departing from the scope of the appended claims. The word “comprising” does not exclude the presence of elements or steps other than those listed in a claim, “a” or “an” does not exclude a plurality, and a single processor or other unit may fulfil the functions of several units recited in the claims. Any reference signs in the claims shall not be construed so as to limit their scope.

Claims

CLAIMS1. A semiconductor structure (200) comprising: a first channel layer (140); a first barrier layer (150) configured to induce a first two-dimensional electron gas, 2DEG (142), in the first channel layer (140); a source contact (160) and a drain contact (170), wherein the first 2DEG (142) is configurable to form a channel between the source contact (160) and the drain contact (170); a gate contact (180) configured to apply a first voltage to the first 2DEG, to modulate the first 2DEG; a first bias layer (210); a second barrier layer (220) configured to induce formation of a second 2DEG (212) in the first bias layer (210); and a bias contact (230) configured to apply a bias voltage to the second 2DEG (212), to apply an electric field to the first 2DEG (142).

2. The semiconductor structure (200) according to claim 1 wherein the first voltage comprises a threshold voltage and wherein the application of the electric field to the first 2DEG (142) is configured to set the threshold voltage, wherein the threshold voltage is a positive.

3. The semiconductor structure (200) according to any preceding claim wherein the application of the electric field to the first 2DEG (142) is configured to suppress carrier movement from the first 2DEG (142) towards the second 2DEG (212).

4. The semiconductor structure (200) according to any preceding claim wherein the first bias layer (210) and / or the second barrier layer (220) is doped.

5. The semiconductor structure (200) according to any preceding claim wherein the channel layer (140) and barrier layer (150) comprise lll-N semiconductor material.

6. The semiconductor structure (200) according to any preceding claim wherein the first 2DEG (142) is along a first axis; and the second 2DEG (212) is along a second axis, in a different plane from the first axis; and wherein the first axis is angled relative to the second axis, wherein the angle is non-zero.

7. The semiconductor structure (200) according to claim 6 wherein the first axis and the second axis intersect a third axis normal to the first axis; and wherein the third axis runs through the gate contact (180).

8. The semiconductor structure (200) according to any preceding claim wherein the source contact (160), the drain contact (170) and the gate contact (180) are along a first contact axis and the bias contact (230) is along a second contact axis, angled relative to the first contact axis, wherein the angle is non-zero; and wherein the gate contact (180) and the bias contact (230) are along a second contact axis, wherein the first contact axis and the second contact axis intersect at the gate contact (180).

9. The semiconductor structure (200) according to claim 8 wherein the second contact axis is normal to the first contact axis.

10. The semiconductor structure (200) according to any preceding claim further comprising: a second channel layer (340); a third barrier layer (350) configured to induce a third 2DEG (342) in the second channel layer (340); and wherein the bias contact (230) is configured to apply the bias voltage to the second 2DEG (212), to apply an electric field to the third 2DEG (342).11 . A semiconductor structure (200) according to any preceding claim wherein the first channel layer (140) comprises a first portion comprising the first 2DEG (142) and a second portion (460) comprising a fourth 2DEG (462), and further comprising: a second source contact (492); a second drain contact (494), wherein the fourth 2DEG (462) is configured to form a channel between the second source contact (492) and the second drain contact (494); a second gate contact (490) configured to apply a second voltage to the fourth 2DEG (462), to modulate the fourth 2DEG (462); wherein the second 2DEG (212) extends under the first 2DEG (142) and does not extend under the fourth 2DEG (462).

12. The semiconductor structure (200) according to claim 11 wherein the second voltage comprises a second threshold voltage, wherein the second threshold voltage is a negative voltage.

13. The semiconductor structure (200) according to claim 11 or 12 wherein the first bias layer (210) comprises a first portion under the first gate contact (180) and a second portion (440) under the second gate contact (490); and wherein the second portion (440) comprises ions.

14. The semiconductor structure (200) according to any of claims 11-13 wherein the second barrier layer (220) comprises a first barrier portion under the first gate contact (180) and a second barrier portion (450) under the second gate contact (490); and wherein the second barrier portion (450) comprises ions.

15. A semiconductor device comprising the semiconductor structure (200) according to any preceding claim.

16. A power management device comprising the semiconductor device (200) according to claim 15.

17. An electronic device comprising the power management device according to claim 16.

18. A method of forming a semiconductor structure (200) comprising: forming a first channel layer (140); forming a first barrier layer (150) configured to induce a first two- dimensional electron gas (2DEG 142) in the first channel layer (140); forming a source contact (160) and a drain contact (170), wherein the first 2DEG (142) is configurable to form a channel between the source contact (160) and the drain contact (170); forming a gate contact (180) configured to apply a first voltage to the first 2DEG (142), to modulate the first 2DEG (142); forming a first bias layer (210); forming a second barrier layer (220) configured to induce formation of a second 2DEG (212) in the first bias layer (210); and forming a bias contact (230) configured to apply a bias voltage to the second 2DEG (212), to apply an electric field to the first 2DEG (142).

19. The method according to claim 18 wherein forming the first bias layer (210) comprises forming a first portion comprising the second 2DEG (212) and forming a second portion (440) that does not comprise the second 2DEG.

20. The method according to claim 19 wherein forming the second portion (440) comprises implanting ions into the first bias layer (210) or implanting ions into the second barrier layer (450).

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