Common mode stable multi-level output stages

Abstract

A multi-level output stage includes a mid-switch switching stage electrically coupled between a first power rail and a reference node, a floating power supply configured generate a second power rail and a third power rail, a first half-bridge switching stage electrically coupled between the third power rail and the second power rail, and a second half-bridge switching stage electrically coupled between the third power rail and the second power rail. The mid-switch switching stage is configured to generate a differential output signal having a first peak-to-peak magnitude. Each of the second power rail and the third power rail is at a different electric potential than the reference node during operation of the multi-level output stage. The first and second half-bridge switching stages and a mid-switch are configured to collectively generate a differential output signal having a second peak-to-peak magnitude that is different from the first peak-to-peak magnitude.

Description

COMMON MODE STABLE MULTI-LEVEL OUTPUT STAGESCROSS-REFERENCE TO RELATED APPLICATION

[0001] This application claims priority to U.S. Provisional Patent Application No. 63 / 661,010, “COMMON MODE STABLE MULTI-LEVEL OUTPUT STAGES”, filed June 17, 2024, the disclosure of which is hereby incorporated by reference in its entirety.BACKGROUND

[0002] An output stage is used, for instance, to generate an output signal for driving a load, such as a speaker or a motor, based on an input signal. For example, an output stage configured as a class-D amplifier may generate an output signal for driving a speaker based on an audio input signal. As another example, an output stage configured as a motor drive may be configured to generate an output signal resembling a sine wave based on an input signal specifying a desired motor drive voltage and frequency. Many output stages are configured to generate a differential output signal, instead of a single-ended output signal, to maximize output signal magnitude.BRIEF DESCRIPTION OF THE DRAWINGS

[0003] FIG. 1 is a schematic diagram of an electrical environment including a multilevel output stage, according to an embodiment.

[0004] FIG. 2 is a schematic diagram of an embodiment of the FIG. 1 electrical environment where switching devices are implemented by transistors.

[0005] FIG. 3 is a graph of differential output voltage versus time illustrating one example of operation of the FIG. 1 multi-level output stage.

[0006] FIG. 4 is a graph of voltage at a first output node in the operating example of FIG. 3.

[0007] FIG. 5 is a graph of voltage at a second output node in the operating example of FIG. 3.

[0008] FIG. 6 is a schematic diagram of one embodiment of a floating power supply of the FIG. 1 multi-level output stage.

[0009] FIG. 7 includes four graphs collectively illustrating one example of operation of charge transfer circuitry of the FIG. 6 floating power supply.

[0010] FIG. 8 is a schematic diagram of one embodiment of the FIG. 6 floating power supply where a current control device is embodied by a transistor and control circuitry is embodied by an error amplifier and resistors.

[0011] FIG. 9 is a schematic diagram of an electrical environment including an embodiment of the FIG. 1 multi-level output stage 100 which includes a modulator and a digital-to-analog converter that are floating with respect to a reference node.

[0012] FIG. 10 is a schematic diagram of an electrical environment including an embodiment of the FIG. 1 multi-level output stage 100 which includes a modulator and a digital-to-analog converter that are electrically referenced to a reference node.

[0013] FIG. 11 is a schematic diagram of an alternate embodiment of the FIG. 1 electrical environment including a multi-level output stage with a booster.

[0014] FIG. 12 is a schematic diagram of an alternate embodiment of the FIG. 1 electrical environment including a multi-level output stage configured to generate second and third power rails from a first power rail.

[0015] FIG. 13 is a schematic diagram of one possible embodiment of a floating power supply of the FIG. 12 multi-level output stage.

[0016] FIG. 14 is a schematic diagram of an alternate embodiment of the FIG. 1 electrical environment including a multi-level output stage supporting additional levels.

[0017] FIG. 15 is a schematic diagram of a third half-bridge switching stage of the FIG. 14 multi-level output stage.

[0018] FIG. 16 is a schematic diagram of a fourth half-bridge switching stage of the FIG. 14 multi-level output stage.

[0019] FIG. 17 is a graph of differential output voltage versus time illustrating one example of operation of the FIG. 14 multi-level output stage.DETAILED DESCRIPTION OF THE EMBODIMENTS

[0020] An output stage may be classified as either a single-level output stage or a multilevel output stage. A single-level output stage is capable of generating an output signal having only one possible non-zero peak-to-peak value. A multi-level output stage, in contrast, is capable of generating an output signal having at least two possible non-zero peak-to-peak values. A multi-level output stage may achieve significant advantages over a single-level output stage. For example, a multi-level output stage is capable generating an output signal with less distortion than an otherwise similar single-level output stage. As another example, a multi-level output stage generally generates ripple current having a smaller magnitude than an otherwise comparable single-level output stage, which promotes low power loss. As an additional example, a multi-level output stage generally requires less filtering than a single- level output stage, which promotes design simplicity, low cost, and small size.

[0021] However, many conventional multi-level output stages capable of generating differential output signals do not maintain a stable common mode output voltage, where common mode output voltage of an output stage is a voltage at each of a first output node of the output stage and a second output node of the output stage when magnitude of a differential signal between the first and second output nodes is zero. Instead, magnitude of common mode output voltage in a multi-level output stage frequently varies according to the peak-to-peak magnitude of a differential output signal between the first output node and the second output node. For example, common mode output voltage may have a small value when a conventional multi-level output stage is generating a differential output signal having a small peak-to-peak magnitude, and the common mode output voltage may have a large value when the conventional multi-level output stage is generating a differential output signal having a large peak-to-peak magnitude. Such variation in common mode output voltage may be problematic. For example, variation in common mode output voltage may cause electromagnetic interference (EMI) between an output stage and other circuitry. As another example, variation in common mode output voltage may cause distortion in a differential output signal generated by an output stage. As a further example, an output stage that exhibits common mode output voltage variation may be unable to quickly respond to a change in an input signal due to need to wait for common mode output voltage to settle before generating a non-zero differential output signal.

[0022] Disclosed herein are new multi-level output stages and associated methods which at least partially overcome the above-discussed drawbacks. The new multi-level output stages are cable of generating a differential output signal having at least two different possible non-zero peak-to-peak magnitudes. Additionally, particular embodiments of the new multilevel output stages are common mode stable, or stated differently, in particular embodiments, magnitude of a common mode output voltage remains constant irrespective of peak-to-peak magnitude of a differential output signal. Consequently, the new multi-level output stages may achieve lower differential output signal distortion, lower power loss, better transient response, and / or less need for filtering, than a conventional multi-level output stage capable of generating a differential output signal.

[0023] Particular embodiments of the new multi-level output stages include a midswitch switching stage, a floating power supply, a first half-bridge switching stage, a second half-bridge switching stage, and a modulator. The mid-switch switching stage is electrically coupled between a first power rail and a reference node, and the floating power supply is configured to generate each of a second power rail and a third power rail, where each of thesecond power rail and the third power rail is at a different electric potential than the reference node during operation of the multi-level output stage. Each of the first half-bridge switching stage and the second half-bridge switching stage is electrically coupled between the third power rail and the second power rail. The modulator is configured to control the mid-switch switching stage, the first half-bridge switching stage, and the second half-bridge switching stage such that the multi-level output stage may operate at least in either a first operating mode or a second operating mode. The first operating mode is characterized by the mid-switch switching stage generating a differential output signal having a first peak-to-peak magnitude. The second operating mode is characterized by the first half-bridge switching stage, the second half-bridge switching stage, and a mid-switch of the mid-switch switching stage collectively generating a differential output signal having a second peak-to-peak magnitude that is different from the first peak-to-peak magnitude.

[0024] FIG. 1 is a schematic diagram of an electrical environment 100 including a multi-level output stage 102, an electric power source 104, a load 106, a first filter inductor 108, a second filter inductor 110, a first filter capacitor 112, and a second filter capacitor 114, where multi-level output stage 102 is one embodiment of the new multi-level output stages disclosed herein. Multi-level output stage 102 includes a mid-switch switching stage 116, a floating power supply (FPS) 118, a first half-bridge switching stage (HBSS) 120, a second halfbridge switching stage 122, and a modulator 124. Multi-level output stage 102 may include additional elements without departing from the scope hereof. For example, certain embodiments of multi-level output stage 102, such as discussed below with respect to FIGS. 9 and 10, further include a digital -to-analog converter (DAC).

[0025] Mid-switch switching stage 116 includes a first upper switching device 126, a first lower switching device 128, a second upper switching device 130, a second lower switching device 132, and a mid-switch switching device 134. First upper switching device 126 is electrically coupled between a first power rail 140 and a first output node 136, and first lower switching device 128 is electrically coupled between first output node 136 and a reference node 142. Second upper switching device 130 is electrically coupled between first power rail 140 and a second output node 138, and second lower switching device 132 is electrically coupled between second output node 138 and reference node 142. As such, midswitch switching stage 116 is electrically coupled between first power rail 140 and reference node 142. Mid-switch switching device 134 is electrically coupled between first output node 136 and second output node 138. First upper switching device 126, first lower switching device 128, second upper switching device 130, second lower switching device 132, and mid-switchswitching device 134 are controlled by a control signal 01, a control signal 02, a control signal 03, a control signal 04, and a control signal 05, respectively, as illustrated in FIG. 1. Reference node 142 is depicted as being a ground node, such as a chassis ground node or an earth ground node. However, reference node 142 need not be a ground node. For example, reference node 142 could be at a different electric potential than an earth ground or a chassis ground.

[0026] Floating power supply 118 is electrically coupled to electric power source 104, and electric power source 104 is electrically referenced to reference node 142. Floating power supply 118 may also be electrically coupled to first power rail 140, as illustrated in FIG. 1. Floating power supply 118 is configured to generate a second power rail 144 and a third power rail 146, each of which is at a different electric potential than reference node 142 during operation of multi-level output stage 102. Specifically, second power rail 144 has a voltage VPr2 with respect to reference node 142, third power rail 146 has a voltage Vprs with respect to reference node 142, and magnitude of voltage Vprs is greater than magnitude of voltage Vpr2. First power rail 140 has a voltage Vpriwith respect to reference node 142, and magnitude of voltage VPri is greater than each of magnitude of voltage Vpr2 and magnitude of voltage Vpr3.

[0027] Floating power supply 118 is additionally configured to regulate magnitude of voltage VPr2 and / or magnitude of voltage Vprs to achieve a stable common mode output voltage of multi-level output stage 102. In particular, floating power supply 118 is configured to regulate magnitude of voltage Vpr2 and / or magnitude of voltage Vprs such that a mid-point between magnitude of voltage Vprs and magnitude of voltage Vpr2 is equal to one half of magnitude of voltage Vpri, as expressed by EQN. 1 below. In certain embodiments, floating power supply 118 is further configured so that magnitude of voltage Vpr2 and magnitude of voltage VPrs are as specified in EQNS. 2 and 3 below, where Vpsis voltage across electric power source 104.

[0028] First half-bridge switching stage 120 include a third upper switching device 148 and a third lower switching device 150 which are controlled by a control signal 06 and a control signal 07, respectively. Third upper switching device 148 is electrically coupled between third power rail 146 and first output node 136, and third lower switching device 150 is electricallycoupled between first output node 136 and second power rail 144. Second half-bridge switching stage 122 includes a fourth upper switching device 152 and a fourth lower switching device 154 which are controlled by a control signal 08 and a control signal (09, respectively. Fourth upper switching device 152 is electrically coupled between third power rail 146 and second output node 138, and fourth lower switching device 154 is electrically coupled between second output node 138 and second power rail 144. As such, each of first half-bridge switching stage 120 and second half-bridge switching stage 122 is electrically coupled between third power rail 146 and second power rail 144. While first half-bridge switching stage 120 and second half-bridge switching stage 122 are referred to herein as being separate elements, it is understood that first half-bridge switching stage 120 and second half-bridge switching stage 122 could alternately be collectively referred to as a single H-bridge switching stage.

[0029] In this document, a switching device operates in its “on-state” when the switching device is being controlled to operate in its conductive state, and a switching device operates in its “off-state” when the switching device is being controlled to operate in its non- conductive state. Each switching device of multi-level output stage 102 is embodied, for example, by one or more transistors, such as one or more field effect transistors (FETs), one or more bipolar junction transistors (BJTs), and / or one or more insulated gate bipolar junction transistors (IGBTs). For example, FIG. 2 is a schematic diagram of an electrical environment 200, which is an embodiment of electrical environment 100 (FIG. 1) where multi-level output stage 102 is embodied by a multi-level output stage 202. Mid-switch switching stage 116, first half-bridge switching stage 120, and second half-bridge switching stage 122 are embodied by a mid-switch switching stage 216, a first half-bridge switching stage 220, and a second halfbridge switching stage 222, respectively, in multi-level output stage 202. First upper switching device 126, first lower switching device 128, second upper switching device 130, and second lower switching device 132 are embodied by an N-channel metal oxide semiconductor field effect transistor (NMOS FET) 226, an NMOS FET 228, an NMOS FET 230, and an NMOS FET 232, respectively, in mid-switch switching stage 216. Additionally, mid-switch switching device 134 is embodied by a combination of an NMOS FET 234 and an NMOS FET 235 electrically coupled in series between first output node 136 and second output 138. While FIG. 2 depicts each of NMOS FET 234 and NMOS FET 235 being controlled by control signal 5, NMOS FET 234 and NMOS FET 235 could alternately be controlled by different respective control signals as long the two NMOS FETs operate in synchronicity, i.e., at any given time,both NMOS FETs are in their respective on-states or both NMOS FETs are in their respective off-states.

[0030] Third upper switching device 148 and third lower switching device 150 are embodied by an NMOS FET 248 and an NMOS FET 250, respectively, in first half-bridge switching stage 220. Fourth upper switching device 152 and fourth lower switching device 154 are embodied by an NMOS FET 252 and an NMOS FET 254, respectively, in second half- bridge switching stage 222. One or more of the NMOS FETs of multi-level output stage 202 could be replaced with a different type of transistor, such as a P-channel metal oxide semiconductor field effect transistor (PMOS FET) or a BJT.

[0031] Referring again to FIG. 1, first filter inductor 108 is electrically coupled between first output node 136 and a first filter node 156, and first filter capacitor 112 is electrically coupled between first filter node 156 and reference node 142. Second filter inductor 110 is electrically coupled between second output node 138 and a second filter node 158, and second filter capacitor 114 is electrically coupled between second filter node 158 and reference node 142. Load 106 is electrically coupled between first filter node 156 and second filter node 158. As such, load 106 is electrically between first output node 136 and second output node 138 via first filter inductor 108 and second filter inductor 110. First filter inductor 108, second filter inductor 110, first filter capacitor 112, and second filter capacitor 114 are omitted in some alternate embodiments of electrical environment 100, and in these alternate embodiments, load 106 is directly electrically coupled between first output node 136 and second output node 138. By way of example and not limitation, load 106 may include a transducer (e.g., a speaker) or a motor.

[0032] Modulator 124 is configured to control each of mid-switch switching stage 116, first half-bridge switching stage 120, and second half-bridge switching stage 122 as a function of an analog input signal Ain, where analog input signal Ainis, for example, a differential signal. Specifically, modulator 124 is configured to generate control signals 01, 02, 03, 04, 05, 06, 07, 08, and 09 in response to analog input signal Ain, to generate a differential output signal Vd between first output node 136 and second output node 138 for driving load 106 in response to analog input signal Ain. Differential output signal v^is a difference between (i) a voltage voi at first output node 136 with respect to reference node 142 and (i) a voltage V02 at second output node 138 with respect to reference node 142. Differential output signal v^is a square wave representation of analog input signal Ain. For example, in certain embodiments, modulator 124 generates differential output signal v^based on analog input signal Ainusing apulse width modulation (PWM) technique where width of pulses of differential output signal Vd are proportional to magnitude of analog input signal Ain. As another example, in certain other embodiments, modulator 124 generates differential output signal Vdiff based on analog input signal Ainusing a pulse frequency modulation (PFM) technique where frequency of pulses of differential output signal v^is inversely proportional to magnitude of analog input signal Am. As an additional example, in some other embodiments, modulator 124 generates differential output signal v^based on analog input signal Ainusing a pulse density modulation (PDM) technique where density of pulses of differential output signal v^is proportional to magnitude of analog input signal Ain.

[0033] Additionally, modulator 124 is configured to cause multi-level output stage 102 to operate in either a first operating mode or a second operating mode, where peak-to-peak magnitude of differential output signal v^varies between the two operating modes. Peak-to- peak magnitude of differential output signal v^is greater in the first operating mode than in the second operating mode. In some embodiments, modulator 124 is configured to cause multilevel output stage 102 to switch between the first operating mode and the second operating mode as a function of magnitude of power provided to load 106 by multi-level output stage 102. For example, in certain embodiments, modulator 124 is configured to (i) cause multi-level output stage 102 to operate in the first operating mode when magnitude of power delivered to load 106 is above a threshold value and (ii) cause multi-level output stage 102 to operate in the second operating mode when magnitude of power delivered to load 106 is below the threshold value.

[0034] The first operating mode of multi-level output stage 102 is characterized by modulator 124 (i) causing mid-switch switching stage 116 to generate differential output signal Vdiff having a peak-to-peak magnitude Vppiof 2*I r7, i.e., twice the magnitude of the voltage between first power rail 140 and reference node 142, and (ii) causing each of first half-bridge switching stage 120 and second half-bridge switching stage 122 to be inactive. For example, FIG. 3 is a graph 300 of differential output signal v^versus time illustrating one example of operation of multi-level output stage 102 in each of a first time period Ti and a second time period T2. First time period Ti corresponds to multi-level output stage 102 operating in the first operating mode, and second time period Z2, discussed below, corresponds to multi-level output stage 102 operating in the second operating mode. It is understood that multi-level output stage 102 may operate in a manner other than that illustrated in the FIG. 3 example. For instance, while FIG. 3 depicts differential output signal Vdiff having a value of zero between consecutivepulses, differential output signal Vdiff could alternately directly transition between a positive value and a negative value without an intervening value of zero.

[0035] Differential output signal Vdiff may have three possible values in the first operating mode of multi-level output stage 102. Specifically, differential output signal v^may have a positive value (see, e.g., time period Taof FIG. 3), a value of zero (see, e.g., time period Tb of FIG. 3), or a negative value (see, e.g., time period Tcof FIG. 3), in the first operating mode. The positive value of differential output signal Vdiff in the first operating mode is characterized by (i) modulator 124 causing each of first upper switching device 126 and second lower switching device 132 to operate in its respective on-state and (ii) modulator 124 causing each of first lower switching device 128, second upper switching device 130, and mid-switch switching device 134 to operate in its respective off-state, resulting in differential output signal Vd being equal to Vpri. The negative value of differential output signal v^in the first operating mode is characterized by (i) modulator 124 causing each of second upper switching device 130 and first lower switching device 128 to operate in its respective on-state and (ii) modulator 124 causing each of first upper switching device 126, second lower switching device 132, and midswitch switching device 134 to operate in its respective off-state, resulting in differential output signal Vdiff being equal to -Vpri. The zero value of differential output signal v^ in the first operating mode is characterized by (i) modulator 124 causing mid-switch switching device 134 to operate in its on-state and (ii) modulator 124 causing each of first upper switching device 126, first lower switching device 128, second upper switching device 130, and second lower switching device 132 to operate in its respective off-state, resulting in differential output signal Vdiff being zero. Modulator 124 further causes each of third upper switching device 148, third lower switching device 150, fourth upper switching device 152, and fourth lower switching device 154 to operate in its respective off-state in the first operating mode, resulting in each of first half-bridge switching stage 120 and second half-bridge switching stage 122 being disabled.

[0036] The second operating mode of multi-level output stage 102 is characterized by (i) modulator 124 causing first half-bridge switching stage 120, second half-bridge switching stage 122, and mid-switch switching device 134 to collectively generate differential output signal Vdiff having a peak-to-peak of magnitude VPP2 of 2*(Ir5 - Vpr2) i.e., twice the magnitude of the voltage between third power rail 146 and second power rail 144, and (ii) modulator 124 causing each first upper switching device 126, first lower switching device 128, second upper switching device 130, and second lower switching device 132 to operate in its respective off- state. Differential output signal v^may also have three possible values in the second operatingmode of multi-level output stage 102. Specifically, differential output signal v^may have a positive value (see, e.g., time period Ta of FIG. 3), a value of zero (see, e.g., time period Teof FIG. 3), or a negative value (see, e.g., time period 7) of FIG. 3), in the second operating mode. The positive value of differential output signal Vdiff in the second operating mode is characterized by (i) modulator 124 causing each of third upper switching device 148 and fourth lower switching device 154 to operate in its respective on-state and (ii) modulator 124 causing each of third lower switching device 150, fourth upper switching device 152, and mid-switch switching device 134 to operate in its respective off-state, resulting in differential output signal Vd being equal to Vprs - Vpr2. The negative value of differential output signal v^in the second operating mode is characterized by (i) modulator 124 causing each of fourth upper switching device 152 and third lower switching device 150 to operate in its respective on-state and (ii) modulator 124 causing each of third upper switching device 148, fourth lower switching device 154, and mid-switch switching device 134 to operate in its respective off-state, resulting in differential output signal v^being equal to -(Vpr3 - Vpr2). The zero value of differential output signal v<y in the second operating mode is characterized by (i) modulator 124 causing midswitch switching device 134 to operate in its on-state and (ii) modulator 124 causing each of third upper switching device 148, third lower switching device 150, fourth upper switching device 152, and fourth lower switching device 154 to operate in its respective off-state, resulting in differential output signal v^being zero.

[0037] Importantly, in particular embodiments, a common mode output voltage of multi-level output stage 102 is the same in each of the first operating mode and the second operating mode, where common mode output voltage is a common voltage at each of first output node 136 and second output node 138 when differential output signal Vdiff is zero. Specifically, as discussed above, in particular embodiments, floating power supply 118 is configured to regulate magnitude of voltage Vpr2 and / or magnitude of voltage Vprs such that a mid-point between magnitude of voltage Vprs and magnitude of voltage Vpr2 is equal to one half of magnitude of voltage Vpri, which results in magnitude of common mode output voltage being one half of magnitude of voltage Vpriin each of the first and second operating modes of multilevel output stage 102, assuming magnitude of differential output signal v^ is symmetrical with respect to Vpri / 2. As such, these embodiments are common mode stable.

[0038] For example, FIG. 4 is a graph 400 of voltage voi versus time and FIG. 5 is a graph 500 of voltage V02 versus time in the same example of operation of multi-level output stage 102 as that depicted in FIG. 3. As discussed above, voltage voi is voltage at first output node 136 with respect to reference node 142, and voltage V02 is voltage at second output node138 with respect to reference node 142. As evident when comparing FIGS. 4 and 5 to FIG. 3, each of voltage voi and voltage v(>2 has a magnitude of Vpri / 2 when magnitude of differential output signal v^is zero, during both of time period Ti and time period T2. As such, common mode output voltage of multi-level output stage 102 is Vpri!2 in both of the first operating mode of multi-level output stage 102 and the second operating mode of multi-level output stage 102.

[0039] Referring again to FIG. 1, floating power supply 118 can have any configuration as long as it is capable of generating second power rail 144 and third power rail 146 as discussed above. Discussed below with respect to FIGS. 6-8 are several example embodiments of floating power supply 118. It is understood, though, that floating power supply 118 is not limited to the example embodiments of FIGS. 6-8.

[0040] FIG. 6 is a schematic diagram of a floating power supply 600, which is one possible embodiment of floating power supply 118 (FIG. 1). Floating power supply 600 includes a base capacitor 602, a floating capacitor 604, charge transfer circuitry 606, a current control device 608, control circuitry 610, and an optional capacitor 612. Base capacitor 602 is electrically coupled between second power rail 144 and reference node 142, and floating capacitor 604 is electrically coupled between third power rail 146 and second power rail 144. Optional capacitor 612, when present, is electrically coupled between first power rail 140 and third power rail 146. Current control device 608 is electrically coupled between first power rail 140 and second power rail 144. Control circuitry 610 is electrically coupled to each of second power rail 144 and third power rail 146 via feedback connections 614, and control circuitry 610 is configured to generate a control signal scfor controlling current control device 608 to regulate a magnitude of voltage Vpr2. Specifically, control circuitry 610 generates control signal scto control operation of current control device 608 and thereby regulate magnitude of a current icflowing through current control device 608 from first power rail 140 to second power rail 144, to control voltage across base capacitor 602 and thereby regulate magnitude of voltage Vpr2. In certain embodiments, control circuitry 610 is configured to control current control device 608 to regulate magnitude of voltage Vpr2 such that magnitude voltage VPr2 is defined by EQN. 2 above.

[0041] Charge transfer circuitry 606 is configured to charge floating capacitor 604 from electric power source 104 such that magnitude of a voltage across floating capacitor 604 is at least substantially equal to voltage Vpsacross electric power source 104. Charge transfer circuitry 606 includes a switching device 616, a switching device 618, a switching device 620, a switching device 622, a flying capacitor 624, and switching control circuitry 626. While switching control circuitry 626 is illustrated as being a discrete element, switching controlcircuitry 626 could be part of one or more other elements without departing from the scope hereof. Switching device 616 is electrically coupled between a positive node 632 of electric power source 104 and a first flying node 628, and switching device 620 is electrically coupled between first flying node 628 and third power rail 146. Switching device 618 is electrically coupled between reference node 142 and second flying node 630, and switching device 622 is electrically coupled between second flying node 630 and second power rail 144. Flying capacitor 624 is electrically coupled between first flying node 628 and second flying node 630. Switching device 616, switching device 618, switching device 620, and switching device 622 are controlled by a control signal <D10, a control signal <D11, a control signal 012, and a control signal 013, respectively.

[0042] Switching control circuitry 626 is configured to generate each of control signal O10, control signal Oi l, control signal 012, and control signal 013 to control operation of charge transfer circuitry 606. Specifically, switching control circuitry 626 controls the switching devices of charge transfer circuitry 606 such that charge transfer circuitry 606 operates in the following repeating sequence: (i) charge transfer circuitry 606 transfers charge from electric power source 104 to flying capacitor 624 and (ii) charge transfer circuitry 606 transfers charge from flying capacitor 624 to floating capacitor 604. For example, FIG. 7 includes graphs 700, 702, 704, and 706 collectively illustrating one example of operation of charge transfer circuitry 606. Graph 700 is of magnitude of control signal 010 versus time, and graph 702 is of magnitude of control signal 11 versus time. Graph 704 is of magnitude of control signal 12 versus time, and graph 706 is of magnitude of control signal 013 versus time. Graphs 700, 702, 704, and 706 have a common time base, and graphs 700, 702, 704, and 706 assume that (i) each switching device is in its on-state when its respective control signal is asserted and (ii) each switching device is in its off-state when its respective control signal is de-asserted. As illustrated in FIG. 7, charge transfer circuitry 606 operates in the following repeating sequence (i) each of switching device 616 and switching device 618 operates in its respective on-state while each of switching device 620 and switching device 622 operates in its respective off-state, and (ii) each of switching device 620 and switching device 622 operates in its respective on-state while each of switching device 616 and switching device 618 operates in its respective off-state. Charge transfer circuitry 606 has a switching frequency of Fct = MTct in the FIG. 7 example, where switching frequency Fct need not be the same as a switching frequency of mid-switch switching stage 116 or a switching frequency of each of first halfbridge switching stage 120 and second half-bridge switching stage 122.

[0043] FIG. 8 is a schematic diagram of a floating power supply 800, which is an embodiment of floating power supply 600 (FIG. 6) where (i) current control device 608 is embodied by an NMOS FET 808 and (ii) control circuitry 610 is embodied by control circuitry 810. NMOS FET 808 includes a drain Z>, and source S, and a gate G. Drain D is electrically coupled to first power rail 140, and source S is electrically coupled to second power rail 144. Control circuitry 810 includes an error amplifier 832, a resistor 834, and a resistor 836. An output of error amplifier 832 is electrically coupled to gate G of NMOS FET 808 such that error amplifier 832 drives gate G of NMOS FET 808. An inverting input of error amplifier 832 is electrically coupled to a divider node 838, and a non-inverting input of error amplifier 832 is electrically coupled to a reference voltage Vref Resistor 834 is electrically coupled between third power rail 146 and divider node 838, and resistor 836 is electrically coupled between divider node 838 and second power rail 144. It can be determined that control circuitry 810 and NMOS FET 808 will collectively regulate magnitude of voltage Vpr2 such that magnitude of voltage Vpr2 is defined by EQN. 2 above when (i) magnitude of reference voltage Fre / is equal to VpriH and (ii) resistor 834 and resistor 836 have a common resistance value.

[0044] Changes may be made to floating power supply 800. For example, NMOS FET 808 could be replaced with a different type of transistor, with appropriate changes to control circuitry 810. As another example, error amplifier 832 could be replaced with (i) a transconductance amplifier and (ii) an integration circuitry electrically coupled to the output of the transconductance amplifier.

[0045] Referring again to FIG. 1, modulator 124 is electrically referenced, for example, to either second power rail 144 or to reference node 142. For example, FIG. 9 is a schematic diagram of an electrical environment 900 including a multi-level output stage 902, where multilevel output stage 902 is an embodiment of multi-level output stage 102 including a modulator 924 and a digital-to-analog converter 960 that are each electrically referenced to second power rail 144, such that modulator 924 and digital-to-analog converter 960 are floating with respect to reference node 142. Details of mid-switch switching stage 116, first half-bridge switching stage 120, and second half-bridge switching stage 122 are not shown in FIG. 9 for illustrative clarity. Additionally, first filter capacitor 112, second filter capacitor 114, and load 106 are not shown in FIG. 9. Modulator 924 is an embodiment of modulator 124, and digital-to-analog converter 960 is configured to generate analog input signal Ainby converting a digital input signal Dm from digital form to analog form. Modulator 924 and digital-to-analog converter 960 are electrically powered from third power rail 146. A feedback resistor 962 electrically couples a positive analog node 964 to first output node 136, and a feedback resistor 966electrically couples a negative analog node 968 to second output node 138, where positive analog node 964 and negative analog node 968 collectively electrically couple an output of digital-to-analog converter 960 to an input of modulator 924. Power dissipation in feedback resistors 962 and 966 is relatively low because solely alternating current flows through these two resistors. Feedback resistor 962 could alternately be electrically coupled between positive analog node 964 and first filter node 156, and feedback resistor 966 could alternately be electrically coupled between negative analog node 968 and second filter node 158.

[0046] FIG. 10 is a schematic diagram of an electrical environment 1000 including a multi-level output stage 1002, where multi-level output stage 1002 is an embodiment of multilevel output stage 102 including a modulator 1024 and a digital-to-analog converter 1060 that are each electrically referenced to reference node 142. Details of mid-switch switching stage 116, first half-bridge switching stage 120, and second half-bridge switching stage 122 are not shown in FIG. 10 for illustrative clarity. Additionally, first filter capacitor 112, second filter capacitor 114, and load 106 are not shown in FIG. 10. Modulator 1024 is an embodiment of modulator 124, and digital-to-analog converter 1060 is configured to generate analog input signal Am by converting a digital input signal Dinfrom digital form to analog form. Modulator 1024 and digital-to-analog converter 1060 are directly electrically powered from electric power source 104. A first feedback resistor 1062 is electrically coupled between output node 136 and a positive analog node 1064, and a second feedback resistor 1066 is electrically coupled between positive analog node 1064 and reference node 142. A third feedback resistor 1068 is electrically coupled between a negative analog node 1070 and second output node 138, and a fourth feedback resistor 1072 is electrically coupled between negative analog node 1070 and reference node 142. Positive analog node 1064 and negative analog node 1070 collectively electrically couple an output of digital-to-analog converter 1060 to an input of modulator 1024. Power dissipation in first feedback resistor 1062, second feedback resistor 1066, third feedback resistor 1068, and fourth feedback resistor 1072 is relatively high because direct current, as well as alternating current flows, flows through these resistors. The direct current flowing through first feedback resistor 1062 and second feedback resistor 1066 is due to the series combination of these two resistors being subject to the common mode output voltage of multilevel output stage 1002. Similarly, the direct current flowing through third feedback resistor 1068 and fourth feedback resistor 1072 is due to the series combination of these two resistors being subject to the common mode output voltage of multi-level output stage 1002.

[0047] Some alternate embodiments of multi-level output stage 102 further include circuitry for generating first power rail 140. For example, FIG. 11 is a schematic diagram ofan electrical environment 1100 including a multi-level output stage 1102 in place of multi-level output stage 102. Multi-level output stage 1102 is an alternate embodiment of multi-level output stage 102 further including a booster 1160 for generating first power rail 140 from electric power source 104. Booster 1160 includes, for example, an inductor-based switching converter, such as a boost converter, or a switched-capacitor converter.

[0048] Some alternate embodiments of multi-level output stage 102 do not require electric power source 104 to generate third power rail 146. For example, FIG. 12 is a schematic diagram of an electrical environment 1200, which is an alternate embodiment of electrical environment 100 where (i) multi-level output stage 102 is replaced with a multi-level output stage 1202 and (ii) electric power source 104 is omitted. Multi-level output stage 1202 is an alternate embodiment of multi-level output stage 102 where floating power supply 118 is replaced with a floating power supply 1218 that is configured to generate each of the second power rail 144 and third power rail 146 from first power rail 140. Floating power supply 1218 is electrically reference to reference node 142.

[0049] FIG. 13 is a schematic diagram of a floating power supply 1300, where floating power supply 1300 is one possible embodiment of floating power supply 1218 of FIG. 12. Floating power supply 1300 includes a floating capacitor 1302, a first current control device 1304, a second current control device 1306, first control circuitry 1308, and second control circuitry 1310. Floating capacitor 1302 is electrically coupled between third power rail 146 and second power rail 144, and first current control device 1304 is electrically coupled between second power rail 144 and reference node 142. Second current control device 1306 is electrically coupled between first power rail 140 and third power rail 146. Although first control circuitry 1308 and second control circuitry 1310 are illustrated as being discrete elements, they could be partially or completely combined with each other and / or with one or more other elements.

[0050] First current control device 1304 and first control circuitry 1308 collectively form a first linear regulator configured to regulate magnitude of voltage Vpr2, e.g., to regulate magnitude of voltage Vpr2 such that magnitude of voltage Vpr2 is governed by EQN. 4 below, where AFpris a desired difference between magnitude of voltage Vprs and magnitude of voltage VPr2. In particular, first current control device 1304 is configured to control magnitude of a current iciflowing therethrough from second power rail 144 to reference node 142 in response to a control signal scigenerated by first control circuitry 1308, and first control circuitry 1308 is configured to generate control signal scito achieve desired regulation of voltage Vpr2. First current control device 1304 includes, for example, one or more transistors.

[0051] Second current control device 1306 and second control circuitry 1310 collectively form a second linear regulator configured to regulate magnitude of voltage Vpr3, e.g., to regulate magnitude of voltage Vprs such that magnitude of Vprs is governed by EQN. 5 below. In particular, second current control device 1306 is configured to control magnitude of a current iC2 flowing therethrough from first power rail 140 to second power rail 144 in response to a control signal sC2 generated by second control circuitry 1310, and second control circuitry 1310 is configured to generate control signal sC2 to achieve desired regulation of voltage Vpr3. Second current control device 1306 includes, for example, one or more transistors. It should be noted that a midpoint between magnitude of voltage Vprs and a magnitude of voltage Vpr2 will be equal to one half of magnitude of voltage Vpriwhen Vprs and Vpr2 are governed by EQNS. 4 and 5, respectively, to realize stable common mode output voltage, as discussed above.

[0052] Any of the multi-level output stages discussed above could be modified such they are capable of generating a differential output signal having three or more possible nonzero peak-to-peak magnitudes, such as by adding one or more additional floating power supplies and associated half-bridge switching stages. For example, FIG. 14 is a schematic diagram of an electrical environment 1400, which is an alternate embodiment of electrical environment 100 (FIG. 1). Electrical environment 1400 differs from electrical environment 100 in that (i) multi-level output stage 102 is replaced with a multi-level output stage 1402 and (ii) electrical environment 1400 further includes a second electric power source 1404. Load 106, first filter inductor 108, second filter inductor 110, first filter capacitor 112, and second filter capacitor 114 are not shown in FIG. 14, although it is understood the electrical environment 1400 may include these elements in a manner analogous to electrical environment 100. A magnitude of a voltage Vps_2 across second electric power source 1404 is different from magnitude of voltage Vpsacross electric power source 104. While not required, the discussion below assumes that magnitude of voltage Vpsis greater than magnitude of voltage Vps_2.

[0053] Multi-level output stage 1402 differs from multi-level output stage 102 in that (i) modulator 124 is replaced with a modulator 1424 and (ii) multi-level output stage 1402 further includes a second floating power supply 1418, a third half-bridge switching stage 1420, and a fourth half-bridge switching stage 1422. Details of mid-switch switching stage 116, first half-bridge switching stage 120, second half-bridge switching stage 122, third half-bridgeswitching stage 1420, and fourth half-bridge switching stage 1422 are not shown in FIG. 14 for illustrative clarity. Second floating power supply 1418 is electrically coupled to second electric power source 1404, and second electric power source 1404 is electrically referenced to reference node 142. Second floating power supply 1418 may also be electrically coupled to first power rail 140, as illustrated in FIG. 14.

[0054] Second floating power supply 1418 is configured to generate a fourth power rail 1444 and a fifth power rail 1446, each of which is at a different electric potential than reference node 142 during operation of multi-level output stage 1402. Specifically, fourth power rail 1444 has a voltage Vpr4 with respect to reference node 142, fifth power rail 1446 has a voltage VPr5 with respect to reference node 142, and magnitude of voltage Vprs is greater than magnitude of voltage VPr4. Second floating power supply 1418 is additionally configured to regulate magnitude of voltage Vpr4 and / or magnitude of voltage Vprs, and while not required, it is anticipated that second floating power supply 1418 will typically be configured to regulate magnitude of voltage Vpr4 and / or magnitude of voltage Vprs such that a mid-point between magnitude of voltage Vprs and magnitude of Vpr4 is equal to one half of magnitude of voltage VPri, to achieve a stable common mode output voltage of multi-level output stage 1402 in a manner analogous to that discussed above with respect to multi-level output stage 102. In certain embodiments, second floating power supply 1418 is further configured so that magnitude of voltage Vpr4 and magnitude of voltage Vprs are as specified in EQNS. 6 and 7 below. ypr4 =Vvr. -Vps_2(EQN 6)Vprs =Vpn +^ps-2(EQN.7)

[0055] Third half-bridge switching stage 1420 is analogous to first half-bridge switching stage 120, and FIG. 15 is a schematic diagram of third half-bridge switching stage 1420. Third half-bridge switching stage 1420 includes a fifth upper switching device 1448 and a fifth lower switching device 1450. Fifth upper switching device 1448 is electrically coupled between fifth power rail 1446 and first output node 136, and fifth lower switching device 1450 is electrically coupled between first output node 136 and fourth power rail 1444. Fifth upper switching device 1448 is controlled by a control signal (DIO, and fifth lower switching device 1450 is controlled by a control signal <D11. Fourth half-bridge switching stage 1422 is analogous to second half-bridge switching stage 122, and FIG. 16 is a schematic diagram of fourth half-bridge switching stage 1422. Fourth half-bridge switching stage 1422 includes a sixth upper switching device 1452 and a sixth lower switching device 1454. Sixth upperswitching device 1452 is electrically coupled between fifth power rail 1446 and second output node 138, and sixth lower switching device 1454 is electrically coupled between second output node 138 and fourth power rail 1444. Sixth upper switching device 1452 is controlled by a control signal 012, and sixth lower switching device 1454 is controlled by a control signal 013.

[0056] Referring again to FIG. 14, modulator 1424 is configured to control each of mid-switch switching stage 116, first half-bridge switching stage 120, second half-bridge switching stage 122, third half-bridge switching stage 1420, and fourth half-bridge switching stage 1422 as a function of analog input signal Ain. Modulator 1424 is similar to modulator 124 except that modulator 1424 is further configured to generate control signal 010, control signal 011, control signal 012, and control signal 013. Modulator 124 is configured to generate control signals 01, 02, 03, 04, 05, 06, 07, 08, 09, 010, Oi l, 012, and 013 in response to analog input signal Ain, to generate a differential output signal v^in response to analog input signal Ain, in a manner analogous to modulator 124. However, modulator 1424 is capable of causing multi-level output stage 1402 to operate in a third operating mode, as well as in the first operating mode and the second operating mode. A peak-to-peak magnitude of differential output signal v^in the third operating mode is different from the respective peak- to-peak magnitudes of differential output signal Vdtff in the first and second operating modes, such that multi-level output stage 1402 may be considered a seven-level output stage. In some embodiments, modulator 1424 is configured to cause multi-level output stage 1402 to switch between the first operating mode, the second operating mode, and the third operating mode as a function of magnitude of power provided to load 106 by multi-level output stage 1402. For example, in certain embodiments, modulator 1424 is configured to (i) cause multi-level output stage 1402 to operate in the first operating mode when magnitude of power delivered to load 106 is above a first threshold value and (ii) cause multi-level output stage 1402 to operate in the second operating mode when magnitude of power delivered to load 106 is between the first threshold value and a second threshold value, and (iii) cause multi-level output stage 1402 to operate in the third operating mode when magnitude of power delivered to load 106 is below the second threshold value.

[0057] The first and second operating modes of multi-level output stage 1402 are like the first and second operating modes of multi-level output stage 102. The third operating mode of multi-level output stage 1402 is characterized by (i) modulator 1424 causing third halfbridge switching stage 1420, fourth half-bridge switching stage 1422, and mid-switchswitching device 134 to collectively generate differential output signal Vdiff having a peak-to- peak of magnitude Vpps of 2* Vpr5 - Vpr4) i.e., twice the magnitude of the voltage between fifth power rail 1446 and fourth power rail 1444, and (ii) modulator 1424 causing each first upper switching device 126, first lower switching device 128, second upper switching device 130, second lower switching device 132, third upper switching device 148, third lower switching device 150, fourth upper switching device 152, and fourth lower switching device 154 to operate in its respective off-state.

[0058] FIG. 17 is a graph 1700 of differential output signal Vdiff versus time illustrating one example of operation of multi-level output stage 1402 in each of a first time period T3, a second time period T4, and a third time period Ts. First time period T3, which is analogous to first time period Ti of FIG. 3, corresponds to multi-level output stage 1402 operating in the first operating mode, and second time period T4, which is analogous to second time period T2 of FIG. 3, corresponds to multi-level output stage 1402 operating in the second operating mode. Third time period T4 corresponds to multi-level output stage 1402 operating the third operating mode. It is understood that multi-level output stage 1402 may operate in a manner other than that illustrated in the FIG. 17 example. For instance, while FIG. 17 depicts differential output signal Vdiff having a value of zero between consecutive pulses, differential output signal Vdiff could alternately directly transition between a positive value and a negative value without an intervening value of zero.

[0059] Differential output signal Vdiff may have three different values in the third operating mode of multi-level output stage 1402. Specifically, differential output signal Vdiff may have a positive value (see, e.g., time period Ti of FIG. 17), a value of zero (see, e.g., time period Th of FIG. 17), or a negative value (see, e.g., time period Tgof FIG. 17), in the third operating mode. The positive value of differential output signal v^in the third operating mode is characterized by (i) modulator 1424 causing each of fifth upper switching device 1448 and sixth lower switching device 1454 to operate in its respective on-state and (ii) modulator 1424 causing each of fifth lower switching device 1450, sixth upper switching device 1452, and midswitch switching device 134 to operate in its respective off-state, resulting in differential output signal Vd being equal to Vprs - Vpr4. The negative value of differential output signal v^in the third operating mode is characterized by (i) modulator 1424 causing each of sixth upper switching device 1452 and fifth lower switching device 1450 to operate in its respective on- state and (ii) modulator 1424 causing each of fifth upper switching device 1448, sixth lower switching device 1454, and mid-switch switching device 134 to operate in its respective off- state, resulting in differential output signal v^being equal to - VPr5 - Vpr4). The zero value ofdifferential output signal v^in the third operating mode is characterized by (i) modulator 1424 causing mid-switch switching device 134 to operate in its on-state and (ii) modulator 1424 causing each of fifth upper switching device 1448, fifth lower switching device 1450, sixth upper switching device 1452, and sixth lower switching device 1454 to operate in its respective off-state, resulting in differential output signal Vdiff being zero. Multi-level output stage 1402 could be modified to support one or more additional peak-to-peak values of differential output signal Vdiff by adding a respective floating power supply and associated pair of half-bridge switching stages for each additional peak-to-peak value.Combinations of Features

[0060] Features described above may be combined in various ways without departing from the scope hereof. The following examples illustrate some possible combinations.

[0061] (Al) A multi-level output stage includes (i) a mid-switch switching stage electrically coupled between a first power rail and a reference node, the mid-switch switching stage being configured to generate a differential output signal having a first peak-to-peak magnitude, (ii) a floating power supply configured generate a second power rail and a third power rail, each of the second power rail and the third power rail being at a different electric potential than the reference node during operation of the multi-level output stage, (iii) a first half-bridge switching stage electrically coupled between the third power rail and the second power rail, and (iv) a second half-bridge switching stage electrically coupled between the third power rail and the second power rail. The first half-bridge switching stage, the second halfbridge switching stage, and a mid-switch of the mid-switch switching stage are configured to collectively generate a differential output signal having a second peak-to-peak magnitude that is different from the first peak-to-peak magnitude.

[0062] (A2) In the multi-level output stage denoted as (Al), the second peak-to-peak magnitude may be smaller than the first peak-to-peak magnitude.

[0063] (A3) In either one of the multi-level output stages denoted as (Al) or (A2), the floating power supply may be further configured to regulate one or more of a magnitude of a voltage between the second power rail and the reference node and a magnitude of a voltage between the third power rail and the reference node.

[0064] (A4) In either one of the multi-level output stages denoted as (Al) or (A2), the floating power supply may be further configured to regulate a magnitude of a voltage between the second power rail and the reference node such that a mid-point between a magnitude of the voltage between the third power rail and the reference node and the magnitude of the voltagebetween the second power rail and the reference node is one half of a magnitude of a voltage between the first power rail and the reference node.

[0065] (A5) In either one of the multi-level output stages denoted as (Al) or (A2), the floating power supply may include (i) a base capacitor electrically coupled between the second power rail and the reference node, (ii) a floating capacitor electrically coupled between the third power rail and the second power rail, (iii) charge transfer circuitry configured to charge the floating capacitor from an electric power source that is electrically referenced to the reference node, (iv) a current control device electrically coupled between the first power rail and the second power rail, and (v) control circuitry configured to control the current control device to regulate a magnitude of a voltage between the second power rail and the reference node.

[0066] (A6) In the multi-level output stage denoted as (A5), the control circuitry may be further configured to control the current control device to regulate the magnitude of the voltage between the second power rail and the reference node such that a mid-point between a magnitude of a voltage between the third power rail and the reference node and the magnitude of the voltage between the second power rail and the reference node is one half of a magnitude of a voltage between the first power rail and the reference node.

[0067] (A7) Any one of the multi-level output stages denoted as (Al) through (A6) may further include (i) a digital-to-analog converter (DAC) configured to convert a digital input signal to an analog input signal and (ii) a modulator configured to control each of the midswitch switching stage, the first half-bridge switching stage, and the second half-bridge switching stage as a function of the analog input signal.

[0068] (A8) In the multi-level output stage denoted as (A7), each of the DAC and the modulator may be electrically referenced to the reference node.

[0069] (A9) In the multi-level output stage denoted as (A7), each of the DAC and the modulator may be electrically referenced to the second power rail.

[0070] (Bl) A multi-level output stage includes (i) a first upper switching device electrically coupled between a first power rail and a first output node, (ii) a first lower switching device electrically coupled between the first output node and a reference node, (iii) a second upper switching device electrically coupled between the first power rail and a second output node, (iv) a second lower switching device electrically coupled between the second output node and the reference node, (v) a mid-switch switching device electrically coupled between the first output node and the second output node, (vi) a floating power supply configured generate a second power rail and a third power rail, each of the second power rail and the third power railbeing at a different electric potential than the reference node during operation of the multi-level output stage, (vii) a third upper switching device electrically coupled between the third power rail and first output power node, (viii) a third lower switching device electrically coupled between the first output node and the second power rail, (ix) a fourth upper switching device electrically coupled between the third power rail and the second output node, and (x) a fourth lower switching device electrically coupled between the second output node and the second power rail.

[0071] (B2) The multi-level output stage denoted as (Bl) may further include a modulator configured to control each of the first upper switching device, the first lower switching device, the second upper switching device, the second lower switching device, the mid-switch switching device, the third upper switching device, the third lower switching device, the fourth upper switching device, and the fourth lower switching device such that (i) the multi-level output stage generates a differential output signal having a peak-to-peak magnitude equal to twice a magnitude of a voltage between the first power rail and the reference node, in a first operating mode of the multi-level output stage and (ii) the multi-level output stage generates a differential output signal having a peak-to-peak magnitude equal to twice a magnitude of a voltage between the third power rail and the second power rail, in a second operating mode of the multi-level output stage.

[0072] (B3) In the multi-level output stage denoted as (B2), the modulator may be electrically referenced to the reference node.

[0073] (B4) In the multi-level output stage denoted as (B2), the modulator may be electrically referenced to the second power rail.

[0074] (B5) In any one of the multi-level output stages denoted as (B2) through (B4), the floating power supply may be further configured to regulate at least one of a magnitude of a voltage between the second power rail and the reference node and a magnitude of a voltage between the third power rail and the reference node such that magnitude of a common mode output voltage of the multi-level output stage is the same in each of the first operating mode of the multi-level output stage and the second operating mode of the multi-level output stage.

[0075] (B6) In any one of the multi-level output stages denoted as (Bl) through (B5), the floating power supply may include (i) a base capacitor electrically coupled between the second power rail and the reference node, (ii) a floating capacitor electrically coupled between the third power rail and the second power rail, (iii) charge transfer circuitry configured to charge the floating capacitor from an electric power source referenced to the reference node, (iv) a current control device electrically coupled between the first power rail and the secondpower rail, and (v) control circuitry configured to control the current control device to regulate a magnitude of a voltage between the second power rail and the reference node.

[0076] (B7) In any one of the multi-level output stages denoted as (Bl) through (B6), the mid-switch switching device may include a first transistor and a second transistor electrically coupled in series between the first output node and the second output node.

[0077] (Cl) A method for generating a multi-level differential output signal using a multi-level output stage includes (1) using a mid-switch switching stage electrically coupled between a first power rail and a reference node, generating a differential output signal having a first peak-to-peak magnitude, in a first operating mode of the multi-level output stage, and (2) using (i) a first half-bridge switching stage electrically coupled between a third power rail and a second power rail, (ii) a second half-bridge switching stage electrically coupled between the third power rail and the second power rail, and (iii) a mid-switch of the mid-switch switching stage, generating a differential output signal having a second peak-to-peak magnitude that is different from the first peak-to-peak magnitude, in a second operating mode of the multi-level output stage.

[0078] (C2) The method denoted as (Cl) may further include regulating at least one of a magnitude of a voltage between the second power rail and the reference node and a magnitude of a voltage between the third power rail and the reference node such that magnitude of a common mode output voltage of the multi-level output stage is the same in the first operating mode and the second operating mode.

[0079] (C3) Either one of the methods denoted as (Cl) or (C2) may further include generating the second power rail and the third power rail using a floating power supply that is powered from an electric power source that is electrically referenced to the reference node.

[0080] (C4) Any one of the methods denoted as (Cl) through (C3) may further include switching between the first operating mode of the multi-level output stage and the second operating mode of the multi-level output stage at least partially based on a magnitude of power provided by the multi-level output stage to a load.

[0081] Changes may be made in the above methods, devices, and systems without departing from the scope hereof. It should thus be noted that the matter contained in the above description and shown in the accompanying drawings should be interpreted as illustrative and not in a limiting sense. The following claims are intended to cover generic and specific features described herein, as well as all statements of the scope of the present method and system, which as a matter of language, might be said to fall therebetween.

Claims

CLAIMSWhat is claimed is:

1. A multi-level output stage, comprising: a mid-switch switching stage electrically coupled between a first power rail and a reference node, the mid-switch switching stage being configured to generate a differential output signal having a first peak-to-peak magnitude; a floating power supply configured generate a second power rail and a third power rail, each of the second power rail and the third power rail being at a different electric potential than the reference node during operation of the multi-level output stage; a first half-bridge switching stage electrically coupled between the third power rail and the second power rail; and a second half-bridge switching stage electrically coupled between the third power rail and the second power rail, wherein the first half-bridge switching stage, the second half-bridge switching stage, and a mid-switch of the mid-switch switching stage are configured to collectively generate a differential output signal having a second peak-to-peak magnitude that is different from the first peak-to-peak magnitude.

2. The multi-level output stage of claim 1, wherein the second peak-to-peak magnitude is smaller than the first peak-to-peak magnitude.

3. The multi-level output stage of claim 1 or 2, wherein the floating power supply is further configured to regulate one or more of a magnitude of a voltage between the second power rail and the reference node and a magnitude of a voltage between the third power rail and the reference node.

4. The multi-level output stage of any of claims 1 to3, wherein the floating power supply is further configured to regulate a magnitude of a voltage between the second power rail and the reference node such that a mid-point between a magnitude of a voltage between the third power rail and the reference node and the magnitude of the voltage between the second power rail and the reference node is one half of a magnitude of a voltage between the first power rail and the reference node.

5. The multi-level output stage of any of claims 1 to 4, wherein the floating power supply comprises: a base capacitor electrically coupled between the second power rail and the reference node; a floating capacitor electrically coupled between the third power rail and the second power rail; charge transfer circuitry configured to charge the floating capacitor from an electric power source that is electrically referenced to the reference node; a current control device electrically coupled between the first power rail and the second power rail; and control circuitry configured to control the current control device to regulate a magnitude of a voltage between the second power rail and the reference node.

6. The multi-level output stage of claim 5, wherein the control circuitry is further configured to control the current control device to regulate the magnitude of the voltage between the second power rail and the reference node such that a mid-point between a magnitude of a voltage between the third power rail and the reference node and the magnitude of the voltage between the second power rail and the reference node is one half of a magnitude of a voltage between the first power rail and the reference node.

7. The multi-level output stage of any of claims 1 to 6, further comprising: a digital-to-analog converter (DAC) configured to convert a digital input signal to an analog input signal; and a modulator configured to control each of the mid-switch switching stage, the first half- bridge switching stage, and the second half-bridge switching stage as a function of the analog input signal.

8. The multi-level output stage of claim 7, wherein each of the DAC and the modulator are electrically referenced to the reference node.

9. The multi-level output stage of claim 7, wherein each of the DAC and the modulator are electrically referenced to the second power rail.

10. A multi-level output stage, comprising: a first upper switching device electrically coupled between a first power rail and a first output node;a first lower switching device electrically coupled between the first output node and a reference node; a second upper switching device electrically coupled between the first power rail and a second output node; a second lower switching device electrically coupled between the second output node and the reference node; a mid-switch switching device electrically coupled between the first output node and the second output node; a floating power supply configured generate a second power rail and a third power rail, each of the second power rail and the third power rail being at a different electric potential than the reference node during operation of the multi-level output stage; a third upper switching device electrically coupled between the third power rail and first output power node; a third lower switching device electrically coupled between the first output node and the second power rail; a fourth upper switching device electrically coupled between the third power rail and the second output node; and a fourth lower switching device electrically coupled between the second output node and the second power rail.

11. The multi-level output stage of claim 10, further comprising a modulator configured to control each of the first upper switching device, the first lower switching device, the second upper switching device, the second lower switching device, the mid-switch switching device, the third upper switching device, the third lower switching device, the fourth upper switching device, and the fourth lower switching device such that: the multi-level output stage generates a differential output signal having a peak-to-peak magnitude equal to twice a magnitude of a voltage between the first power rail and the reference node, in a first operating mode of the multi-level output stage; and the multi-level output stage generates a differential output signal having a peak-to-peak magnitude equal to twice a magnitude of a voltage between the third power rail and the second power rail, in a second operating mode of the multi-level output stage.

12. The multi-level output stage of claim 11, wherein the modulator is electrically referenced to the reference node.

13. The multi-level output stage of claim 11, wherein the modulator is electrically referenced to the second power rail.

14. The multi-level output stage of any of claims 11 to 13, wherein the floating power supply is further configured to regulate at least one of a magnitude of a voltage between the second power rail and the reference node and a magnitude of a voltage between the third power rail and the reference node such that magnitude of a common mode output voltage of the multilevel output stage is the same in each of the first operating mode of the multi-level output stage and the second operating mode of the multi-level output stage.

15. The multi-level output stage of any of claims 10 to 14, wherein the floating power supply comprises: a base capacitor electrically coupled between the second power rail and the reference node; a floating capacitor electrically coupled between the third power rail and the second power rail; charge transfer circuitry configured to charge the floating capacitor from an electric power source referenced to the reference node; a current control device electrically coupled between the first power rail and the second power rail; and control circuitry configured to control the current control device to regulate a magnitude of a voltage between the second power rail and the reference node.

16. The multi-level output stage of any of claims 10 to 15, wherein the mid-switch switching device comprises a first transistor and a second transistor electrically coupled in series between the first output node and the second output node.

17. A method for generating a multi-level differential output signal using a multi-level output stage, the method comprising: using a mid-switch switching stage electrically coupled between a first power rail and a reference node, generating a differential output signal having a first peak-to- peak magnitude, in a first operating mode of the multi-level output stage; andusing (i) a first half-bridge switching stage electrically coupled between a third power rail and a second power rail, (ii) a second half-bridge switching stage electrically coupled between the third power rail and the second power rail, and (iii) a midswitch of the mid-switch switching stage, generating a differential output signal having a second peak-to-peak magnitude that is different from the first peak-to- peak magnitude, in a second operating mode of the multi-level output stage.

18. The method of claim 17, further comprising regulating at least one of a magnitude of a voltage between the second power rail and the reference node and a magnitude of a voltage between the third power rail and the reference node such that magnitude of a common mode output voltage of the multi-level output stage is the same in the first operating mode and the second operating mode.

19. The method of claim 17 or 18, further comprising generating the second power rail and the third power rail using a floating power supply that is powered from an electric power source that is electrically referenced to the reference node.

20. The method of any of claims 17 to 19, further comprising switching between the first operating mode of the multi-level output stage and the second operating mode of the multilevel output stage at least partially based on a magnitude of power provided by the multi-level output stage to a load.

Images