Semiconductor device

Abstract

Provided is a semiconductor device suitable for high integration. The semiconductor device has first and second transistors. The first transistor has a first semiconductor layer, a first insulating layer, and a first conductive layer, and the second transistor has a second semiconductor layer, a second insulating layer, and a second conductive layer. The first and second semiconductor layers each have a sheet-like shape. The first conductive layer surrounds the upper surface, the side surfaces, and the lower surface of the first semiconductor layer, and the first insulating layer is located between the first semiconductor layer and the first conductive layer. The second conductive layer surrounds the upper surface, the side surfaces, and the lower surface of the second semiconductor layer, and the second insulating layer is located between the second semiconductor layer and the second conductive layer. The first transistor is a p-type transistor, and the first semiconductor layer includes silicon or silicon germanium. The second transistor is an n-type transistor, and the second semiconductor layer includes an oxide semiconductor.

Description

Semiconductor Devices

[0001] FIELD OF THE INVENTION One embodiment of the present invention relates to a semiconductor device and a transistor.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. Examples of the technical field of one embodiment of the present invention disclosed in this specification and the like include semiconductor devices, display devices, light-emitting devices, power storage devices, memory devices, electronic devices, lighting devices, input devices, input / output devices, driving methods thereof, and manufacturing methods thereof. A semiconductor device refers to any device that can function by utilizing semiconductor characteristics.

[0003] In recent years, the development of semiconductor devices has progressed, and CPUs, memories, and other large-scale integrated circuits (LSIs) are mainly used in semiconductor devices. A CPU is an assembly of semiconductor elements that have semiconductor integrated circuits (at least transistors and memories) formed into chips by processing a semiconductor wafer and on which electrodes serving as connection terminals are formed.

[0004] 2. Description of the Related Art A CPU, a memory, or other LSI semiconductor circuit (IC chip) is mounted on a circuit board, such as a printed wiring board, and is used as one of the components of various electronic devices.

[0005] Furthermore, a technology for constructing a transistor using a semiconductor thin film formed on a substrate having an insulating surface has attracted attention. Such transistors are widely used in electronic devices such as integrated circuits and image display devices (also simply referred to as display devices). While silicon-based semiconductor materials are widely known as semiconductor thin films applicable to transistors, oxide semiconductors have also attracted attention as other materials.

[0006] Furthermore, it is known that a transistor including an oxide semiconductor has an extremely small leakage current in a non-conducting state. For example, Patent Document 1 discloses a low-power consumption CPU that utilizes the property of a small leakage current. Furthermore, Patent Document 2 discloses a memory device that can retain stored data for a long period of time.

[0007] JP 2012-257187 A JP 2011-151383 A

[0008] Takashi Koida, "High Mobility Transparent Conductive Film," National Institute of Advanced Industrial Science and Technology, AIST Photovoltaic Power Generation Research Results Report 2019, Internet <URL: https: / / unit.aist.go.jp / rpd-envene / PV / ja / results / 2019 / oral / T13.pdf>

[0009] An object of one embodiment of the present invention is to provide a semiconductor device that can be miniaturized. Another object is to provide a semiconductor device that occupies a small area. Another object is to provide a semiconductor device that is suitable for high integration. Another object is to provide a semiconductor device with low power consumption. Another object is to provide a semiconductor device with low leakage current. Another object is to provide a semiconductor device with favorable electrical characteristics. Another object is to provide a highly reliable semiconductor device.

[0010] An object of one embodiment of the present invention is to provide a semiconductor device, a computing device, a memory device, or an electronic device having a novel structure.An object of one embodiment of the present invention is to alleviate at least one of the problems of the prior art.

[0011] Note that the description of these problems does not preclude the existence of other problems. Note that one embodiment of the present invention does not necessarily solve all of these problems. Note that problems other than these can be extracted from the description of the specification, drawings, claims, etc.

[0012] One embodiment of the present invention is a semiconductor device including a first transistor and a second transistor. The first transistor includes a first semiconductor layer, a first insulating layer, and a first conductive layer. The second transistor includes a second semiconductor layer, a second insulating layer, and a second conductive layer. The first semiconductor layer and the second semiconductor layer each have a sheet-like shape. The first conductive layer is provided to surround an upper surface, a side surface, and a lower surface of the first semiconductor layer. The first insulating layer has a portion located between the first semiconductor layer and the first conductive layer. The second conductive layer is provided to surround an upper surface, a side surface, and a lower surface of the second semiconductor layer. The second insulating layer has a portion located between the second semiconductor layer and the second conductive layer. The first transistor is a p-type transistor, and the first semiconductor layer contains silicon or silicon germanium. The second transistor is an n-type transistor, and the second semiconductor layer contains an oxide semiconductor.

[0013] Another embodiment of the present invention is a semiconductor device including a first transistor, a second transistor, and a third insulating layer. The first transistor includes a first semiconductor layer, a first insulating layer, and a first conductive layer. The second transistor includes a second semiconductor layer, a second insulating layer, and a second conductive layer. The first semiconductor layer and the second semiconductor layer each have a sheet-like shape. The first conductive layer is provided to surround an upper surface, a side surface, and a lower surface of the first semiconductor layer. The first insulating layer has a portion located between the first semiconductor layer and the first conductive layer. The second conductive layer is provided to surround an upper surface, a side surface, and a lower surface of the second semiconductor layer. The second insulating layer has a portion located between the second semiconductor layer and the second conductive layer. The second transistor is located above the first transistor. The third insulating layer is located between the first transistor and the second transistor. The first transistor is a p-type transistor, and the first semiconductor layer includes silicon or silicon germanium. The second transistor is an n-type transistor, and the second semiconductor layer includes an oxide semiconductor.

[0014] In the above, the third insulating layer preferably includes a silicon nitride film, a silicon nitride oxide film, an aluminum oxide film, a magnesium oxide film, a hafnium oxide film, or a gallium oxide film.

[0015] Another embodiment of the present invention is a semiconductor device including a first transistor and a second transistor. The first transistor includes a first semiconductor layer, a first insulating layer, and a first conductive layer. The second transistor includes a second semiconductor layer, a second insulating layer, and a first conductive layer. The first semiconductor layer and the second semiconductor layer each have a sheet-like shape. The first conductive layer includes a portion surrounding an upper surface, a side surface, and a lower surface of the first semiconductor layer, and a portion surrounding an upper surface, a side surface, and a lower surface of the second semiconductor layer. The first insulating layer includes a portion located between the first semiconductor layer and the first conductive layer. The second insulating layer includes a portion located between the second semiconductor layer and the first conductive layer. The first semiconductor layer and the second semiconductor layer are arranged side by side. The first transistor is a p-type transistor, and the first semiconductor layer includes silicon or silicon germanium. The second transistor is an n-type transistor, and the second semiconductor layer includes an oxide semiconductor.

[0016] Another embodiment of the present invention is a semiconductor device including n first transistors (n is an integer of 2 or more) and n second transistors. The n first transistors are stacked. The n second transistors are stacked and overlapped on the n first transistors. The n first transistors each independently include a first semiconductor layer, a first insulating layer, and a first conductive layer. The n second transistors each independently include a second semiconductor layer, a second insulating layer, and a second conductive layer. The first conductive layer is provided to surround a top surface, a side surface, and a bottom surface of the first semiconductor layer. The first insulating layer has a portion located between the first semiconductor layer and the first conductive layer. The second conductive layer is provided to surround a top surface, a side surface, and a bottom surface of the second semiconductor layer. The second insulating layer has a portion located between the second semiconductor layer and the second conductive layer. The first transistor is a p-type transistor, and the first semiconductor layer includes silicon or silicon germanium. The second transistor is an n-type transistor, and the second semiconductor layer includes an oxide semiconductor.

[0017] Another embodiment of the present invention is a semiconductor device including n first transistors (n is an integer of 2 or more) and n second transistors. The n first transistors are stacked. The n second transistors are stacked. The n first transistors each independently include a first semiconductor layer, a first insulating layer, and a first conductive layer. The n second transistors each independently include a second semiconductor layer, a second insulating layer, and a first conductive layer. In the k-th (k is an integer of 1 to n) first and second transistors from the bottom, the first conductive layer has a portion surrounding a top surface, a side surface, and a bottom surface of the first semiconductor layer and a portion surrounding a top surface, a side surface, and a bottom surface of the second semiconductor layer. The first insulating layer has a portion located between the first semiconductor layer and the first conductive layer. The second insulating layer has a portion located between the second semiconductor layer and the first conductive layer. In the k-th first and second transistors from the bottom, the first and second semiconductor layers are arranged side by side, the first transistor is a p-type transistor, and the first semiconductor layer includes silicon or silicon germanium, and the second transistor is an n-type transistor, and the second semiconductor layer includes an oxide semiconductor.

[0018] In any of the above, the oxide semiconductor is preferably indium oxide. Furthermore, it is preferable that the first semiconductor layer has a single crystal structure or a polycrystalline structure, and the second semiconductor layer has a single crystal structure or a polycrystalline structure.

[0019] In any of the above, the first transistor preferably has a first electrode functioning as one of a source electrode and a drain electrode and a second electrode functioning as the other. The second transistor preferably has a third electrode functioning as one of a source electrode and a drain electrode and a fourth electrode functioning as the other. In this case, it is preferable that the first electrode is connected to a first power supply line that transmits a high power supply potential, the second electrode and the third electrode are connected, and the fourth electrode is connected to a second power supply line that transmits a low power supply potential.

[0020] According to one embodiment of the present invention, a semiconductor device that can be miniaturized can be provided. Alternatively, a semiconductor device that occupies a small area can be provided. Alternatively, a semiconductor device that is suitable for high integration can be provided. Alternatively, a semiconductor device with low power consumption can be provided. Alternatively, a semiconductor device with low leakage current can be provided. Alternatively, a semiconductor device with favorable electrical characteristics can be provided. Alternatively, a semiconductor device with high reliability can be provided.

[0021] According to one aspect of the present invention, it is possible to provide a semiconductor device, a computing device, a memory device, or an electronic device having a novel configuration. According to one aspect of the present invention, it is possible to at least alleviate at least one of the problems of the prior art.

[0022] Note that the description of these effects does not preclude the existence of other effects. Note that one embodiment of the present invention does not necessarily have all of these effects. Note that effects other than these can be extracted from the description in the specification, drawings, claims, etc.

[0023] FIGS. 1A, 1B, and 1C illustrate structural examples of a semiconductor device. FIGS. 2A and 2B illustrate structural examples of a semiconductor device. FIG. 3 illustrates a structural example of a semiconductor device. FIGS. 4A, 4B, 4C, and 4D illustrate structural examples of a semiconductor device. FIG. 5 illustrates a structural example of a semiconductor device. FIG. 6A is a circuit diagram illustrating a semiconductor device of one embodiment of the present invention. FIG. 6B is a block diagram illustrating a semiconductor device of one embodiment of the present invention. FIG. 7 is a circuit diagram illustrating a semiconductor device of one embodiment of the present invention. FIG. 8A is a circuit diagram illustrating a semiconductor device of one embodiment of the present invention. FIG. 8B is a block diagram illustrating a semiconductor device of one embodiment of the present invention. FIG. 9 is a circuit diagram illustrating a semiconductor device of one embodiment of the present invention. FIG. 10A is a block diagram illustrating a semiconductor device of one embodiment of the present invention. FIG. 10B is a circuit diagram illustrating a semiconductor device of one embodiment of the present invention. FIG. 11 is a circuit diagram illustrating a semiconductor device of one embodiment of the present invention. FIG. 12A is a block diagram illustrating a semiconductor device of one embodiment of the present invention. FIG. 12B is a circuit diagram illustrating a semiconductor device of one embodiment of the present invention. FIG. 13A is a block diagram illustrating a semiconductor device of one embodiment of the present invention. FIG. 13B is a circuit diagram illustrating a semiconductor device of one embodiment of the present invention. FIG. 14A is a block diagram illustrating a semiconductor device of one embodiment of the present invention. FIG. 14B is a circuit diagram illustrating a semiconductor device of one embodiment of the present invention. FIGS. 15A and 15B are diagrams illustrating carrier concentration dependence of Hall mobility. FIG. 15C is a cross-sectional view illustrating an indium oxide film. FIG. 16A is an equivalent circuit diagram of a logic circuit. FIG. 16B is a diagram illustrating circuit symbols of a logic circuit. FIG. 16C is a timing chart illustrating operation of the logic circuit. FIGS. 17A and 17D are equivalent circuit diagrams of logic circuits. FIGS. 17B, 17C, 17E, and 17F are diagrams illustrating circuit symbols of logic circuits. FIG. 18A is a diagram illustrating the circuit symbols of a buffer circuit. FIG. 18B is a diagram illustrating a configuration example of a buffer circuit. FIG. 18C is a timing chart illustrating operation of the buffer circuit. FIG. 18D is a diagram illustrating a configuration example of a ring oscillator. FIG. 18E is a diagram illustrating oscillation of a ring oscillator. FIG. 19A is an equivalent circuit diagram of a DFF circuit. FIG. 19B is a diagram showing a circuit symbol of a DFF circuit.FIG. 20A is a diagram illustrating an example of the configuration of a shift register circuit. FIG. 20B is a timing chart illustrating the operation of the shift register circuit. FIG. 21 is a block diagram illustrating an example of the configuration of a semiconductor device. FIGS. 22A, 22B, 22C, 22D, 22E, 22F, 22G, and 22H are diagrams illustrating an example of the circuit configuration of a memory cell. FIGS. 23A and 23B are diagrams illustrating an example of an electronic component. FIGS. 24A, 24B, and 24C are diagrams illustrating an example of a mainframe computer. FIG. 24D is a diagram illustrating an example of space equipment. FIG. 24E is a diagram illustrating an example of a storage system applicable to a data center.

[0024] Hereinafter, embodiments will be described with reference to the drawings. However, it will be readily understood by those skilled in the art that the embodiments can be implemented in many different ways and that various changes in form and details can be made without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the following description of the embodiments.

[0025] In the configuration of the invention described below, the same parts or parts having similar functions are denoted by the same reference numerals in different drawings, and repeated explanations thereof will be omitted. Furthermore, when referring to similar functions, the same hatching pattern may be used and no particular reference numeral may be assigned.

[0026] In the drawings described in this specification, the size of each component, the thickness of a layer, or an area may be exaggerated for clarity, and therefore, the drawings are not necessarily limited to the scale.

[0027] In this specification, ordinal numbers such as "first" and "second" are used to avoid confusion of components and do not limit the number.

[0028] A transistor is a type of semiconductor element that can perform functions such as amplifying current or voltage and performing switching operations to control conduction or non-conduction. The term "transistor" as used herein includes an insulated gate field effect transistor (IGFET) and a thin film transistor (TFT).

[0029] Furthermore, the functions of "source" and "drain" may be interchangeable when transistors of different polarities are used, or when the direction of current flow changes during circuit operation, etc. For this reason, the terms "source" and "drain" may be used interchangeably in this specification.

[0030] In this specification and the like, either the source or the drain of a transistor may be referred to as a “first electrode,” and the other of the source or the drain may be referred to as a “second electrode.” The gate may also be referred to as a “gate” or a “gate electrode.”

[0031] In this specification, "connection" includes "electrical connection." "A and B are electrically connected" means that, among the cases where A and B are connected without an insulator (where A and B are connected via a conductor or semiconductor, or where A and B are in contact), there is a time when an exchange of electrical signals or an interaction of potentials occurs between A and B during circuit operation. In other words, even if there is a time during circuit operation when an exchange of electrical signals or an interaction of potentials does not occur between A and B, it can be said that "A and B are electrically connected" as long as there is a time when an exchange of electrical signals or an interaction of potentials occurs between A and B.

[0032] An "electrical connection" includes a connection (direct connection) that does not involve a circuit element (for example, a transistor, but excluding wiring), and a connection (indirect connection) that involves one or more circuit elements.

[0033] In this specification, the phrase "top surface shapes generally match" refers to the overlap of at least a portion of the contours between stacked layers. For example, this includes cases where the upper and lower layers are processed using the same mask pattern or a portion of the same mask pattern. However, strictly speaking, the contours may not overlap, and the upper layer may be located inside the lower layer, or outside the lower layer. In these cases, the phrase "top surface shapes generally match" may also be used.

[0034] In this specification, the top surface shape of a certain component refers to the contour shape of the component in a plan view. The plan view refers to a view from the normal direction of the surface on which the component is formed or the surface of a support (e.g., a substrate) on which the component is formed.

[0035] In the following, expressions indicating directions such as "up" and "down" will basically be used in accordance with the directions in the drawings. However, for purposes such as facilitating explanation, the directions indicated by "up" or "down" in the specification may not match those in the drawings. For example, when explaining the stacking order (or formation order) of a laminate, etc., even if the surface on which the laminate is provided (such as a forming surface, a support surface, an adhesive surface, or a flat surface) is located above the laminate in the drawings, the forming surface side may be expressed as "down" and the direction opposite to the forming surface as "up."

[0036] In this specification, the channel length direction of a transistor refers to one of the directions parallel to the line connecting the source region and the drain region at the shortest distance. In other words, the channel length direction corresponds to one of the directions of current flowing through the semiconductor layer when the transistor is in an on-state. The channel width direction refers to a direction perpendicular to the channel length direction. Depending on the structure or shape of the transistor, the channel length direction and the channel width direction may not be defined as a single direction.

[0037] In addition, in this specification and the like, the terms "film" and "layer" are interchangeable. For example, the term "insulating layer" may be interchangeable with the term "insulating film."

[0038] Unless otherwise specified, in this specification and the like, the off-state current refers to the drain current when a transistor is in an off state (also referred to as a non-conducting state or a cut-off state). Unless otherwise specified, the off-state refers to a state in which the gate-source voltage Vgs is lower than the threshold voltage Vth in an n-type transistor (also referred to as an n-channel transistor) (higher than Vth in a p-type transistor (also referred to as a p-channel transistor)).

[0039] In this specification, space groups are expressed using short notation in international notation (or Hermann-Mauguin notation). Crystal planes and crystal orientations are expressed using Miller indices. In crystallography, space groups, crystal planes, and crystal orientations are expressed by adding a superscript bar to the numbers. However, due to formatting restrictions, in this specification, instead of adding a bar above the numbers, they may be expressed by adding a minus sign (-) before the numbers. Furthermore, individual orientations indicating directions within a crystal are expressed with [ ], collective orientations indicating all equivalent orientations are expressed with < >, individual planes indicating crystal planes are expressed with ( ), and collective planes with equivalent symmetry are expressed with {}.

[0040] In this specification, "two lines parallel" refers to a state in which the two lines are arranged at an angle of -10 degrees or more and 10 degrees or less. "Two lines approximately parallel" refers to a state in which the two lines are arranged at an angle of -30 degrees or more and 30 degrees or less (including parallel). "Two lines perpendicular" refers to a state in which the two lines are arranged at an angle of 80 degrees or more and 100 degrees or less. "Two lines approximately perpendicular" refers to a state in which the two lines are arranged at an angle of 60 degrees or more and 120 degrees or less (including perpendicular).

[0041] In this specification, "two surfaces are parallel" refers to a state in which their interior angle is between -10 degrees and 10 degrees. "Two surfaces are approximately parallel" refers to a state in which their interior angle is between -30 degrees and 30 degrees (including parallel). "Two surfaces are perpendicular" refers to a state in which their interior angle is between 80 degrees and 100 degrees (including perpendicular). "Two surfaces are approximately perpendicular" refers to a state in which their interior angle is between 60 degrees and 120 degrees (including perpendicular).

[0042] Embodiment 1 In this embodiment, a structural example of a semiconductor device according to one embodiment of the present invention will be described.

[0043] One embodiment of the present invention is a semiconductor device including two types of transistors. One transistor (also referred to as a first transistor) is a p-type transistor (also referred to as a p-channel transistor), and the other transistor (also referred to as a second transistor) is an n-type transistor (also referred to as an n-channel transistor). By including the p-type first transistor and the n-type second transistor, a semiconductor chip including various logic circuits, functional circuits, memory circuits, driver circuits, and the like, such as a so-called complementary metal oxide semiconductor (CMOS) circuit, can be realized.

[0044] The first transistor and the second transistor each include a sheet-shaped semiconductor layer, a gate electrode provided so as to surround the upper surface, side surfaces, and lower surface of the semiconductor layer, a gate insulating layer located between the semiconductor layer and the gate electrode, and a source electrode and a drain electrode each in contact with the semiconductor layer. Because the gate electrodes of the first transistor and the second transistor are provided so as to surround the semiconductor layer, they can also be called transistors with a Gate All Around (GAA) structure.

[0045] The semiconductor layer of the first transistor (also referred to as the first semiconductor layer) is preferably made of a semiconductor material such as silicon, germanium, or silicon-germanium. Single-crystal or polycrystalline silicon or silicon-germanium is preferably used for the first semiconductor layer. Alternatively, a p-type oxide semiconductor or a compound semiconductor may be used.

[0046] An oxide semiconductor is preferably used for the semiconductor layer (also referred to as the second semiconductor layer) of the second transistor. This makes it possible to realize a semiconductor circuit that combines low power consumption and high-speed operation. In particular, it is preferable to use single-crystal or polycrystalline indium oxide for the second semiconductor layer. Alternatively, an oxide semiconductor such as In—Ga—Zn oxide (IGZO) may be used as the semiconductor applied to the second transistor. A transistor using an oxide semiconductor for the semiconductor layer can have a significantly lower off-state current than a silicon transistor. Therefore, when used in a CMOS circuit or the like, standby power consumption can be dramatically reduced. In particular, indium oxide has higher hole mobility than an oxide semiconductor such as IGZO, and can realize a transistor with a high on-state current, making it suitable for a CMOS circuit or the like.

[0047] The first transistor and the second transistor are preferably stacked, which can reduce the area occupied by the semiconductor device and enable higher circuit integration.

[0048] In this case, it is preferable to provide the second transistor over the first transistor. For example, when silicon or silicon germanium is used for the first transistor and indium oxide is used for the second transistor, the temperature required for the manufacturing process (for example, the temperature required for crystallization of the semiconductor layer) may be higher for the first transistor. On the other hand, when an oxide semiconductor such as indium oxide is exposed to extremely high temperatures, oxygen vacancies may occur, which may adversely affect the electrical characteristics, reliability, and the like. Therefore, a highly reliable semiconductor device can be realized by providing the first transistor, which requires processing at a higher temperature, below the second transistor.

[0049] Furthermore, since the first p-channel transistor and the second n-channel transistor are three-dimensionally stacked and integrated, the semiconductor device of one embodiment of the present invention can also be called a complementary field effect transistor (CFET).

[0050] A more specific example will be described below with reference to the drawings.

[0051] [Configuration Example 1] Fig. 1A shows a schematic top view of a semiconductor device 10. Fig. 1B and Fig. 1C show schematic cross-sectional views taken along the cutting lines A-B and C-D in Fig. 1A, respectively. Fig. 1B corresponds to a cross-section in the channel width direction of a transistor, and Fig. 1C corresponds to a cross-section in the channel length direction. Note that some components (such as insulating layers) are omitted in Fig. 1A.

[0052] The semiconductor device 10 is provided on a substrate 11, and has a configuration in which a transistor 20 and a transistor 30 are stacked above the transistor 20. An insulating layer 41 is provided between the transistors 20 and 30.

[0053] The transistor 20 includes a semiconductor layer 21, an insulating layer 22, a conductive layer 23, a conductive layer 24, and a conductive layer 25. A part of the insulating layer 22 functions as a gate insulating layer, a part of the conductive layer 23 functions as a gate electrode, the conductive layer 24 functions as one of a source electrode and a drain electrode, and the conductive layer 25 functions as the other.

[0054] The transistor 30 includes a semiconductor layer 31, an insulating layer 32, a conductive layer 33, a conductive layer 34, and a conductive layer 35. A part of the insulating layer 32 functions as a gate insulating layer, a part of the conductive layer 33 functions as a gate electrode, the conductive layer 34 functions as one of a source electrode and a drain electrode, and the conductive layer 35 functions as the other.

[0055] An insulating layer 42 is provided over the substrate 11, and the transistor 20 is provided over the insulating layer 42. The insulating layer 42 functions as a base insulating layer.

[0056] Conductive layers 24 and 25 are provided on the insulating layer 42, and an insulating layer 43 is provided to cover the conductive layers 24 and 25. The insulating layer 43 functions as an interlayer insulating layer. The semiconductor layer 21 has a sheet-like shape that is long in the channel length direction. One of a pair of ends in the channel length direction is provided in contact with the conductive layer 24, and the other is provided in contact with the conductive layer 25.

[0057] Here, an example is shown in which the semiconductor layer 21 is disposed so as to fit into the recesses of the conductive layer 24 and the conductive layer 25. Both the upper and lower surfaces of the semiconductor layer 21 are in contact with the conductive layer 24 or the conductive layer 25, thereby reducing the contact resistance therebetween. For example, such a configuration can be achieved by forming the conductive layer 24 and the conductive layer 25 into a stacked structure, with the semiconductor layer 21 sandwiched between the lower and upper layers. Note that the conductive layer 24 and the conductive layer 25 only need to be in contact with at least the semiconductor layer 21, and may also be configured to be in contact with either the lower surface or the upper surface of the semiconductor layer 21.

[0058] A conductive layer 23 is provided between the conductive layer 24 and the conductive layer 25 so as to surround the top surface, side surfaces, and bottom surface of the semiconductor layer 21. An insulating layer 22 is provided between the conductive layer 23 and the semiconductor layer 21. The region of the semiconductor layer 21 surrounded by the conductive layer 23 functions as a channel formation region. By surrounding the channel formation region with the gate electrode in this manner, a gate electric field can be efficiently applied. Therefore, the controllability of the transistor 20 can be improved, and an increase in on-current and a decrease in off-current can be expected.

[0059] The insulating layer 22 has portions located between the conductive layer 24, the conductive layer 25, the insulating layer 42, and the insulating layer 43 and the conductive layer 23, respectively. FIG. 1C shows an example in which an insulating layer 46 functioning as a spacer is provided between the conductive layer 24 and the insulating layer 22 and between the conductive layer 25 and the insulating layer 22. By providing the insulating layer 46, it is possible to reduce the parasitic capacitance between the conductive layer 23 and the conductive layer 24 and between the conductive layer 23 and the conductive layer 25. The insulating layer 45 is preferably made of an insulating material with a low dielectric constant, such as silicon oxide. Note that the insulating layer 46 may be omitted, leaving a space, or the conductive layer 24 and the conductive layer 25 may each be in contact with the insulating layer 22.

[0060] An insulating layer 41 is provided over the insulating layer 43, and an insulating layer 44 is provided over the insulating layer 41. In addition, the transistor 30 is provided over the insulating layer 44, and an insulating layer 45 is provided to cover the transistor 30.

[0061] The transistor 30 has a similar configuration to the transistor 20, except that the materials of the components such as the semiconductor layer 31 are different. The description of the structure of the transistor 30 will be omitted and reference will be made to the description of the transistor 20. In this case, in the description of the transistor 20, the insulating layer 42 is replaced with the insulating layer 44, the insulating layer 43 is replaced with the insulating layer 45, the insulating layer 46 is replaced with the insulating layer 47, the semiconductor layer 21 is replaced with the semiconductor layer 31, the insulating layer 22 is replaced with the insulating layer 32, the conductive layer 23 is replaced with the conductive layer 33, the conductive layer 24 is replaced with the conductive layer 34, and the conductive layer 25 is replaced with the conductive layer 35, respectively.

[0062] The semiconductor layer 21 may be, for example, a semiconductor made of a single element or a compound semiconductor. Examples of semiconductors made of a single element include Si (including single crystal, polycrystalline, microcrystalline, and amorphous) and Ge. Examples of compound semiconductors include GaAs and SiGe. Examples of compound semiconductors include organic semiconductors, nitride semiconductors, and oxide semiconductors. These semiconductor materials may also contain impurities as dopants.

[0063] Alternatively, the semiconductor layer 21 can be made of a material having a layered crystal structure. A material having a layered crystal structure has high in-plane electrical conductivity. Therefore, by using such a material having a layered crystal structure in the channel formation region, a transistor with a large on-state current can be provided. Examples of such a material include graphene, silicene, and chalcogenides. Examples of chalcogenides include chalcogenides of transition elements such as Mo, W, Hf, and Zr. In this case, examples of chalcogen elements include elements of Group 16 of the periodic table, such as S, Se, and Te.

[0064] In particular, it is preferable to use single crystal or polycrystalline silicon, or silicon germanium as the semiconductor layer 21 .

[0065] The transistor 20 is preferably a p-type transistor. Therefore, portions other than the channel formation region (the source region and the drain region) preferably contain impurities that impart p-type conductivity. When silicon or silicon germanium is used for the semiconductor layer 21, an element of Group 13 of the periodic table, such as boron (B), aluminum (Al), or gallium (Ga), can be used as the impurity that imparts p-type conductivity.

[0066] It is particularly preferable to use a metal oxide (oxide semiconductor) that exhibits semiconductor properties as the semiconductor material used for the semiconductor layer 31. In this case, it is also preferable to use a metal oxide in the portions of the conductive layer 34 and the conductive layer 35 that contact the semiconductor layer. This is preferable because it allows the contact resistance between the semiconductor layer 31 and the conductive layer 34 or the conductive layer 35 to be low.

[0067] In particular, it is preferable to use a metal oxide that can be an n-type semiconductor for the semiconductor layer 31. By making the source region and drain region of the semiconductor layer 31 an n-type semiconductor, the transistor 30 can be an n-type transistor, and by combining it with the p-type transistor 20, various circuits including a CMOS circuit can be realized.

[0068] Here, it is preferable to use a metal oxide with high crystallinity for the semiconductor layer 31. For example, a metal oxide having a single crystal structure or a polycrystalline structure is preferable. In particular, a metal oxide with a single crystal structure is preferable. In this case, the semiconductor film used to form the semiconductor layer 31 has a stacked structure, and a crystalline metal oxide film that functions as a seed crystal is formed in advance on a film (first film) located below, and a metal oxide film (second film) that will become the semiconductor layer 31 is formed so as to be in contact with this, thereby making it possible to form the semiconductor layer 31 with high crystallinity. The first film that functions as the seed crystal may be removed or may be used as part of the semiconductor layer 31.

[0069] In this case, the crystalline structure of the second film may be affected by the crystalline structure of the first film. More specifically, the crystalline structure of the second film may be a structure in which the crystalline orientation of the crystalline regions of the second film is aligned in a specific direction depending on the crystalline orientation of the crystalline regions of the first film. For example, when a metal oxide having a hexagonal crystalline structure, such as In—Ga—Zn oxide, is used for the first film and a metal oxide having a cubic crystalline structure, such as indium oxide, is used for the second film, if the

[001] orientation of the crystalline regions of the first film is oriented perpendicular to the surface on which the film is formed, the second film may have a single-crystal structure or a polycrystalline structure in which the

[111] orientation of the crystalline regions is oriented perpendicular to the surface on which the film is formed. In this way, by using a metal oxide having uniaxially oriented crystalline regions as the crystalline first film, a highly crystalline second film can be obtained. This allows for the realization of a transistor with high on-state current and high reliability.

[0070] The conductive layer 34 and the conductive layer 35 preferably contain a metal oxide containing the same metal element as the semiconductor layer 31. In particular, it is preferable that both the conductive layer 34 and the conductive layer 35 and the semiconductor layer 31 contain a metal oxide containing indium. This can reduce the contact resistance between the semiconductor layer 31 and the conductive layer 34 or the conductive layer 35. It is preferable to use a metal oxide containing indium and tin for the conductive layer 34 and the conductive layer 35, because this can increase the conductivity.

[0071] When silicon is used for the semiconductor layer 21 of the transistor 20, terminating dangling bonds with hydrogen is expected to improve reliability. On the other hand, when hydrogen diffuses into the semiconductor layer 31 of the transistor 30, carriers are generated, which may cause the channel formation region of the semiconductor layer 31 to become n-type. Therefore, it is preferable to use a film having barrier properties against hydrogen and oxygen for the insulating layer 41 provided between the transistors 20 and 30. This can prevent hydrogen from diffusing from below the insulating layer 41 into the semiconductor layer 31 and causing the semiconductor layer 31 to become n-type. Furthermore, oxygen contained in the semiconductor layer 31 and its vicinity from diffusing below the insulating layer 41 can prevent oxygen vacancies from occurring in the semiconductor layer 31.

[0072] The insulating layer 41 is preferably made of a silicon nitride film, a silicon nitride oxide film, an aluminum oxide film, a magnesium oxide film, a hafnium oxide film, a gallium oxide film, or the like.

[0073] In the semiconductor device 10, the transistor 20 and the transistor 30 are stacked, and therefore the occupied area can be significantly reduced compared to a configuration in which these transistors are provided separately. In this case, the gates, sources, and drains of the transistors 20 and 30 can be connected via plugs to wirings provided above or below the transistor 30. This allows various circuits to be configured by changing the wiring connections.

[0074] 2A is a schematic perspective view of a transistor 20 and a transistor 30, each having wirings connected to the gate, source, and drain thereof. FIG. 2B is a schematic perspective view including a cross section in the channel length direction. In FIG. 2B, only the cut surface is indicated by a hatched pattern. Note that some components (such as insulating layers) are omitted in FIGS. 2A and 2B.

[0075] In the following explanation, when describing matters common to components distinguished by numbers attached to their symbols (such as wiring 63_1 and wiring 63_2), the explanation may use symbols with omitted numbers (such as wiring 63).

[0076] Wirings 63_1 and 63_2 are provided above the transistor 30, and wirings 64_1 and 64_2, as well as wirings 65_1 and 65_2, are provided above them. The extension direction of the wiring 63 intersects (preferably orthogonal to) the extension directions of the wirings 64 and 65. Note that one or both of the wirings 64 and 65 may be provided below the wiring 63. Furthermore, the wirings 64 and 65 may be disposed at different heights, and their extension directions may intersect.

[0077] The conductive layer 23 is connected to a wiring 63_1 via a plug 53_1, and the conductive layer 33 is connected to a wiring 63_2 via a plug 53_2. The conductive layer 24 is connected to a wiring 64_1 via a plug 54_1, and the conductive layer 34 is connected to a wiring 64_2 via a plug 54_2. The conductive layer 25 is connected to a wiring 65_1 via a plug 55_1, and the conductive layer 35 is connected to a wiring 65_2 via a plug 55_2.

[0078] 2A, various circuits can be realized by connecting the wirings 63, 64, and 65 according to the desired circuit. In this case, wirings located at different heights can be connected to each other via plugs embedded in the interlayer insulating film located between them. Furthermore, wirings located at the same height can be connected to each other directly or via other wirings located at different heights.

[0079] Note that although an example in which the wiring 63, the wiring 64, and the wiring 65 are provided above the transistor 30 has been shown here, one or more of these wirings may be provided below the transistor 20 (between the insulating layer 42 and the substrate 11). Alternatively, one or more of these wirings may be provided below the substrate 11. In this case, a configuration can be adopted in which the wiring provided below the substrate 11 is connected to the transistor 20 or the transistor 30 via a through electrode such as a TSV (Through Silicon Via) in the substrate 11.

[0080] Although the above example shows a semiconductor device 10 having one transistor 20 and one transistor 30, by stacking multiple transistors of each type, a more complex circuit can be configured in a smaller area.

[0081] FIG. 3 shows an example in which four transistors 20 (transistors 20_1 to 20_4) and four transistors 30 (transistors 30_1 to 30_4) are stacked above the four transistors 20, for a total of eight transistors.

[0082] In the configuration shown in FIG. 3, there are provided eight plugs 54 each connected to the conductive layer 24 or the conductive layer 34, eight wires 64 each connected to the plugs 54, eight plugs 55 each connected to the conductive layer 25 or the conductive layer 35, eight wires 65 each connected to the plugs 55, eight plugs 53 each connected to the conductive layer 23 or the conductive layer 33, and eight wires 63 each connected to the plugs 53.

[0083] Here, an example is shown in which the bottom four of the eight transistors are p-type transistors 20 and the top four are n-type transistors 30, but this is not limiting. For example, four transistors 20 may be arranged above four transistors 30, or the transistors 20 and 30 may be arranged alternately.

[0084] Further, although the configuration in which four transistors 20 and four transistors 30 are stacked has been described here, the number of stacked transistors is not limited to this, and each may be two, three, or five or more.

[0085] For example, n (n is an integer of 2 or more) transistors 20 and n transistors 30 can be stacked. In this case, each transistor 20 can have a configuration that independently includes a semiconductor layer 21, an insulating layer 22, and a conductive layer 23, and each transistor 30 can have a configuration that independently includes a semiconductor layer 31, an insulating layer 32, and a conductive layer 33.

[0086] Here, the number of transistors 20 and the number of transistors 30 can be changed as appropriate depending on the target circuit. When applying an inverter circuit using one n-type transistor and one p-type transistor, it is preferable to make the number of transistors 20 and the number of transistors 30 equal.

[0087] [Configuration Example 2] The following describes an example in which the transistor 20 and the transistor 30 are arranged side by side. To avoid redundancy, the same parts as those in Configuration Example 1 above will be referred to and descriptions thereof will be omitted.

[0088] Fig. 4A shows a schematic perspective view of a semiconductor device 10A, which will be described below. Fig. 4B, Fig. 4C, and Fig. 4D show schematic cross-sectional views taken along the cutting lines E-F, G-H, and J-K shown in Fig. 4A, respectively. Fig. 4B corresponds to a cross-section of transistors 20 and 30 in the channel width direction, Fig. 4C corresponds to a cross-section of transistor 20 in the channel length direction, and Fig. 4D corresponds to a cross-section of transistor 30 in the channel length direction.

[0089] The transistor 20 and the transistor 30 are provided side by side on the insulating layer 42. Figure 4A and other figures show an example in which the transistor 20 and the transistor 30 are arranged so that their channel length directions are parallel to each other.

[0090] The transistor 20 and the transistor 30 share a conductive layer 23 that functions as a gate electrode. That is, the semiconductor layer 21 and the semiconductor layer 31 each have a structure in which a channel formation region is surrounded by the conductive layer 23. An insulating layer 22 is provided between the semiconductor layer 21 and the conductive layer 23, and an insulating layer 32 is provided between the semiconductor layer 31 and the conductive layer 23. The insulating layer 22 and the insulating layer 32 can be formed in the same process using the same material. Alternatively, the insulating layer 22 and the insulating layer 32 may be different in either or both of the material and the thickness. Optimizing the material and thickness of the gate insulating layer to match the material of the semiconductor layer can realize a semiconductor device with higher performance.

[0091] Note that the conductive layer 23 functioning as the gate electrode may be provided separately for the transistor 20 and the transistor 30. This allows the operations of the transistor 20 and the transistor 30 to be controlled separately, thereby increasing the degree of freedom in design. In this case, by connecting a wiring connected to the gate electrode of the transistor 20 and a wiring connected to the gate electrode of the transistor 30, a common gate potential can be supplied to the transistor 20 and the transistor 30.

[0092] The conductive layer 24, the conductive layer 25, the conductive layer 34, and the conductive layer 35 are each provided on the insulating layer 42. The conductive layer 24 and the conductive layer 25, and the conductive layer 34 and the conductive layer 35 may be formed in the same process using the same conductive material, or different conductive materials may be used.

[0093] In this way, even when transistor 20 and transistor 30 are arranged side by side, by sharing the gate electrode, the occupied area can be reduced compared to when separate gate electrodes are provided, thereby realizing a highly integrated semiconductor chip.

[0094] Next, an example in which the transistor 20 and the transistor 30 are stacked will be described.

[0095] FIG. 5 shows an example in which a configuration in which four transistors 20 are stacked and a configuration in which four transistors 30 are stacked are arranged side by side.

[0096] In the configuration shown in Figure 5, there are provided four plugs 53 and four wires 63 connected to each conductive layer 23, four plugs 54 and four wires 64 connected to each conductive layer 24, and four plugs 55 and four wires 65 connected to each conductive layer 34.

[0097] Also shown here is an example in which transistors 20 and 30 located at the same height are connected in series. Specifically, this example shows an example in which transistors 20 and 30 share the conductive layer 25. Therefore, transistors 20 and 30 share a gate and are connected in series, realizing a so-called inverter connection.

[0098] Since the conductive layer 25 is in contact with both the semiconductor layer 21 and the semiconductor layer 31, it is preferable to use a material that has low contact resistance with both of them. Alternatively, the conductive layer 25 may be configured such that a material that has low contact resistance with the semiconductor layer 21 or the semiconductor layer 31 is provided in a portion that contacts the semiconductor layer 21 or a portion that contacts the semiconductor layer 31. Alternatively, the conductive layer 25 may have a two-layer structure sandwiching the semiconductor layer 21 and the semiconductor layer 31, with a conductive film that has low contact resistance with one of the semiconductor layer 21 and the semiconductor layer 31 used as the lower layer and a conductive film that has low contact resistance with the other of the semiconductor layer 21 and the semiconductor layer 31 used as the upper layer.

[0099] The configuration shown in Fig. 5 has the advantage of being able to reduce the number of wires by half compared to the configuration shown in Fig. 3. On the other hand, the configuration shown in Fig. 3 has one wire for each terminal, which increases the degree of freedom in circuit design.

[0100] Here, a configuration in which four transistors 20 and four transistors 30 are stacked has been described, but the number of stacked transistors is not limited to this, and may be two, three, five or more.

[0101] For example, n transistors 20 (n is an integer of 2 or more) and n transistors 30 can be stacked. In this case, each transistor 20 can be configured to have a semiconductor layer 21, an insulating layer 22, and a conductive layer 23, and each transistor 30 can be configured to have a semiconductor layer 31, an insulating layer 32, and a conductive layer 23. Furthermore, when focusing on the k-th transistor 20 and transistor 30 (k is an integer of 1 to n) from the bottom, it is preferable that the semiconductor layer 21 and the semiconductor layer 31 are arranged side by side and share the same conductive layer 23. That is, one conductive layer 23 can be configured to have a portion surrounding the semiconductor layer 21 via the insulating layer 22 and a portion surrounding the semiconductor layer 31 via the insulating layer 32.

[0102] The above is a description of the configuration example.

[0103] [Regarding Components] <Substrate> The substrate on which a transistor is formed may be, for example, an insulating substrate, a semiconductor substrate, or a conductive substrate. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (e.g., yttria-stabilized zirconia substrates), and resin substrates. Examples of semiconductor substrates include semiconductor substrates made of silicon or germanium, or compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, gallium oxide, and gallium nitride. Examples of semiconductor substrates include those having an insulating region within the aforementioned semiconductor substrate, such as an SOI (Silicon-On-Insulator) substrate. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Alternatively, substrates containing metal nitrides or metal oxides may also be used. Further, there are substrates in which a conductive layer or a semiconductor layer is provided on an insulating substrate, substrates in which a conductive layer or an insulating layer is provided on a semiconductor substrate, and substrates in which a semiconductor layer or an insulating layer is provided on a conductive substrate. Alternatively, any of these substrates may be provided with elements. The elements provided on the substrate include capacitor elements, resistor elements, switch elements (including transistors), light-emitting elements, memory elements, and the like.

[0104] <Semiconductor Layer> The semiconductor layer 31 preferably contains a metal oxide (oxide semiconductor) that exhibits semiconductor properties.

[0105] The semiconductor layer 31 is preferably made of indium oxide.

[0106] Examples of metal oxides that can be used for the semiconductor layer 31 include Ga oxide and Zn oxide. The metal oxide preferably contains at least In or Zn. The metal oxide preferably contains two or three elements selected from In, element M, and Zn. The element M is a metal element or semimetal element having a high bond energy with oxygen, such as a metal element or semimetal element having a bond energy with oxygen higher than that of indium. Specific examples of the element M include Al, Ga, Sn, Y, Ti, V, Cr, Mn, Fe, Co, Ni, Zr, Mo, Hf, Ta, W, La, Ce, Nd, Mg, Ca, Sr, Ba, B, Si, Ge, and Sb. The element M contained in the metal oxide is preferably one or more of the above elements, and is particularly preferably one or more selected from Al, Ga, Y, and Sn, with Ga being more preferred. Hereinafter, a metal oxide having In, M, and Zn may be referred to as an In-M-Zn oxide. In this specification and the like, metal elements and metalloid elements may be collectively referred to as "metal elements," and the "metal elements" described in this specification and the like may include metalloid elements.

[0107] When the metal oxide is an In-M-Zn oxide, the atomic ratio of In in the In-M-Zn oxide is preferably equal to or greater than the atomic ratio of M. For example, the atomic ratios of metal elements in such an In-M-Zn oxide may be In:M:Zn = 1:1:1, In:M:Zn = 1:1:1.2, In:M:Zn = 2:1:3, In:M:Zn = 3:1:2, In:M:Zn = 4:2:3, In:M:Zn = 4:2:4.1, In:M:Zn = 5:1:3, In:M:Zn = 5:1:6, In:M:Zn = 5:1:7, In:M:Zn = 5:1:8, In:M:Zn = 6:1:6, In:M:Zn = 5:2:5, or compositions in the vicinity thereof. Note that the term "composition in the vicinity" refers to a range of ±30% of the desired atomic ratio. By increasing the atomic ratio of indium in the metal oxide, the on-state current, field-effect mobility, and the like of a transistor can be increased.

[0108] Furthermore, the atomic ratio of In in the In-M-Zn oxide may be less than the atomic ratio of M. For example, the atomic ratio of metal elements in such an In-M-Zn oxide may be In:M:Zn=1:3:2, In:M:Zn=1:3:3, In:M:Zn=1:3:4, or a composition close to these. By increasing the atomic ratio of M in the metal oxide, the generation of oxygen vacancies can be suppressed.

[0109] The semiconductor layer 31 can be made of, for example, In—Zn oxide, In—Ga oxide, In—Sn oxide, In—Ti oxide, In—Ga—Al oxide, In—Ga—Sn oxide, In—Ga—Zn oxide, In—Sn—Zn oxide, In—Al—Zn oxide, In—Ti—Zn oxide, In—Ga—Sn—Zn oxide, or In—Ga—Al—Zn oxide. Ga—Zn oxide may also be used. On the other hand, a material containing Zn is preferred because it is easy to increase crystallinity.

[0110] Note that the metal oxide may contain one or more metal elements with higher period numbers in the periodic table instead of or in addition to indium. The greater the overlap of the orbitals of metal elements, the greater the carrier conduction in the metal oxide tends to be. Therefore, including a metal element with a higher period number may improve the field-effect mobility of a transistor. Examples of metal elements with higher period numbers include metal elements belonging to the fifth period and the sixth period. Specific examples of such metal elements include Y, Zr, Ag, Cd, Sn, Sb, Ba, Pb, Bi, La, Ce, Pr, Nd, Pm, Sm, and Eu. Note that La, Ce, Pr, Nd, Pm, Sm, and Eu are called light rare earth elements.

[0111] The metal oxide may also contain one or more nonmetallic elements, which may increase the field-effect mobility of the transistor. Examples of nonmetallic elements include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.

[0112] The metal oxide can be preferably formed by sputtering or atomic layer deposition (ALD). In particular, it is preferable to form the metal oxide by the ALD method, which has excellent coating properties. When forming the metal oxide by sputtering, the composition of the metal oxide after film formation may differ from the composition of the target. In particular, the zinc content in the metal oxide after film formation may be reduced to about 50% compared to the target. Furthermore, the sputtering method and the ALD method can be combined as a method for forming the metal oxide. For example, a method in which a metal oxide is formed by sputtering and then formed by ALD, or a method in which a metal oxide is formed by ALD and then formed by sputtering, can be used.

[0113] The semiconductor layer 31 may have a stacked structure including two or more metal oxide layers. The two or more metal oxide layers included in the semiconductor layer 31 may have the same or substantially the same composition. By using a stacked structure of metal oxide layers with the same composition, for example, the same sputtering target can be used for formation, thereby reducing manufacturing costs. A stacked structure in which two or more oxide semiconductor layers with different compositions are stacked may also be used. Furthermore, by using the ALD method, it is possible to form a metal oxide layer whose composition varies continuously in the thickness direction. This not only broadens the range of design options compared to using a film with a fixed composition, but also prevents the generation of interface states between two layers with different compositions, thereby improving electrical characteristics and reliability. Furthermore, a metal oxide layer having a stacked structure may be formed using both the sputtering method and the ALD method.

[0114] For example, when the semiconductor layer 31 has a three-layer structure, it is preferable to use a material with higher mobility (higher conductivity) for the first and third layers, i.e., the layers closer to the gate electrode, than for the second layer. This reduces the contact resistance between the semiconductor layer 31 and the conductive layer 34 or 35, resulting in a transistor with a large on-state current. Alternatively, when the semiconductor layer 31 has a three-layer structure, it is preferable to use a material with higher mobility for the second layer than for the first and third layers. This mainly serves as the second layer, suppressing interface scattering with the gate insulating layer and realizing a highly reliable transistor.

[0115] The difference in the mobility and conductivity described above can be expressed, for example, by the indium content. In addition, whether or not an element other than indium that contributes to improving conductivity is included, and the content of that element, also affect the mobility and conductivity. Examples of high-mobility materials include In:Ga:Zn = 4:3:2, In:Zn = 1:1, In:Zn = 2:1, In:Zn = 4:1, In:Sn:Zn = 40:X:10 (where X is 0.1 or more and 5 or less, typically X = 1), or materials with compositions similar to these. On the other hand, materials with lower mobility or conductivity than the above-mentioned materials include In:Ga:Zn = 1:3:2, In:Ga:Zn = 1:3:4, In:Ga:Zn = 2:2:1, In:Ga:Zn = 1:1:1, In:Ga:Zn = 1:1:2, or materials with compositions similar to these.

[0116] It is preferable to use a crystalline metal oxide layer for the semiconductor layer 31. For example, a metal oxide layer having a single crystal structure, a c-axis aligned crystalline (CAAC) structure, a polycrystalline structure, a nanocrystalline (nc) structure, or the like can be used. By using a crystalline metal oxide layer for the semiconductor layer 31, the density of defect states in the semiconductor layer 31 can be reduced, and a highly reliable semiconductor device can be realized.

[0117] When an IGZO (In—Ga—Zn oxide) film is used as the metal oxide layer applied to the semiconductor layer 31, the higher the crystallinity of the metal oxide layer, the more the defect level density in the semiconductor layer 31 can be reduced. On the other hand, by using a metal oxide layer with low crystallinity, the carrier concentration can be increased, and a transistor capable of passing a large current can be realized in some cases.

[0118] In particular, it is preferable to use indium oxide for the semiconductor layer 31. In particular, it is preferable to use a single-crystal indium oxide film. Note that it is preferable to use a crystalline film for the semiconductor layer 31, and it is particularly preferable to use indium oxide with a single-crystal structure. However, indium oxide with a polycrystalline structure or a microcrystalline structure can also be used. By using indium oxide with a single-crystal structure, carrier scattering at crystal grain boundaries can be suppressed, and a transistor with high field-effect mobility can be realized. Furthermore, a highly reliable transistor can be realized. When indium oxide with a polycrystalline structure is used, it is preferable that crystal grain boundaries are not observed at least in the channel formation region (the region overlapping with the conductive layer 23). As a result, even indium oxide with a polycrystalline structure can achieve the same effects as indium oxide with a single-crystal structure.

[0119] The thickness of the semiconductor layer 31 is preferably 1 nm to 50 nm, more preferably 1.5 nm to 40 nm, more preferably 2.5 nm to 30 nm, more preferably 2.5 nm to 20 nm, more preferably 5 nm to 20 nm, and even more preferably 5 nm to 10 nm. The thinner the semiconductor layer 31, the smaller the subthreshold value (S value) may be. Furthermore, the thinner the semiconductor layer 31, the more the threshold voltage may be shifted in the positive direction. Furthermore, by making the semiconductor layer 31 2 nm or more in thickness, the crystallinity of the semiconductor layer 31 can be improved. Note that if the semiconductor layer 31 is less than 2 nm in thickness, clear crystallinity may not be confirmed.

[0120] Among oxide semiconductors with high crystallinity, indium oxide is a film in which one or both of hydrogen and oxygen move more easily than, for example, an IGZO (In-Ga-Zn oxide) film. Therefore, indium oxide is a film in which one or both of hydrogen and oxygen are more easily supplied and discharged than, for example, an IGZO film. This means that excess oxygen or excess hydrogen, which can become carriers or fixed charges, is less likely to accumulate in the semiconductor layer 31, thereby making it possible to provide a transistor with good electrical characteristics and reliability.

[0121] The semiconductor layer 31 preferably has a reduced concentration of elements that reduce crystallinity. For example, the concentration of elements such as boron and aluminum is preferably 1 atomic % or less, more preferably 0.1 atomic % or less, and even more preferably 0.01 atomic % (100 ppm) or less.

[0122] Furthermore, when indium oxide is used for the semiconductor layer 31, unintentionally mixed gallium has a tendency to easily bond with excess oxygen atoms, which may result in a large amount of fluctuation in threshold voltage in a PBTS (Positive Bias Temperature Stress) test. Therefore, when indium oxide is used for the semiconductor layer 31, the gallium concentration in the semiconductor layer 31 is preferably 1 atomic % or less, more preferably 0.1 atomic % or less, and even more preferably 0.01 atomic % (100 ppm) or less.

[0123] A transistor using an oxide semiconductor (hereinafter referred to as an OS transistor) has significantly higher field-effect mobility than a transistor using amorphous silicon. Furthermore, an OS transistor has significantly lower source-drain leakage current in an off state (hereinafter also referred to as an off-state current) and can hold charge accumulated in a capacitor connected in series with the transistor for a long period of time. Furthermore, the use of an OS transistor can reduce the power consumption of a semiconductor device.

[0124] The semiconductor device according to one embodiment of the present invention can be applied to, for example, a processor, a memory device, or various ICs. The transistor according to one embodiment of the present invention is capable of passing a large current and has an extremely low off-state current, and therefore, high-speed operation of a circuit and low power consumption can be achieved at the same time.

[0125] A semiconductor device according to one embodiment of the present invention can also be applied to a display device, for example. To increase the emission luminance of a light-emitting device included in a pixel circuit of a display device, it is necessary to increase the amount of current flowing through the light-emitting device. To achieve this, it is necessary to increase the source-drain voltage of a driving transistor included in the pixel circuit. Since an OS transistor has a higher withstand voltage between the source and drain than a transistor using silicon (hereinafter referred to as a Si transistor), a high voltage can be applied between the source and drain of the OS transistor. Therefore, by using an OS transistor as the driving transistor included in the pixel circuit, it is possible to increase the amount of current flowing through the light-emitting device and increase the emission luminance of the light-emitting device.

[0126] When a transistor operates in the saturation region, an OS transistor can reduce the change in source-drain current with respect to a change in gate-source voltage compared to a Si transistor. Therefore, by using an OS transistor as a driving transistor included in a pixel circuit, the amount of current flowing through the light-emitting device can be precisely controlled. This allows for a larger number of gray levels in the pixel circuit. Furthermore, even if the electrical characteristics (e.g., resistance) of the light-emitting device fluctuate or vary, a stable current can flow.

[0127] As described above, by using an OS transistor for a driving transistor included in a pixel circuit, it is possible to achieve "suppression of black floating," "increase in light emission luminance," "multiple gradations," "suppression of the influence of manufacturing variations in light-emitting devices," and the like.

[0128] OS transistors exhibit smaller variations in electrical characteristics due to radiation exposure than Si transistors, i.e., have high radiation resistance, and therefore can be suitably used in environments where radiation may be incident. It can also be said that OS transistors have high reliability against radiation. For example, OS transistors can be suitably used in pixel circuits of X-ray flat panel detectors. Furthermore, OS transistors can be suitably used in semiconductor devices used in outer space. Examples of radiation include electromagnetic radiation (e.g., X-rays and gamma rays) and particle radiation (e.g., alpha rays, beta rays, proton rays, and neutron rays).

[0129] Examples of semiconductor materials that can be used for the semiconductor layer 21 include semiconductors made of simple elements and compound semiconductors. Examples of semiconductors made of simple elements include silicon (including single crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon) and germanium. Examples of compound semiconductors include gallium arsenide and silicon germanium. Examples of compound semiconductors include organic semiconductors, nitride semiconductors, and oxide semiconductors. Note that these semiconductor materials may contain impurities as dopants.

[0130] Alternatively, the semiconductor layer 21 may have a layered material that functions as a semiconductor. A layered material is a general term for a group of materials that have a layered crystal structure. A layered crystal structure is a structure in which layers formed by covalent or ionic bonds are stacked via bonds weaker than covalent or ionic bonds, such as van der Waals bonds. A layered material has high electrical conductivity within a unit layer, that is, high two-dimensional electrical conductivity. By using a material that functions as a semiconductor and has high two-dimensional electrical conductivity in the channel formation region, a transistor with a large on-current can be provided.

[0131] Examples of the layered material include graphene, silicene, and chalcogenides. Chalcogenides are compounds containing chalcogen (an element belonging to Group 16 of the periodic table). Examples of chalcogenides include transition metal chalcogenides and Group 13 chalcogenides. Specific examples of transition metal chalcogenides that can be used as semiconductor layers of transistors include molybdenum sulfide (typically MoS ２ ), molybdenum selenide (typically MoSe ２ ), molybdenum telluride (typically MoTe ２ ), tungsten sulfide (typically WS ２ ), tungsten selenide (typically WSe ２ ), tungsten tellurium (typically WTe ２ ), hafnium sulfide (typically HfS ２ ), hafnium selenide (typically HfSe ２ ), zirconium sulfide (typically ZrS ２ ), zirconium selenide (typically ZrSe ２ ) etc.

[0132] <Gate Insulating Layer> The insulating layer 22 and the insulating layer 32 function as gate insulating layers of the transistor.

[0133] When an oxide semiconductor is used for the semiconductor layer 31, it is preferable to use an oxide insulating film for at least a film of the insulating layer 32 that is in contact with the semiconductor layer 31. For example, one or more of silicon oxide, silicon oxynitride, aluminum oxide, aluminum oxynitride, hafnium oxide, hafnium oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, and Ga-Zn oxide can be used. Alternatively, a nitride insulating film such as silicon nitride, silicon nitride oxide, aluminum nitride, or aluminum nitride oxide can also be used for the insulating layer 32. Furthermore, the insulating layer 32 may have a stacked structure, for example, a stacked structure including one or more oxide insulating films and one or more nitride insulating films.

[0134] Furthermore, the insulating layers 22 and 32 are preferably formed by stacking insulating materials made of high-k materials with a high dielectric constant, and preferably by stacking a high-k material and a material with a higher dielectric strength than the high-k material. For example, the insulating layers 22 and 32 can be formed by stacking insulating films (also referred to as ZAZ) in which zirconium oxide, aluminum oxide, and zirconium oxide are stacked in this order. Alternatively, the insulating layers 22 and 32 can be formed by stacking insulating films (also referred to as ZAZA) in which zirconium oxide, aluminum oxide, zirconium oxide, and aluminum oxide are stacked in this order. Alternatively, the insulating films can be formed by stacking insulating films (also referred to as hafnium zirconium oxide, aluminum oxide, hafnium zirconium oxide, and aluminum oxide) in this order. By stacking an insulator with a relatively high dielectric strength, such as aluminum oxide, the dielectric strength can be improved, and electrostatic breakdown can be suppressed.

[0135] Furthermore, a material exhibiting ferroelectricity may be used for the insulating layer 22 and the insulating layer 32. Examples of the material exhibiting ferroelectricity include hafnium oxide, zirconium oxide, and HfZrO. Ｘ (X is a real number greater than 0).

[0136] When the insulating layer 32 has a two-layer structure, it is preferable to use an insulating film having a function of capturing or fixing hydrogen as the film in contact with the semiconductor layer 31, and to use an insulating film having a barrier property against hydrogen as the film located on the conductive layer 33 side that functions as the gate electrode. This makes it possible to suppress diffusion of hydrogen from the conductive layer 33 side to the semiconductor layer 31, thereby realizing a highly reliable transistor.

[0137] As an insulating film that captures or fixes hydrogen, it is preferable to use a hafnium oxide film, a hafnium silicate film, an aluminum oxide film, etc. Furthermore, as an insulating film having a barrier property against hydrogen, it is preferable to use a silicon nitride film, a silicon nitride oxide film, an aluminum oxide film, a magnesium oxide film, a hafnium oxide film, a gallium oxide film, etc.

[0138] Alternatively, an insulating film that releases oxygen when heated may be used as a film in contact with the semiconductor layer 31, and an insulating film having a barrier property against hydrogen may be used as a film located on the conductive layer 33 side. Alternatively, an insulating film that releases oxygen when heated may be used as a film in contact with the semiconductor layer 31, and an insulating film that has a function of capturing or fixing hydrogen may be used as a film located on the conductive layer 33 side.

[0139] When the insulating layer 32 has a three-layer structure, it is preferable to use an insulating film made of a material through which oxygen easily diffuses as the film in contact with the semiconductor layer 31, an insulating film having barrier properties against hydrogen and oxygen as the film located on the conductive layer 33 side, and an insulating film having the function of capturing or fixing hydrogen as the film located between them. Silicon oxide or silicon oxynitride can be used as a material with a low relative dielectric constant. With this structure, oxygen can be supplied to the semiconductor layer 31 from the film in contact with the semiconductor layer 31. Furthermore, the film located on the conductive layer 33 side prevents oxygen from diffusing toward the conductive layer 33, thereby suppressing oxidation of the conductive layer 33.

[0140] As the insulating film having a barrier property against oxygen, it is preferable to use an aluminum oxide film, a silicon nitride film, a hafnium oxide film, a hafnium silicate film, etc. As the insulating film having a barrier property against oxygen and hydrogen, it is preferable to use an aluminum oxide film, a silicon nitride film, a hafnium oxide film, etc.

[0141] When the insulating layer 32 has a four-layer structure, it is preferable to use an insulating film having a barrier property against oxygen as the film in contact with the semiconductor layer 31, followed by an insulating film made of a material into which oxygen easily diffuses, an insulating film having a function of capturing or fixing hydrogen, and an insulating film having a barrier property against hydrogen and oxygen, in order from the side closer to the semiconductor layer 31. That is, in addition to the above-described three-layer structure, a structure can be obtained in which a film in contact with the semiconductor layer 31 is added. By using an insulating film having a barrier property against oxygen as the film in contact with the semiconductor layer 31, oxygen can be prevented from being desorbed from the semiconductor layer 31. In this case, it is preferable to use an aluminum oxide film as the film in contact with the semiconductor layer 31. Aluminum oxide not only has a barrier property against oxygen but also has a function of capturing or fixing hydrogen, and therefore has the effect of preventing hydrogen from diffusing into the semiconductor layer 31.

[0142] When the insulating layer 32 has a stacked structure, each insulating film is preferably a thin film. For example, the thickness of the insulating layer 32 is 1 nm to 20 nm, preferably 3 nm to 10 nm, to reduce the subthreshold swing (also referred to as the S value) of the transistor. The thickness of each insulating film is preferably 0.1 nm to 10 nm, more preferably 0.1 nm to 5 nm, still more preferably 0.5 nm to 5 nm, still more preferably 1 nm to less than 5 nm, and even more preferably 1 nm to 3 nm.

[0143] As a specific example, the insulating layer 32 has a four-layer structure in which an aluminum oxide film, a silicon oxide film, a hafnium oxide film, and a silicon nitride film are stacked in this order from the semiconductor layer 31 side, and it is preferable that the thicknesses of these films are 1 nm, 2 nm, 2 nm, and 1 nm from the semiconductor layer 31 side.

[0144] In this specification and the like, the barrier property refers to a property that makes it difficult for a corresponding substance to diffuse (also referred to as a property that makes it difficult for a corresponding substance to permeate, a property that the permeability of a corresponding substance is low, or a function that suppresses the diffusion of a corresponding substance). Note that when hydrogen is described as a corresponding substance, it can refer to, for example, a hydrogen atom, a hydrogen molecule, a water molecule, and OH. −Furthermore, unless otherwise specified, impurities when described as corresponding substances refer to impurities in the channel formation region or semiconductor layer, and include, for example, hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules (N ２ O, NO, NO ２ The term "oxygen" refers to at least one of an oxygen atom, an oxygen molecule, etc., when described as a corresponding substance.

[0145] Here, a transistor using a metal oxide film can have stable electrical characteristics by being surrounded by an insulating film that has a function of suppressing the permeation of impurities such as water and hydrogen and oxygen. Examples of insulating films that have a function of suppressing the permeation of impurities and oxygen include metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, and oxides containing aluminum and hafnium (hafnium aluminate). Nitrides such as aluminum nitride, silicon nitride oxide, and silicon nitride can also be used.

[0146] Examples of insulating film materials capable of capturing or adhering hydrogen include metal oxides such as oxides containing hafnium, oxides containing magnesium, oxides containing aluminum, and oxides containing aluminum and hafnium (hafnium aluminate). These metal oxides may further contain zirconium, such as oxides containing hafnium and zirconium. Metal oxides with an amorphous structure have dangling bonds in some oxygen atoms, which enhance their ability to capture or adhering hydrogen. Therefore, these metal oxides preferably have an amorphous structure. For example, an amorphous structure may be achieved by including silicon in these oxides. For example, it is preferable to use an oxide containing hafnium and silicon (hafnium silicate). Metal oxides may have crystalline regions and / or grain boundaries in some regions.

[0147] <Conductive Layer> The conductive layer 24 and the conductive layer 25 are in contact with the semiconductor layer 21. The conductive layer 34 and the conductive layer 35 are in contact with the semiconductor layer 31.

[0148] Here, when an oxide semiconductor is used as the semiconductor layer 31, if an easily oxidized metal such as aluminum is used in the portions of the conductive layers 34 and 35 that contact the semiconductor layer 31, an insulating oxide (e.g., aluminum oxide) may be formed between the conductive layers 34 and 35 and the semiconductor layer 31, preventing electrical continuity therebetween. Therefore, it is preferable to use a conductive material that is resistant to oxidation, a conductive material that maintains low electrical resistance even when oxidized, or a conductive oxide material for at least the portions of the conductive layers 34 and 35 that contact the semiconductor layer 31.

[0149] For the conductive layer 34 and the conductive layer 35 in contact with the semiconductor layer 31, it is preferable to use, for example, titanium, tantalum nitride, titanium nitride, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, etc. These are preferable because they are conductive materials that are difficult to oxidize or materials that maintain conductivity even when oxidized.

[0150] Alternatively, conductive oxides such as indium oxide, zinc oxide, In—Sn oxide, In—Zn oxide, In—W oxide, In—W—Zn oxide, In—Ti oxide, In—Ti—Sn oxide, In—Sn—Si oxide, and Ga—Zn oxide can be used. Conductive oxides containing indium are particularly preferred because of their high conductivity. Alternatively, oxide materials such as In—Ga—Zn oxide that can be used for the semiconductor layer 31 can also be used as a conductive layer by increasing the carrier concentration.

[0151] For example, the conductive layer 34 and the conductive layer 35 can each have a single-layer structure of the above-mentioned conductive oxide film, a three-layer structure in which a titanium nitride film, a tungsten film, and a titanium nitride film are stacked in this order, a two-layer structure in which a ruthenium film or a ruthenium oxide film is stacked on tungsten, a two-layer structure in which a ruthenium film or a ruthenium oxide film is stacked on the above-mentioned conductive oxide film, or a two-layer structure in which the above-mentioned conductive oxide film is stacked on a ruthenium film or a ruthenium oxide film.

[0152] It is preferable to use a low-resistance conductive material for the conductive layers 23, 33, 24, and 25. For example, it is preferable to use a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, cobalt, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing such a metal element. Nitrides of the above metals or alloys, or oxides of the above metals or alloys, may also be used. For example, it is preferable to use tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc. It is also preferable to use semiconductors with high electrical conductivity, such as polycrystalline silicon containing impurity elements such as phosphorus, or silicides such as nickel silicide.

[0153] The conductive layers 23, 33, 24, and 25 can also be formed using the nitrides and oxides that can be used for the conductive layers 34 and 35.

[0154] <Insulating Layer> The insulating layer 42, the insulating layer 43, the insulating layer 44, and the insulating layer 45 can be used as interlayer insulating films. For example, they are preferably formed by a film formation method such as a sputtering method or a plasma CVD method. In particular, when the insulating layer 44 and the insulating layer 45 are formed by a sputtering method, hydrogen gas is not used as a film formation gas, and therefore the insulating layer 44 and the insulating layer 45 can be formed into films with an extremely low hydrogen content. Therefore, the supply of hydrogen to the semiconductor layer 31 can be suppressed, and the electrical characteristics of the transistor 30 can be stabilized.

[0155] The insulating layers 42, 43, 44, and 45 preferably have a low dielectric constant. By using a material with a low dielectric constant as the interlayer insulating film, the parasitic capacitance generated between wirings can be reduced. For example, it is preferable to have one or more of silicon oxide, silicon oxynitride, silicon oxide doped with fluorine, silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, and silicon oxide having vacancies. Silicon oxide and silicon oxynitride are preferable because they are thermally stable.

[0156] Since the insulating layers 42, 43, 44, and 45 function as interlayer insulating layers, it is preferable to use a film formation method that allows film formation at a high film formation rate compared to other insulating layers. For example, the insulating layers 42, 43, 44, and 45 may be formed using TEOS (Tetra-Ethyl-Ortho-Silicate, chemical formula: Si(OC ２ H ５ ) ４ Alternatively, a silicon oxide film formed by plasma CVD using a silicon dioxide film containing SiO 2 may be used. This can improve productivity.

[0157] The insulating layers 46 and 47, which function as spacers, are preferably made of the above-mentioned material having a low relative dielectric constant.

[0158] This concludes the description of the components.

[0159] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0160] Embodiment Mode 2 In this embodiment mode, an example of a circuit configuration using the semiconductor device described in Embodiment Mode 1 will be described.

[0161] One embodiment of the present invention can be applied to a logic circuit having a CMOS circuit configuration, such as a basic logic gate such as a NOT (also referred to as an inverter or a NOT circuit), and also to a combinational circuit and a sequential circuit in which logic gates are combined.

[0162] 6A shows an example of a circuit configuration combining NOT circuits. Fig. 6A illustrates a NOT circuit 100_1 having transistors PM1 and NM1, and a NOT circuit 100_2 having transistors PM2 and NM2. The transistors PM1 and PM2 are p-type transistors (pMOS), and the transistors NM1 and NM2 are n-type transistors (nMOS).

[0163] 6A illustrates the NOT circuits 100_1 and 100_2, as well as the power supply lines VHL and VLL, the wiring MDL, and the signal lines INL and OUTL. The transistors included in the NOT circuits 100_1 and 100_2 are connected to the power supply lines VHL and VLL, the wiring MDL, and the signal lines INL and OUTL as illustrated in FIG.

[0164] The power supply line VHL is a power supply line that transmits a high power supply potential, and the power supply line VLL is a power supply line that transmits a low power supply potential. The wiring MDL is a wiring that transmits an output signal of the NOT circuit 100_1 as an input signal of the NOT circuit 100_2.

[0165] The signal line INL is a wiring that transmits an input signal. The signal line OUTL is a wiring that transmits an output signal. For example, when the signal line INL that transmits an input signal is at H (High) level, the line MDL is at L (Low) level. When the line MDL is at L level, the signal line OUTL that transmits an output signal is at H level.

[0166] The transistors PM1 and PM2 can be the transistor 20 described in the first embodiment. The transistor 20 has a GAA structure and is a transistor (Si transistor) that uses silicon for the semiconductor layer. Therefore, improvement in transistor controllability, improvement in on-current, and reduction in off-current can be expected.

[0167] The transistor 30 described in Embodiment 1 can be applied to the transistors NM1 and NM2. The transistor 30 has a GAA structure and is a transistor (OS transistor) using a metal oxide for a semiconductor layer. Therefore, improvement in controllability, increase in on-state current, and decrease in off-state current of the transistor can be expected.

[0168] The transistors PM1 and PM2 and the transistors NM1 and NM2 can have different semiconductor materials in their semiconductor layers and can be arranged in different layers. Therefore, the transistors included in the NOT circuits 100_1 and 100_2 can be arranged to overlap with each other, thereby increasing the number of transistors per unit area.

[0169] FIG. 6B is a block diagram showing an example of stacking layers including transistors PM1, PM2, NM1, and NM2. The layer including transistor PM1 is designated PL1, the layer including transistor PM2 is designated PL2, the layer including transistor NM1 is designated NL1, and the layer including transistor NM2 is designated NL2. The layers are stacked in this order. The power supply lines VHL and VLL and the signal lines INL and OUTL are preferably provided in layers other than the layers including transistors. By arranging wiring such as power supply lines and signal lines in layers other than the layers including transistors, the number of transistors per unit area in the layers PL1, PL2, NL1, and NL2 can be increased. As an example, the layer SL including the power supply lines VHL and VLL and the signal lines INL and OUTL can be provided above the layer NL2.

[0170] In the block diagrams in this specification, drawings, etc., the direction perpendicular to the surface of the substrate on which the transistors are provided is defined as the Z direction in order to explain the overlap of layers. For example, the Z direction is defined in the block diagram shown in Figure 6B. For ease of understanding, the Z direction may be referred to as the direction perpendicular to the surface of the substrate in the specification.

[0171] 7 is a circuit diagram schematically illustrating the layers PL1, PL2, NL1, NL2, and SL described in FIG. 6B. The circuit diagram shown in FIG. 7 corresponds to the circuit diagram shown in FIG. 6A. The layer PL1 shown in FIG. 7 includes the transistor PM1, the layer PL2 shown in FIG. 7 includes the transistor PM2, the layer NL1 shown in FIG. 7 includes the transistor NM1, the layer NL2 shown in FIG. 7 includes the transistor NM2, and the layer SL shown in FIG. 7 includes the power supply lines VHL and VLL and the signal lines INL and OUTL. Also, in FIG. 7, wiring MDL connecting the transistors PM1 and NM1 to the transistors PM2 and NM2 is provided across the layers PL1, PL2, NL1, and NL2.

[0172] In this specification, drawings, etc., X, Y, and Z directions may be defined to explain the arrangement of each element provided on multiple layers. For example, in the circuit diagram shown in Figure 7, X, Y, and Z directions are defined to explain the arrangement of each element. The X, Y, and Z directions are perpendicular to each other.

[0173] As shown in Figure 7, transistors PM1, PM2, NM1, and NM2, which comprise NOT circuits 100_1 and 100_2, are provided on separate layers. The conductive or non-conductive state of each of transistors PM1, PM2, NM1, and NM2 can be individually controlled. By varying the wiring relationships of the stacked transistors PM1, PM2, NM1, and NM2, a basic logic gate can be configured. This allows for a semiconductor device with a high degree of integration of transistors per unit area.

[0174] For example, one embodiment of the present invention can be applied to an SRAM (Static RAM) in which a NOT circuit and a transistor are combined. The case where one embodiment of the present invention is applied to an SRAM will be described with reference to FIGS. 8A, 8B, and 9. Note that in the description of FIGS. 8A, 8B, and 9, the same configurations as those in FIGS. 6A, 6B, and 7 may refer to the above description, and repeated description may be omitted.

[0175] The SRAM memory cell 200 shown in Figure 8A has transistors SW1 and SW2 and NOT circuits 100_1 and 100_2. The SRAM memory cell 200 shown in Figure 8A corresponds to a configuration in which bit lines BL and BLB are used instead of the signal lines INL and OUTL in Figure 6A, and transistors SW1 and SW2 controlled by a word line WL are added. The transistors PM1, PM2, NM1, and NM2, the transistors SW1 and SW2, the power supply lines VHL and VLL, the bit lines BL and BLB, and the word line WL are connected as shown in Figure 8A.

[0176] The bit line BL is a wiring for writing and reading data signals. The bit line BLB is a wiring for writing and reading data signals with inverted logic of the bit line BLB. The transistors SW1 and SW2 are transistors that function as switches. The transistors SW1 and SW2 may be nMOS. The on / off of the transistors SW1 and SW2 is controlled in accordance with a word signal supplied to the word line WL.

[0177] The transistors SW1 and SW2 can be OS transistors, similar to the transistors NM1 and NM2. The transistors SW1 and SW2 can be arranged in different layers, similar to the transistors NM1 and NM2. Therefore, the transistors included in the SRAM memory cell 200 can be arranged in a stacked manner, thereby increasing the number of transistors per unit area.

[0178] 8B is a block diagram showing an example in which a layer SWL1 having a transistor SW1 and a layer SWL2 having a transistor SW2 are stacked in addition to the layers PL1, PL2, NL1, NL2, and SL described in FIG. 6B. The layers SWL1 and SWL2 are shown to be provided between the layers NL2 and SL. In the layer SL shown in FIG. 8B, bit lines BL and BLB and word lines WL are provided in addition to power supply lines VHL and VLL.

[0179] Fig. 9 is a circuit diagram schematically showing the layers PL1, PL2, NL1, NL2, SWL1, SWL2, and SL described in Fig. 8B. The circuit diagram shown in Fig. 9 corresponds to the circuit diagram shown in Fig. 8A. The layer SWL1 shown in Fig. 9 is provided with the transistor SW1, the layer SW2 shown in Fig. 9 is provided with the transistor SW2, and the layer SL shown in Fig. 9 is provided with the power supply lines VHL and VLL, the bit lines BL and BLB, and the word line WL.

[0180] 9, the transistors PM1, PM2, NM1, NM2, SW1, and SW2 are provided in different layers, thereby making it possible to provide a semiconductor device with an increased integration density of transistors per unit area.

[0181] 6B and 7, the layer SL having the power supply lines VHL and VLL and the signal lines INL and OUTL can be divided and arranged in multiple layers. For example, as shown in the block diagram of FIG. 10A, a configuration can be adopted in which a layer SL1 having the power supply lines VHL and the signal lines INL and OUTL is provided below a layer PL1, and a layer SL2 having the power supply line VLL is provided above a layer NL2.

[0182] FIG. 10B is a circuit diagram schematically illustrating the layers SL1, PL1, PL2, NL1, NL2, and SL2 shown in FIG. 10A. The circuit diagram shown in FIG. 10B represents the circuit diagram shown in FIG. 1A. As shown in FIGS. 10A and 10B, the power supply line VHL and the signal lines INL and OUTL are arranged separately from the power supply line VLL on the layers SL1 and SL2, thereby increasing the degree of freedom in arranging wiring for connections within the circuit. Also, in FIGS. 10A and 10B, layers NL1 and NL2 having nMOS transistors are provided above layers PL1 and PL2 having pMOS transistors. Therefore, by arranging the power supply line VHL connected to the pMOS transistors below layers PL1 and PL2 and arranging the power supply line VLL connected to the nMOS transistors above layers NL1 and NL2, the wiring functioning as a power supply line can be shortened.

[0183] Furthermore, for example, one embodiment of the present invention can be applied to a circuit in which the number of connected NOT circuits is increased. A case in which one embodiment of the present invention is applied to a circuit having four NOT circuits will be described with reference to FIGS. 11, 12A, and 12B. Note that in the description of FIGS. 11, 12A, and 12B, the same configurations as those in FIGS. 6A to 10B may refer to the above description, and repeated description may be omitted.

[0184] 11 corresponds to a configuration in which a NOT circuit 100_3 having transistors PM3 and NM3 and a NOT circuit 100_4 having transistors PM4 and NM4 are added to the NOT circuits 100_1 and 100_2 in FIG. 6A. The transistors PM3 and PM4 are p-type transistors (pMOS), and the transistors NM3 and NM4 are n-type transistors (nMOS).

[0185] 11 illustrates the NOT circuits 100_1 to 100_4, as well as power supply lines VHL and VLL, wirings MDL1 to MDL3, and signal lines INL and OUTL. The transistors included in the NOT circuits 100_1 to 100_4, the power supply lines VHL and VLL, the wirings MDL1 to MDL3, and the signal lines INL and OUTL are connected as illustrated in FIG. 11. The wiring MDL1 is a wiring that transmits the output signal of the NOT circuit 100_1 as an input signal of the NOT circuit 100_2. The wiring MDL2 is a wiring that transmits the output signal of the NOT circuit 100_2 as an input signal of the NOT circuit 100_3. The wiring MDL3 is a wiring that transmits the output signal of the NOT circuit 100_3 as an input signal of the NOT circuit 100_4.

[0186] Si transistors can be used as the transistors PM3 and PM4. OS transistors can be used as the transistors NM3 and NM4. The transistors PM3, PM4, NM3, and NM4 can be arranged in different layers. Therefore, the transistors included in the NOT circuits 100_1 to 100_4 can be arranged in a stacked manner, thereby increasing the number of transistors per unit area.

[0187] 12A is a block diagram showing an example in which, in addition to the layers PL1, PL2, NL1, and NL2 described in FIG. 6B, a layer PL3 having a transistor PM3, a layer PL4 having a transistor PM4, a layer NL3 having a transistor NM3, and a layer NL4 having a transistor NM4 are stacked. The layers PL3 and PL4 are shown to be provided above the layer PL2. The layers NL3 and NL4 are shown to be provided above the layer NL2. Note that FIG. 12A also shows the configuration in which the layers SL1 and SL2 described in FIGS. 10A and 10B are provided.

[0188] Fig. 12B is a circuit diagram schematically showing layers SL1, PL1, PL2, PL3, PL4, NL1, NL2, NL3, NL4, and SL2 shown in Fig. 12A. The circuit diagram shown in Fig. 12B corresponds to the circuit diagram shown in Fig. 11.

[0189] As shown in FIG. 12B, the transistors PM1 to PM4 and NM1 to NM4, which include the NOT circuits 100_1 to 100_4, are provided on separate layers. The transistors PM1, PM2, PM3, PM4, NM1, NM2, NM3, and NM4 can be individually controlled to be conductive or non-conductive. By varying the wiring relationships of the stacked transistors PM1, PM2, PM3, PM4, NM1, NM2, NM3, and NM4, a basic logic gate can be configured. This allows for a semiconductor device with a high degree of transistor integration per unit area.

[0190] 12B, the power supply line VHL and the signal lines INL and OUTL are arranged separately on layers SL1 and SL2, and the power supply line VLL can be arranged more freely for interconnection within the circuit. Also, in FIG. 12B, layers NL1 to NL4 having nMOS transistors are provided on layers PL1 to PL4 having pMOS transistors. Therefore, by arranging the power supply line VHL connected to the pMOS transistors in a layer below layers PL1 to PL4 and arranging the power supply line VLL connected to the nMOS transistors in a layer above layers NL1 to NL4, the length of the interconnects that function as power supply lines can be shortened.

[0191] For example, one embodiment of the present invention can be applied to the structure in which the Si transistor and the OS transistor described in Embodiment 1 are arranged in the same layer and driven by a common gate. The case where this structure is applied to the circuit diagram described in FIG. 11 will be described with reference to FIGS. 13A and 13B. Note that in the description of FIGS. 13A and 13B, the same structures as those in FIGS. 6A to 12B may refer to the above description, and repeated description may be omitted.

[0192] 13A is a block diagram showing an example in which layers including transistors PM1 to PM4 and transistors NM1 to NM4 are stacked one on top of the other, with the layer including transistors PM1 and NM1 designated CML1, the layer including transistors PM2 and NM2 designated CML2, the layer including transistors PM3 and NM3 designated CML3, and the layer including transistors PM4 and NM4 designated CML4.

[0193] The power supply lines VHL and VLL and the signal lines INL and OUTL are preferably provided in a layer different from the layer in which the transistors are provided. By arranging wiring such as power supply lines and signal lines in a layer different from the layer in which the transistors are provided, the number of transistors per unit area in the layers CML1 to CML4 can be increased. As an example, the layer SL2 having the power supply lines VHL and VLL and the signal lines INL and OUTL can be provided in the layer above the layer NL2. Note that FIG. 13A applies the configuration in which the layers SL1 and SL2 described in FIGS. 10A and 12A are provided.

[0194] FIG. 13B is a circuit diagram schematically illustrating layers SL1, CML1, CML2, CML3, CML4, and SL2 shown in FIG. 13A. As shown in FIG. 13B, transistors PM1 and NM1, transistors PM2 and NM2, transistors PM3 and NM3, and transistors PM4 and NM4 are provided on different layers. Transistors PM1 and NM1, transistors PM2 and NM2, transistors PM3 and NM3, and transistors PM4 and NM4 can be individually controlled to be conductive or non-conductive. By varying the wiring relationships between stacked transistors PM1 and NM1, transistors PM2 and NM2, transistors PM3 and NM3, and transistors PM4 and NM4, a basic logic gate can be configured. This allows for a semiconductor device with a high degree of integration of transistors per unit area.

[0195] 13B, the power supply line VHL and the signal line INL, and the OUTL and the power supply line VLL are arranged separately on layers SL1 and SL2, thereby increasing the degree of freedom in arranging wiring for connections within the circuit. Also, as shown in FIG. 13B, it is preferable to arrange the pMOS transistors PM1 to PM4 and the nMOS transistors NM1 to NM4 in an overlapping manner. In this configuration, by arranging the power supply line VHL and the power supply line VLL to extend in the Z direction, the pMOS transistors and the power supply line VHL and the nMOS transistors and the power supply line VLL can be connected, thereby shortening the routing of the power supply lines extending in the X or Y direction.

[0196] The configuration in which a Si transistor and an OS transistor are arranged in the same layer and driven by a common gate, as described in Embodiment 1, can be applied to the SRAM described in FIG. 8A. The application of this configuration to the SRAM will be described with reference to FIGS. 14A and 14B. In the description of FIGS. 14A and 14B, the same configurations as those in FIGS. 6A to 13B may refer to the above description, and repeated description may be omitted.

[0197] FIG. 14A is a block diagram illustrating an example in which layers SL1, CML1, CML2, SWL1, SWL2, and SL2 are stacked when a Si transistor and an OS transistor are arranged in the same layer and driven by a common gate.

[0198] Fig. 14B is a circuit diagram schematically illustrating the layers SL1, CML1, CML2, SWL1, SWL2, and SL2 shown in Fig. 14A. Fig. 14B illustrates an example in which power supply lines VHL and VLL are provided in the layer SL1, and bit lines BL and BLB and word lines WL are provided in the layer SL2.

[0199] 14B, the transistors PM1 and NM1, the transistors PM2 and NM2, the transistor SW1, and the transistor SW2 are provided in different layers, thereby providing a semiconductor device with an increased degree of integration of transistors per unit area.

[0200] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0201] Embodiment 3 In this embodiment, an indium oxide film that can be used for a semiconductor layer of a transistor included in a semiconductor device of one embodiment of the present invention will be described.

[0202] In this specification and the like, indium oxide having at least a crystalline portion or a crystalline region in a film is referred to as crystalline indium oxide (crystal IO) or crystalline indium oxide (crystalline IO). Examples of crystalline IO or crystalline IO include single-crystalline indium oxide, polycrystalline indium oxide, and microcrystalline indium oxide.

[0203] Indium oxide is a semiconductor material having physical properties that are completely different from those of oxide semiconductors such as In—Ga—Zn oxide (hereinafter also referred to as IGZO) and zinc oxide.

[0204] The carrier concentration dependence of the Hall mobility of indium oxide, silicon, and IGZO will be explained. FIG. 15A shows the carrier concentration dependence of the Hall mobility of silicon (Si) and indium oxide (InO Ｘ ) and FIG. 15B is a schematic diagram showing the carrier concentration dependence of the hole mobility for IGZO.

[0205] First, IGZO tends to exhibit higher hole mobility as the carrier concentration increases, as shown by the arrows in Figure 15B. On the other hand, indium oxide tends to exhibit higher hole mobility as the carrier concentration decreases, as shown by the arrows in Figure 15A (see Non-Patent Document 1). This trend is similar to that of silicon; the lower the dopant (impurity) concentration in the material, the less impurity scattering there is and the higher the hole mobility. In other words, the higher the purity and intrinsic indium oxide, the higher the hole mobility. From these results, it can be said that indium oxide, unlike IGZO, is a material with physical properties similar to those of silicon. Note that the characteristics of indium oxide shown in Figure 15A are assumed to be single crystal. Therefore, when indium oxide is non-single crystal (e.g., polycrystalline), the characteristics may differ from those shown in Figure 15A.

[0206] 15A, the range R1 of low carrier concentration has extremely high hole mobility, and therefore can be said to be a range of carrier concentration suitable for, for example, a channel formation region of a transistor. For example, in the case of indium oxide, the range R1 is a range where the carrier concentration value is 1×10 １５ cm −３ The range includes, for example, 1×10 １４ cm −３ That's it, 1 x 10 １８ cm −３ By sufficiently reducing the carrier concentration, the Hall mobility can be reduced to 270 cm ２ It is expected that the resistance can be increased to about / (V·s).

[0207] In addition, in indium oxide, the region where the carrier concentration is in the range R1 may contain an element that lowers the carrier concentration. Examples of elements that lower the carrier concentration include magnesium, calcium, zinc, cadmium, and copper. By substituting these elements for indium, the carrier concentration can be lowered. Examples of elements that lower the carrier concentration include nitrogen, phosphorus, arsenic, and antimony. For example, by substituting nitrogen, phosphorus, arsenic, or antimony for oxygen, the carrier concentration can be lowered.

[0208] On the other hand, the range R2 with a high carrier concentration has a low electrical resistance, and can be said to be a range of carrier concentrations suitable for, for example, the source and drain regions of a transistor, a resistor, or a transparent conductive film. ２０ cm −３ The range includes, for example, 1×10 １９ cm −３ That's it, 1 x 10 ２２ cm −３ By increasing the carrier concentration sufficiently, the resistivity can be reduced to 1×10 −４ It is expected that the resistance can be reduced to Ω·cm or less.

[0209] In addition, in indium oxide, the region where the carrier concentration is in the range R2 may contain an element that increases the carrier concentration. For example, it is preferable that the indium oxide contains an element that is common to the source electrode and drain electrode of the transistor. Examples of elements that increase the carrier concentration include titanium, zirconium, hafnium, tantalum, tungsten, molybdenum, tin, silicon, and boron. In particular, it is more preferable to use an element whose oxide has conductive or semiconducting properties. Note that, as a method for supplying an element that increases the carrier concentration, a method of forming a film containing the element and diffusing it, ion implantation, ion doping, plasma immersion ion implantation, or plasma treatment can be used. Note that, unless otherwise specified in this specification, the presence or absence of mass separation is not limited. For example, in this specification, a method of supplying ions after mass separation is referred to as an ion implantation method, and a method of supplying ions without mass separation is referred to as an ion doping method.

[0210] In this way, indium oxide uses a region with a low carrier concentration as the channel formation region of a transistor, and a region with a high carrier concentration as the source and drain regions of the transistor. In other words, indium oxide can be said to be an oxide capable of valence electron control. Note that IGZO may experience strain in the source and drain regions due to stress from electrodes in contact with the IGZO, resulting in the formation of n-type regions. On the other hand, unlike IGZO, indium oxide is capable of valence electron control, and therefore does not require strain to be formed in the film as with IGZO. Less strain in the film is expected to improve reliability. For example, by separately creating a region with a carrier concentration in the range R1 shown in FIG. 15A and a region with a carrier concentration in the range R2 in the indium oxide film, a so-called n-i-n junction (a junction between an n-type region, an i-type region, and an n-type region) can be created. Note that valence electron control in transistors using silicon is generally known. On the other hand, valence electron control in transistors using indium oxide is a novel technical concept that would not normally be conceived.

[0211] By using the above technical concept, the transistor having indium oxide in this specification and the like has two or more, preferably three or more, more preferably four or more, and most preferably five of the following characteristics (1) to (5): (1) high on-current (in other words, high mobility); (2) low off-current; (3) normally-off operation; (4) high reliability; and (5) high cutoff frequency (fT). For example, the transistor having indium oxide in this specification and the like has high mobility, low off-current, and is normally-off operation. The transistor has high mobility and is different from a normally-on transistor.

[0212] In addition, a semiconductor being i-type can be rephrased as having the same Fermi level (Ef) and intrinsic Fermi level (Ei) (Ef = Ei). As shown in FIG. 15B, in IGZO, the lower the carrier concentration, the smaller the hole mobility. Therefore, when Ef = Ei is finally achieved, the carriers disappear (in other words, the physical properties become similar to those of an insulator), and the transistor may no longer function. On the other hand, in indium oxide, as shown in FIG. 15A, the lower the carrier concentration, the larger the hole mobility. When Ef = Ei is finally achieved, the hole mobility is maximized. In other words, a transistor containing indium oxide can achieve high field-effect mobility by setting Ef = Ei. Note that a transistor containing indium oxide is likely to be normally-off due to its low carrier concentration. Therefore, a transistor containing indium oxide can be normally-off and achieve high field-effect mobility.

[0213] Note that normally-off refers to a state in which no current flows through a transistor when no potential is applied to the gate or when the gate-source voltage is 0 V. Furthermore, normally-off can be evaluated by the threshold voltage (Vth) or shift value (Vsh) of the transistor. Unless otherwise specified, Vth is calculated by a constant current method. More specifically, Vth refers to a state in which the value of drain current (Id) × channel length (L) ÷ channel width (W) in the Id-Vg characteristics of a transistor is 1 nA (1 × 10 −９ A). Vsh is the gate voltage (Vg) when the drain current (Id) in the Id-Vg characteristic of the transistor is expressed logarithmically and the tangent of the maximum slope is Id = 1 pA (1 × 10 −１２ The gate voltage (Vg) is the intersection point between the line of Id = 1 pA and the line extrapolated from two points where the slope of Id is maximum when Id is expressed logarithmically in the Id-Vg characteristics of the transistor. For example, if either or both of Vth and Vsh are zero or a positive value, the transistor can be considered to be normally-off.

[0214] In addition, in a transistor containing indium oxide, in order to make the semiconductor i-type, that is, to achieve Ef = Ei, the film structure in contact with the indium oxide film is important. For example, in a transistor containing indium oxide, a film structure in which a silicon oxide film in contact with the indium oxide film, a hafnium oxide film, and a silicon nitride film are stacked is exemplified. By using this film structure, a semiconductor device with high reliability and Ef = Ei can be obtained.

[0215] In the above film configuration, a film containing oxygen, such as a silicon oxynitride film, a silicon nitride oxide film, an aluminum oxide film, or a gallium oxide film, can be used instead of the silicon oxide film. Also, in the above film configuration, a silicon nitride oxide film, a silicon oxynitride film, or the like can be used instead of the silicon nitride film. The hafnium oxide film, which is located closer to the indium oxide film than the silicon nitride film, functions as a gettering site for hydrogen.

[0216] The above film configuration can also be considered as a stacked structure of a film (e.g., a silicon oxide film) capable of supplying oxygen to the indium oxide film from the indium oxide film side, a film (e.g., a hafnium oxide film) capable of gettering hydrogen, and a film (e.g., a silicon nitride film) that suppresses the penetration of oxygen and hydrogen. With this configuration, oxygen vacancies in the indium oxide film are filled with oxygen in the silicon oxide film. Hydrogen in the indium oxide film is captured by the hafnium oxide film by heat treatment or the like. Furthermore, the provision of the silicon nitride film results in a film configuration that reduces the penetration of oxygen and hydrogen from the outside. That is, with the above film configuration, the indium oxide film can be made closer to i-type. Therefore, a transistor having the above-described indium oxide film has high field-effect mobility and high reliability.

[0217] Next, an indium oxide film applied to a transistor will be described. The indium oxide film preferably has crystallinity (i.e., has crystal grains). Examples of films having crystal grains include single-crystal films, polycrystalline films, and amorphous films containing crystal grains (also called microcrystalline films). In particular, the indium oxide film is preferably a polycrystalline film, and more preferably a single-crystal film. A single-crystal film does not have grain boundaries. Impurities (typically, insulating impurities, insulating oxides, etc.) that hinder carrier flow tend to segregate at grain boundaries. The use of a single-crystal film can suppress carrier scattering at grain boundaries, thereby realizing a transistor exhibiting high field-effect mobility. Furthermore, the use of a single-crystal film has the excellent effect of suppressing variations in transistor characteristics due to the grain boundaries.

[0218] Furthermore, polycrystalline films are preferable because they can reduce carrier scattering and exhibit high field-effect mobility compared to microcrystalline or amorphous films. When using a polycrystalline film, it is preferable to use a film with as large a crystal grain size as possible and with few crystal grain boundaries. Note that in a transistor using an indium oxide polycrystalline film, if there is no crystal grain boundary in the channel formation region or no crystal grain boundary is observed, the channel formation region is located within a single crystal region included in the polycrystalline film, and therefore the transistor can be considered to be using single-crystal indium oxide.

[0219] The crystallinity of indium oxide can be analyzed by, for example, X-ray diffraction (XRD), transmission electron microscope (TEM), or electron diffraction (ED). Alternatively, a combination of these methods may be used for analysis.

[0220] In this specification and the like, a semiconductor layer in which no crystal grain boundary is observed in the channel formation region, a semiconductor layer in which the channel formation region is included in one crystal grain, or a semiconductor layer in which the crystal axis direction is the same in at least two regions in the channel formation region can be called a single crystal film. Also, a semiconductor layer in which, in the channel formation region, within one crystal grain, the direction of another crystal axis continuously changes around a certain crystal axis or a certain crystal orientation as the axis of rotation can be called a single crystal film.

[0221] The channel formation region refers to a region of the semiconductor layer that overlaps (or faces) the gate electrode via the gate insulating layer, and is located between the region in contact with the source electrode and the region in contact with the drain electrode. The current path in the channel formation region is the shortest distance between the source electrode and the drain electrode. Therefore, the crystal grains, crystal grain boundaries, crystal axes, crystal orientation, etc. in the channel formation region can be confirmed by observing a cross section including the semiconductor layer, the source electrode, and the drain electrode.

[0222] The indium oxide film in the channel formation region preferably has a lower impurity concentration. Impurities in the indium oxide film in the channel formation region can be a scattering source of carriers, which can lead to a decrease in field-effect mobility. These impurities can also hinder the crystal growth of the indium oxide film. Examples of impurities in the indium oxide film include boron and silicon. The indium oxide film preferably contains these impurities at concentrations of 0.1% or less, and more preferably 0.01% (100 ppm) or less. Carbon, hydrogen, and other elements may be contained in the film-forming gas or precursor during film formation, and may remain in the indium oxide film in greater amounts than the above-mentioned impurities.

[0223] The indium oxide film in the channel formation region may contain an element that can become the same trivalent cation as indium, as long as the crystal maintains a cubic crystal structure (bixbyite type). Examples of such an element include Group 13 elements of the periodic table, such as gallium and aluminum, and Group 3 elements of the periodic table. These elements exist mainly as trivalent cations in oxides, and therefore the carrier concentration of indium oxide can be maintained low.

[0224] By using such an indium oxide film in a transistor, the field effect mobility of the transistor can be increased to 50 cm ２ / (V·s) or more, preferably 100 cm ２ / (V·s) or more, more preferably 150 cm ２ / (V·s) or more, more preferably 200 cm ２ / (V·s) or more, more preferably 250 cm ２ / (V·s) or more.

[0225] One of the features of an indium oxide film is that it has higher oxygen permeability (diffusibility) than an IGZO film. As shown in FIG. 15C, an indium oxide film (InO Ｘ Oxygen (O) diffusing into the indium oxide film passes through the indium oxide film and becomes oxygen molecules (O ２ ) and is released as water molecules (H ２O) may be released in the film. Ｏ In the case where an indium oxide film is present, oxygen atoms diffuse to compensate for the oxygen vacancies. Since oxygen diffuses easily in the indium oxide film, it can be said that oxygen vacancies are more easily compensated for in the indium oxide film than in the IGZO film.

[0226] As described above, an indium oxide film can more easily reduce oxygen vacancies in the film than an IGZO film. Therefore, by using such an indium oxide film in a transistor, a transistor exhibiting extremely high reliability can be realized.

[0227] Furthermore, as shown in FIG. 15C, the indium oxide film diffuses hydrogen. Hydrogen that diffuses into the indium oxide film from the outside passes through the indium oxide film and becomes hydrogen molecules (H ２ ) or reacts with oxygen contained in the membrane and is released as water molecules.

[0228] A transistor using an indium oxide film is an accumulation-type transistor that uses electrons as majority carriers. Assuming that the carrier relaxation time is constant, the smaller the effective mass of the electrons (carriers), the higher the electron mobility. In other words, by using indium oxide, which has a small effective mass of electrons, for a transistor, the on-state current or field-effect mobility of the transistor can be increased.

[0229] Table 1 shows the results of single crystal indium oxide (here, In ２ O ３ ) and single-crystal silicon (Si). As shown in Table 1, indium oxide is characterized by a small effective mass of electrons and a large effective mass of holes. Indium oxide also has the characteristic that the effective mass of electrons is almost independent of the crystal orientation. Therefore, by using crystalline indium oxide in a transistor, a transistor with high field-effect mobility and high frequency characteristics (also called f characteristics) can be realized. Furthermore, since the effective mass of holes is large, a transistor with extremely small off-current can be realized. For example, by applying an indium oxide film to a vertical transistor, the off-current per 1 μm of channel width can be reduced to 1 fA (1×10) in an environment of 125° C.−１５ A) or less, or 1aA (1 x 10 −１８ A) or less, and under room temperature (25°C) conditions, −１８ A) or less, or 1zA (1 x 10 −２１ Furthermore, as shown in Table 1, indium oxide has a smaller effective mass of electrons and a larger effective mass of holes than silicon, and therefore may be able to realize a transistor with higher field-effect mobility and lower off-state current than a Si transistor.

[0230]

[0231] It is preferable to provide a seed layer so as to be in contact with at least a portion of the crystalline indium oxide film. The seed layer is preferably made of a material containing crystals with a small difference in lattice constant (also called lattice mismatch) with indium oxide. This can improve the crystallinity of the indium oxide film. Note that a substrate (e.g., a single-crystal substrate) may be used as one of the layers in contact with at least a portion of the crystalline indium oxide film.

[0232] One method for evaluating the degree of lattice mismatch is to use the value of the lattice mismatch shown below. The lattice mismatch Δa [%] of the crystals of the formed film (here, the indium oxide film) with respect to the crystals of the seed layer is expressed as Δa = ((L １ -L ２ ) / L ２ ) × 100, where L １ is the length or lattice constant of the unit lattice vector of the crystal of the formed film, and L ２ is the length of the unit cell vector or the lattice constant of the crystal of the seed layer.

[0233] The smaller the absolute value of the lattice mismatch Δa between the seed layer and the indium oxide film, the more preferable, and it is most preferably 0. For example, Δa can be set to −5% or more and 5% or less, preferably −4% or more and 4% or less, more preferably −3% or more and 3% or less, and even more preferably −2% or more and 2% or less.

[0234] Here, the indium oxide crystal has a cubic crystal structure (bixbyite type). For example, the crystal of yttria-stabilized zirconia (YSZ) can have a cubic crystal structure (fluorite type). The lattice mismatch of the indium oxide crystal with the cubic YSZ crystal is in the range of −2% to 2%, and a single crystal film of indium oxide can be epitaxially grown on the YSZ substrate.

[0235] It should be noted that the crystal structure of the seed layer and the crystal structure of the indium oxide film may not necessarily have the same crystal system or crystal orientation. For example, a film having crystals of a hexagonal or trigonal structure may be used under an indium oxide film having crystals of a cubic structure. For example, by setting the crystal orientation of the surface of the seed layer to

[001] and the crystal orientation of the underside of the indium oxide film to

[111] , the requirements related to the crystal orientation necessary for epitaxial growth can be satisfied. Examples of hexagonal or trigonal crystals include wurtzite structure, YbFe ２ O ４ Type structure, Yb ２ Fe ３ O ７ YbFeFe alloys have the following structures: ２ O ４ Type structure or Yb ２ Fe ３ O ７ An example of a crystal having a crystalline structure is IGZO. It should be noted that a single crystal film of indium oxide can be formed not only on a YSZ substrate but also on an insulating film. On the other hand, it is difficult to form a single crystal film of silicon on an insulating film. Silicon crystals have a diamond structure. As such, indium oxide and silicon have similar properties in terms of single crystal. However, when comparing indium oxide and silicon in terms of whether they can be formed as single crystals on an insulating film, they have different properties.

[0236] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0237] Embodiment 4 In this embodiment, an example of a CMOS circuit configuration using Si transistors and OS transistors will be described.

[0238] Si transistors have higher field-effect mobility and faster operation speed than OS transistors. Furthermore, OS transistors have significantly lower off-state current than Si transistors. In particular, OS transistors that use indium oxide for the semiconductor layer in which a channel is formed have significantly lower off-state current and higher field-effect mobility comparable to that of Si transistors. By using an OS transistor and a Si transistor in combination, a CMOS circuit that consumes less power and operates at high speed can be realized.

[0239] In this embodiment, examples of circuits using Si transistors and OS transistors will be described, including a NOT circuit, a NOR circuit, and a NAND circuit, which are logic circuits. Also, examples of circuits using Si transistors and OS transistors will be described, including a buffer circuit, a ring oscillator, a delay flip-flop (DFF) circuit, a shift register circuit using a DFF circuit, a selector, and an analog switch.

[0240] [NOT Circuit] Fig. 16A is a circuit diagram showing an example of the configuration of a NOT circuit (NOT). A NOT circuit is also called an inversion circuit, an inverter circuit, etc. Fig. 16B shows the circuit symbol of a NOT circuit. Fig. 16C is a timing chart explaining the operation of the NOT circuit.

[0241] The NOT circuit shown in FIG. 16A includes transistors Tr11 and Tr12. The transistor Tr11 is a Si transistor functioning as a p-type transistor, and the transistor Tr12 is an OS transistor functioning as an n-type transistor. A potential H (e.g., a high power supply potential VDD) is supplied to one of the source and the drain of the transistor Tr11. The other of the source and the drain of the transistor Tr11 is connected to one of the source and the drain of the transistor Tr12 and to a terminal Y. A potential L (e.g., a low power supply potential VSS) is supplied to the other of the source and the drain of the transistor Tr12. The gates of the transistors Tr11 and Tr12 are connected to a terminal A.

[0242] 16A, the terminal A functions as an input terminal, and the terminal Y functions as an output terminal. When a potential H is input to the terminal A of the NOT circuit, the terminal Y outputs a potential L, and when a potential L is input to the terminal A, the terminal Y outputs a potential H (see FIG. 16C).

[0243] As shown in FIG. 16C , the NOT circuit has a function of correcting an input signal distorted by wiring resistance, parasitic capacitance, noise, etc., to a signal that is distorted or has reduced distortion, and outputting the corrected signal (also referred to as a "waveform shaping function"). The NOT circuit also has a function of amplifying the voltage amplitude of the input signal and outputting the signal. The output of the NOT circuit is supplied to a load such as a capacitance element Cx and a transistor Trx. Since power is supplied to the output of the NOT circuit via transistor Tr11 or transistor Tr12, the ability to drive a load connected to the output can be improved. The NOT circuit has a function of improving the ability to drive a load (also referred to as a "driving force improvement function").

[0244] [NOR Circuit] Fig. 17A is a circuit diagram showing an example of the configuration of a two-input, one-output NOR circuit (NOR). Fig. 17B shows a circuit symbol for the NOR circuit. The NOR circuit shown in Fig. 17A includes transistors Tr21, Tr22, Tr23, and Tr24. Si transistors functioning as p-channel transistors are used as the transistors Tr21 and Tr22, and OS transistors functioning as n-channel transistors are used as the transistors Tr23 and Tr24.

[0245] 17A , a potential H is supplied to one of the source or drain of transistor Tr21. The other of the source or drain of transistor Tr21 is connected to one of the source or drain of transistor Tr22. The other of the source or drain of transistor Tr22 is connected to one of the source or drain of transistor Tr23, one of the source or drain of transistor Tr24, and terminal Y. A potential L is supplied to the other of the source or drain of transistor Tr23 and the other of the source or drain of transistor Tr24.

[0246] The gate of the transistor Tr21 is connected to the gate of the transistor Tr23 and the terminal A. The gate of the transistor Tr22 is connected to the gate of the transistor Tr24 and the terminal B.

[0247] 17A and 17B has a function of outputting a potential H from a terminal Y when a potential L is input to both a terminal A and a terminal B. In addition, the NOR circuit has a function of outputting a potential L from a terminal Y when a potential H is input to one or both of the terminals A and B.

[0248] Furthermore, as shown in FIG. 17C, an OR circuit can be realized by connecting the input of a NOT circuit to the output of a NOR circuit.

[0249] [NAND Circuit] Fig. 17D is a circuit diagram showing a configuration example of a two-input, one-output NAND circuit (NAND). Fig. 17E shows a circuit symbol of the NAND circuit. The NAND circuit shown in Fig. 17D includes transistors Tr31, Tr32, Tr33, and Tr34. Si transistors functioning as p-channel transistors are used as the transistors Tr31 and Tr32, and OS transistors functioning as n-channel transistors are used as the transistors Tr33 and Tr34.

[0250] 17D, a potential H is supplied to one of the source or drain of transistor Tr31 and one of the source or drain of transistor Tr32. The other of the source or drain of transistor Tr31 and the other of the source or drain of transistor Tr32 are connected to one of the source or drain of transistor Tr33 and terminal Y. The other of the source or drain of transistor Tr33 is connected to one of the source or drain of transistor Tr34. A potential L is supplied to the other of the source or drain of transistor Tr34.

[0251] The gate of the transistor Tr31 is connected to the gate of the transistor Tr34 and the terminal B. The gate of the transistor Tr32 is connected to the gate of the transistor Tr33 and the terminal A.

[0252] 17D and 17E has a function of outputting a potential L from a terminal Y when a potential H is input to both the terminal A and the terminal B. In addition, the NAND circuit has a function of outputting a potential H from a terminal Y when a potential L is input to one or both of the terminal A and the terminal B.

[0253] Furthermore, as shown in FIG. 17F, an AND circuit can be realized by combining a NAND circuit with a NOT circuit.

[0254] [Buffer Circuit] Figure 18A shows the circuit symbol for a buffer circuit. A buffer circuit (BF) can be realized by connecting an even number of NOT circuits in series. Figure 18B shows an example configuration of a buffer circuit composed of two NOT circuits. Figure 18C is a timing chart explaining the operation of the buffer circuit.

[0255] The buffer circuit does not perform a logical operation, but outputs the same value as the input logical value. Specifically, when a potential H is input, a potential H is output, and when a potential L is input, a potential L is output. In addition, like a NOT circuit, the buffer circuit has a waveform shaping function (see FIG. 18C ) and a driving force improving function. By using a buffer circuit, it is possible to correct a distorted signal and improve the driving force for a load without inverting the signal.

[0256] [Ring Oscillator] A ring oscillator (also called an "oscillating circuit") can be realized by connecting an odd number of NOT circuits in a ring. FIG. 18D shows an example of the configuration of a ring oscillator (RO) made up of NOT circuits. FIG. 18D shows a ring oscillator made up of five NOT circuits. A ring oscillator has the function of generating (oscillating) an AC signal when power is supplied. FIG. 18E is a diagram illustrating the oscillation of a ring oscillator.

[0257] Generally, the first of n NOT circuits (n is an odd number equal to or greater than 3) that make up a ring oscillator is sometimes called the "first stage." The nth circuit is sometimes called the "nth stage." A ring oscillator made up of NOT circuits has a configuration in which the output of each NOT circuit is connected to the input of the NOT circuit in the next stage. The output of the nth NOT circuit is connected to the input of the first NOT circuit.

[0258] Furthermore, in a NOT circuit, a certain delay time occurs before the inverted signal of the input signal is output. Since n is an odd number, the signal output from the first stage is delayed by n stages before being input to the first stage. This causes the ring oscillator to oscillate. That is, an AC signal is supplied to terminal Y shown in FIG. 18C. By using a ring oscillator, for example, a clock signal can be generated within the circuit. Furthermore, the delay time of the NOT circuit can be determined by measuring the oscillation frequency of the ring oscillator.

[0259] [DFF Circuit] Fig. 19A is a circuit diagram showing an example of the configuration of a D flip-flop circuit (DFF). Fig. 19B shows the circuit symbol of the D flip-flop circuit. The DFF has a clock signal input terminal CK, an input terminal D, and an output terminal Q.

[0260] 19A includes transistors Tr41 to Tr49, transistors Tr51 to Tr59, transistor Tr61, transistor Tr62, transistor Tr71, and transistor Tr72. Si transistors functioning as p-channel transistors are used as the transistors Tr41 to Tr49, transistors Tr61, and transistor Tr62, and OS transistors functioning as n-channel transistors are used as the transistors Tr51 to Tr59, transistors Tr71, and transistor Tr72.

[0261] A potential H is supplied to one of the source or drain of transistor Tr41, one of the source or drain of transistor Tr42, one of the source or drain of transistor Tr44, one of the source or drain of transistor Tr46, one of the source or drain of transistor Tr48, one of the source or drain of transistor Tr61, and one of the source or drain of transistor Tr62.

[0262] The other of the source or drain of transistor Tr41 is connected to one of the source or drain of transistor Tr51, the gate of transistor Tr44, the gate of transistor Tr46, the gate of transistor Tr53, and the gate of transistor Tr59. The gate of transistor Tr41 is connected to clock signal input terminal CK, the gate of transistor Tr51, the gate of transistor Tr42, the gate of transistor Tr48, the gate of transistor Tr55, and the gate of transistor Tr57.

[0263] The other of the source or drain of transistor Tr42 is connected to one of the source or drain of transistor Tr43. The other of the source or drain of transistor Tr44 is connected to one of the source or drain of transistor Tr45. The other of the source or drain of transistor Tr43 is connected to the other of the source or drain of transistor Tr45, one of the source or drain of transistor Tr52, one of the source or drain of transistor Tr54, the gate of transistor Tr61, and the gate of transistor Tr71. The gate of transistor Tr43 is connected to the gate of transistor Tr52 and input terminal D.

[0264] The other of the source or drain of transistor Tr52 is connected to one of the source or drain of transistor Tr53. The other of the source or drain of transistor Tr54 is connected to one of the source or drain of transistor Tr55. The gate of transistor Tr45 is connected to the gate of transistor Tr54, the other of the source or drain of transistor Tr61, one of the source or drain of transistor Tr71, the gate of transistor Tr47, and the gate of transistor Tr56. The other of the source or drain of transistor Tr46 is connected to one of the source or drain of transistor Tr47. The other of the source or drain of transistor Tr48 is connected to one of the source or drain of transistor Tr49.

[0265] The other of the source or drain of transistor Tr47 is connected to one of the source or drain of transistor Tr56, the other of the source or drain of transistor Tr49, one of the source or drain of transistor Tr58, the gate of transistor Tr62, and the gate of transistor Tr72. The other of the source or drain of transistor Tr62 is connected to one of the source or drain of transistor Tr72, the gate of transistor Tr49, the gate of transistor Tr58, and output terminal Q.

[0266] The other of the source or the drain of transistor Tr56 is connected to one of the source or the drain of transistor Tr57. The other of the source or the drain of transistor Tr58 is connected to one of the source or the drain of transistor Tr59. A potential L is supplied to the other of the source or the drain of transistor Tr51, the other of the source or the drain of transistor Tr53, the other of the source or the drain of transistor Tr55, the other of the source or the drain of transistor Tr71, the other of the source or the drain of transistor Tr57, the other of the source or the drain of transistor Tr59, and the other of the source or the drain of transistor Tr72.

[0267] 19A and 19B has a function in which information (potential) supplied to input terminal D is written to DFF at the timing when the signal input to clock signal input terminal CK changes from potential L to potential H, and the information is held until the next timing when the signal input to clock signal input terminal CK changes from potential L to potential H. In addition, a signal (potential H or potential L) based on the information held by DFF is always output from output terminal Q.

[0268] FIG. 20A is a block diagram showing an example configuration of a shift register circuit (SR). The SR includes multiple DFFs. In this specification and elsewhere, the first-stage (first) DFF is referred to as "DFF[1]," and the potential (data) output from the output terminal Q of DFF[1] is referred to as "DATA OUT[1]." FIG. 20A shows a block diagram of an SR including four stages (four) of DFFs (DFF[1] to DFF[4]). In FIG. 20A, the data output from the output terminals Q of DFF[1] to DFF[4] are referred to as DATA OUT[1] to DATA OUT[4].

[0269] 20B is a timing chart illustrating the operation of the SR. A clock signal CLK is input to the clock signal input terminal CK of the odd-numbered DFF. An inverted version of the signal CLK is input to the clock signal input terminal CK of the even-numbered DFF.

[0270] A pulse signal SPL is input to the input terminal D of DFF[1]. DFF[1] holds a signal corresponding to the input signal SPL in synchronization with the signal CLK and outputs it as data OUT[1]. Note that data OUT[1] has a value corresponding to the data held by DFF[1].

[0271] Furthermore, data OUT[1] is input to input terminal D of DFF[2]. DFF[2] holds a signal corresponding to the input data OUT[1] in synchronization with signal CLK and outputs it as data OUT[2]. Similarly, data OUT[2] is input to input terminal D of DFF[3], and data OUT[3] is input to input terminal D of DFF[4].

[0272] In this way, the SR has the function of sequentially transferring the input signal SPL to the subsequent DFF in synchronization with the signal CLK, and also has the function of sequentially switching the potential of the data OUT output from the multiple DFFs in synchronization with the signal CLK.

[0273] Furthermore, it is preferable to provide an overlapping structure between a Si transistor and an OS transistor. By providing an overlapping structure between a Si transistor and an OS transistor, a circuit with a small occupancy area can be realized. Furthermore, an OS transistor operates stably even in a high-temperature environment and exhibits little fluctuation in characteristics. Therefore, the OS transistor is less susceptible to the heat generated by the Si transistor and can operate stably. Furthermore, by providing an overlapping structure between a Si transistor and an OS transistor, the connection distance between them can be made extremely short. As a result, wiring resistance and parasitic capacitance are reduced, enabling the circuit to operate at high speed. Furthermore, the power consumption of the circuit is reduced.

[0274] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0275] Embodiment 5 In this embodiment, a semiconductor device 900 according to one embodiment of the present invention will be described. The semiconductor device 900 can function as a memory device.

[0276] Fig. 21 is a block diagram showing a configuration example of a semiconductor device 900. The semiconductor device 900 shown in Fig. 21 has a driver circuit 910 and a memory array 920. The memory array 920 has one or more memory cells 950. Fig. 21 shows an example in which the memory array 920 has a plurality of memory cells 950 arranged in a matrix.

[0277] The transistor described as an example in Embodiment 1 can be applied to the memory cell 950. By using the transistor, the operation speed of the memory device can be improved. Furthermore, miniaturization and high integration of the memory device can be achieved. Furthermore, the capacitance per area of ​​the memory device can be increased.

[0278] The drive circuit 910 includes a PSW 931 (power switch), a PSW 932, and a peripheral circuit 915. The peripheral circuit 915 includes a peripheral circuit 911, a control circuit 912, and a voltage generation circuit 928.

[0279] The transistors described as examples in Embodiment 1 can also be applied to the circuits included in the driver circuit 910. This enables reduction in the circuit area and power consumption.

[0280] In the semiconductor device 900, each circuit, signal, and voltage can be appropriately selected or omitted as needed. Alternatively, other circuits or signals may be added. The signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1, and PON2 are input signals from the outside, and the signal RDA is an output signal to the outside. The signal CLK is a clock signal.

[0281] Furthermore, signals BW, CE, and GW are control signals. Signal CE is a chip enable signal, signal GW is a global write enable signal, and signal BW is a byte write enable signal. Signal ADDR is an address signal. Signal WDA is a write data signal, and signal RDA is a read data signal. Signals PON1 and PON2 are power gating control signals. Note that signals PON1 and PON2 may be generated by the control circuit 912.

[0282] The control circuit 912 is a logic circuit having a function of controlling the overall operation of the semiconductor device 900. For example, the control circuit 912 performs a logical operation on the signals CE, GW, and BW to determine the operation mode (e.g., write operation, read operation) of the semiconductor device 900. Alternatively, the control circuit 912 generates a control signal for the peripheral circuit 911 so that this operation mode is executed.

[0283] The voltage generating circuit 928 has a function of generating a voltage. The signal WAKE has a function of controlling the input of the signal CLK to the voltage generating circuit 928. For example, when an H-level signal is given as the signal WAKE, the signal CLK is input to the voltage generating circuit 928, and the voltage generating circuit 928 generates a voltage.

[0284] The peripheral circuit 911 is a circuit for writing and reading data to and from the memory cells 950. The peripheral circuit 911 includes a row decoder 941, a column decoder 942, a row driver 923, a column driver 924, an input circuit 925, an output circuit 926, and a sense amplifier 927.

[0285] The row decoder 941 and the column decoder 942 have the function of decoding the signal ADDR. The row decoder 941 is a circuit for specifying a row to be accessed, and the column decoder 942 is a circuit for specifying a column to be accessed. The row driver 923 has the function of selecting the row specified by the row decoder 941. The column driver 924 has the function of writing data to the memory cells 950, reading data from the memory cells 950, and retaining the read data.

[0286] The input circuit 925 has a function of holding a signal WDA. The data held by the input circuit 925 is output to the column driver 924. The output data of the input circuit 925 is data (Din) to be written to the memory cell 950. The data (Dout) read from the memory cell 950 by the column driver 924 is output to the output circuit 926. The output circuit 926 has a function of holding Dout. In addition, the output circuit 926 has a function of outputting Dout to the outside of the semiconductor device 900. The data output from the output circuit 926 is a signal RDA.

[0287] The PSW 931 is a V ＤＤ The PSW 932 has the function of controlling the supply of V to the row driver 923. ＨＭHere, the high power supply potential of the semiconductor device 900 is V ＤＤ and the low power supply potential is GND (ground potential). ＨＭ is the high power supply potential used to drive the word line high, and V ＤＤ The signal PON1 controls the on / off of the PSW 931, and the signal PON2 controls the on / off of the PSW 932. In FIG. 21, in the peripheral circuit 915, V ＤＤ Although the number of power domains to which power is supplied is set to one, it is also possible to set it to a plurality of power domains. In this case, a power switch may be provided for each power domain.

[0288] 22A to 22H, other examples of memory cell configurations that can be applied to the memory cell 950 will be described.

[0289] 22A shows an example of a circuit configuration of a DRAM memory cell. In this specification and the like, a DRAM using an OS transistor is referred to as a DOSRAM (Dynamic Oxide Semiconductor Random Access Memory). The memory cell 951 includes a transistor M1 and a capacitor CA.

[0290] The transistor M1 may have a front gate (sometimes simply referred to as a gate) and a back gate. In this case, the back gate may be connected to a wiring that supplies a constant potential or a signal, or the front gate and the back gate may be connected to each other.

[0291] A first terminal of the transistor M1 is connected to a first terminal of the capacitance element CA, a second terminal of the transistor M1 is connected to the wiring BIL, and a gate of the transistor M1 is connected to the wiring WOL. The second terminal of the capacitance element CA is connected to the wiring CAL.

[0292] The wiring BIL functions as a bit line, and the wiring WOL functions as a word line. The wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitance element CA. When writing and reading data, it is preferable to apply a low-level potential (sometimes referred to as a reference potential) to the wiring CAL.

[0293] Data is written and read by applying a high-level potential to the wiring WOL, turning on the transistor M1, and connecting the wiring BIL and the first terminal of the capacitor CA.

[0294] Furthermore, the memory cell that can be used for the memory cell 950 is not limited to the memory cell 951, and the circuit configuration can be changed. For example, the memory cell 952 shown in FIG. 22B may have a configuration. The memory cell 952 is an example in which the memory cell 952 does not include a capacitor CA and a wiring CAL. The first terminal of the transistor M1 is in an electrically floating state.

[0295] In the memory cell 952, the potential written through the transistor M1 is held in a capacitance (also referred to as a parasitic capacitance) between the first terminal and the gate, which is indicated by a dashed line. With this configuration, the configuration of the memory cell can be significantly simplified.

[0296] Note that the OS transistor described in Embodiment 1 is preferably used as the transistor M1. By using the OS transistor described in Embodiment 1, the operation speed of the memory device can be improved. Furthermore, the area occupied by the memory cell can be reduced. Furthermore, the OS transistor has a characteristic of extremely low off-state current. By using an OS transistor as the transistor M1, the leakage current of the transistor M1 can be significantly reduced. That is, written data can be held by the transistor M1 for a long time, which reduces the frequency of refreshing the memory cell. Alternatively, the refresh operation of the memory cell can be eliminated. Furthermore, since the leakage current is extremely low, multilevel data or analog data can be held in the memory cell 951 and the memory cell 952.

[0297] 22C shows an example circuit configuration of a gain cell type memory cell having two transistors and one capacitor. The memory cell 953 includes a transistor M2, a transistor M3, and a capacitor CB. In this specification and the like, a storage device having a gain cell type memory cell in which the transistor M2 is an OS transistor is referred to as a nonvolatile oxide semiconductor RAM (NOSRAM).

[0298] The first terminal of transistor M2 is connected to the first terminal of capacitance element CB, the second terminal of transistor M2 is connected to wiring WBL, and the gate of transistor M2 is connected to wiring WOL. The second terminal of capacitance element CB is connected to wiring CAL. The first terminal of transistor M3 is connected to wiring RBL, the second terminal of transistor M3 is connected to wiring RL, and the gate of transistor M3 is connected to the first terminal of capacitance element CB.

[0299] The wiring WBL functions as a write bit line, the wiring RBL functions as a read bit line, and the wiring WOL functions as a word line. The wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitance element CB. When writing data, while retaining data, and when reading data, it is preferable to apply a low-level potential (sometimes referred to as a reference potential) to the wiring CAL.

[0300] Data is written by applying a high-level potential to the wiring WOL, turning on the transistor M2, and connecting the wiring WBL to the first terminal of the capacitance element CB. Specifically, when the transistor M2 is on, a potential corresponding to the information to be recorded is applied to the wiring WBL, and the potential is written to the first terminal of the capacitance element CB and the gate of the transistor M3. Then, a low-level potential is applied to the wiring WOL, turning off the transistor M2, thereby maintaining the potential of the first terminal of the capacitance element CB and the potential of the gate of the transistor M3.

[0301] Data is read by applying a predetermined potential to the wiring RL. The current flowing between the source and drain of the transistor M3 and the potential of the first terminal of the transistor M3 are determined by the potential of the gate of the transistor M3 and the potential of the second terminal of the transistor M3. Therefore, by reading the potential of the wiring RBL connected to the first terminal of the transistor M3, the potential held in the first terminal of the capacitance element CB (or the gate of the transistor M3) can be read. In other words, information written in this memory cell can be read from the potential held in the first terminal of the capacitance element CB (or the gate of the transistor M3).

[0302] Alternatively, for example, the wiring WBL and the wiring RBL may be combined into a single wiring BIL. An example circuit configuration of such a memory cell is shown in FIG. 22D. The memory cell 954 is configured such that the wiring WBL and the wiring RBL of the memory cell 953 are combined into a single wiring BIL, and the second terminal of the transistor M2 and the first terminal of the transistor M3 are connected to the wiring BIL. In other words, the memory cell 954 is configured to operate as a write bit line and a read bit line using a single wiring BIL.

[0303] 22E is an example in which the capacitor element CB and the wiring CAL in the memory cell 953 are omitted. Also, the memory cell 956 in Fig. 22F is an example in which the capacitor element CB and the wiring CAL in the memory cell 954 are omitted. With such a configuration, the integration degree of the memory cells can be increased.

[0304] Note that at least the transistor M2 is preferably the OS transistor described in Embodiment 1. For example, the transistor described in Embodiment 1 is preferably used as one or both of the transistors M2 and M3 in the memory cells 953 and 954. By using the OS transistor described in Embodiment 1, the operation speed of the memory device can be improved. In addition, the area occupied by the memory cell can be reduced.

[0305] Since the OS transistor has an extremely low off-state current, written data can be held by the transistor M2 for a long time, which reduces the frequency of refreshing the memory cell. Alternatively, the refresh operation of the memory cell can be eliminated. Furthermore, since the leakage current is extremely low, multilevel data or analog data can be held in the memory cell 953, the memory cell 954, the memory cell 955, and the memory cell 956.

[0306] The memory cell 953, the memory cell 954, the memory cell 955, and the memory cell 956, in which an OS transistor is used as the transistor M2, are one embodiment of an NOSRAM.

[0307] It should be noted that a Si transistor may be used as the transistor M3. The Si transistor can increase the field effect mobility and can also be used as a p-type transistor, thereby increasing the degree of freedom in circuit design.

[0308] When an OS transistor is used as the transistor M3, the memory cell can be configured as a unipolar circuit.

[0309] 22G shows a three-transistor, one-capacitor gain cell type memory cell 957. The memory cell 957 has transistors M4 to M6 and a capacitor CC.

[0310] The first terminal of transistor M4 is connected to the first terminal of capacitor CC, the second terminal of transistor M4 is connected to wiring BIL, and the gate of transistor M4 is connected to wiring WOL. The second terminal of capacitor CC is connected to the first terminal of transistor M5 and wiring GNDL. The second terminal of transistor M5 is connected to the first terminal of transistor M6, and the gate of transistor M5 is connected to the first terminal of capacitor CC. The second terminal of transistor M6 is connected to wiring BIL, and the gate of transistor M6 is connected to wiring RWL.

[0311] The wiring BIL functions as a bit line, the wiring WOL functions as a write word line, and the wiring RWL functions as a read word line. The wiring GNDL is a wiring that applies a low-level potential.

[0312] Data is written by applying a high-level potential to the wiring WOL, turning on the transistor M4, and connecting the wiring BIL to the first terminal of the capacitor CC. Specifically, when the transistor M4 is turned on, a potential corresponding to the information to be recorded is applied to the wiring BIL, and the potential is written to the first terminal of the capacitor CC and the gate of the transistor M5. Then, a low-level potential is applied to the wiring WOL, turning off the transistor M4, thereby maintaining the potential of the first terminal of the capacitor CC and the potential of the gate of the transistor M5.

[0313] Data is read by precharging the wiring BIL to a predetermined potential, then electrically floating the wiring BIL, and applying a high-level potential to the wiring RWL. Because the wiring RWL is at a high-level potential, the transistor M6 is turned on, and the wiring BIL is connected to the second terminal of the transistor M5. At this time, the potential of the wiring BIL is applied to the second terminal of the transistor M5. The potential of the second terminal of the transistor M5 and the potential of the wiring BIL change depending on the potential held in the first terminal of the capacitor CC (or the gate of the transistor M5). By reading the potential of the wiring BIL, the potential held in the first terminal of the capacitor CC (or the gate of the transistor M5) can be read. In other words, information written in this memory cell can be read from the potential held in the first terminal of the capacitor CC (or the gate of the transistor M5).

[0314] Note that at least the transistor M4 is preferably the OS transistor described in Embodiment 1. By using the OS transistor described in Embodiment 1, the area occupied by the memory cell can be reduced.

[0315] Note that Si transistors may be used as the transistors M5 and M6. As described above, Si transistors may have higher field-effect mobility than OS transistors depending on the crystalline state of silicon used in the semiconductor layer.

[0316] When OS transistors are used as the transistors M5 and M6, the memory cell can be configured as a unipolar circuit.

[0317] 22H shows an example of a static random access memory (SRAM) using an OS transistor. In this specification and the like, an SRAM using an OS transistor is referred to as an oxide semiconductor SRAM (OS-SRAM). Note that a memory cell 958 shown in FIG. 22H is a memory cell of an SRAM capable of backing up data.

[0318] The memory cell 958 includes transistors M7 to M10, transistors MS1 to MS4, and capacitors CD1 and CD2. Note that the transistors MS1 and MS2 are p-type transistors, and the transistors MS3 and MS4 are n-type transistors.

[0319] A first terminal of transistor M7 is connected to wiring BIL, and a second terminal of transistor M7 is connected to a first terminal of transistor MS1, a first terminal of transistor MS3, the gate of transistor MS2, the gate of transistor MS4, and a first terminal of transistor M10. The gate of transistor M7 is connected to wiring WOL. A first terminal of transistor M8 is connected to wiring BILB, and a second terminal of transistor M8 is connected to a first terminal of transistor MS2, the first terminal of transistor MS4, the gate of transistor MS1, the gate of transistor MS3, and a first terminal of transistor M9. The gate of transistor M8 is connected to wiring WOL.

[0320] A second terminal of the transistor MS1 is connected to the wiring VDL. A second terminal of the transistor MS2 is connected to the wiring VDL. A second terminal of the transistor MS3 is connected to the wiring GNDL. A second terminal of the transistor MS4 is connected to the wiring GNDL.

[0321] A second terminal of the transistor M9 is connected to a first terminal of the capacitor CD1, and a gate of the transistor M9 is connected to the wiring BRL. A second terminal of the transistor M10 is connected to a first terminal of the capacitor CD2, and a gate of the transistor M10 is connected to the wiring BRL.

[0322] A second terminal of the capacitance element CD1 is connected to the wiring GNDL, and a second terminal of the capacitance element CD2 is connected to the wiring GNDL.

[0323] The wirings BIL and BILB function as bit lines, the wiring WOL functions as a word line, and the wiring BRL is a wiring that controls the conductive state and non-conductive state of the transistors M9 and M10.

[0324] The wiring VDL is a wiring that applies a high-level potential, and the wiring GNDL is a wiring that applies a low-level potential.

[0325] Data is written by applying a high-level potential to the wiring WOL and a high-level potential to the wiring BRL. Specifically, when the transistor M10 is in a conductive state, a potential corresponding to information to be recorded is applied to the wiring BIL, and the potential is written to the second terminal of the transistor M10.

[0326] Since the memory cell 958 includes an inverter loop formed by the transistors MS1 to MS4, an inverted signal of the data signal corresponding to the potential is input to the second terminal of the transistor M8. Because the transistor M8 is conductive, the potential applied to the wiring BIL, i.e., the inverted signal of the signal input to the wiring BIL, is output to the wiring BILB. Furthermore, because the transistors M9 and M10 are conductive, the potentials of the second terminals of the transistors M7 and M8 are held in the first terminals of the capacitors CD2 and CD1, respectively. Subsequently, a low-level potential is applied to the wiring WOL and a low-level potential is applied to the wiring BRL to turn off the transistors M7 to M10, thereby holding the potentials of the first terminals of the capacitors CD1 and CD2.

[0327] The following describes how data is read. First, the wirings BIL and BILB are precharged to a predetermined potential. Next, a high-level potential is applied to the wiring WOL, and a high-level potential is applied to the wiring BRL. At this time, the potential of the first terminal of the capacitor CD1 is refreshed by the inverter loop of the memory cell 958 and output to the wiring BILB. The potential of the first terminal of the capacitor CD2 is refreshed by the inverter loop of the memory cell 958 and output to the wiring BIL. Since the potentials of the wirings BIL and BILB change from the precharged potentials to the potentials of the first terminals of the capacitor CD2 and the first terminals of the capacitor CD1, respectively, the potential held in the memory cell can be read from the potential of the wiring BIL or the wiring BILB.

[0328] Note that the OS transistors described in Embodiment 1 are preferably used as the transistors M7 to M10. This allows written data to be held by the transistors M7 to M10 for a long time, thereby reducing the frequency of refreshing the memory cells. Alternatively, the refresh operation of the memory cells can be eliminated. Furthermore, the operating speed of the memory device can be improved. Furthermore, the area occupied by the memory cells can be reduced.

[0329] Note that Si transistors may be used as the transistors MS1 to MS4.

[0330] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0331] Embodiment 6 In this embodiment, application examples of a semiconductor device of one embodiment of the present invention will be described with reference to FIGS. 23A to 24E.

[0332] The semiconductor device of one embodiment of the present invention can be used in, for example, electronic components, mainframes, space equipment, data centers (also referred to as DCs), and various electronic devices. By using the semiconductor device of one embodiment of the present invention, low power consumption and high performance can be achieved for the electronic components, mainframes, space equipment, data centers, and various electronic devices.

[0333] Examples of electronic devices include electronic devices with relatively large screens such as television sets, desktop or notebook computers, computer monitors, digital signage, large game machines such as pachinko machines, as well as digital cameras, digital video cameras, digital photo frames, mobile phones, portable game machines, personal digital assistants, and sound reproduction devices.

[0334] The electronic device of this embodiment may have a sensor (including the function of detecting, detecting, or measuring force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared rays).

[0335] The electronic device of the present embodiment can have various functions, such as a function to display various information (still images, videos, text images, etc.) on a display unit, a touch panel function, a function to display a calendar, date, time, etc., a function to execute various software (programs), a wireless communication function, and a function to read out programs or data recorded on a recording medium.

[0336] [Electronic Component] FIG. 23A shows a perspective view of a substrate (mounting substrate 989) on which an electronic component 980 is mounted. The electronic component 980 shown in FIG. 23A has a semiconductor device 981 inside a mold 984. FIG. 23A omits some parts in order to show the interior of the electronic component 980. The electronic component 980 has lands 985 on the outside of the mold 984. The lands 985 are connected to electrode pads 986, and the electrode pads 986 are connected to the semiconductor device 981 via wires 987. The electronic component 980 is mounted on, for example, a printed circuit board 988. A plurality of such electronic components are combined and connected on the printed circuit board 988 to complete the mounting substrate 989.

[0337] The semiconductor device 981 also includes a drive circuit layer 982 and a memory layer 983. The memory layer 983 has a configuration in which multiple memory cell arrays are stacked. The stacked configuration of the drive circuit layer 982 and the memory layer 983 can be a monolithic stacked configuration. In a monolithic stacked configuration, the layers can be connected without using through-electrode technology such as TSV (Through Silicon Via) or bonding technology such as Cu-Cu direct bonding. By monolithically stacking the drive circuit layer 982 and the memory layer 983, for example, a so-called on-chip memory configuration can be achieved in which the memory is formed directly on the processor. The on-chip memory configuration enables the operation of the interface between the processor and the memory to be faster.

[0338] Furthermore, by configuring an on-chip memory, the size of the connection wiring can be reduced compared to technologies that use through electrodes such as TSVs, and the number of connection pins can be increased. Increasing the number of connection pins enables parallel operation, which makes it possible to improve the memory bandwidth (also called memory bandwidth).

[0339] Furthermore, it is preferable that the memory cell arrays included in the memory layer 983 are formed using OS transistors and the memory cell arrays are monolithically stacked. By forming the memory cell arrays in a monolithic stacked configuration, it is possible to improve one or both of the memory bandwidth and the memory access latency. Note that the bandwidth is the amount of data transferred per unit time, and the access latency is the time from access to the start of data exchange. Note that when Si transistors are used for the memory layer 983, it is more difficult to form a monolithic stacked configuration than when OS transistors are used. Therefore, it can be said that OS transistors have a superior structure to Si transistors in a monolithic stacked configuration.

[0340] Alternatively, an OS transistor can be used for the driver circuit layer 982. The OS transistor described in the above embodiment can pass a large current, which enables the semiconductor device 994 to operate at high speed.

[0341] The semiconductor device 981 may also be referred to as a die. In this specification, a die refers to a chip piece obtained during the semiconductor chip manufacturing process by forming a circuit pattern on, for example, a disk-shaped substrate (also called a wafer) and dicing it into cubes. Semiconductor materials that can be used for the die include, for example, silicon (Si), silicon carbide (SiC), and gallium nitride (GaN). For example, a die obtained from a silicon substrate (also called a silicon wafer) may be called a silicon die.

[0342] Although the above example shows the semiconductor device 981 functioning as a memory device, the present invention is not limited to this. For example, the semiconductor device 981 can also function as a processor such as a CPU, a GPU, or a field programmable gate array (FPGA). In this case, an OS transistor is preferably used for the semiconductor device 981. The OS transistor described in the above embodiment can pass a large current. This enables the semiconductor device 981 to operate at high speed.

[0343] 23B shows a perspective view of an electronic component 990. The electronic component 990 is an example of a SiP (System in Package) or an MCM (Multi-Chip Module). The electronic component 990 has an interposer 991 provided on a package substrate 992 (printed circuit board), and a semiconductor device 994 and a plurality of semiconductor devices 981 provided on the interposer 991.

[0344] The electronic component 990 shows an example in which the semiconductor device 981 is used as a high bandwidth memory (HBM). The semiconductor device 994 can be used in an integrated circuit such as a CPU, a GPU, or an FPGA.

[0345] In addition, an OS transistor is preferably used for the semiconductor device 994. The OS transistor described in the above embodiment can pass a large current, which enables the semiconductor device 994 to operate at high speed.

[0346] For example, a ceramic substrate, a plastic substrate, or a glass epoxy substrate can be used as the package substrate 992. For example, a silicon interposer or a resin interposer can be used as the interposer 991.

[0347] The interposer 991 has multiple wirings and functions to connect multiple integrated circuits with different terminal pitches. The multiple wirings are provided in a single layer or multiple layers. The interposer 991 also functions to connect the integrated circuits provided on the interposer 991 to electrodes provided on the package substrate 992. For these reasons, the interposer is sometimes called a "rewiring substrate" or "intermediate substrate." In some cases, through electrodes are provided in the interposer 991, and the integrated circuits and the package substrate 992 are connected using the through electrodes. In addition, in a silicon interposer, TSVs can also be used as through electrodes.

[0348] In an HBM, many wirings must be connected to achieve a wide memory bandwidth. Therefore, the interposer on which the HBM is mounted must have fine and high-density wiring. Therefore, it is preferable to use a silicon interposer for the interposer on which the HBM is mounted.

[0349] Furthermore, in SiPs, MCMs, and the like that use silicon interposers, a decrease in reliability due to differences in the coefficient of expansion between the integrated circuit and the interposer is unlikely to occur. Furthermore, because the silicon interposer has a highly flat surface, poor connection between the integrated circuit mounted on the silicon interposer and the silicon interposer is unlikely to occur. In particular, it is preferable to use silicon interposers in 2.5D packages (2.5-dimensional packaging) in which multiple integrated circuits are arranged horizontally on an interposer.

[0350] On the other hand, when connecting multiple integrated circuits with different terminal pitches using a silicon interposer, a TSV, or the like, a space is required, such as the width of the terminal pitch. Therefore, when attempting to reduce the size of the electronic component 990, the width of the terminal pitch becomes an issue, and it may be difficult to provide the many wirings necessary to achieve a wide memory bandwidth. Therefore, as described above, a monolithic stacked structure using OS transistors is preferable. A composite structure may be formed by combining a memory cell array stacked using TSVs and a monolithic stacked memory cell array.

[0351] A heat sink (heat dissipation plate) may be provided over the electronic component 990. When a heat sink is provided, it is preferable to align the height of an integrated circuit provided on the interposer 991. For example, in the electronic component 990 shown in this embodiment, it is preferable to align the height of the semiconductor device 981 and the height of the semiconductor device 994.

[0352] Electrodes 993 may be provided on the bottom of the package substrate 992 in order to mount the electronic component 990 on another substrate. FIG. 23B shows an example in which the electrodes 993 are formed of solder balls. By providing solder balls in a matrix on the bottom of the package substrate 992, BGA (Ball Grid Array) mounting can be achieved. The electrodes 993 may also be formed of conductive pins. By providing conductive pins in a matrix on the bottom of the package substrate 992, PGA (Pin Grid Array) mounting can be achieved.

[0353] The electronic component 990 can be mounted on other substrates using various mounting methods, not limited to BGA and PGA, such as a staggered pin grid array (SPGA), a land grid array (LGA), a quad flat package (QFP), a quad flat J-leaded package (QFJ), and a quad flat non-leaded package (QFN).

[0354] 24A shows a perspective view of a mainframe computer 5600. The mainframe computer 5600 shown in Fig. 24A has a rack 5610 housing a plurality of rack-mounted computers 5620. The mainframe computer 5600 may also be called a supercomputer.

[0355] The computer 5620 can have the configuration shown in the perspective view in Fig. 24B, for example. In Fig. 24B, the computer 5620 has a motherboard 5630, which has a plurality of slots 5631 and a plurality of connection terminals. A PC card 5621 is inserted into the slot 5631. In addition, the PC card 5621 has connection terminals 5623, 5624, and 5625, which are each connected to the motherboard 5630.

[0356] PC card 5621 shown in Figure 24C is an example of a processing board equipped with a CPU, a GPU, a storage device, etc. PC card 5621 has board 5622. Board 5622 also has connection terminal 5623, connection terminal 5624, connection terminal 5625, semiconductor device 5626, semiconductor device 5627, semiconductor device 5628, and connection terminal 5629. Note that Figure 24C illustrates semiconductor devices other than semiconductor device 5626, semiconductor device 5627, and semiconductor device 5628, but for these semiconductor devices, the following descriptions of semiconductor device 5626, semiconductor device 5627, and semiconductor device 5628 can be referred to.

[0357] The connection terminal 5629 has a shape that allows it to be inserted into a slot 5631 of the motherboard 5630, and the connection terminal 5629 functions as an interface for connecting the PC card 5621 and the motherboard 5630. An example of the standard for the connection terminal 5629 is PCIe.

[0358] The connection terminals 5623, 5624, and 5625 can be, for example, interfaces for supplying power to the PC card 5621, inputting signals, etc. Furthermore, they can be, for example, interfaces for outputting signals calculated by the PC card 5621. Examples of standards for the connection terminals 5623, 5624, and 5625 include USB (Universal Serial Bus), SATA (Serial ATA), and SCSI (Small Computer System Interface). Furthermore, when a video signal is output from the connection terminals 5623, 5624, and 5625, examples of the respective standards include HDMI (registered trademark).

[0359] The semiconductor device 5626 has a terminal (not shown) for inputting and outputting signals, and the semiconductor device 5626 can be connected to the board 5622 by inserting the terminal into a socket (not shown) provided on the board 5622.

[0360] The semiconductor device 5627 has a plurality of terminals, and the semiconductor device 5627 can be connected to the board 5622 by, for example, reflow soldering the terminals to wiring provided on the board 5622. Examples of the semiconductor device 5627 include an FPGA, a GPU, and a CPU. For example, the electronic component 990 can be used as the semiconductor device 5627.

[0361] The semiconductor device 5628 has a plurality of terminals, and the semiconductor device 5628 can be connected to the board 5622 by, for example, reflow soldering the terminals to wiring provided on the board 5622. Examples of the semiconductor device 5628 include a memory device. For example, the electronic component 990 can be used as the semiconductor device 5628.

[0362] The mainframe computer 5600 can also function as a parallel computer. By using the mainframe computer 5600 as a parallel computer, it is possible to perform large-scale calculations required for learning and inference in artificial intelligence, for example.

[0363] [Space Equipment] The semiconductor device of one embodiment of the present invention can be suitably used in space equipment.

[0364] A semiconductor device according to one embodiment of the present invention includes an OS transistor. Compared to a Si transistor, an OS transistor exhibits smaller variations in electrical characteristics due to radiation exposure. That is, the OS transistor has high radiation resistance and is therefore highly reliable and suitable for use in environments where radiation may be incident. For example, an OS transistor can be suitably used in outer space. Specifically, an OS transistor can be used as a transistor for a semiconductor device provided in a space shuttle, an artificial satellite, or a space probe. Examples of radiation include X-rays and neutrons. Note that outer space refers to an altitude of 100 km or higher, and the outer space described in this specification can include one or more of the thermosphere, the mesosphere, and the stratosphere.

[0365] Fig. 24D shows an artificial satellite 6800 as an example of space equipment. The artificial satellite 6800 has a body 6801, a solar panel 6802, an antenna 6803, a secondary battery 6805, and a control device 6807. Note that Fig. 24D illustrates a planet 6804 in space.

[0366] 24D , a battery management system (also referred to as a BMS) or a battery control circuit may be provided for the secondary battery 6805. The use of an OS transistor in the battery management system or the battery control circuit is preferable because it consumes low power and has high reliability even in space.

[0367] Furthermore, outer space is an environment with radiation levels 100 times higher than on Earth. Examples of radiation include electromagnetic waves (electromagnetic radiation) such as X-rays and gamma rays, and particle radiation such as alpha rays, beta rays, neutron rays, proton rays, heavy ion rays, and meson rays.

[0368] When sunlight is irradiated onto the solar panel 6802, the power required for the operation of the satellite 6800 is generated. However, for example, in a situation where sunlight is not irradiated onto the solar panel or where the amount of sunlight irradiating the solar panel is small, the generated power is small. Therefore, there is a possibility that the power required for the operation of the satellite 6800 will not be generated. In order to operate the satellite 6800 even in a situation where the generated power is small, it is preferable to provide a secondary battery 6805 on the satellite 6800. Note that the solar panel may be called a solar cell module.

[0369] The satellite 6800 can generate a signal. The signal is transmitted via an antenna 6803, and can be received by, for example, a receiver installed on the ground or another satellite. By receiving the signal transmitted by the satellite 6800, the position of the receiver that received the signal can be determined. As described above, the satellite 6800 can constitute a satellite positioning system.

[0370] The control device 6807 has a function of controlling the artificial satellite 6800. The control device 6807 is configured using, for example, one or more selected from a CPU, a GPU, and a storage device. Note that the control device 6807 is preferably a semiconductor device including an OS transistor which is one embodiment of the present invention.

[0371] The artificial satellite 6800 can also be configured to include a sensor. For example, by including a visible light sensor, the artificial satellite 6800 can have the function of detecting sunlight reflected from an object on the ground. Alternatively, by including a thermal infrared sensor, the artificial satellite 6800 can have the function of detecting thermal infrared rays emitted from the earth's surface. As described above, the artificial satellite 6800 can function as, for example, an earth observation satellite.

[0372] Although an artificial satellite is described as an example of space equipment in this embodiment, the present invention is not limited thereto. For example, the semiconductor device of one embodiment of the present invention can be suitably used in space equipment such as a spaceship, a space capsule, or a space probe.

[0373] As described above, OS transistors have excellent advantages over Si transistors, such as the ability to achieve a wide memory bandwidth and high radiation resistance.

[0374] [Data Center] The semiconductor device of one embodiment of the present invention can be suitably used in a storage system applied to, for example, a data center. The data center is required to perform long-term management of data, such as ensuring data immutability. To manage long-term data, the building must be large enough to accommodate the installation of storage and servers for storing a huge amount of data, a stable power source for storing the data, or cooling equipment required for storing the data.

[0375] By using the semiconductor device of one embodiment of the present invention in a storage system applied to a data center, it is possible to reduce the power required to store data and the size of the semiconductor device that stores data. Therefore, it is possible to reduce the size of the storage system, the size of the power supply for storing data, the scale of the cooling equipment, and the like. Therefore, it is possible to reduce the space required for the data center.

[0376] Furthermore, the semiconductor device of one embodiment of the present invention has low power consumption, which allows heat generation from the circuit to be reduced. Therefore, adverse effects of the heat generation on the circuit itself, peripheral circuits, and modules can be reduced. Furthermore, by using the semiconductor device of one embodiment of the present invention, a data center that operates stably even in a high-temperature environment can be realized. Therefore, the reliability of the data center can be improved.

[0377] Fig. 24E shows a storage system applicable to a data center. The storage system 7010 shown in Fig. 24E has multiple servers 7001sb as hosts 7001 (illustrated as Host Computers). It also has multiple storage devices 7003md as storage 7003 (illustrated as Storage). The host 7001 and storage 7003 are shown connected via a storage area network 7004 (illustrated as SAN: Storage Area Network) and a storage control circuit 7002 (illustrated as Storage Controller).

[0378] The host 7001 corresponds to a computer that accesses data stored in the storage 7003. The hosts 7001 may be connected to each other via a network.

[0379] Although the storage 7003 uses flash memory to reduce the data access speed, i.e., the time required to store and output data, this time is significantly longer than the time required for DRAM, which can be used as cache memory within the storage. In order to solve the problem of the long access speed of the storage 7003, a storage system typically provides cache memory within the storage to reduce the time required to store and output data.

[0380] The cache memory described above is used in the storage control circuit 7002 and the storage 7003. Data exchanged between the host 7001 and the storage 7003 is stored in the cache memory in the storage control circuit 7002 and the storage 7003, and then output to the host 7001 or the storage 7003.

[0381] By using OS transistors as transistors for storing data in the cache memory and holding a potential corresponding to the data, the frequency of refresh operations can be reduced, and power consumption can be reduced.

[0382] Note that the semiconductor device of one embodiment of the present invention can reduce power consumption by applying it to any one or more of electronic components, mainframe computers, space equipment, data centers, and electronic devices. Therefore, while energy demand is expected to increase with the improvement in performance or high integration of semiconductor devices, the use of the semiconductor device of one embodiment of the present invention can reduce carbon dioxide (CO ２ Furthermore, the semiconductor device of one embodiment of the present invention is effective as a countermeasure against global warming because it consumes low power.

[0383] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0384] 10: semiconductor device, 10A: semiconductor device, 11: substrate, 20: transistor, 20_1: transistor, 20_4: transistor, 21: semiconductor layer, 22: insulating layer, 23: conductive layer, 24: conductive layer, 25: conductive layer, 30: transistor, 30_1: transistor, 30_4: transistor, 31: semiconductor layer, 32: insulating layer, 33: conductive layer, 34: conductive layer, 35: conductive layer, 41: insulating layer, 42: insulating layer, 43: insulating layer, 44: insulating layer, 45: insulating layer, 46: insulating layer, 47: insulating layer, 53: plug, 53_1: plug, 53_2: plug, 54: plug, 54 _1: plug, 54_2: plug, 55: plug, 55_1: plug, 55_2: plug, 63: wiring, 63_1: wiring, 63_2: wiring, 64: wiring, 64_1: wiring, 64_2: wiring, 65: wiring, 65_1: wiring, 65_2: wiring, 100_1: NOT circuit, 100_2: NOT circuit, 100_3: NOT circuit, 100_4: NOT circuit, 200: memory cell, 900: semiconductor device, 910: driver circuit, 911: peripheral circuit, 912: control circuit, 915: peripheral circuit, 920: memory array, 923: row driver, 924: column driver, 925 : input circuit, 926: output circuit, 927: sense amplifier, 928: voltage generation circuit, 931: PSW, 932: PSW, 941: row decoder, 942: column decoder, 950: memory cell, 951: memory cell, 952: memory cell, 953: memory cell, 954: memory cell, 955: memory cell, 956: memory cell, 957: memory cell, 958: memory cell, 980: electronic component, 981: semiconductor device, 982: drive circuit layer, 983: memory layer, 984: mold, 985: land, 986: electrode pad, 987: wire, 988: printed circuit board, 989 : Mounting board, 990: Electronic component, 991: Interposer, 992: Package substrate, 993: Electrode, 994: Semiconductor device, 5600: Mainframe, 5610: Rack, 5620: Calculator, 5621: PC card, 5622: Board, 5623: Connection terminal, 5624: Connection terminal, 5625: Connection terminal, 5626: Semiconductor device, 5627: Semiconductor device, 5628: Semiconductor device, 5629: Connection terminal, 5630: Motherboard, 5631: Slot, 6800: Artificial satellite, 6801: Airframe, 6802: Solar panel, 6803: Antenna, 6804: Planet,6805: secondary battery, 6807: control device, 7001: host, 7001sb: server, 7002: storage control circuit, 7003: storage, 7003md: storage device, 7010: storage system,

Claims

a first transistor and a second transistor; the first transistor has a first semiconductor layer, a first insulating layer, and a first conductive layer; the second transistor has a second semiconductor layer, a second insulating layer, and a second conductive layer; the first semiconductor layer and the second semiconductor layer each have a sheet-like shape, the first conductive layer is provided so as to surround an upper surface, a side surface, and a lower surface of the first semiconductor layer; the first insulating layer has a portion located between the first semiconductor layer and the first conductive layer; the second conductive layer is provided so as to surround an upper surface, a side surface, and a lower surface of the second semiconductor layer; the second insulating layer has a portion located between the second semiconductor layer and the second conductive layer; the first transistor is a p-type transistor, the first semiconductor layer includes silicon or silicon germanium; the second transistor is an n-type transistor, the second semiconductor layer includes an oxide semiconductor; Semiconductor device. 　 a first transistor, a second transistor, and a third insulating layer; the first transistor has a first semiconductor layer, a first insulating layer, and a first conductive layer; the second transistor has a second semiconductor layer, a second insulating layer, and a second conductive layer; the first semiconductor layer and the second semiconductor layer each have a sheet-like shape, the first conductive layer is provided so as to surround an upper surface, a side surface, and a lower surface of the first semiconductor layer; the first insulating layer has a portion located between the first semiconductor layer and the first conductive layer; the second conductive layer is provided so as to surround an upper surface, a side surface, and a lower surface of the second semiconductor layer; the second insulating layer has a portion located between the second semiconductor layer and the second conductive layer; the second transistor is located above the first transistor; the third insulating layer is located between the first transistor and the second transistor; the first transistor is a p-type transistor, the first semiconductor layer includes silicon or silicon germanium; the second transistor is an n-type transistor, the second semiconductor layer includes an oxide semiconductor; Semiconductor device.

3. The method according to claim 2, wherein the third insulating layer includes a silicon nitride film, a silicon nitride oxide film, an aluminum oxide film, a magnesium oxide film, a hafnium oxide film, or a gallium oxide film. Semiconductor device. 　 a first transistor and a second transistor; the first transistor has a first semiconductor layer, a first insulating layer, and a first conductive layer; the second transistor has a second semiconductor layer, a second insulating layer, and the first conductive layer; the first semiconductor layer and the second semiconductor layer each have a sheet-like shape, the first conductive layer has a portion surrounding an upper surface, a side surface, and a lower surface of the first semiconductor layer, and a portion surrounding an upper surface, a side surface, and a lower surface of the second semiconductor layer; the first insulating layer has a portion located between the first semiconductor layer and the first conductive layer; the second insulating layer has a portion located between the second semiconductor layer and the first conductive layer; the first semiconductor layer and the second semiconductor layer are arranged side by side, the first transistor is a p-type transistor, the first semiconductor layer includes silicon or silicon germanium; the second transistor is an n-type transistor, the second semiconductor layer includes an oxide semiconductor; Semiconductor device. 　 n first transistors (n is an integer of 2 or more) and n second transistors; the n first transistors are stacked, the n second transistors are stacked and provided on the n first transistors; each of the n first transistors independently includes a first semiconductor layer, a first insulating layer, and a first conductive layer; each of the n second transistors independently includes a second semiconductor layer, a second insulating layer, and a second conductive layer; the first conductive layer is provided so as to surround an upper surface, a side surface, and a lower surface of the first semiconductor layer; the first insulating layer has a portion located between the first semiconductor layer and the first conductive layer; the second conductive layer is provided so as to surround an upper surface, a side surface, and a lower surface of the second semiconductor layer; the second insulating layer has a portion located between the second semiconductor layer and the second conductive layer; the first transistor is a p-type transistor, the first semiconductor layer includes silicon or silicon germanium; the second transistor is an n-type transistor, the second semiconductor layer includes an oxide semiconductor; Semiconductor device. 　 n first transistors (n is an integer of 2 or more) and n second transistors; the n first transistors are stacked, the n second transistors are stacked, each of the n first transistors independently includes a first semiconductor layer, a first insulating layer, and a first conductive layer; each of the n second transistors independently includes a second semiconductor layer, a second insulating layer, and the first conductive layer; In the k-th (k is an integer of 1 to n) first transistor and the k-th (k is an integer of 1 to n) first transistor and the k-th (k is an integer of 1 to n) second transistor from the bottom, the first conductive layer has a portion surrounding an upper surface, a side surface, and a lower surface of the first semiconductor layer, and a portion surrounding an upper surface, a side surface, and a lower surface of the second semiconductor layer, the first insulating layer has a portion located between the first semiconductor layer and the first conductive layer; the second insulating layer has a portion located between the second semiconductor layer and the first conductive layer; In the k-th first transistor and the k-th second transistor from the bottom, the first semiconductor layer and the second semiconductor layer are arranged side by side, the first transistor is a p-type transistor, the first semiconductor layer includes silicon or silicon germanium; the second transistor is an n-type transistor, the second semiconductor layer includes an oxide semiconductor; Semiconductor device. 　 In any one of claims 1 to 6, the oxide semiconductor is indium oxide; Semiconductor device. 　 In claim 7, the first semiconductor layer has a single crystal structure or a polycrystalline structure; the second semiconductor layer has a single crystal structure or a polycrystalline structure; Semiconductor device. 　 In any one of claims 1 to 6, the first transistor has a first electrode functioning as one of a source electrode and a drain electrode, and a second electrode functioning as the other of the first electrode and the drain electrode; the second transistor has a third electrode functioning as one of a source electrode and a drain electrode, and a fourth electrode functioning as the other of the source electrode and the drain electrode; the first electrode is connected to a first power supply line that transmits a high power supply potential; the second electrode and the third electrode are connected, the fourth electrode is connected to a second power supply line transmitting a low power supply potential; Semiconductor device.

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