Light-emitting device, print head, and printer

Abstract

This light-emitting device comprises: a light-emitting region which includes first to n-th light-emitting elements (D1 to D4) when n represents an integer of at least 2 and m equals n−1, and in which sequential light emission of the n-number of light-emitting elements is repeated; first to n-th control circuits (X1 to X4) that each include a drive transistor and an output end; first to n-th relay lines (L1 to L4) that electrically connect the output ends of the first to n-th control circuits to the first to n-th light-emitting elements; and a first auxiliary line (WF) that, together with the gate electrode of the drive transistor (TD) of the n-th control circuit (X4), forms a capacitor (C4) and is connected to the output end (Q) of any one (X2) of the first to m-th control circuits (X1 to X3).

Description

Light-emitting device, print head, printer

[0001] The present disclosure relates to a light emitting device.

[0002] Japanese Patent Application Laid-Open No. 2003-144222 discloses a wiring pattern in an LED print head.

[0003] Japanese Patent Publication No. 2010-177306

[0004] In a light emitting device that includes a plurality of control circuits that control a plurality of light emitting elements, there is a problem in that uneven light emission occurs due to the parasitic capacitance of wiring connected to each control circuit.

[0005] The light emitting device according to the present disclosure comprises: a light emitting region including first to nth light emitting elements, where n is an integer of 2 or more and m=n-1, and in which the n light emitting elements are sequentially and repeatedly illuminated; first to nth control circuits, each including a drive transistor and an output terminal; first to nth relay lines electrically connecting the output terminals of the first to nth control circuits to the first to nth light emitting elements; and a first auxiliary line which forms a capacitance with the gate electrode of the drive transistor of the nth control circuit and is connected to the output terminal of any one of the first to mth control circuits.

[0006] In a light emitting device including a plurality of light emitting elements, uneven light emission is reduced.

[0007] FIG. 1 is a schematic diagram showing the configuration of a light emitting device according to the present embodiment; FIG. 2 is a timing chart showing a method for driving the light emitting device according to the present embodiment; FIG. 3 is a cross-sectional view of a control circuit; FIG. 4 is a cross-sectional view of a control circuit; FIG. 5 is a cross-sectional view of a control circuit; FIG. 6 is a cross-sectional view of a control circuit; FIG. 7 is a schematic diagram showing the configuration of a light emitting device according to the present embodiment; FIG. 8 is a timing chart showing a method for driving the light emitting device according to the present embodiment; FIG. 9 is a cross-sectional view of a control circuit; FIG. 10 is a cross-sectional view of a control circuit; FIG. 11 is a cross-sectional view of a control circuit; FIG. 12 is a plan view showing the configuration of a light emitting region; FIG. 13 is a plan view showing an example of an exposure result; FIG. 14 is a schematic diagram showing the configuration of a printer according to the

[0008] FIG. 1 is a schematic diagram showing the configuration of a light-emitting device according to this embodiment. FIG. 2 is a timing chart showing a driving method of the light-emitting device. The light-emitting device 10 according to this embodiment includes a light-emitting area EA including first to n-th light-emitting elements D1 to Dn, where n is an integer greater than or equal to 2 and m=n-1, and in which the n light-emitting elements are sequentially illuminated. It also includes first to n-th control circuits X1 to Xn, each including a drive transistor TD and an output terminal Q. It also includes first to n-th relay lines L1 to Ln that electrically connect the output terminal Q of the first to n-th control circuits X1 to Xn to the first to n-th light-emitting elements D1 to Dn. It also includes a first auxiliary line WF that forms a capacitance with the gate electrode of the drive transistor TD of the n-th control circuit Xn and is connected to the output terminal Q of one of the first to m-th control circuits X1 to Xn. When n is 3 or greater, the first auxiliary line WF may be connected to the output terminal Q of the second control circuit X2.

[0009] The light emitting device 10 has a circuit area CA including first to n-th control circuits X1 to Xn, and the n-th light emitting element Dn (D4) electrically connected to the output terminal Q of the n-th control circuit Xn (X4) is closest to the circuit area CA. The first to n-th control circuits X1 to Xn are arranged in this order in the first direction Y1, and the n-th control circuit Xn is furthest from the light emitting area EA.

[0010] In the light emitting device 10, each of the first to n-th relay lines L1 to Ln forms a capacitance (parasitic capacitance) with the gate electrode of the drive transistor TD included in at least one of the first to m-th control circuits X1 to Xm (X3). The first to m-th relay lines L1 to Lm do not form a capacitance with the gate electrode of the drive transistor TD of the n-th control circuit Xn. FIG. 1 shows an example where n = 4 and m = 3. Hereinafter, the first to n-th control circuits X1 to Xn may be collectively referred to as control circuit X.

[0011] 2, when the first to n-th control circuits X1 to Xn are repeatedly activated in this order, the gate electrode of the drive transistor TD of the first control circuit X1 is affected by potential fluctuations at the output terminal Q of the third control circuit X3 (next-next stage) during the light-emitting period due to parasitic capacitance C1 between the first control circuit X1 and the third relay line L3. Meanwhile, the gate electrode of the drive transistor TD of the n-th control circuit Xn (X4) is affected by potential fluctuations at the output terminal Q of the second control circuit X2 (next-next stage) during the light-emitting period due to capacitance C4 formed between the first control circuit X1 and the first auxiliary line WF. This makes it possible to reduce light-emission unevenness (brightness unevenness) between the first light-emitting element D1 connected to the first control circuit X1 and the n-th light-emitting element Dn (D4) connected to the n-th control circuit Xn (X4).

[0012] In FIG. 1 , the output terminal Q of the first control circuit X1 is connected to the first light-emitting element D1 via a first relay line L1. The first relay line L1 may be connected to the anode of the first light-emitting element D1. The output terminal Q of the second control circuit X2 is connected to the second light-emitting element D2 via a second relay line L2. The second relay line L2 may be connected to the anode of the second light-emitting element D2. The output terminal Q of the third control circuit X3 is connected to the third light-emitting element D3 via a third relay line L3. The third relay line L3 may be connected to the anode of the third light-emitting element D3. The output terminal Q of the fourth control circuit X4 is connected to the fourth light-emitting element D4 via a fourth relay line L4. The fourth relay line L4 may be connected to the anode of the fourth light-emitting element D4.

[0013] The light emitting device 10 in Figure 1 includes a first auxiliary line WF that forms a capacitance with the gate electrode of the drive transistor TD of the nth control circuit Xn (X4) and is connected to the output terminal Q of the second control circuit X2, as well as a second auxiliary line WS that forms a capacitance with the gate electrode of the drive transistor TD of the mth control circuit Xm (X3) and is connected to the output terminal Q of the first control circuit X1.

[0014] A parasitic capacitance C1 exists between the gate electrode of the drive transistor TD of the first control circuit X1 and the third relay line L3, a parasitic capacitance C2 exists between the gate electrode of the drive transistor TD of the second control circuit X2 and the fourth relay line L4, a capacitance C3 exists between the gate electrode of the drive transistor TD of the third control circuit X3 and the second auxiliary line WS, and a capacitance C4 exists between the gate electrode of the drive transistor TD of the fourth control circuit X4 and the first auxiliary line WF.

[0015] 2, the first to n-th control circuits X1 to Xn are repeatedly activated in this order. Specifically, for i=1 to n and n=4, binary data Ai (data voltage corresponding to light emission / non-emission) is written to the control circuit Xi during the active (low) period of the scanning line Gi, the light-emitting element Di is selected (light emission / non-emission) during the active (low) period of the light-emission control line Ei, and the output terminal Q of the control circuit Xi is discharged (the anode potential is initialized) during the active (low) period of the discharge line Zi. Each of A1 to A4 may be photosensitive data.

[0016] The gate electrode of the drive transistor TD of the first control circuit X1 is affected by the discharge (potential fluctuation at output terminal Q) of the third control circuit X3, which is the next stage after the first control circuit. The gate electrode of the drive transistor TD of the second control circuit X2 is affected by the discharge (potential fluctuation at output terminal Q) of the fourth control circuit X4, which is the next stage after the first control circuit. The gate electrode of the drive transistor TD of the third control circuit X3 is affected by the discharge (potential fluctuation at output terminal Q) of the first control circuit X1, which is the next stage after the first control circuit. The gate electrode of the drive transistor TD of the fourth control circuit X4 is affected by the discharge (potential fluctuation at output terminal Q) of the second control circuit X2, which is the next stage after the second control circuit.

[0017] 1 and 2 , the gate electrode of the drive transistor TD of the first control circuit X1 is subjected to potential fluctuations due to capacitance C1 (parasitic capacitance) during the light-emitting period of the light-emitting element D1, the gate electrode of the drive transistor TD of the second control circuit X2 is subjected to potential fluctuations due to capacitance C2 (parasitic capacitance) during the light-emitting period of the light-emitting element D2, the gate electrode of the drive transistor TD of the third control circuit X3 is subjected to potential fluctuations due to capacitance C3 (compensation capacitance due to the second auxiliary line WS) during the light-emitting period of the light-emitting element D3, and the gate electrode of the drive transistor TD of the fourth control circuit X4 is subjected to potential fluctuations due to capacitance C4 (compensation capacitance due to the first auxiliary line WF) during the light-emitting period of the light-emitting element D4. This reduces light-emission unevenness (brightness unevenness) of the first to n-th light-emitting elements D1 to Dn (D4).

[0018] The first auxiliary line WF may be routed so as not to form a capacitance with the gate electrode of the drive transistor TD of the third control circuit X3, and the second auxiliary line WS may be routed so as not to form a capacitance with the gate electrode of the drive transistor TD of the second control circuit X2.

[0019] The n-th control circuit Xn (X4) does not have to overlap with the light emitting area EA in a planar view. All of the first to n-th control circuits X1 to Xn (X4) do not have to overlap with the light emitting area EA in a planar view.

[0020] The control circuit X may include a light-emitting control transistor T6, and the drain electrode of the drive transistor TD may be connected to the output terminal Q via the light-emitting control transistor T6. The gate electrode of the power supply transistor T5 and the gate electrode of the light-emitting control transistor T6 may be connected to a light-emitting control line Ei (i=1 to n).

[0021] The light-emitting device 10 may include a high-potential power line VH and an initialization voltage line VS. The control circuit X may include a discharge transistor T7 and a capacitance element Cp. In the control circuit X, the gate electrode of the drive transistor TD may be connected to the high-potential power line VH via the capacitance element Cp, and the output terminal Q may be connected to the initialization voltage line VS via the discharge transistor T7. The gate electrode of the drive transistor TD may be connected to the initialization voltage line VS via a reset transistor TS. The gate electrode of the discharge transistor T7 may be connected to a discharge line Zi (i = 1 to n).

[0022] The light-emitting device 10 may include a data line DL, which may be connected to a source electrode of a drive transistor TD via a write transistor TW. The source electrode of the drive transistor TD may be connected to a high-potential power line VH via a power transistor T5. A scanning line Gi (i = 1 to n) may be connected to a gate electrode of the write transistor TW and a gate electrode of a threshold setting transistor TH. The gate electrode of the drive transistor TD may be connected to a drain electrode of the drive transistor TD via the threshold setting transistor TH.

[0023] 3 to 7 are cross-sectional views of the control circuit. The drive transistor TD of the control circuit X may include a semiconductor layer SC (e.g., LTPS) located on a substrate 16, an insulating film 17 (gate insulating film), and a gate electrode GE. The control circuit X includes a capacitive electrode CE, and in a plan view of the control circuit X, the capacitive electrode CE and the gate electrode GE of the drive transistor TD may overlap with each other via an inorganic insulating film 18, and this overlapping portion may constitute a capacitive element Cp.

[0024] 3, in a plan view, the first auxiliary line WF and the gate electrode GE of the drive transistor TD of the nth control circuit (X4) may overlap with each other via inorganic insulating films 18 and 19, and this overlapping portion may be a capacitance C4 (compensation capacitance). The first auxiliary line WF may be connected to the drain DR (output terminal Q) of the light-emitting control transistor T6 of the second control circuit X2. As shown in FIG. 4, an organic insulating film 20 may be formed on the inorganic insulating film 19, and the first auxiliary line WF may be formed on the organic insulating film 20.

[0025] 5 , in a plan view, the second auxiliary line WS and the gate electrode GE of the drive transistor TD of the m-th control circuit (X3) overlap with each other via inorganic insulating films 18 and 19, and the overlapping portion may be a capacitance C3 (compensation capacitance). The second auxiliary line WS may be connected to the drain DR (output terminal Q) of the light-emission control transistor T6 of the first control circuit X1.

[0026] 6 , the third relay line L3 may be connected to the drain DR (output end Q) of the light-emitting control transistor T6 of the third control circuit X3. In plan view, the third relay line L3 and the gate electrode GE of the drive transistor TD of the first control circuit (X1) may overlap with inorganic insulating films 18 and 19 interposed therebetween, and the overlapping portion may be a capacitance C1 (parasitic capacitance).

[0027] 7 , the fourth relay line L4 may be connected to the drain DR (output end Q) of the light-emitting control transistor T6 of the fourth control circuit X4. In plan view, the fourth relay line L4 and the gate electrode GE of the drive transistor TD of the second control circuit (X2) may overlap with each other via inorganic insulating films 18 and 19, and this overlapping portion may be a capacitance C2 (parasitic capacitance).

[0028] FIG. 8 is a schematic diagram showing the configuration of a light-emitting device according to this embodiment. FIG. 9 is a timing chart showing a driving method of the light-emitting device. The light-emitting device 10 according to this embodiment includes a light-emitting area EA including first to n-th light-emitting elements D1 to Dn, where n is an integer of 2 or greater and m=n-1, in which the n light-emitting elements are sequentially illuminated. It also includes first to n-th control circuits X1 to Xn, each including a drive transistor TD and an output terminal Q. It also includes first to n-th relay lines L1 to Ln that electrically connect the output terminal Q of the first to n-th control circuits X1 to Xn to the first to n-th light-emitting elements D1 to Dn. It also includes a first auxiliary line WF that forms a capacitance with the gate electrode of the drive transistor TD of the n-th control circuit Xn and is connected to the output terminal Q of one of the first to m-th control circuits X1 to Xn. When n is 3 or greater, the first auxiliary line WF may be connected to the output terminal Q of the first control circuit X1.

[0029] The first to n-th control circuits X1 to Xn are arranged in this order in the first direction Y1, with the n-th control circuit Xn (X4) being the farthest from the light-emitting area EA. Each of the first to n-th relay lines L1 to Ln forms a capacitance (parasitic capacitance) with the gate electrode of the drive transistor TD included in at least one of the first to m-th control circuits X1 to Xm, and the first to m-th relay lines L1 to Lm do not form a capacitance with the gate electrode of the drive transistor TD of the n-th control circuit Xn (X4).

[0030] 9 , when the first to n-th control circuits X1 to Xn are repeatedly activated in the reverse order (X4 → X3 → X2 → X1), the gate electrode of the drive transistor TD of the first control circuit X1 is affected by potential fluctuations at the output terminal Q of the second control circuit X2 (previous stage) during the light-emitting period due to parasitic capacitance C1 between the first control circuit X1 and the second relay line L2. Meanwhile, the gate electrode of the drive transistor TD of the n-th control circuit Xn (X4) is affected by potential fluctuations at the output terminal Q of the first control circuit X1 (previous stage) during the light-emitting period due to capacitance C4 formed between the first control circuit X1 and the first auxiliary line WF. This reduces uneven light emission (uneven brightness) between the first light-emitting element D1 connected to the first control circuit X1 and the n-th light-emitting element Dn (D4) connected to the n-th control circuit Xn (X4).

[0031] 9, the first to n-th control circuits X1 to Xn are repeatedly activated in the reverse order (X4 → X3 → X2 → X1). Specifically, for i = 1 to n and n = 4, binary data (data voltage corresponding to light emission / non-emission) is written to the control circuit Xi during the active (low) period of the scanning line Gi, the light-emitting element Di is selected (light emission / non-emission) during the active (low) period of the light-emission control line Ei, and the output terminal Q of the control circuit Xi is discharged (the anode potential is initialized) during the active (low) period of the discharge line Zi.

[0032] 8 and 9, the gate electrode of the drive transistor TD of the first control circuit X1 is affected by the discharge of the second control circuit X2 (potential fluctuation at the output terminal Q), which is the preceding stage. The gate electrode of the drive transistor TD of the second control circuit X2 is affected by the discharge of the third control circuit X3 (potential fluctuation at the output terminal Q), which is the preceding stage. The gate electrode of the drive transistor TD of the third control circuit X3 is affected by the discharge of the fourth control circuit X4 (potential fluctuation at the output terminal Q), which is the preceding stage. The gate electrode of the drive transistor TD of the fourth control circuit X4 is affected by the discharge of the first control circuit X1 (potential fluctuation at the output terminal Q), which is the preceding stage.

[0033] 8 and 9, the gate electrode of the drive transistor TD of the first control circuit X1 is subjected to potential fluctuations due to capacitance C1 (parasitic capacitance) during the light-emitting period of the light-emitting element D1, the gate electrode of the drive transistor TD of the second control circuit X2 is subjected to potential fluctuations due to capacitance C2 (parasitic capacitance) during the light-emitting period of the light-emitting element D2, the gate electrode of the drive transistor TD of the third control circuit X3 is subjected to potential fluctuations due to capacitance C3 (parasitic capacitance) during the light-emitting period of the light-emitting element D3, and the gate electrode of the drive transistor TD of the fourth control circuit X4 is subjected to potential fluctuations due to capacitance C4 (compensation capacitance due to the first auxiliary line WF) during the light-emitting period of the light-emitting element D4. This reduces light-emission unevenness (brightness unevenness) of the first to n-th light-emitting elements D1 to Dn (D4).

[0034] 10 to 13 are cross-sectional views of the control circuit. The drive transistor TD of the control circuit X may include a semiconductor layer SC (e.g., LTPS), an insulating film 17 (gate insulating film), and a gate electrode GE. The control circuit X includes a capacitive electrode CE, and in a plan view of the control circuit X, the capacitive electrode CE and the gate electrode GE of the drive transistor TD may overlap with each other via an inorganic insulating film 18, and this overlapping portion may constitute a capacitive element Cp.

[0035] 10 , in a plan view, the first auxiliary line WF and the gate electrode GE of the drive transistor TD of the n-th control circuit (X4) overlap with each other via inorganic insulating films 18 and 19, and the overlapping portion may be a capacitance C4 (compensation capacitance). The first auxiliary line WF may be connected to the drain DR (output terminal Q) of the light-emission control transistor T6 of the first control circuit X1.

[0036] 11 , the second relay line L2 may be connected to the drain DR (output terminal Q) of the light-emitting control transistor T6 of the second control circuit X2. In plan view, the second relay line L2 and the gate electrode GE of the drive transistor TD of the first control circuit (X1) may overlap with each other via inorganic insulating films 18 and 19, and the overlapping portion may be a capacitance C1 (parasitic capacitance).

[0037] 12 , the third relay line L3 may be connected to the drain DR (output end Q) of the light-emitting control transistor T6 of the third control circuit X3. In plan view, the third relay line L3 and the gate electrode GE of the drive transistor TD of the second control circuit (X2) may overlap with each other via inorganic insulating films 18 and 19, and the overlapping portion may be a capacitance C2 (parasitic capacitance).

[0038] 13 , the fourth relay line L4 may be connected to the drain DR (output end Q) of the light-emission control transistor T6 of the fourth control circuit X4. In plan view, the fourth relay line L4 and the gate electrode GE of the drive transistor TD of the third control circuit (X3) may overlap with each other via inorganic insulating films 18 and 19, and this overlapping portion may be a capacitance C3 (parasitic capacitance).

[0039] FIG. 14 is a plan view showing the configuration of the light-emitting region. FIG. 15 is a plan view showing an example of the exposure result. As shown in FIG. 14, in the light-emitting region EA, the first to n-th light-emitting elements D1 to Dn may be arranged in a direction oblique to the first direction Y1 (sub-scanning direction). Each of the first to n-th light-emitting elements D1 to Dn may be an OLED (organic light-emitting diode) diode having an organic light-emitting layer or a quantum dot light-emitting layer (e.g., a light-emitting layer containing light-emitting nanoparticles with a semiconductor core), or an inorganic semiconductor light-emitting layer (e.g., a light-emitting layer formed of a crystal growth layer of an inorganic semiconductor).

[0040] The light-emitting area EA may have a plurality of light-emitting element groups U, each including first to nth light-emitting elements D1 to Dn, aligned in a second direction Y2 (main scanning direction) perpendicular to the first direction Y1. Figure 15 shows the results of ten exposures of the photosensitive drum using two light-emitting element groups U1 and U2 aligned in the second direction Y2. The data (binary exposure data) of the light-emitting element group U1 is denoted as A1 to A4, and the data (binary exposure data) of the light-emitting element group U2 is denoted as B1 to B4.

[0041] Fig. 16 is a schematic diagram showing the configuration of a printer according to this embodiment. Fig. 17 is a flowchart showing the operation of the printer according to this embodiment. As shown in Figs. 16 and 17, a printer 20 (image forming apparatus) includes a photosensitive drum 5, a print head 30 that performs the exposure process of Fig. 17, a developing device 40 that performs the development process of Fig. 17, a transfer device 50 that performs the transfer process of Fig. 17, a fixing device 60 that performs the fixing process of Fig. 17, a cooling device 70, and a charging device 80. The print head 30 includes the light-emitting device 10 described with reference to Figs. 1 to 15.

[0042] The print head 30 irradiates the photosensitive drum 5 with light to form a charge pattern according to the image data. The developing device 40, for example, attaches toner to the latent image. The transfer device 50 transfers the toner to a recording medium P (e.g., printing paper). The fixing device 60 fixes the transferred toner to the recording medium P using heat and pressure. The cooling device 70 removes toner and other residue remaining on the photosensitive drum 5. The charging device 80 charges the surface of the photosensitive drum 5.

[0043] 1 to 15 is used in a print head 30 in Fig. 16, but is not limited to this. A light-emitting device 10 including first to n-th light-emitting elements D1 to Dn can also be used in a display device. In this case, the first to n-th light-emitting elements D1 to Dn may each be a diode having an organic light-emitting layer, a quantum dot light-emitting layer, or an inorganic semiconductor light-emitting layer, and uneven light emission (uneven brightness) of the first to n-th light-emitting elements D1 to Dn is reduced.

[0044] The above-described embodiments are intended to be illustrative and explanatory, and are not intended to be limiting. Based on these examples and explanations, it will be apparent to those skilled in the art that many modifications are possible. The gist of the present embodiments will be described below. In the following, "the above" includes the technical content disclosed in at least one of FIGS. 1 to 17.

[0045] [Summary] A light emitting device comprising: a light emitting region including first to nth light emitting elements, where n is an integer of 2 or more and m=n-1, and in which the n light emitting elements are sequentially and repeatedly illuminated; first to nth control circuits, each including a drive transistor and an output terminal; first to nth relay lines electrically connecting the output terminals of the first to nth control circuits and the first to nth light emitting elements; and a first auxiliary line, which forms a capacitance (compensation capacitance) with the gate electrode of the drive transistor of the nth control circuit and is connected to the output terminal of any one of the first to mth control circuits.

[0046] The light emitting device described above, wherein the first to n-th control circuits are arranged in this order in a first direction, and the n-th control circuit is the farthest from the light emitting region.

[0047] The light emitting device described above, wherein output terminals of the first to nth control circuits are electrically connected to the anodes of the first to nth light emitting elements, respectively.

[0048] The light emitting device described above, wherein each of the first to nth relay lines forms a capacitance with a gate electrode of a driving transistor included in at least one of the first to mth control circuits.

[0049] The light emitting device described above, wherein the nth control circuit does not overlap the light emitting region in a plan view.

[0050] The light emitting device described above, wherein the first to mth control circuits do not overlap the light emitting region in a plan view.

[0051] The light emitting device described above, wherein the first to m-th relay lines do not form capacitance with the gate electrode of the drive transistor of the nth control circuit.

[0052] The light emitting device described above further comprises a second auxiliary line that forms a capacitance with the gate electrode of the drive transistor of the mth control circuit and is connected to the output terminal of any one of the first to (m-1)th control circuits.

[0053] The light emitting device described above, wherein the first to n-th light emitting elements are arranged in a direction oblique to the first direction.

[0054] The light emitting device described above has a circuit area including the first to nth control circuits, and the nth light emitting element electrically connected to an output terminal of the nth control circuit is closest to the circuit area.

[0055] The light emitting device described above, wherein the first to nth control circuits are scanned in this order, and the first to nth light emitting elements emit light in this order.

[0056] The light emitting device described above, wherein the first to nth control circuits are scanned in the reverse order, and the first to nth light emitting elements emit light in the reverse order.

[0057] The light emitting device according to any one of the preceding claims, wherein n is 3 or greater, and the first auxiliary line is connected to an output terminal of the first control circuit or the second control circuit.

[0058] The light emitting device described above, wherein the first auxiliary line and the gate electrode of the drive transistor of the nth control circuit overlap with each other via an insulating film in plan view.

[0059] The light-emitting device described above, wherein the insulating film includes an organic insulating film.

[0060] The light emitting device described above, wherein each of the first to nth control circuits includes a light emission control transistor, and in each of the first to nth control circuits, the drain electrode of the drive transistor is connected to the output terminal via the light emission control transistor.

[0061] The light-emitting device described above includes a high-potential power supply line and an initialization voltage line, wherein each of the first to nth control circuits includes a discharge transistor and a capacitance element, and in each of the first to nth control circuits, the gate electrode of the drive transistor is connected to the high-potential power supply line via the capacitance element, and the output terminal is connected to the initialization voltage line via the discharge transistor.

[0062] The light-emitting device as described above, wherein each of the first to nth control circuits includes a capacitance electrode connected to the high-potential side power supply line, and in a plan view of each of the first to nth control circuits, the capacitance electrode and the gate electrode of the driving transistor overlap.

[0063] The light emitting device described above, wherein the light emitting region includes a plurality of light emitting element groups arranged in a second direction perpendicular to the first direction, and each of the plurality of light emitting element groups has the first to n-th light emitting elements.

[0064] The light emitting device described above, wherein the first to nth light emitting elements are OLEDs.

[0065] A print head comprising the above-described light-emitting device.

[0066] A printer comprising the print head described above and a photosensitive drum onto which light from the print head is irradiated.

[0067] 10 Light emitting device 30 Print head Q Output terminal G1 to Gn Scanning lines D1 to Dn Light emitting elements L1 to Ln Relay lines X1 to Xn Control circuit TD Drive transistor T6 Light emitting control transistor C4 Capacitor (compensation capacitor) EA Light emitting area CA Circuit area

Claims

1. A light emitting device comprising: a light emitting region including first to n-th light emitting elements, where n is an integer of 2 or more and m=n-1, and in which the n light emitting elements are sequentially and repeatedly illuminated; first to n-th control circuits, each including a drive transistor and an output terminal; first to n-th relay lines electrically connecting the output terminals of the first to n-th control circuits and the first to n-th light emitting elements; and a first auxiliary line, which forms a capacitance with the gate electrode of the drive transistor of the n-th control circuit and is connected to the output terminal of any one of the first to m-th control circuits.

2. The light emitting device according to claim 1, wherein the first to nth control circuits are arranged in this order in the first direction, and the nth control circuit is the furthest from the light emitting region.

3. The light emitting device according to claim 2, wherein output terminals of the first to nth control circuits are electrically connected to the anodes of the first to nth light emitting elements, respectively.

4. The light emitting device according to claim 2, wherein each of the first to nth relay lines forms a capacitance with a gate electrode of a drive transistor included in at least one of the first to mth control circuits.

5. The light emitting device according to claim 2, wherein the nth control circuit does not overlap the light emitting region in a plan view.

6. The light emitting device according to claim 5, wherein the first to mth control circuits do not overlap the light emitting region in a plan view.

7. The light emitting device according to claim 2, wherein the first to m-th relay lines do not form capacitance with the gate electrode of the drive transistor of the nth control circuit.

8. The light emitting device according to claim 2, further comprising a second auxiliary line that forms a capacitance with the gate electrode of the drive transistor of the mth control circuit and is connected to the output terminal of any one of the first to (m-1)th control circuits.

9. The light emitting device according to claim 2, wherein the first to nth light emitting elements are arranged in a direction oblique to the first direction.

10. A light emitting device according to claim 2, further comprising a circuit area including the first to nth control circuits, wherein the nth light emitting element electrically connected to the output terminal of the nth control circuit is closest to the circuit area.

11. The light emitting device according to claim 2, wherein the first to nth control circuits are scanned in this order, and the first to nth light emitting elements emit light in this order.

12. The light emitting device according to claim 2, wherein the first to nth control circuits are scanned in the reverse order, and the first to nth light emitting elements emit light in the reverse order.

13. The light emitting device according to claim 2, wherein n is 3 or more, and the first auxiliary line is connected to an output terminal of the first control circuit or the second control circuit.

14. The light emitting device according to any one of claims 1 to 13, wherein, in plan view, the first auxiliary line and the gate electrode of the drive transistor of the nth control circuit overlap with each other via an insulating film.

15. The light-emitting device according to claim 14, wherein the insulating film includes an organic insulating film.

16. A light-emitting device according to any one of claims 1 to 15, wherein each of the first to nth control circuits includes a light-emitting control transistor, and in each of the first to nth control circuits, the drain electrode of the drive transistor is connected to the output terminal via the light-emitting control transistor.

17. The light-emitting device according to claim 16, comprising a high-potential power supply line and an initialization voltage line, wherein each of the first to nth control circuits includes a discharge transistor and a capacitance element, and in each of the first to nth control circuits, the gate electrode of the drive transistor is connected to the high-potential power supply line via the capacitance element, and the output terminal is connected to the initialization voltage line via the discharge transistor.

18. The light-emitting device according to claim 17, wherein each of the first to nth control circuits includes a capacitance electrode connected to the high-potential power supply line, and in a plan view of each of the first to nth control circuits, the capacitance electrode overlaps with the gate electrode of the drive transistor.

19. The light emitting device according to claim 9, wherein the light emitting region includes a plurality of light emitting element groups arranged in a second direction perpendicular to the first direction, and each of the plurality of light emitting element groups has the first to nth light emitting elements.

20. The light emitting device according to any one of claims 1 to 19, wherein each of the first to nth light emitting elements is a diode having an organic light emitting layer or a quantum dot light emitting layer.

21. A print head comprising a light emitting device according to any one of claims 1 to 20.

22. A printer comprising the print head according to claim 21 and a photosensitive drum onto which light from said print head is irradiated.

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